TI TMS320C6670

TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
Data Manual
ADVANCE INFORMATION concerns new products in the sampling
or preproduction phase of development. Characteristic data and
other specifications are subject to change without notice.
Literature Number: SPRS689
November 2010
TMS320C6670
Data Manual
SPRS689—November 2010
www.ti.com
Release History
Release
Date
Chapter/Topic
Description/Comments
1.0
November 2010
All
Initial Release
2
Release History
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Contents
1
TMS320C6670 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.1 KeyStone Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.2 Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2
Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
CPU (DSP Core) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Memory Map Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Boot Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Boot Modes Supported and PLL Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.5.1 Boot Device Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.5.2 Device Configuration Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.5.3 PLL Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Second-Level Bootloaders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.9.1 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.9.2 Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
3.1 Device Configuration at Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
3.2 Peripheral Selection After Device Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3.3 Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3.3.1 Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
3.3.2 Device Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
3.3.3 JTAG ID (JTAGID) Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
3.3.4 Kicker Mechanism (KICK0 and KICK1) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
3.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
3.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
3.3.7 Reset Status (RESET_STAT) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
3.3.8 Reset Status Clear (RESET_STAT_CLR) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
3.3.9 Boot Complete (BOOTCOMPLETE) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
3.3.10 Power State Control (PWRSTATECTL) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
3.3.11 NMI Even Generation to CorePac (NMIGRx) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
3.3.12 IPC Generation (IPCGRx) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
3.3.13 IPC Acknowledgement (IPCARx) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
3.3.14 IPC Generation Host (IPCGRH) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
3.3.15 IPC Acknowledgement Host (IPCARH) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
3.3.16 Timer Input Selection Register (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
3.3.17 Timer Output Selection Register (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
3.3.18 Reset Mux (RSTMUXx) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
3.4 Pullup/Pulldown Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
4
System Interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
4.1
4.2
4.3
4.4
5
Internal Buses, Bridges, and Switch Fabrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Data Switch Fabric Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Configuration Switch Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Bus Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
C66x CorePac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
5.1 Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
5.1.1 L1P Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
5.1.2 L1D Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
5.1.3 L2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
5.1.4 MSM SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
5.1.5 L3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
5.2 Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Copyright 2010 Texas Instruments Incorporated
Contents
3
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
5.3
5.4
5.5
5.6
5.7
6
www.ti.com
Bandwidth Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Power-Down Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
CorePac Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
CorePac Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
C66x CorePac Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Device Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
6.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
6.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
6.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
7
TMS320C6670 Peripheral Information and Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
7.1 Parameter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
7.1.1 1.8-V Signal Transition Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
7.1.2 Timing Parameters and Board Routing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
7.2 Recommended Clock and Control Signal Transition Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
7.3 Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
7.3.1 Power-Up Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
7.3.2 Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.3.3 Power Supply Decoupling and Bulk Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7.3.4 SmartReflex. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
7.4 Enhanced Direct Memory Access (EDMA3) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.4.1 EDMA3 Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.4.2 EDMA3 Channel Synchronization Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
7.5.1 Interrupt Sources and Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
7.5.2 INTC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
7.5.3 Inter-Processor Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
7.5.4 NMI and LRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
7.5.5 External Interrupts Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.6 Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
7.6.1 MPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.6.2 MPU Programmable Range Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
7.7 Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
7.7.1 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
7.7.2 Hard Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
7.7.3 Soft Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
7.7.4 Local Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
7.7.5 Reset Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
7.7.6 Reset Controller Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
7.7.7 Reset Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
7.8 Main PLL and the PLL Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
7.8.1 Main PLL Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
7.8.2 PLL Controller Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
7.8.3 Main PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
7.8.4 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
7.9 DDR3 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
7.9.1 DDR3 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
7.9.2 DDR3 PLL Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
7.9.3 DDR3 PLL Input Clock Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
7.10 PASS PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
7.10.1 PASS PLL Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
7.10.2 PASS PLL Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
7.10.3 PASS PLL Input Clock Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
7.11 DDR3 Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
7.11.1 DDR3 Memory Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
7.11.2 DDR3 Memory Controller Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
7.12 I2C Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
7.12.1 I2C Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
7.12.2 I2C Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
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Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
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7.12.3 I C Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.13 SPI Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.13.1 SPI Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.14 HyperLink Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.15 UART Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.16 PCIe Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.17 Packet Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.18 Security Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.19 Ethernet MAC (EMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.20 Management Data Input/Output (MDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.21 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.21.1 Timers Device-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.21.2 Timers Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.22 Rake Search Accelerator (RSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.23 Enhanced Viterbi-Decoder Coprocessor (VCP2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.24 Third-Generation Turbo Decoder Coprocessor (TCP3d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.25 Turbo Encoder Coprocessor (TCP3e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.26 Serial RapidIO (SRIO) Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.27 General-Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.27.1 GPIO Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.27.2 GPIO Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.28 Semaphore2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.29 Antenna Interface Subsystem 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.30 FFTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.31 Emulation Features and Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.31.1 Advanced Event Triggering (AET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.31.2 Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.31.3 IEEE 1149.1 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
8.1 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
8.2 Package CYP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Copyright 2010 Texas Instruments Incorporated
Contents
5
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
List of Figures
Figure 1-1
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 2-5
Figure 2-6
Figure 2-7
Figure 2-8
Figure 2-9
Figure 2-10
Figure 2-11
Figure 3-1
Figure 3-2
Figure 3-3
Figure 3-4
Figure 3-5
Figure 3-6
Figure 3-7
Figure 3-8
Figure 3-9
Figure 3-10
Figure 3-11
Figure 3-12
Figure 3-13
Figure 3-14
Figure 3-15
Figure 3-16
Figure 3-17
Figure 4-1
Figure 5-1
Figure 5-2
Figure 5-3
Figure 5-4
Figure 7-1
Figure 7-2
Figure 7-3
Figure 7-4
Figure 7-5
Figure 7-6
Figure 7-7
Figure 7-8
Figure 7-9
Figure 7-10
Figure 7-11
Figure 7-12
Figure 7-13
Figure 7-14
Figure 7-15
Figure 7-16
Figure 7-17
Figure 7-18
6
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
TMS320C6670 CPU (DSP Core) Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Boot Mode Pin Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Sleep Configuration Bit Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Ethernet (SGMII) Device Configuration Bit Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Serial Rapid I/O Device Configuration Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
PCI Device Configuration Bit Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
I2C Master Mode Device Configuration Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
I2C Passive Mode Device Configuration Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
SPI Device Configuration Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
HyperLink Boot Device Configuration Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
CYP 841-PIN BGA Package Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Device Configuration Register (DEVCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
JTAG ID (JTAGID) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
LRESETNMI PIN Status Register (LRSTNMIPINSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Reset Status Register (RESET_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Reset Status Clear Register (RESET_STAT_CLR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Boot Complete Register (BOOTCOMPLETE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Power State Control Register (PWRSTATECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
NMI Generation Register (NMIGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
IPC Generation Registers (IPCGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
IPC Acknowledgement Registers (IPCARx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
IPC Generation Registers (IPCGRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
IPC Acknowledgement Register (IPCARH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Timer Input Selection Register (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Timer Output Selection Register (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Reset Mux Register (RSTMUX0 through RSTMUX3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
C66x CorePac Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
TMS320C6670 L1P Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
TMS320C6670 L1D Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
TMS320C6670 L2 Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Test Load Circuit for AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Input and Output Voltage Reference Levels for AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Rise and Fall Transition Time Voltage Reference Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Board-Level Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
POR-Controlled Power Sequencing — Core Before IO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
POR-Controlled Power Sequencing — IO Before Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
RESETFULL-Controlled Device Initialization — Core Before IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
RESETFULL-Controlled Device Initialization — IO Before Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
SmartReflex 4-Pin VID Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
SmartReflex I2C Interface Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
SmartReflex I2C Interface Transmit Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
TMS320C6670 Interrupt Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
NMI and LRESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
Programmable Range n Start Address Register (PROGn_MPSAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
Programmable Range n End Address Register (PROGn_MPEAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
POR Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
List of Figures
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Figure 7-19
Figure 7-20
Figure 7-21
Figure 7-22
Figure 7-23
Figure 7-24
Figure 7-25
Figure 7-26
Figure 7-27
Figure 7-28
Figure 7-29
Figure 7-30
Figure 7-31
Figure 7-32
Figure 7-33
Figure 7-34
Figure 7-35
Figure 7-36
Figure 7-37
Figure 7-38
Figure 7-39
Figure 7-40
Figure 7-41
Figure 7-42
Figure 7-43
Figure 7-44
Figure 7-45
Figure 7-46
Figure 7-47
Figure 7-48
Figure 7-49
Figure 7-50
Figure 7-51
Figure 7-52
Figure 7-53
Figure 7-54
Figure 7-55
Figure 7-56
Figure 7-57
Figure 7-58
Figure 7-59
Figure 7-60
Figure 7-61
Figure 7-62
Figure 7-63
Figure 7-64
Figure 7-65
Figure 7-66
Figure 8-1
RESETFULL Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Hard-Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Soft-Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Boot Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
Main PLL and PLL Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
PLL Secondary Control Register (SECCTL)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
PLL Controller Divider Register (PLLDIVn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
PLL Controller Clock Align Control Register (ALNCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
PLLDIV Divider Ratio Change Status Register (DCHANGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
SYSCLK Status Register (SYSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
Reset Type Status Register (RSTYPE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
Reset Control Register (RSTCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
Reset Configuration Register (RSTCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
Reset Isolation Register (RSISO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
Main PLL Control Register (MAINPLLCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
Main PLL Transition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
DDR3 PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
DDR3 PLL Control Register (DDR3PLLCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
DDR3 PLL DDRCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
PASS PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
PASS PLL Control Register (PASSPLLCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
PASS PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
I2C Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
I2C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
I2C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
SPI Master Mode Timing Diagrams — Base Timings for 3-Pin Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
SPI Additional Timings for 4-Pin Master Mode with Chip Select Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
HyperLink Station Management Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
HyperLink Station Management Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
HyperLink Station Management Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
UART Receive Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
UART Transmit Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
UART RTS (Request-to-Send Output) – Autoflow Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
MACID1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
MACID2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
MDIO Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
MDIO Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
AIF2 RP1 Frame Synchronization Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
AIF2 RP1 Frame Synchronization Burst Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
AIF2 Physical Layer Synchronization Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
AIF2 Radio Synchronization Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
AIF2 Timer External Frame Event Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
Trace Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
JTAG Test-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
CYP (S–PBGA–N841) Plastic Ball Grid Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
Copyright 2010 Texas Instruments Incorporated
List of Figures
7
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
List of Tables
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 2-5
Table 2-6
Table 2-7
Table 2-8
Table 2-9
Table 2-10
Table 2-11
Table 2-12
Table 2-13
Table 2-14
Table 2-15
Table 2-16
Table 2-17
Table 2-18
Table 3-1
Table 3-2
Table 3-3
Table 3-4
Table 3-5
Table 3-6
Table 3-7
Table 3-8
Table 3-9
Table 3-10
Table 3-11
Table 3-12
Table 3-13
Table 3-14
Table 3-15
Table 3-16
Table 3-17
Table 3-18
Table 3-19
Table 4-1
Table 4-2
Table 4-3
Table 5-1
Table 5-2
Table 5-3
Table 5-4
Table 6-1
Table 6-2
Table 6-3
Table 7-1
Table 7-2
Table 7-3
Table 7-4
Table 7-5
8
List of Tables
Characteristics of the C6670 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
TMS320C6670 Memory Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Boot Mode Pins: Boot Device Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Sleep Configuration Bit Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Ethernet (SGMII) Configuration Bit Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Serial Rapid I/O Configuration Bit Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
PCI Device Configuration Bit Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
BAR Config / PCIe Window Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
I2C Master Mode Device Configuration Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
I2C Passive Mode Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
SPI Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
HyperLink Boot Device Configuration Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
C66x CorePac System PLL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
I/O Functional Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Terminal Functions — Signals and Control by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Terminal Functions — Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Terminal Functions — By Signal Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Terminal Functions — By Ball Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
TMS320C6670 Device Configuration Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Device Status Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Device Configuration Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
JTAG ID Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Reset Status Register (RESET_STAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Boot Complete Register (BOOTCOMPLETE) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Power State Control Register (PWRSTATECTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
NMI Generation Register (NMIGRx) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
IPC Generation Registers (IPCGRx) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
IPC Acknowledgement Registers (IPCARx) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
IPC Generation Registers (IPCGRH) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
IPC Acknowledgement Register (IPCARH) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Timer Input Selection Field Description (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Timer Output Selection Field Description (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Reset Mux Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
CPU/2 Data SCR Connection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
CPU/3 Data SCR Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Available Memory Page Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
CorePac Reset (Global or Local) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
CorePac Revision ID Register (MM_REVID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
CorePac Revision ID Register (MM_REVID) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Board-Level Timing Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Power Supply Rails on TMS320C6670 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
POR-Controlled Power Sequencing — Core Before IO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
POR-Controlled Power Sequencing — IO Before Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
RESETFULL-Controlled Device Initialization — Core Before IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Table 7-6
Table 7-7
Table 7-8
Table 7-9
Table 7-10
Table 7-11
Table 7-12
Table 7-13
Table 7-14
Table 7-15
Table 7-16
Table 7-17
Table 7-18
Table 7-19
Table 7-20
Table 7-21
Table 7-22
Table 7-23
Table 7-24
Table 7-25
Table 7-26
Table 7-27
Table 7-28
Table 7-29
Table 7-30
Table 7-31
Table 7-32
Table 7-33
Table 7-34
Table 7-35
Table 7-36
Table 7-37
Table 7-38
Table 7-39
Table 7-40
Table 7-41
Table 7-42
Table 7-43
Table 7-44
Table 7-45
Table 7-46
Table 7-47
Table 7-48
Table 7-49
Table 7-50
Table 7-51
Table 7-52
Table 7-53
Table 7-54
Table 7-55
Table 7-56
Table 7-57
Table 7-58
Table 7-59
RESETFULL-Controlled Device Initialization — IO Before Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Clock Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
SmartReflex 4-Pin VID Interface Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
SmartReflex I2C Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
SmartReflex I2C Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
EDMA3 Parameter RAM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
TPCC0 Events for C6670 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
TPCC1 Events for C6670 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
TPCC2 Events for C6670 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
TMS320C6670 System Event Mapping — C66x CorePac Primary Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
INTC0 Event Inputs — C66x CorePac Secondary Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
INTC1 Event Inputs (Secondary Events for TPCC1 and TPCC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
INTC2 Event Inputs (Secondary Events for TPCC0 and HyperLink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
INTC0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
INTC1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
INTC2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
IPC Generation Registers (IPCGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
LRESET and NMI Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
NMI and LRESET Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
MPU Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
MPU Memory Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Device Master Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
MPU0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
MPU1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
MPU2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
MPU3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
Configuration Register (CONFIG) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions (MPU0) . . . . . . . . . . . . . . . . . . . . . . . .145
Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions (MPU1) . . . . . . . . . . . . . . . . . . . . . . . .145
Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions (MPU2) . . . . . . . . . . . . . . . . . . . . . . . .146
Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions (MPU3) . . . . . . . . . . . . . . . . . . . . . . . .147
Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions (MPU0). . . . . . . . . . . . . . . . . . . . . . . . .147
Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions (MPU1) . . . . . . . . . . . . . . . . . . . . . . . .148
Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions (MPU2). . . . . . . . . . . . . . . . . . . . . . . . .148
Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions (MPU3) . . . . . . . . . . . . . . . . . . . . . . . .149
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions . . . . . . . . . . . .150
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Reset Values . . . . . . . . . . . . . . . . .151
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
Reset Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
Reset Switching Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
Boot Configuration Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
Main PLL Stabilization, Lock, and Reset Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
PLL Controller Registers (Including Reset Controller). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
PLL Secondary Control Register (SECCTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
PLL Controller Divider Register (PLLDIVn) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
SYSCLK Status Register (SYSTAT) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
Reset Type Status Register (RSTYPE) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
Reset Control Register (RSTCTRL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
Reset Configuration Register (RSTCFG) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
Reset Isolation Register (RSISO) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
Main PLL Control Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
Copyright 2010 Texas Instruments Incorporated
List of Tables
9
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 7-60
Table 7-61
Table 7-62
Table 7-63
Table 7-64
Table 7-65
Table 7-66
Table 7-67
Table 7-68
Table 7-69
Table 7-70
Table 7-71
Table 7-72
Table 7-73
Table 7-74
Table 7-75
Table 7-76
Table 7-77
Table 7-78
Table 7-79
Table 7-80
Table 7-81
Table 7-82
Table 7-83
Table 7-84
Table 7-85
10
www.ti.com
DDR3 PLL Control Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
DDR3 PLL DDRREFCLK(N|P) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
PASS PLL Control Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
PASS PLL Timing Requirments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
I2C Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
I2C Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
SPI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
SPI Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
HyperLink Peripheral Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
HyperLink Peripheral Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
UART Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
UART Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
MACID1 Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
MACID2 Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
MDIO Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
MDIO Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
Timer Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
Timer Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
GPIO Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
GPIO Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
AIF2 Timer Module Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
AIF2 Timer Module Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
Trace Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
JTAG Test Port Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
JTAG Test Port Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
List of Tables
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
1 TMS320C6670 Features
• Multicore Shared Memory Controller (MSMC)
– 2048 KB MSM SRAM Memory Shared by Four DSP
Cores
– Memory Protection Unit for Both MSM SRAM and
DDR3_EMIF
• Hardware Coprocessors
– Two Enhanced Coprocessors for Turbo Decoding
› Supports WCDMA/HSPA/HSPA+/TD-SCDMA,
LTE, and WiMAX
› Supports up to 365 Mbps for LTE and up to
233 Mbps for WCDMA
› Low DSP Overhead – HW Interleaver Table
Generation and CRC Check
– One Enhanced Coprocessor for Turbo Encoding
› Supports up to 643 Mbps for LTE and up to 746
Mbps for WCDMA
– Four Viterbi Decoders
› Supports More Than 38 Mbps @ 40 bit Block Size
– Two Fast Fourier Transform Coprocessors
› 1365 pt FFT in 4.8 μs
• Multicore Navigator
– 8192 Multipurpose Hardware Queues with Queue
Manager
– Packet-Based DMA for Zero-Overhead Transfers
• Network Coprocessors
– Packet Accelerator Enables Support for
› Transport Plane IPsec, GTP-U, SCTP, PDCP
› L2 User Plane PDCP (RoHC, Air Ciphering)
› 1 Gbps Wire Speed Throughput at 1.5M Packets
Per Second
– Security Accelerator Engine Enables Support for
› IPSec, SRTP, 3GPP and WiMAX Air Interface, and
SSL/TLS Security
› ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC,
CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW
3G, SHA-1, SHA-2 (256-bit Hash), MD5
› Up to 2.8 Gbps Encryption Speed
• Four Rake/Search Accelerators (RSA) for
– Chip Rate Processing for WCDMA Rel'99, HSDPA,
and HSDPA+
– Reed-Muller Decoding
• Peripherals
– Six Lane SerDes-Based Antenna Interface (AIF2)
› Operating at up to 6.144 Gbps
› Compliant with OBSAI RP3 and CPRI Standards
for 3G / 4G (WCDMA, LTE TDD, LTE FDD,
TD-SCDMA, and WiMAX)
– Four Lanes of SRIO 2.1
› 5 GBaud Operation Per Lane
› Supports Direct I/O, Message Passing
– Two Lanes PCIe Gen2
› Supports Up To 5 GBaud
– Hyperlink
› Supports Connections to Other KeyStone
Architecture Devices Providing Resource
Scalability
› Supports up to 50 Gbaud
– Ethernet MAC Subsystem (EMAC)
› Two SGMII Ports
› IEEE1588 Support
– 64-Bit DDR3 Interface
– UART Interface
– I2C Interface
– 16 GPIO pins
– SPI Interface
– Semaphore Module
– Eight 64-Bit Timers
– Three On-Chip PLLs
• Commercial Temperature:
– 0°C to 100°C
• Extended Temperature:
– - 40°C to 105°C
Copyright 2010 Texas Instruments Incorporated
ADVANCE INFORMATION
• Four TMS320C66x™ DSP Core Subsystems, Each With
– 1.2 GHz C66x Fixed/Floating-Point DSP Core
› 32 GMacs/Core for Fixed Point @ 1.2 GHz
› 16 GFlops/Core for Floating Point @ 1.2 GHz
– Memory
› 32K Byte L1P Per Core
› 32K Byte L1D Per Core
› 1024K Byte Local L2 Per Core
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
1.1 KeyStone Architecture
TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores
with application specific coprocessors and I/O. KeyStone is the first of its kind that provides adequate internal
bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This is achieved with
four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and
HyperLink.
ADVANCE INFORMATION
Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to
the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate
available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched
central resource to move packets. The Multicore Shared Memory Controller enables processing cores to access
shared memory directly without drawing from TeraNet’s capacity, so packet movement cannot be blocked by
memory access.
HyperLink provides a 50-Gbps chip-level interconnect that allows SoCs to work in tandem. Its low-protocol
overhead and high throughput make Hyperlink an ideal interface for chip-to-chip interconnections. Working with
Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are
running on local resources.
1.2 Device Description
The TMS320C6670 Communications Infrastructure KeyStone SoC is a member of the C66xx SoC family based on
TI's new KeyStone Multicore SoC Architecture designed specifically for high performance wireless infrastructure
applications. The C6670 provides a very high performance macro basestation platform for developing all wireless
standards including WCDMA/HSPA/HSPA+, TD-SCDMA, GSM, TDD-LTE, FDD-LTE, and WiMAX. The C6670
also sets a new standard for clock speed with operating frequencies up to 1.2 GHz.
TI's SoC architecture provides a programmable platform integrating various subsystems (C66x cores, IP network,
radio layers 1 and 2, and transport processing) and uses a queue-based communication system that allows the SoC
resources to operate efficiently and seamlessly. This unique SoC architecture also includes a TeraNet Switch that
enables the wide mix of system elements, from programmable cores to dedicated coprocessors and high speed IO,
to each operate at maximum efficiency with no blocking or stalling.
TI's new C66x core launches a new era of DSP technology by combining fixed point and floating point
computational capability in the processor without sacrificing speed, size, or power consumption. The
raw computational performance is an industry-leading 32 GMACS/core and 16 Gflops/core (@ 1.2 GHz operating
frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x core
incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing. These
enhancements yield tremendous performance improvements in multi-antenna 4.8G signal processing for
algorithms like MIMO and beamforming.
The C6670 contains many wireless basestation coprocessors to offload the bulk of the processing demands of layer 1
and layer 2 base station processing. This keeps the cores free for receiver algorithms and other differentiating
functions. The SoC contains numerous copies of key coprocessors such as the FFTC and TCP3d. The architectural
elements of the SoC (Multicore Navigator) ensure that all the bits are processed without any CPU intervention or
overhead, allowing the system to make optimal use of its resources.
TI's scalable multicore SoC architecture solutions provide developers with a range of software- and
hardware-compatible devices to minimize development time and maximize reuse across all base station platforms
from Femto to Macro.
12
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
The C6670 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to
simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.
1.3 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the TMS320C6670 device.
Functional Block Diagram
C6670
Memory Subsystem
2MB
MSM
SRAM
64-Bit
DDR3 EMIF
ADVANCE INFORMATION
Figure 1-1
MSMC
RSA
Debug & Trace
RSA
´2
Coprocessors
Boot ROM
VCP2
Semaphore
C66x™
CorePac
Power
Management
PLL
32KB L1
P-Cache
´3
´4
TCP3d
32KB L1
D-Cache
´2
TCP3e
1024KB L2 Cache
EDMA
FFTC
´3
4 Cores @ 1.0 GHz / 1.2 GHz
´2
TeraNet
HyperLink
Multicore Navigator
Copyright 2010 Texas Instruments Incorporated
Switch
Ethernet
Switch
´4
SRIO
SGMII
´2
´6
AIF2
SPI
UART
´2
PCIe
I2C
Others
Queue
Manager
Packet
DMA
Security
Accelerator
Packet
Accelerator
Network Coprocessor
13
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
2 Device Overview
2.1 Device Characteristics
Table 2-1 provides an overview of the TMS320C6670 DSP. The table shows significant features of the C6670 device,
including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count.
2.2 CPU (DSP Core) Description
Table 2-1
Characteristics of the C6670 Processor (Part 1 of 2)
HARDWARE FEATURES
ADVANCE INFORMATION
Peripherals
Encoder/Decoder
Coprocessors
Accelerators
1
EDMA3 (16 independent channels) [CPU/2 clock rate]
1
EDMA3 (64 independent channels) [CPU/3 clock rate]
2
High-speed 1×/2x/4× Serial RapidIO Port (4 lanes)
1
Second generation Antenna Interface (AIF2)
1
2
IC
1
SPI
1
PCIe (2 lanes)
1
UART
1
10/100/1000 Ethernet MAC (EMAC)
2
Management Data Input/Output (MDIO)
1
64-Bit Timers (Configurable)
(internal clock source = CPU/6 clock frequency)
Eight 64-bit or Sixteen 32-bit
General-Purpose Input/Output Port (GPIO)
16
VCP2 (clock source = CPU/3 clock frequency)
4
TCP3d (clock source = CPU/2 clock frequency)
2
TCP3e (clock source = CPU/3 clock frequency)
1
FFTC (clock source = CPU/3 clock frequency)
2
Rake/Search Accelerator
4
Packet Accelerator
Security Accelerator
On-Chip Memory
TMS320C6670
DDR3 Memory Controller (64-bit bus width) [1.5 V I/O]
(clock source = DDRREFCLKN|P)
1
(1)
1
Size (Bytes)
6528K
Organization
128KB L1 Program Memory Controller
[SRAM/Cache] 128KB L1 Data Memory Controller
[SRAM/Cache] 4096KB L2 Unified Memory/Cache
2048KB MSM SRAM
128KB L3 ROM
C66x CorePac
Revision ID
CorePac Revision ID Register (address location: 0181 2000h)
See Section 5.6 ‘‘CorePac Revision’’ on page 88.
JTAG BSDL_ID
JTAGID register (address location: 0x02620018)
See Section 3.3.3 ‘‘JTAG ID (JTAGID) Register
Description’’ on page 65
Frequency
MHz
1200 (1.2 GHz) [-1200]
Cycle Time
ns
0.83 ns [-1200]
1000 (1.0 GHz) [-1000]
1 ns [-1000]
Voltage
BGA Package
14
Device Overview
Core (V)
SmartReflex variable supply
I/O (V)
1.0 V, 1.5 V, and 1.8 V
24 mm × 24 mm
841-Pin Flip-Chip Plastic BGA (CYP)
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Table 2-1
Characteristics of the C6670 Processor (Part 2 of 2)
HARDWARE FEATURES
Process Technology
Product Status
(2)
TMS320C6670
μm
0.040 μm
Product Preview (PP), Advance Information (AI),
or Production Data (PD)
AI
End of Table 2-1
The C66x Central Processing Unit (CPU) extends the performance of the C64x+ and C674x CPUs through
enhancements and new features. Many of the new features target increased performance for vector processing. The
C64x+ and C674x CPUs support 2-way SIMD operations for 16-bit data and 4-way SIMD operations for 8-bit data.
On the C66x CPU, the vector processing capability is improved by extending the width of the SIMD instructions.
C66x CPUs can execute instructions that operate on 128-bit vectors. For example the QMPY32 instruction is able
to perform the element-to-element multiplication between two vectors of four 32-bit data each. The C66x CPU also
supports SIMD for floating-point operations. Improved vector processing capability (each instruction can process
multiple data in parallel) combined with the natural instruction level parallelism of C6000 architecture (e.g
execution of up to 8 instructions per cycle) results in a very high level of parallelism that can be exploited by DSP
programmers through the use of TI's optimized C/C++ compiler.
The C66x CPU consists of eight functional units, two register files, and two data paths as shown in Figure 2-1. The
two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The
general-purpose registers can be used for data or can be data address pointers. The data types supported include
packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Multiplies also support 128-bit data.
40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and
the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register). 128-bit data
values are stored in register quadruplets, with the 32 LSBs of data placed in a register that is a multiple of 4 and the
remaining 96 MSBs in the next 3 upper registers.
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction
every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set
of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and
store results from the register file into memory.
Each C66x .M unit can perform one of the following fixed-point operations each clock cycle: four 32 × 32 bit
multiplies, sixteen 16 × 16 bit multiplies, four 16 × 32 bit multiplies, four 8 × 8 bit multiplies, four 8 × 8 bit multiplies
with add operations, and four 16 × 16 multiplies with add/subtract capabilities. There is also support for Galois field
multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require
complex multiplication. Each C66x .M unit can perform one 16 × 16 bit complex multiply with or without rounding
capabilities, two 16 × 16 bit complex multiplies with rounding capability, and a 32 × 32 bit complex multiply with
rounding capability. The C66x can also perform two 16 × 16 bit and one 32 × 32 bit complex multiply instructions
that multiply a complex number with a complex conjugate of another number with rounding capability.
Communication signal processing also requires an extensive use of matrix operations. Each C66x .M unit is capable
of multiplying a [1 × 2] complex vector by a [2 × 2] complex matrix per cycle with or without rounding capability.
A version also exists allowing multiplication of the conjugate of a [1 × 2] vector with a [2 × 2] complex matrix.
Each C66x .M unit also includes IEEE floating-point multiplication operations from the C674x CPU. This includes
one single-precision multiply each cycle and one double precision multiply every 4 cycles. There is also a
mixed-precision multiply that allows multiplication of a single-precision value by a double-precision value and an
operation allowing multiplication of two single-precision numbers resulting in a double-precision number. The
Copyright 2010 Texas Instruments Incorporated
Device Overview
15
ADVANCE INFORMATION
1 The Security Accelerator function is subject to export control and will be enabled only for approved device shipments.
2 ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change
without notice.
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
C66x CPU improves the performance over the C674x double-precision multiplies by adding a instruction allowing
one double-precision multiply per cycle and also reduces the number of delay slots from 10 down to 4. Each C66x
.M unit can also perform one the following floating-point operations each clock cycle: one, two, or four
single-precision multiplies or a complex single-precision multiply.
ADVANCE INFORMATION
The .L and .S units can now support up to 64-bit operands. This allows for new versions of many of the arithmetic,
logical, and data packing instructions to allow for more parallel operations per cycle. Additional instructions were
added yielding performance enhancements of the floating point addition and subtraction instructions, including the
ability to perform one double precision addition or subtraction per cycle. Conversion to/from integer and
single-precision values can now be done on both .L and .S units on the C66x. Also, by taking advantage of the larger
operands, instructions were also added to double the number of these conversions that can be done. The .L unit also
has additional instructions for logical AND and OR instructions, as well as, 90 degree or 270 degree rotation of
complex numbers (up to two per cycle). Instructions have also been added that allow for the computing the
conjugate of a complex number.
The MFENCE instruction is a new instruction introduced on the C66x DSP. This instruction will create a CPU stall
until the completion of all the CPU-triggered memory transactions, including:
•
•
•
•
•
•
Cache line fills
Writes from L1D to L2 or from the CorePac to MSMC and/or other system endpoints
Victim write backs
Block or global coherence operations
Cache mode changes
Outstanding XMC prefetch requests
This is useful as a simple mechanism for programs to wait for these requests to reach their endpoint. It also provides
ordering guarantees for writes arriving at a single endpoint via multiple paths, multiprocessor algorithms that
depend on ordering, and manual coherence operations.
For more details on the C66x CPU and its enhancements over the C64x+ and C674x architectures, see the following
documents ( ‘‘Related Documentation from Texas Instruments’’ on page 59):
• C66x CPU and Instruction Set Reference Guide
• C66x DSP Cache User Guide
• C66x CorePac User Guide
16
Device Overview
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Figure 2-1 shows the DSP core functional units and data paths.
Figure 2-1
TMS320C6670 CPU (DSP Core) Data Paths
Note:
Default bus width
is 64 bits
(i.e. a register pair)
src1
.L1
Register
File A
(A0, A1, A2,
...A31)
src2
dst
ST1
src1
src2
ADVANCE INFORMATION
.S1
dst
src1
src1_hi
Data Path A
.M1
src2
src2_hi
dst2
dst1
LD1
32
src1
DA1
32
.D1
dst
32
src2
32
32
2´
1´
src2
DA2
32
.D2
dst
src1
Register
File B
(B0, B1, B2,
...B31)
32
32
32
32
32
LD2
dst1
dst2
src2_hi
.M2
src2
src1_hi
src1
Data Path B
dst
.S2
src2
src1
ST2
dst
.L2
src2
src1
32
66xx
Copyright 2010 Texas Instruments Incorporated
Control
Register
32
Device Overview
17
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
2.3 Memory Map Summary
Table 2-2 shows the memory map address ranges of the TMS320C6670 device.
Table 2-2
TMS320C6670 Memory Map Summary (Part 1 of 9)
Logical 32 bit Address
Physical 36 bit Address
Start
End
Start
End
Bytes
Description
0000 0000
007F FFFF
0 0000 0000
0 007F FFFF
8M
Reserved
0080 0000
008F FFFF
0 0080 0000
0 008F FFFF
1M
L2 SRAM
0090 0000
00DF FFFF
0 0090 0000
0 00DF FFFF
5M
Reserved
ADVANCE INFORMATION
00E00000
00E0 7FFF
0 00E00000
0 00E0 7FFF
32K
L1P SRAM
00E08000
00EF FFFF
0 00E08000
0 00EF FFFF
1M-32K
Reserved
00F00000
00F0 7FFF
0 00F00000
0 00F0 7FFF
32K
L1D SRAM
00F08000
00FF FFFF
0 00F08000
0 00FF FFFF
1M-32K
Reserved
0100 0000
01BF FFFF
0 0100 0000
0 01BF FFFF
12 M
C66x CorePac Registers
01C0 0000
01CF FFFF
0 01C0 0000
0 01CF FFFF
1M
Reserved
01D0 0000
01D0 007F
0 01D0 0000
0 01D0 007F
128
Tracer 0
01D0 0080
01D0 7FFF
0 01D0 0080
0 01D0 7FFF
32K-128
Reserved
01D0 8000
01D0 807F
0 01D0 8000
0 01D0 807F
128
Tracer 1
01D0 8080
01D0 FFFF
0 01D0 8080
0 01D0 FFFF
32K-128
Reserved
01D1 0000
01D1 007F
0 01D1 0000
0 01D1 007F
128
Tracer 2
01D1 0080
01D1 7FFF
0 01D1 0080
0 01D1 7FFF
32K-128
Reserved
01D1 8000
01D1 807F
0 01D1 8000
0 01D1 807F
128
Tracer 3
01D1 8080
01D1 FFFF
0 01D1 8080
0 01D1 FFFF
32K-128
Reserved
01D2 0000
01D2 007F
0 01D2 0000
0 01D2 007F
128
Tracer 4
01D2 0080
01D2 7FFF
0 01D2 0080
0 01D2 7FFF
32K-128
Reserved
01D2 8000
01D2 807F
0 01D2 8000
0 01D2 807F
128
Tracer 5
01D2 8080
01D2 FFFF
0 01D2 8080
0 01D2 FFFF
32K-128
Reserved
01D3 0000
01D3 007F
0 01D3 0000
0 01D3 007F
128
Tracer 6
01D3 0080
01D3 7FFF
0 01D3 0080
0 01D3 7FFF
32K-128
Reserved
01D3 8000
01D3 807F
0 01D3 8000
0 01D3 807F
128
Tracer 7
01D3 8080
01D3 FFFF
0 01D3 8080
0 01D3 FFFF
32K-128
Reserved
01D4 0000
01D4 007F
0 01D4 0000
0 01D4 007F
128
Tracer 8
01D4 0080
01D4 7FFF
0 01D4 0080
0 01D4 7FFF
32K-128
Reserved
01D4 8000
01D4 807F
0 01D4 8000
0 01D4 807F
128
Tracer 9
01D4 8080
01D4 FFFF
0 01D4 8080
0 01D4 FFFF
32K-128
Reserved
01D5 0000
01D5 007F
0 01D5 0000
0 01D5 007F
128
Tracer 10
01D5 0080
01D5 7FFF
0 01D5 0080
0 01D5 7FFF
32K-128
Reserved
01D5 8000
01D5 807F
0 01D5 8000
0 01D5 807F
128
Tracer 11
01D5 8080
01D5 FFFF
0 01D5 8080
0 01D5 FFFF
32K-128
Reserved
01D6 0000
01D6 007F
0 01D6 0000
0 01D6 007F
128
Tracer 12
01D6 0080
01D6 7FFF
0 01D6 0080
0 01D6 7FFF
32K-128
Reserved
01D6 8000
01D6 807F
0 01D6 8000
0 01D6 807F
128
Tracer 13
01D6 8080
01D6 FFFF
0 01D6 8080
0 01D6 FFFF
32K-128
Reserved
01D7 0000
01D7 007F
0 01D7 0000
0 01D7 007F
128
Tracer 14
01D7 0080
01D7 7FFF
0 01D7 0080
0 01D7 7FFF
32K-128
Reserved
01D7 8000
01D7 807F
0 01D7 8000
0 01D7 807F
128
Tracer 15
18
Device Overview
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
TMS320C6670 Memory Map Summary (Part 2 of 9)
Logical 32 bit Address
Start
End
Physical 36 bit Address
Start
End
Bytes
Description
01D7 8080
01D7 FFFF
0 01D7 8080
0 01D7 FFFF
32K-128
Reserved
01D8 0000
01D8 007F
0 01D8 0000
0 01D8 007F
128
Reserved
01D8 0080
01D8 7FFF
0 01D8 0080
0 01D8 7FFF
32K-128
Reserved
01D8 8000
01DF FFFF
0 01D8 8000
0 01DF FFFF
480K
Reserved
01E0 0000
01E3 FFFF
0 01E0 0000
0 01E3 FFFF
256K
Reserved
01E4 0000
01E7 FFFF
0 01E4 0000
0 01E7 FFFF
256K
Reserved
01E8 0000
01EB FFFF
0 01E8 0000
0 01EB FFFF
256K
Reserved
01EC 0000
01EF FFFF
0 01EC 0000
0 01EF FFFF
256K
Reserved
01F0 0000
01F7 FFFF
0 01F0 0000
0 01F7 FFFF
512k
AIF2 Control
01F80000
01F8FFFF
01F80000
01F8FFFF
64K
Reserved
01F90000
01F9FFFF
01F90000
01F9FFFF
64K
Reserved
01FA0000
01FBFFFF
01FA0000
01FBFFFF
128K
Reserved
01FC0000
01FDFFFF
01FC0000
01FDFFFF
128K
Reserved
01FE 0000
01FF FFFF
0 01FE 0000
0 01FF FFFF
128k
Reserved
0200 0000
0208 FFFF
0 0200 0000
0 0208 FFFF
576K
Packet Accelerator Configuration
0209 0000
020B FFFF
0 0209 0000
0 020B FFFF
192K
Ethernet Switch Subsystem Configuration
020C 0000
020F FFFF
0 020C 0000
0 020F FFFF
256K
Security Accelerator Subsystem Configuration
02100000
0210FFFF
02100000
0210FFFF
64K
Reserved
02110000
0211FFFF
02110000
0211FFFF
64K
Reserved
02120000
0213FFFF
02120000
0213FFFF
128K
Reserved
02140000
0215FFFF
02140000
0215FFFF
128K
Reserved
0216 0000
0217 FFFF
0 0216 0000
0 0217 FFFF
128K
Reserved
02180000
02187FFF
02180000
02187FFF
32k
Reserved
02188000
0218FFFF
02188000
0218FFFF
32k
Reserved
02190000
0219FFFF
02190000
0219FFFF
64k
Reserved
021A0000
021AFFFF
021A0000
021AFFFF
64K
Reserved
021B 0000
021B FFFF
0 021B 0000
0 021B FFFF
64K
Reserved
021C 0000
021C 03FF
0 021C 0000
0 021C 03FF
1K
TCP3d-A
021C 0400
021C 7FFF
0 021C 0400
0 021C 7FFF
31K
Reserved
021C 8000
021C 83FF
0 021C 8000
0 021C 83FF
1K
TCP3d-B
021C 8400
021C FFFF
0 021C 8400
0 021C FFFF
31K
Reserved
021D 0000
021D 00FF
0 021D 0000
0 021D 00FF
256
VCP2_A
021D 0100
021D 3FFF
0 021D 0100
0 021D 3FFF
16K
Reserved
021D 4000
021D 40FF
0 021D 4000
0 021D 40FF
256
VCP2_B
021D 4100
021D 7FFF
0 021D 4100
0 021D 7FFF
16K
Reserved
021D 8000
021D 80FF
0 021D 8000
0 021D 80FF
256
VCP2_C
021D 8100
021D BFFF
0 021D 8100
0 021D BFFF
16K
Reserved
021D C000
021D C0FF
0 021D C000
0 021D C0FF
256
VCP2_D
021D C100
021D FFFF
0 021D C100
0 021D FFFF
16K
Reserved
021E 0000
021E 0FFF
0 021E 0000
0 021E 0FFF
4K
TCP3e
021E 1000
021E FFFF
0 021E 1000
0 021E FFFF
60k
Reserved
021F 0000
021F 07FF
0 021F 0000
0 021F 07FF
2K
FFTC-A Configuration
021F 0800
021F 3FFF
0 021F 0800
0 021F 3FFF
14K
Reserved
Copyright 2010 Texas Instruments Incorporated
Device Overview
ADVANCE INFORMATION
Table 2-2
19
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 2-2
Logical 32 bit Address
Start
www.ti.com
TMS320C6670 Memory Map Summary (Part 3 of 9)
End
Physical 36 bit Address
Start
End
Bytes
Description
021F 4000
021F 47FF
0 021F 4000
0 021F 47FF
2K
FFTC-B Configuration
021F 4800
021F FFFF
0 021F 4800
0 021F FFFF
46K
Reserved
0220 0000
0220 007F
0 0220 0000
0 0220 007F
128
Timer0
0220 0080
0220 FFFF
0 0220 0080
0 0220 FFFF
64K-128
Reserved
0221 0000
0221 007F
0 0221 0000
0 0221 007F
128
Timer1
0221 0080
0221 FFFF
0 0221 0080
0 0221 FFFF
64K-128
Reserved
ADVANCE INFORMATION
0222 0000
0222 007F
0 0222 0000
0 0222 007F
128
Timer2
0222 0080
0222 FFFF
0 0222 0080
0 0222 FFFF
64K-128
Reserved
0223 0000
0223 007F
0 0223 0000
0 0223 007F
128
Timer3
0223 0080
0223 FFFF
0 0223 0080
0 0223 FFFF
64K-128
Reserved
0224 0000
0224 007F
0 0224 0000
0 0224 007F
128
Timer4
0224 0080
0224 FFFF
0 0224 0080
0 0224 FFFF
64K-128
Reserved
0225 0000
0225 007F
0 0225 0000
0 0225 007F
128
Timer5
0225 0080
0225 FFFF
0 0225 0080
0 0225 FFFF
64K-128
Reserved
0226 0000
0226 007F
0 0226 0000
0 0226 007F
128
Timer6
0226 0080
0226 FFFF
0 0226 0080
0 0226 FFFF
64K-128
Reserved
0227 0000
0227 007F
0 0227 0000
0 0227 007F
128
Timer7
0227 0080
0227 FFFF
0 0227 0080
0 0227 FFFF
64K-128
Reserved
0228 0000
0228 007F
0 0228 0000
0 0228 007F
128
Reserved
0228 0080
0228 FFFF
0 0228 0080
0 0228 FFFF
64K-128
Reserved
0229 0000
0229 007F
0 0229 0000
0 0229 007F
128
Reserved
0229 0080
0229 FFFF
0 0229 0080
0 0229 FFFF
64K-128
Reserved
022A 0000
022A 007F
0 022A 0000
0 022A 007F
128
Reserved
022A 0080
022A FFFF
0 022A 0080
0 022A FFFF
64K-128
Reserved
022B 0000
022B 007F
0 022B 0000
0 022B 007F
128
Reserved
022B 0080
022B FFFF
0 022B 0080
0 022B FFFF
64K-128
Reserved
022C 0000
022C 007F
0 022C 0000
0 022C 007F
128
Reserved
022C 0080
022C FFFF
0 022C 0080
0 022C FFFF
64K-128
Reserved
022D 0000
022D 007F
0 022D 0000
0 022D 007F
128
Reserved
022D 0080
022D FFFF
0 022D 0080
0 022D FFFF
64K-128
Reserved
022E 0000
022E 007F
0 022E 0000
0 022E 007F
128
Reserved
022E 0080
022E FFFF
0 022E 0080
0 022E FFFF
64K-128
Reserved
022F 0000
022F 007F
0 022F 0000
0 022F 007F
128
Reserved
022F 0080
022F FFFF
0 022F 0080
0 022F FFFF
64K-128
Reserved
0230 0000
0230 FFFF
0 0230 0000
0 0230 FFFF
64K
Reserved
0231 0000
0231 01FF
0 0231 0000
0 0231 01FF
512
PLL Controller
0231 0200
0231 FFFF
0 0231 0200
0 0231 FFFF
64K-512
Reserved
0232 0000
0232 00FF
0 0232 0000
0 0232 00FF
256
GPIO
0232 0100
0232 FFFF
0 0232 0100
0 0232 FFFF
64K-256
Reserved
0233 0000
0233 03FF
0 0233 0000
0 0233 03FF
1K
SmartReflex
0233 0400
0233 FFFF
0 0233 0400
0 0233 FFFF
63K
Reserved
0234 0000
0234 FFFF
0 0234 0000
0 0234 FFFF
64K
Reserved
0235 0000
0235 0FFF
0 0235 0000
0 0235 0FFF
4K
Power Sleep Controller
20
Device Overview
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
TMS320C6670 Memory Map Summary (Part 4 of 9)
Logical 32 bit Address
Physical 36 bit Address
Start
End
Start
End
Bytes
Description
0235 1000
0235 FFFF
0 0235 1000
0 0235 FFFF
64K-4K
Reserved
0236 0000
0236 03FF
0 0236 0000
0 0236 03FF
1K
Memory Protection Unit (MPU) 0
0236 0400
0236 7FFF
0 0236 0400
0 0236 7FFF
31K
Reserved
0236 8000
0236 83FF
0 0236 8000
0 0236 83FF
1K
Memory Protection Unit (MPU) 1
0236 8400
0236 FFFF
0 0236 8400
0 0236 FFFF
31K
Reserved
0237 0000
0237 03FF
0 0237 0000
0 0237 03FF
1K
Memory Protection Unit (MPU) 2
0237 0400
0237 7FFF
0 0237 0400
0 0237 7FFF
31K
Reserved
0237 8000
0237 83FF
0 0237 8000
0 0237 83FF
1K
Memory Protection Unit (MPU) 3
0237 8400
0237 FFFF
0 0237 8400
0 0237 FFFF
31K
Reserved
0238 0000
0238 03FF
0 0238 0000
0 0238 03FF
1K
Reserved
0238 0400
023F FFFF
0 0238 0400
0 023F FFFF
511K
Reserved
0240 0000
0243 FFFF
0 0240 0000
0 0243 FFFF
256K
Reserved
0244 0000
0244 3FFF
0 0244 0000
0 0244 3FFF
16K
DSP Trace Formatter 0
0244 4000
0244 FFFF
0 0244 4000
0 0244 FFFF
48K
Reserved
0245 0000
0245 3FFF
0 0245 0000
0 0245 3FFF
16K
DSP Trace Formatter 1
0245 4000
0245 FFFF
0 0245 4000
0 0245 FFFF
48K
Reserved
0246 0000
0246 3FFF
0 0246 0000
0 0246 3FFF
16K
DSP Trace Formatter 2
0246 4000
0246 FFFF
0 0246 4000
0 0246 FFFF
48K
Reserved
0247 0000
0247 3FFF
0 0247 0000
0 0247 3FFF
16K
DSP Trace Formatter 3
0247 4000
0247 FFFF
0 0247 4000
0 0247 FFFF
48K
Reserved
0248 0000
0248 3FFF
0 0248 0000
0 0248 3FFF
16K
Reserved
0248 4000
0248 FFFF
0 0248 4000
0 0248 FFFF
48K
Reserved
0249 0000
0249 3FFF
0 0249 0000
0 0249 3FFF
16K
Reserved
0249 4000
0249 FFFF
0 0249 4000
0 0249 FFFF
48K
Reserved
024A 0000
024A 3FFF
0 024A 0000
0 024A 3FFF
16K
Reserved
024A 4000
024A FFFF
0 024A 4000
0 024A FFFF
48K
Reserved
024B 0000
024B 3FFF
0 024B 0000
0 024B 3FFF
16K
Reserved
024B 4000
024B FFFF
0 024B 4000
0 024B FFFF
48K
Reserved
024C 0000
024C 01FF
0 024C 0000
0 024C 01FF
512
Reserved
024C 0200
024C 03FF
0 024C 0200
0 024C 03FF
1K-512
Reserved
024C 0400
024C 07FF
0 024C 0400
0 024C 07FF
1K
Reserved
024C 0800
024C FFFF
0 024C 0800
0 024C FFFF
62K
Reserved
024D 0000
024F FFFF
0 024D 0000
0 024F FFFF
192K
Reserved
0250 0000
0250 007F
0 0250 0000
0 0250 007F
128
Reserved
0250 0080
0250 7FFF
0 0250 0080
0 0250 7FFF
32K-128
Reserved
0250 8000
0250 FFFF
0 0250 8000
0 0250 FFFF
32K
Reserved
0251 0000
0251 FFFF
0 0251 0000
0 0251 FFFF
64K
Reserved
0252 0000
0252 03FF
0 0252 0000
0 0252 03FF
1K
Reserved
0252 0400
0252 FFFF
0 0252 0400
0 0252 FFFF
64K-1K
Reserved
0253 0000
0253 007F
0 0253 0000
0 0253 007F
128
I2C Data & Control
0253 0080
0253 FFFF
0 0253 0080
0 0253 FFFF
64K-128
Reserved
0254 0000
0254 003F
0 0254 0000
0 0254 003F
64
UART
02540 400
0254 FFFF
0 02540 400
0 0254 FFFF
64K-64
Reserved
Copyright 2010 Texas Instruments Incorporated
ADVANCE INFORMATION
Table 2-2
Device Overview
21
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 2-2
www.ti.com
TMS320C6670 Memory Map Summary (Part 5 of 9)
Logical 32 bit Address
Start
End
0255 0000
0258 0000
Physical 36 bit Address
Start
End
ADVANCE INFORMATION
Bytes
Description
0257 FFFF
0 0255 0000
025B FFFF
0 0258 0000
0 0257 FFFF
192K
Reserved
0 025B FFFF
256K
Reserved
025C 0000
025F FFFF
0260 0000
0260 1FFF
0 025C 0000
0 025F FFFF
256K
Reserved
0 0260 0000
0 0260 1FFF
8K
Secondary Interrupt Contoller (INTC) 0
0260 2000
0260 4000
0260 3FFF
0 0260 2000
0 0260 3FFF
8K
Reserved
0260 5FFF
0 0260 4000
0 0260 5FFF
8K
Secondary Interrupt Contoller (INTC) 1
0260 6000
0260 7FFF
0 0260 6000
0 0260 7FFF
8K
Reserved
0260 8000
0260 9FFF
0 0260 8000
0 0260 9FFF
8K
Secondary Interrupt Contoller (INTC) 2
0260 A000
0260 BFFF
0 0260 A000
0 0260 BFFF
8K
Reserved
0260 C000
0260 DFFF
0 0260 C000
0 0260 DFFF
8K
Reserved
0260 E000
0260 FFFF
0 0260 E000
0 0260 FFFF
8K
Reserved
0261 0000
0261 FFFF
0 0261 0000
0 0261 FFFF
64K
Reserved
0262 0000
0262 03FF
0 0262 0000
0 0262 03FF
1K
Chip-Level Registers
0262 0400
0262 FFFF
0 0262 0400
0 0262 FFFF
63K
Reserved
0263 0000
0263 FFFF
0 0263 0000
0 0263 FFFF
64K
Reserved
0264 0000
0264 07FF
0 0264 0000
0 0264 07FF
2K
Semaphore
0264 0800
0264 FFFF
0 0264 0800
0 0264 FFFF
64K-2K
Reserved
0265 0000
026F FFFF
0 0265 0000
0 026F FFFF
704K
Reserved
0270 0000
0270 7FFF
0 0270 0000
0 0270 7FFF
32K
EDMA Channel Controller (TPCC) 0
0270 8000
0271 FFFF
0 0270 8000
0 0271 FFFF
96K
Reserved
0272 0000
0272 7FFF
0 0272 0000
0 0272 7FFF
32K
EDMA Channel Controller (TPCC) 1
0272 8000
0273 FFFF
0 0272 8000
0 0273 FFFF
96K
Reserved
02740000
0274 7FFF
0 02740000
0 0274 7FFF
32K
EDMA Channel Controller (TPCC) 2
0274 8000
0275 FFFF
0 0274 8000
0 0275 FFFF
96K
Reserved
0276 0000
0276 03FF
0 0276 0000
0 0276 03FF
1K
EDMA TPCC0 Transfer Controller (TPTC) 0
0276 0400
0276 7FFF
0 0276 0400
0 0276 7FFF
31K
Reserved
0276 8000
0276 83FF
0 0276 8000
0 0276 83FF
1K
EDMA TPCC0 Transfer Controller (TPTC) 1
0276 8400
0276 FFFF
0 0276 8400
0 0276 FFFF
31K
Reserved
0277 0000
0277 03FF
0 0277 0000
0 0277 03FF
1K
EDMA TPCC1 Transfer Controller (TPTC) 0
0277 0400
0277 7FFF
0 0277 0400
0 0277 7FFF
31K
Reserved
0277 8000
0277 83FF
0 0277 8000
0 0277 83FF
1K
EDMA TPCC1 Transfer Controller (TPTC) 1
0278 0400
0277 FFFF
0 0278 0400
0 0277 FFFF
31K
Reserved
0278 0000
0278 03FF
0 0278 0000
0 0278 03FF
1K
EDMA TPCC1 Transfer Controller (TPTC) 2
0278 0400
0278 7FFF
0 0278 0400
0 0278 7FFF
31K
Reserved
0278 8000
0278 83FF
0 0278 8000
0 0278 83FF
1K
EDMA TPCC1 Transfer Controller (TPTC) 3
0278 8400
0278 FFFF
0 0278 8400
0 0278 FFFF
31K
Reserved
0279 0000
0279 03FF
0 0279 0000
0 0279 03FF
1K
EDMA TPCC2 Transfer Controller (TPTC) 0
0279 0400
0279 7FFF
0 0279 0400
0 0279 7FFF
31K
Reserved
0279 8000
0279 83FF
0 0279 8000
0 0279 83FF
1K
EDMA TPCC2 Transfer Controller (TPTC) 1
0279 8400
0279 FFFF
0 0279 8400
0 0279 FFFF
31K
Reserved
027A 0000
027A 03FF
0 027A 0000
0 027A 03FF
1K
EDMA TPCC2 Transfer Controller (TPTC) 2
027A 0400
027A 7FFF
0 027A 0400
0 027A 7FFF
31K
Reserved
027A 8000
027A 83FF
0 027A 8000
0 027A 83FF
1K
EDMA TPCC2 Transfer Controller (TPTC) 3
22
Device Overview
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
TMS320C6670 Memory Map Summary (Part 6 of 9)
Logical 32 bit Address
Start
End
Physical 36 bit Address
Start
End
Bytes
Description
027A 8400
027A FFFF
0 027A 8400
0 027A FFFF
31K
Reserved
027B 0000
027B FFFF
0 027B 0000
0 027B FFFF
64K
Reserved
027C 0000
027C FFFF
0 027C 0000
0 027C FFFF
64k
Reserved
027D 0000
027D 3FFF
0 027D 0000
0 027D 3FFF
16k
TI Embedded Trace Buffer (TETB) - Core 0
027D 4000
027D FFFF
0 027D 4000
0 027D FFFF
48k
Reserved
027E 0000
027E 3FFF
0 027E 0000
0 027E 3FFF
16k
TI Embedded Trace Buffer (TETB) - Core 1
027E 4000
027E FFFF
0 027E 4000
0 027E FFFF
48k
Reserved
027F 0000
027F 3FFF
0 027F 0000
0 027F 3FFF
16k
TI Embedded Trace Buffer (TETB) - Core 2
027F 4000
027F FFFF
0 027F 4000
0 027F FFFF
48k
Reserved
0280 0000
0280 3FFF
0 0280 0000
0 0280 3FFF
16k
TI Embedded Trace Buffer (TETB) - Core 3
0280 4000
0280 FFFF
0 0280 4000
0 0280 FFFF
48k
Reserved
0281 0000
0281 3FFF
0 0281 0000
0 0281 3FFF
16k
Reserved
0281 4000
0281 FFFF
0 0281 4000
0 0281 FFFF
48k
Reserved
0282 0000
0282 3FFF
0 0282 0000
0 0282 3FFF
16k
Reserved
0282 4000
0282 FFFF
0 0282 4000
0 0282 FFFF
48k
Reserved
0283 0000
0283 3FFF
0 0283 0000
0 0283 3FFF
16k
Reserved
0283 4000
0283 FFFF
0 0283 4000
0 0283 FFFF
48k
Reserved
0284 0000
0284 3FFF
0 0284 0000
0 0284 3FFF
16k
Reserved
0284 4000
0284 FFFF
0 0284 4000
0 0284 FFFF
48k
Reserved
0285 0000
0285 7FFF
0 0285 0000
0 0285 7FFF
32k
TI Embedded Trace Buffer (TETB) - System
0285 8000
0285 FFFF
0 0285 8000
0 0285 FFFF
32k
Reserved
0286 0000
028F FFFF
0 0286 0000
0 028F FFFF
640K
Reserved
0290 0000
0290 7FFF
0 0290 0000
0 0290 7FFF
32K
Serial RapidIO Configuration
0290 8000
029F FFFF
0 0290 8000
0 029F FFFF
1M-32k
Reserved
02A0 0000
02AF FFFF
0 02A0 0000
0 02AF FFFF
1M
Queue Manager Subsystem Configuration
02B0 0000
02BF FFFF
0 02B0 0000
0 02BF FFFF
1M
Reserved
02C0 0000
02FF FFFF
0 02C0 0000
0 02FF FFFF
4M
Reserved
03000 000
07FF FFFF
0 03000 000
0 07FF FFFF
80M
Reserved
0800 0000
0800 FFFF
0 0800 0000
0 0800 FFFF
64k
Extended Memory Controller (XMC) Configuration
0801 0000
0BBF FFFF
0 0801 0000
0 0BBF FFFF
60M-64k
Reserved
0BC0 0000
0BCF FFFF
0 0BC0 0000
0 0BCF FFFF
1M
Multicore Shared Memory Controller (MSMC) Config
0BD0 0000
0BFF FFFF
0 0BD0 0000
0 0BFF FFFF
3M
Reserved
0C00 0000
0C1F FFFF
0 0C00 0000
0 0C1F FFFF
2M
Multicore Shared Memory (MSM)
0C20 0000
0C3F FFFF
0 0C20 0000
0 0C3F FFFF
2M
Reserved
0C40 0000
0FFF FFFF
0 0C40 0000
0 0FFF FFFF
60 M
Reserved
1000 0000
107F FFFF
0 1000 0000
0 107F FFFF
8M
Reserved
1080 0000
108F FFFF
0 1080 0000
0 108F FFFF
1M
Core 0 L2 SRAM
1090 0000
10DF FFFF
0 1090 0000
0 10DF FFFF
5M
Reserved
10E0 0000
10E0 7FFF
0 10E0 0000
0 10E0 7FFF
32k
Core 0 L1P SRAM
10E0 8000
10EF FFFF
0 10E0 8000
0 10EF FFFF
1M-32K
Reserved
10F0 0000
10F0 7FFF
0 10F0 0000
0 10F0 7FFF
32k
Core 0 L1D SRAM
10F0 8000
117F FFFF
0 10F0 8000
0 117F FFFF
9M-32k
Reserved
1180 0000
118F FFFF
0 1180 0000
0 118F FFFF
1M
Core 1 L2 SRAM
Copyright 2010 Texas Instruments Incorporated
Device Overview
ADVANCE INFORMATION
Table 2-2
23
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 2-2
www.ti.com
TMS320C6670 Memory Map Summary (Part 7 of 9)
Logical 32 bit Address
Physical 36 bit Address
Start
End
Start
End
Bytes
Description
1190 0000
11DF FFFF
0 1190 0000
0 11DF FFFF
5M
Reserved
11E0 0000
11E0 7FFF
0 11E0 0000
0 11E0 7FFF
32k
Core 1 L1P SRAM
11E0 8000
11EF FFFF
0 11E0 8000
0 11EF FFFF
1M-32K
Reserved
11F0 0000
11F0 7FFF
0 11F0 0000
0 11F0 7FFF
32k
Core 1 L1D SRAM
ADVANCE INFORMATION
11F0 8000
127F FFFF
0 11F0 8000
0 127F FFFF
9M-32k
Reserved
1280 0000
128F FFFF
0 1280 0000
0 128F FFFF
1M
Core 2 L2 SRAM
1290 0000
12DF FFFF
0 1290 0000
0 12DF FFFF
5M
Reserved
12E0 0000
12E0 7FFF
0 12E0 0000
0 12E0 7FFF
32k
Core 2 L1P SRAM
12E0 8000
12EF FFFF
0 12E0 8000
0 12EF FFFF
1M-32K
Reserved
12F0 0000
12F0 7FFF
0 12F0 0000
0 12F0 7FFF
32k
Core 2 L1D SRAM
12F0 8000
137F FFFF
0 12F0 8000
0 137F FFFF
9M-32k
Reserved
1380 0000
1388 FFFF
0 1380 0000
0 1388 FFFF
1M
Core 3 L2 SRAM
1390 0000
13DF FFFF
0 1390 0000
0 13DF FFFF
5M
Reserved
13E0 0000
13E0 7FFF
0 13E0 0000
0 13E0 7FFF
32k
Core 3 L1P SRAM
13E0 8000
13EF FFFF
0 13E0 8000
0 13EF FFFF
1M-32K
Reserved
13F0 0000
13F0 7FFF
0 13F0 0000
0 13F0 7FFF
32k
Core 3 L1D SRAM
13F0 8000
147F FFFF
0 13F0 8000
0 147F FFFF
9M-32k
Reserved
1480 0000
1487 FFFF
0 1480 0000
0 1487 FFFF
512K
Reserved
1488 0000
148F FFFF
0 1488 0000
0 148F FFFF
512K
Reserved
1490 0000
14DF FFFF
0 1490 0000
0 14DF FFFF
5M
Reserved
14E0 0000
14E0 7FFF
0 14E0 0000
0 14E0 7FFF
32k
Reserved
14E0 8000
14EF FFFF
0 14E0 8000
0 14EF FFFF
1M-32K
Reserved
14F0 0000
14F0 7FFF
0 14F0 0000
0 14F0 7FFF
32k
Reserved
14F0 8000
157F FFFF
0 14F0 8000
0 157F FFFF
9M-32k
Reserved
1580 0000
1587 FFFF
0 1580 0000
0 1587 FFFF
512K
Reserved
1588 0000
158F FFFF
0 1588 0000
0 158F FFFF
512K
Reserved
1590 0000
15DF FFFF
0 1590 0000
0 15DF FFFF
5M
Reserved
15E0 0000
15E0 7FFF
0 15E0 0000
0 15E0 7FFF
32k
Reserved
15E0 8000
15EF FFFF
0 15E0 8000
0 15EF FFFF
1M-32K
Reserved
15F0 0000
15F0 7FFF
0 15F0 0000
0 15F0 7FFF
32k
Reserved
15F0 8000
167F FFFF
0 15F0 8000
0 167F FFFF
9M-32k
Reserved
1680 0000
1687 FFFF
0 1680 0000
0 1687 FFFF
512K
Reserved
1688 0000
168F FFFF
0 1688 0000
0 168F FFFF
512K
Reserved
1690 0000
16DF FFFF
0 1690 0000
0 16DF FFFF
5M
Reserved
16E0 0000
16E0 7FFF
0 16E0 0000
0 16E0 7FFF
32k
Reserved
16E0 8000
16EF FFFF
0 16E0 8000
0 16EF FFFF
1M-32K
Reserved
16F0 0000
16F0 7FFF
0 16F0 0000
0 16F0 7FFF
32k
Reserved
16F0 8000
177F FFFF
0 16F0 8000
0 177F FFFF
9M-32k
Reserved
1780 0000
1787 FFFF
0 1780 0000
0 1787 FFFF
512K
Reserved
1788 0000
178F FFFF
0 1788 0000
0 178F FFFF
512K
Reserved
1790 0000
17DF FFFF
0 1790 0000
0 17DF FFFF
5M
Reserved
17E0 0000
17E0 7FFF
0 17E0 0000
0 17E0 7FFF
32k
Reserved
17E0 8000
17EF FFFF
0 17E0 8000
0 17EF FFFF
1M-32K
Reserved
24
Device Overview
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
TMS320C6670 Memory Map Summary (Part 8 of 9)
Logical 32 bit Address
Physical 36 bit Address
Start
End
Start
End
Bytes
Description
17F0 0000
17F0 7FFF
17F0 8000
1FFF FFFF
0 17F0 0000
0 17F0 7FFF
32k
Reserved
0 17F0 8000
0 1FFF FFFF
129M-32k
Reserved
2000 0000
200F FFFF
2010 0000
201F FFFF
0 2000 0000
0 200F FFFF
1M
System Trace Manager (STM) Configuration
0 2010 0000
0 201F FFFF
1M
Reserved
20200000
205FFFFF
20200000
205FFFFF
4M
Reserved
2060 0000
206F FFFF
0 2060 0000
0 206F FFFF
1M
TCP3d-B Data
2070 0000
207F FFFF
0 2070 0000
0 207F FFFF
1M
Reserved
2080 0000
208F FFFF
0 2080 0000
0 208F FFFF
1M
TCP3d-A Data
2090 0000
2090 1FFF
0 2090 0000
0 2090 1FFF
8K
TCP3e Data Write Port
2090 2000
2090 3FFF
0 2090 2000
0 2090 3FFF
8K
TCP3e Data Read Port
2090 4000
209F FFFF
0 2090 4000
0 209F FFFF
1M-16K
Reserved
20A0 0000
20A3 FFFF
0 20A0 0000
0 20A3 FFFF
256K
Reserved
20A4 0000
20A4 FFFF
0 20A4 0000
0 20A4 FFFF
64K
Reserved
20A5 0000
20AF FFFF
0 20A5 0000
0 20AF FFFF
704k
Reserved
20B0 0000
20B1 FFFF
0 20B0 0000
0 20B1 FFFF
128k
Boot ROM
20B2 0000
20BE FFFF
0 20B2 0000
0 20BE FFFF
832k
Reserved
20BF 0000
20BF 03FF
0 20BF 0000
0 20BF 03FF
1k
SPI
20BF 0400
20BF FFFF
0 20BF 0400
0 20BF FFFF
63k
Reserved
20C0 0000
20C0 00FF
0 20C0 0000
0 20C0 00FF
256
Reserved
20C0 0100
20FF FFFF
0 20C0 0100
0 20FF FFFF
4M-256
Reserved
2100 0000
2100 00FF
0 2100 0000
0 2100 00FF
256
DDR3 EMIF Configuration
2100 0100
213F FFFF
0 2100 0100
0 213F FFFF
4M-256
Reserved
2140 0000
2140 03FF
0 2140 0000
0 2140 03FF
1K
HyperLink Config
2140 0400
217F FFFF
0 2140 0400
0 217F FFFF
4M-1K
Reserved
2180 0000
2180 7FFF
0 2180 0000
0 2180 7FFF
32K
PCIe Config
2180 8000
21BF FFFF
0 2180 8000
0 21BF FFFF
4M-32K
Reserved
21C0 0000
21FF FFFF
0 21C0 0000
0 21FF FFFF
4M
Reserved
2200 0000
229F FFFF
0 2200 0000
0 229F FFFF
10M
Reserved
22A0 0000
22A0 FFFF
0 22A0 0000
0 22A0 FFFF
64K
VCP2_A
22A1 0000
22AF FFFF
0 22A1 0000
0 22AF FFFF
1M-64K
Reserved
22B0 0000
22B0 FFFF
0 22B0 0000
0 22B0 FFFF
64K
VCP2_B
22B1 0000
22BF FFFF
0 22B1 0000
0 22BF FFFF
1M-64K
Reserved
22C0 0000
22C0 FFFF
0 22C0 0000
0 22C0 FFFF
64K
VCP2_C
22C1 0000
22CF FFFF
0 22C1 0000
0 22CF FFFF
1M-64K
Reserved
22D0 0000
22D0 FFFF
0 22D0 0000
0 22D0 FFFF
64K
VCP2_D
22D1 0000
22DF FFFF
0 22D1 0000
0 22DF FFFF
1M-64K
Reserved
22E0 0000
23FF FFFF
0 22E0 0000
0 23FF FFFF
18M
Reserved
2400 0000
2FFF FFFF
0 2400 0000
0 2FFF FFFF
192M
Reserved
3000 0000
331F FFFF
0 3000 0000
0 331F FFFF
50M
Reserved
33200000
335FFFFF
33200000
335FFFFF
4M
Reserved
3360 0000
33FF FFFF
0 3360 0000
0 33FF FFFF
10M
Reserved
3400 0000
341F FFFF
0 3400 0000
0 341F FFFF
2M
Queue Manager Subsystem Data
3420 0000
342F FFFF
0 3420 0000
0 342F FFFF
1M
Reserved
Copyright 2010 Texas Instruments Incorporated
ADVANCE INFORMATION
Table 2-2
Device Overview
25
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 2-2
Logical 32 bit Address
Start
www.ti.com
TMS320C6670 Memory Map Summary (Part 9 of 9)
End
Physical 36 bit Address
Start
End
Bytes
Description
3430 0000
3439 FFFF
0 3430 0000
0 3439 FFFF
640K
Reserved
343A 0000
343F FFFF
0 343A 0000
0 343F FFFF
384K
Reserved
3440 0000
347F FFFF
0 3440 0000
0 347F FFFF
4M
Reserved
3480 0000
34BF FFFF
0 3480 0000
0 34BF FFFF
4M
Reserved
ADVANCE INFORMATION
34C00000
34C2FFFF
34C00000
34C2FFFF
192K
Reserved
34C3 0000
34FF FFFF
0 34C3 0000
0 34FF FFFF
4M-192K
Reserved
3500 0000
37FF FFFF
0 3500 0000
0 37FF FFFF
48M
Reserved
3800 0000
3FFF FFFF
0 3800 0000
0 3FFF FFFF
128M
Reserved
4000 0000
4FFF FFFF
0 4000 0000
0 4FFF FFFF
256M
HyperLink Data
5000 0000
5FFF FFFF
0 5000 0000
0 5FFF FFFF
256M
Reserved
6000 0000
6FFF FFFF
0 6000 0000
0 6FFF FFFF
256M
PCIe Data
7000 0000
73FF FFFF
0 7000 0000
0 73FF FFFF
64M
Reserved
7400 0000
77FF FFFF
0 7400 0000
0 77FF FFFF
64M
Reserved
7800 0000
7BFF FFFF
0 7800 0000
0 7BFF FFFF
64M
Reserved
7C00 0000
7FFF FFFF
0 7C00 0000
0 7FFF FFFF
64M
Reserved
8000 0000
FFFF FFFF
8 8000 0000
8 FFFF FFFF
2G
DDR3 EMIF Data
End of Table 2-2
26
Device Overview
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
2.4 Boot Sequence
The C6670 supports several boot processes that begins execution at the ROM base address, which contains the
bootloader code necessary to support various device boot modes. The boot processes are software-driven and use
the BOOTMODE[12:0] device configuration inputs to determine the software configuration that must be
completed. For more details on Boot Sequence see the Bootloader for the C66x DSP User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 59.
2.5 Boot Modes Supported and PLL Settings
The device supports several boot processes, which leverage the internal boot ROM. Most boot processes are software
driven, using the BOOTMODE[3:0] device configuration inputs to determine the software configuration that must
be completed. From a hardware perspective, there are two possible boot modes:
• Public ROM Boot - C66x CorePac is released from reset and begins executing from the L3 ROM base address.
2
After performing the boot process (e.g., from I C ROM, Ethernet, or RapidIO), the C66x CorePac then begins
execution from the L2 RAM base address.
• Secure ROM Boot - On secure devices, the C66x CorePac is released from reset and begin executing from
secure ROM. Software in the secure ROM will free up internal RAM pages, after which the C66x CorePac
initiates the boot process. The C66x CorePac performs any authentication and decryption required on the
bootloaded image prior to beginning execution.
The boot process performed by the C66x CorePac in public ROM boot and secure ROM boot are determined by the
BOOTMODE[12:0] value in the DEVSTAT register. The C66x CorePac reads this value, and then executes the
associated boot process in software. Figure 2-2 shows the bits associated with BOOTMODE[12:0]. The PLL settings
is shown at the end of this section, and the PLL setup details can be found in Section 7.8 ‘‘Main PLL and the PLL
Controller’’ on page 160
Figure 2-2
Boot Mode Pin Decoding
Boot Mode Pins
12
11
10
9
2
PLL Mult I C /SPI Ext Dev Cfg
Copyright 2010 Texas Instruments Incorporated
8
7
Device Configuration
6
5
4
3
Reserved
2
1
0
Boot Device
Device Overview
27
ADVANCE INFORMATION
The boot sequence is a process by which the DSP's internal memory is loaded with program and data sections. The
DSP's internal registers are programmed with predetermined values. The boot sequence is started automatically
after each power-on reset. A Hard reset, Soft reset or Local reset to an individual C66x CorePac should not affect the
state of the hardware boot controller on the device. For more details on the initiators of the resets, see section
7.7 ‘‘Reset Controller’’ on page 153.
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
2.5.1 Boot Device Field
The Boot Device field BOOTMODE[2:0] defines the boot device that is chosen. Table 2-3 ‘‘Boot Mode Pins: Boot
Device Values’’ shows the supported boot modes.
Table 2-3
Boot Mode Pins: Boot Device Values
Bit
Field
Value
Description
2-0
Boot Device
0
No boot
1
Serial Rapid I/O
ADVANCE INFORMATION
2
Ethernet (SGMII) (PA driven from core clk)
3
Ethernet (SGMII) (PA driver from PA clk)
4
PCI
5
I2C
6
SPI
7
HyperLink
2.5.2 Device Configuration Field
The device configuration fields BOOTMODE[9:3] are used to configure the boot peripheral and, therefore, the bit
definitions depend on the boot mode
2.5.2.1 No Boot Device Configuration
Figure 2-3
Sleep Configuration Bit Fields
9
8
7
Reserved
Table 2-4
Wait Enable
Bit
Field
Reserved
7
Wait Enable
Value
4
Sub-Mode
3
Reserved
Description
Reserved
Sub-Mode
0
Wait enable disabled
1
Wait enable enabled
0
No Boot
1-3
4-3
5
Sleep Configuration Bit Field Descriptions
9-8
6-5
6
Reserved
Reserved
Reserved
2.5.2.2 Ethernet (SGMII) Boot Device Configuration
Figure 2-4
Ethernet (SGMII) Device Configuration Bit Fields
9
8
SerDes Clock Mult
28
Device Overview
7
6
Ext connection
5
4
3
Dev ID
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Ethernet (SGMII) Configuration Bit Field Descriptions
Bit
Field
9-8
SerDes clock mult
7-6
5-3
Ext connection
Device ID
Value
Description
The output frequency of the PLL must be 1.25 GBs.
0
×8 for input clock of 156.25 MHz
1
×5 for input clock of 250 MHz
2
×4 for input clock of 312.5 MHz
3
Reserved
0
Mac to Mac connection, master with auto negotiation
1
Mac to Mac connection, slave, and Mac to Phy
2
Mac to Mac, forced link
3
Mac to fiber connection
0-7
ADVANCE INFORMATION
Table 2-5
This value is used in the device ID field of the Ethernet-ready frame.
Copyright 2010 Texas Instruments Incorporated
Device Overview
29
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
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2.5.2.3 Serial Rapid I/O Boot Device Configuration
The device ID is always set to 0xff (8-bit node IDs) or 0xffff (16 bit node IDs) at power-on reset.
Figure 2-5
Serial Rapid I/O Device Configuration Bit Fields
9
8
Lane Setup
Table 2-6
9
Lane Setup
4
Ref Clock
Value
3
Reserved
Description
0
ADVANCE INFORMATION
Data Rate
Ref Clock
4-3
5
Serial Rapid I/O Configuration Bit Field Descriptions
Field
6-5
6
Data Rate
Bit
8-7
7
Reserved
Port Configured as 4 ports each 1 lane wide (4 -1× ports)
1
Port Configured as 2 ports 2 lanes wide (2 – 2× ports)
0
Data Rate = 1.25 GBs
1
Data Rate = 2.5 GBs
2
Data Rate = 3.125 GBs
3
Data Rate = 5.0 GBs
0
Reference Clock = 156.25 MHz
1
Reference Clock = 250 MHz
2
Reference Clock = 312.5 MHz
0-3
Reserved
In SRIO boot mode, both the message mode and DirectIO mode will be enabled by default. If use of the memory
reserved for received messages is required and reception of messages cannot be prevented, the master can disable
the message mode by writing to the boot table and generating a boot restart.
2.5.2.4 PCI Boot Device Configuration
Extra device configuration is provided in the PCI bits in the DEVSTAT register.
Figure 2-6
PCI Device Configuration Bit Fields
9
8
7
Reserved
Table 2-7
5
4
BAR Config
3
Reserved
PCI Device Configuration Bit Field Descriptions
Bit
Field
9
Reserved
8-5
Bar Config
0-0xf
4-3
Reserved
0-3
30
6
Device Overview
Value
Description
Reserved
See Table 2-8.
Reserved
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
BAR Config / PCIe Window Sizes
32-Bit Address Translation
64-Bit Address Translation
BAR cfg
BAR0
BAR1
BAR2
BAR3
BAR4
BAR5
0b0000
PCIe MMRs
32
32
32
32
Clone of BAR4
BAR1/2
BAR3/4
0b0001
16
16
32
64
0b0010
16
32
32
64
0b0011
32
32
32
64
0b0100
16
16
64
64
0b0101
16
32
64
64
0b0110
32
32
64
64
0b0111
32
32
64
128
0b1000
64
64
128
256
0b1001
4
128
128
128
0b1010
4
128
128
256
0b1011
0b1100
4
128
256
256
256
256
0b1101
512
512
0b1110
1024
1024
0b1111
2048
2048
2.5.2.5 I2C Boot Device Configuration
2.5.2.5.1 I2C Master Mode
In master mode, the I2C device configuration uses ten bits of device configuration instead of seven as used in other
2
boot modes. In this mode, the device will make the initial read of the I C EEPROM while the PLL is in bypass mode.
The initial read will contain the desired clock multiplier, which will be set up prior to any subsequent reads.
I2C Master Mode Device Configuration Bit Fields
Figure 2-7
12
11
10
9
Reserved
Speed
Address
Mode
8
7
6
5
4
Parameter Index
(0)
Table 2-9
Field
12
Reserved
11
Speed
9
Reserved
I2C Master Mode Device Configuration Field Descriptions
Bit
10
3
Address
Mode
Value
Description
Reserved
0
I2C data rate set to approximately 20 kHz
1
I C fast mode. Data rate set to approximately 400 kHz (will not exceed)
0
Boot from I2C EEPROM at I2C bus address 0x50
1
Boot from I C EEPROM at I C bus address 0x51
0
Master mode
1
Passive mode (see ‘‘I2C Passive Mode’’ on page 32)
2
2
2
8-3
Parameter Index
0-63
Identifies the index of the configuration table initially read from the I2C EEPROM
4-3
Reserved
0-3
Reserved
Copyright 2010 Texas Instruments Incorporated
Device Overview
31
ADVANCE INFORMATION
Table 2-8
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
2.5.2.5.2 I2C Passive Mode
In passive mode, the device does not drive the clock, but simply acks data received on the specified address.
I2C Passive Mode Device Configuration Bit Fields
Figure 2-8
9
8
7
Mode (1)
Table 2-10
6
5
4
2
Receive I C Address
3
Reserved
I2C Passive Mode Device Configuration Field Descriptions
ADVANCE INFORMATION
Bit
Field
Value
9
Mode
0
Master Mode (see ‘‘I2C Master Mode’’ on page 31)
1
Passive Mode
2
Description
2
8-5
Receive I C Address
0-15
The I C Bus address the device will listen to for data
4-3
Reserved
0-3
Reserved
2.5.2.6 SPI Boot Device Configuration
In SPI boot mode, the SPI device configuration uses ten bits of device configuration instead of seven as used in other
boot modes.
Figure 2-9
SPI Device Configuration Bit Fields
12
11
Mode
Table 2-11
Bit
Field
12-11
Mode
10
9
10
9
4, 5 Pin
Addr Width
8
7
Chip Select
5
4
Parameter Table Index
3
Reserved
SPI Device Configuration Field Descriptions
4, 5 Pin
Addr Width
Value
Description
Clk Pol / Phase
0
Data is output on the rising edge of SPICLK. Input data is latched on the falling edge.
1
Data is output one half-cycle before the first rising edge of SPICLK and on subsequent falling edges.
Input data is latched on the rising edge of SPICLK.
2
Data is output on the falling edge of SPICLK. Input data is latched on the rising edge.
3
Data is output one half-cycle before the first falling edge of SPICLK and on subsequent rising edges.
Input data is latched on the falling edge of SPICLK.
0
4-pin mode used
1
5-pin mode used
0
16-bit address values are used
1
24-bit address values are used
8-7
Chip Select
0-3
The chip select field value
6-5
Parameter Table Index
0-3
Specifies which parameter table is loaded
4-3
Reserved
0-3
Reserved
32
6
Device Overview
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
2.5.2.7 HyperLink Boot Device Configuration
Figure 2-10
HyperLink Boot Device Configuration Fields
9
8
7
Reserved
Data Rate
Field
9
Reserved
8-7
Data Rate
4-3
4
3
Ref Clock
Reserved
HyperLink Boot Device Configuration Field Descriptions
Bit
6-5
5
Value
Description
Reserved
Ref Clocks
Reserved
0
1.25 GBs
1
3.125 GBs
2
6.25 GBs
3
12.5 GBs
0
156.25 MHz
1
250 MHz
2
312.5 MHz
0-3
Reserved
2.5.3 PLL Settings
The PLL default settings are determined by the BOOTMODE[12:10] bits. Table 2-13 shows settings for various
input clock frequencies. This will set the PLL to the maximum clock setting for the device.
CLK = CLKIN × (PLLM+1) ÷ (2 × (PLLD+1))
The PA configuration is also shown. The PA is configured with these values only if the Ethernet boot mode is
selected with the input clock set to match the main PLL clock (not the PA SerDes clock). See Table 2-3 for details on
configuring Ethernet boot mode.
The Main PLL is controlled using a PLL controller and a chip level MMR. The DDR3 PLL and PASS PLL are
controlled by chip level MMRs. For details on how to setup the PLL see Section 7.8 ‘‘Main PLL and the PLL
Controller’’ on page 160. For details on the operation of the PLL controller module, see the Phase Locked Loop (PLL)
Controller for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59.
Table 2-13
BOOTMODE
[12:10]
C66x CorePac System PLL Configuration
Input Clock
Freq (MHz)
800 MHz Device
PLLD
PLLM
DSP ƒ
1000 MHz Device
PLLD
PLLM
DSP ƒ
PA = 350 MHz (1)
1200 MHz Device
PLLD
PLLM
DSP ƒ
PLLD
PLLM
DSP ƒ
(2)
0b000
50.00
0
31
800
0
39
1000
0
47
1200
0
41
1050
0b001
66.67
0
23
800.04
0
29
1000.05
0
35
1200.06
1
62
1050.053
0b010
80.00
0
19
800
0
24
1000
0
29
1200
3
104
1050
0b011
100.00
0
15
800
0
19
1000
0
23
1200
0
20
1050
0b100
156.25
24
255
800
4
63
1000
24
383
1200
24
335
1050
0b101
250.00
4
31
800
0
7
1000
4
47
1200
4
41
1050
0b110
312.50
24
127
800
4
31
1000
24
191
1200
24
167
1050
0b111
122.88
47
624
800
28
471
999.989
31
624
1200
11
204
1049.6
1 The PASS PLL generates 1050 MHz and is internally divided by 3 to feed 350 MHz to the Packet Accelerator.
2 ƒ represents frequency in MHz.
Copyright 2010 Texas Instruments Incorporated
Device Overview
33
ADVANCE INFORMATION
Table 2-12
6
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
2.6 Second-Level Bootloaders
Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader allows for any
level of customization to current boot methods as well as the definition of a completely customized boot.
2.7 Terminals
Figure 2-11 shows the TMS320C6670 CYP ball grid array package (bottom view).
Figure 2-11
CYP 841-PIN BGA Package Bottom View
AH
ADVANCE INFORMATION
AF
AD
AB
Y
V
T
AJ
AG
AE
AC
AA
W
U
R
P
N
M
L
K
J
H
F
D
G
E
C
B
A
3
1
2
34
Device Overview
5
4
9
7
6
8
11 13 15 17 19 21 23 25 27 29
10 12 14 16 18 20 22 24 26 28
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
2.8 Terminal Functions
The terminal functions table (Table 2-15) identifies the external signal names, the associated pin (ball) numbers, the
pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors, and gives functional pin
descriptions. This table is arranged by function. The power terminal functions table (Table 2-16) lists the various
power supply pins and ground pins and gives functional pin descriptions. Table 2-17 shows all pins arranged by
signal name. Table 2-18 shows all pins arranged by ball number.
There are 17 pins that have a secondary function as well as a primary function. The secondary function is indicated
with a dagger (†).
ADVANCE INFORMATION
For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and
pullup/pulldown resistors, see chapter 3 ‘‘Device Configuration’’ on page 60.
Use the symbol definitions in Table 2-14 when reading Table 2-15.
Table 2-14
I/O Functional Symbol Definitions
Functional
Symbol
IPD or IPU
A
Definition
Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can
be used to oppose the IPD/IPU. For more detailed information on pulldown/pullup resistors and
situations in which external pulldown/pullup resistors are required, see the Hardware Design Guide for
KeyStone Devices in ‘‘Related Documentation from Texas Instruments’’ on page 59.
Table 2-15
Column Heading
IPD/IPU
Analog signal
Type
Ground
Type
Input terminal
Type
O
Output terminal
Type
S
Supply voltage
Type
Z
Three-state terminal or high impedance
Type
GND
I
End of Table 2-14
Table 2-15
Signal Name
Terminal Functions — Signals and Control by Function (Part 1 of 12)
Ball No. Type IPD/IPU Description
AIF
AIFRXN0
L28
I
AIFRXP0
M28
I
AIFRXN1
K29
I
AIFRXP1
L29
I
AIFRXN2
R28
I
AIFRXP2
P28
I
AIFRXN3
P29
I
AIFRXP3
N29
I
AIFRXN4
T29
I
AIFRXP4
U29
I
AIFRXN5
U28
I
AIFRXP5
V28
I
Copyright 2010 Texas Instruments Incorporated
Antenna Interface Receive Data (6 links)
Device Overview
35
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 2-15
www.ti.com
Terminal Functions — Signals and Control by Function (Part 2 of 12)
Signal Name
Ball No. Type IPD/IPU Description
AIFTXN0
L26
O
AIFTXP0
M26
O
AIFTXN1
L27
O
AIFTXP1
K27
O
AIFTXN2
R26
O
AIFTXP2
P26
O
AIFTXN3
P27
O
ADVANCE INFORMATION
AIFTXP3
N27
O
AIFTXN4
U27
O
AIFTXP4
T27
O
AIFTXN5
U26
O
AIFTXP5
V26
O
Antenna Interface Transmit Data (6 links)
AIF2 Timer (AT) Module
RP1CLKP
Y28
I
RP1CLKN
AA28
I
EXTFRAMEEVENT
AE17
OZ
RP1FBP
Y29
I
RP1FBN
AA29
I
PHYSYNC
AB27
I
down
Alternate Frame Sync Clock Input (vs. FSYNCCLK(N|P))
RADSYNC
AA27
I
down
Alternate Frame Sync Input (vs. FRAMBURST (N|P))
Frame Sync Interface Clock used to drive the frame synchronization interface (OBSAI RP1 clock)
Down
Frame Sync Clock Output
Frame Burst to drive frame indicators to the frame synchronization module (OBSAI RP1)
Boot Configuration Pins
LENDIAN †
AJ20
IOZ
Up
BOOTMODE00 †
AG18
IOZ
Down
BOOTMODE01†
AD19
IOZ
Down
BOOTMODE02 †
AE19
IOZ
Down
BOOTMODE03 †
AF18
IOZ
Down
BOOTMODE04 †
AE18
IOZ
Down
BOOTMODE05 †
AG20
IOZ
Down
BOOTMODE06 †
AH19
IOZ
Down
BOOTMODE07 †
AJ19
IOZ
Down
BOOTMODE08 †
AE21
IOZ
Down
BOOTMODE09 †
AG19
IOZ
Down
BOOTMODE10 †
AD20
IOZ
Down
BOOTMODE11 †
AE20
IOZ
Down
BOOTMODE12 †
AF21
IOZ
Down
PCIESSMODE0 †
AH20
IOZ
Down
PCIESSMODE1 †
AD21
IOZ
Down
PCIESSEN †
AJ23
I
Endian configuration pin (Pin shared with GPIO[0])
See Section 2.5 ‘‘Boot Modes Supported and PLL Settings’’ on page 27 for more details
(Pins shared with GPIO[1:13])
PCIe Mode selection pins (Pins shared with GPIO[14:15])
PCIe module enable (Pin shared with TIMI0)
Clock / Reset
SYSCLKP
AC29
I
SYSCLKN
AC28
I
PASSCLKP
AJ18
I
PASSCLKN
AH18
I
36
Device Overview
System Clock Input to Antenna Interface and Main PLL (Main PLL optional vs. ALTCORECLK)
PA Sub-system Reference Clock to PA Sub-system PLL (PASS PLL optional vs. REFCLK)
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Terminal Functions — Signals and Control by Function (Part 3 of 12)
Signal Name
Ball No. Type IPD/IPU Description
ALTCORECLKP
AB29
I
ALTCORECLKN
AB28
I
SRIOSGMIICLKP
AJ16
I
SRIOSGMIICLKN
AH16
I
DDRCLKP
G29
I
DDRCLKN
H29
I
PCIECLKP
AH17
I
PCIECLKN
AJ17
I
MCMCLKP
W1
I
MCMCLKN
W2
I
SYSCLKOUT
AA26
OZ
Down
System Clock Output to be used as a general purpose output clock for debug purposes
CORECLKSEL
AB25
I
Down
Core Clock Select to select between SYSCLK and ALTCORECCLK to the Main PLL
PACLKSEL
AD23
IOZ
Down
PA Clock select to choose between PASSCLK and the output of Main PLL MUX (dependent on
CORECLKSEL pin) to the PA Sub-system PLL
HOUT
AC18
OZ
Up
Interrupt output pulse created by IPCGRH
NMI
AC25
I
Up
Non-maskable Interrupt
LRESET
AE22
I
Up
Local Reset
LRESETNMIEN
AC20
I
Up
Enable for core selects
CORESEL0
AH15
I
down
CORESEL1
AC16
I
down
CORESEL2
AD15
I
down
RESETFULL
AE23
I
Up
Full Reset Power-on Reset
RESET
AC24
I
Up
Reset of non isolated portion on the IC
POR
AC19
I
RESETSTAT
AD18
O
Up
Reset Status Output
BOOTCOMPLETE
AC21
OZ
Down
Boot progress indication output
PTV15
H24
A
Alternate System Clock Input to Main PLL (Main PLL optional vs. SYSCLK)
RapidIO/SGMII Reference Clock to drive the RapidIO and SGMII SERDES
DDR Reference Clock Input to DDR PLL
PCIe Reference Clock Input to drive PCIe SERDES
ADVANCE INFORMATION
Table 2-15
HyperLink Reference Clock Input to drive the HyperLink SERDES
Select for the target core for LRESET and NMI. For more details see Table 7-24 ‘‘NMI and LRESET
Timing Requirements’’ on page 137
POR Power-on Reset
Copyright 2010 Texas Instruments Incorporated
PTV Compensation NMOS Reference Input
Device Overview
37
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 2-15
Signal Name
www.ti.com
Terminal Functions — Signals and Control by Function (Part 4 of 12)
Ball No. Type IPD/IPU Description
DDR
ADVANCE INFORMATION
DDRDQS0P
C28
IOZ
DDRDQS0N
C29
IOZ
DDRDQS1P
A27
IOZ
DDRDQS1N
B27
IOZ
DDRDQS2P
A24
IOZ
DDRDQS2N
B24
IOZ
DDRDQS3P
A21
IOZ
DDRDQS3N
B21
IOZ
DDRDQS4P
A9
IOZ
DDRDQS4N
B9
IOZ
DDRDQS5P
B6
IOZ
DDRDQS5N
A6
IOZ
DDRDQS6P
B3
IOZ
DDRDQS6N
A3
IOZ
DDRDQS7P
D1
IOZ
DDRDQS7N
C1
IOZ
DDRDQS8P
A19
IOZ
DDRDQS8N
B19
IOZ
DDRCB00
E19
IOZ
DDRCB01
C20
IOZ
DDRCB02
D19
IOZ
DDRCB03
B20
IOZ
DDRCB04
C19
IOZ
DDRCB05
C18
IOZ
DDRCB06
B18
IOZ
DDRCB07
A18
IOZ
38
Device Overview
DDR EMIF Data Strobe
DDR EMIF Check Bits
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Terminal Functions — Signals and Control by Function (Part 5 of 12)
Signal Name
Ball No. Type IPD/IPU Description
DDRD00
E28
IOZ
DDRD01
D29
IOZ
DDRD02
E27
IOZ
DDRD03
D28
IOZ
DDRD04
D27
IOZ
DDRD05
B28
IOZ
DDRD06
E26
IOZ
DDRD07
F25
IOZ
DDRD08
F24
IOZ
DDRD09
E24
IOZ
DDRD10
E25
IOZ
DDRD11
D25
IOZ
DDRD12
D26
IOZ
DDRD13
C26
IOZ
DDRD14
B26
IOZ
DDRD15
A26
IOZ
DDRD16
F23
IOZ
DDRD17
F22
IOZ
DDRD18
D24
IOZ
DDRD19
E23
IOZ
DDRD20
A23
IOZ
DDRD21
B23
IOZ
DDRD22
C24
IOZ
DDRD23
E22
IOZ
DDRD24
D21
IOZ
DDRD25
F20
IOZ
DDRD26
E21
IOZ
DDRD27
F21
IOZ
DDRD28
D22
IOZ
DDRD29
C21
IOZ
Copyright 2010 Texas Instruments Incorporated
ADVANCE INFORMATION
Table 2-15
DDR EMIF Data Bus
Device Overview
39
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 2-15
www.ti.com
Terminal Functions — Signals and Control by Function (Part 6 of 12)
ADVANCE INFORMATION
Signal Name
Ball No. Type IPD/IPU Description
DDRD30
B22
DDRD31
C22
IOZ
DDRD32
E10
IOZ
DDRD33
D10
IOZ
DDRD34
B10
IOZ
DDRD35
D9
IOZ
DDRD36
E9
IOZ
DDRD37
C9
IOZ
DDRD38
B8
IOZ
DDRD39
E8
IOZ
DDRD40
A7
IOZ
DDRD41
D7
IOZ
DDRD42
E7
IOZ
DDRD43
C7
IOZ
DDRD44
B7
IOZ
DDRD45
E6
IOZ
DDRD46
D6
IOZ
DDRD47
C6
IOZ
DDRD48
C5
IOZ
DDRD49
A5
IOZ
DDRD50
B4
IOZ
DDRD51
A4
IOZ
DDRD52
D4
IOZ
DDRD53
E4
IOZ
DDRD54
C4
IOZ
DDRD55
C3
IOZ
DDRD56
F4
IOZ
DDRD57
D2
IOZ
DDRD58
E2
IOZ
DDRD59
C2
IOZ
DDRD60
F2
IOZ
DDRD61
F3
IOZ
DDRD62
E1
IOZ
DDRD63
F1
IOZ
DDRCE0
C11
OZ
DDRCE1
C12
OZ
DDRBA0
A13
OZ
DDRBA1
B13
OZ
DDRBA2
C13
OZ
40
Device Overview
IOZ
DDR EMIF Data Bus
DDR EMIF Chip Enables
DDR EMIF Bank Address
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Terminal Functions — Signals and Control by Function (Part 7 of 12)
Signal Name
Ball No. Type IPD/IPU Description
DDRA00
A14
OZ
DDRA01
B14
OZ
DDRA02
F14
OZ
DDRA03
F13
OZ
DDRA04
A15
OZ
DDRA05
C15
OZ
DDRA06
B15
OZ
DDRA07
D15
OZ
DDRA08
F15
OZ
DDRA09
E15
OZ
DDRA10
E16
OZ
DDRA11
D16
OZ
DDRA12
E17
OZ
DDRA13
C16
OZ
DDRA14
D17
OZ
DDRA15
C17
OZ
DDRCAS
D12
OZ
DDR EMIF Column Address Strobe
DDRRAS
C10
OZ
DDR EMIF Row Address Strobe
DDRWE
E12
OZ
DDR EMIF Write Enable
DDRCKE0
D11
OZ
DDRCKE1
E18
OZ
DDRCLKOUTP0
A12
OZ
DDRCLKOUTN0
B12
OZ
DDRCLKOUTP1
A16
OZ
DDRCLKOUTN1
B16
OZ
DDRODT0
D13
OZ
DDRODT1
E13
OZ
DDRRESET
E11
OZ
DDRSLRATE0
H27
I
Down
DDRSLRATE1
H26
I
Down
VREFSSTL
E14
P
DDR EMIF Address Bus
ADVANCE INFORMATION
Table 2-15
DDR EMIF Clock Enables
DDR EMIF Output Clocks to drive SDRAMs (one clock pair per SDRAM)
DDR EMIF On Die Termination Outputs used to set termination on the SDRAMs
DDR Reset signal
Copyright 2010 Texas Instruments Incorporated
DDR Slew rate control
Reference Voltage Input for SSTL15 buffers used by DDR EMIF (VDDS15 ÷ 2)
Device Overview
41
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 2-15
Signal Name
www.ti.com
Terminal Functions — Signals and Control by Function (Part 8 of 12)
Ball No. Type IPD/IPU Description
EMU
EMU00
AE29
IOZ
Up
EMU01
AF29
IOZ
Up
EMU02
AE28
IOZ
Up
EMU03
AF28
IOZ
Up
EMU04
AE26
IOZ
Up
EMU05
AD25
IOZ
Up
ADVANCE INFORMATION
EMU06
AF25
IOZ
Up
EMU07
AE25
IOZ
Up
EMU08
AF27
IOZ
Up
EMU09
AG29
IOZ
Up
EMU10
AF26
IOZ
Up
EMU11
AG28
IOZ
Up
EMU12
AG27
IOZ
Up
EMU13
AG25
IOZ
Up
EMU14
AH28
IOZ
Up
EMU15
AJ27
IOZ
Up
EMU16
AH27
IOZ
Up
EMU17
AJ26
IOZ
Up
EMU18
AH25
IOZ
Up
Emulation and Trace Ports
General Purpose Input/Output (GPIO)
GPIO00
AJ20
IOZ
Up
GPIO01
AG18
IOZ
Down
GPIO02
AD19
IOZ
Down
GPIO03
AE19
IOZ
Down
GPIO04
AF18
IOZ
Down
GPIO05
AE18
IOZ
Down
GPIO06
AG20
IOZ
Down
GPIO07
AH19
IOZ
Down
GPIO08
AJ19
IOZ
Down
GPIO09
AE21
IOZ
Down
GPIO10
AG19
IOZ
Down
GPIO11
AD20
IOZ
Down
GPIO12
AE20
IOZ
Down
GPIO13
AF21
IOZ
Down
GPIO14
AH20
IOZ
Down
GPIO15
AD21
IOZ
Down
42
Device Overview
General Purpose Input/Output
These GPIO pins have secondary functions assigned to them as mentioned in the Boot
Configuration Pins section above.
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Table 2-15
Terminal Functions — Signals and Control by Function (Part 9 of 12)
Signal Name
Ball No. Type IPD/IPU Description
HyperLink
T2
I
MCMRXP0
R2
I
MCMRXN1
P1
I
MCMRXP1
R1
I
MCMRXN2
L1
I
MCMRXP2
M1
I
MCMRXN3
N2
I
MCMRXP3
M2
I
MCMTXN0
T5
O
MCMTXP0
R5
O
MCMTXN1
R4
O
MCMTXP1
P4
O
MCMTXN2
L4
O
MCMTXP2
M4
O
MCMTXN3
M5
O
MCMTXP3
N5
O
Serial HyperLink Receive Data (4 links)
ADVANCE INFORMATION
MCMRXN0
Serial HyperLink Transmit Data (4 links)
MCMRXFLCLK
V3
O
down
MCMRXFLDAT
W3
O
down
MCMTXFLCLK
Y1
I
down
MCMTXFLDAT
Y2
I
down
MCMRXPMCLK
AA3
I
down
MCMRXPMDAT
Y3
I
down
MCMTXPMCLK
AA2
O
down
MCMTXPMDAT
AA1
O
down
MCMREFCLKOUTP
V2
O
MCMREFCLKOUTN
V1
O
Serial HyperLink Sideband Signals
HyperLink reference clock output for daisy chain connection
2
I C
2
SCL
AC17
IOZ
I C Clock
SDA
AD17
IOZ
I2C Data
TCK
AD29
I
Up
JTAG Clock Input
TDI
AD28
I
Up
JTAG Data Input
TDO
AC27
OZ
Up
JTAG Data Output
TMS
AC26
I
Up
JTAG Test Mode Input
TRST
AD26
I
Down
JTAG Reset
JTAG
MDIO
MDIO
AG16
IOZ
Up
MDIO Data
MDCLK
AF16
O
Down
MDIO Clock
Copyright 2010 Texas Instruments Incorporated
Device Overview
43
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 2-15
Signal Name
www.ti.com
Terminal Functions — Signals and Control by Function (Part 10 of 12)
Ball No. Type IPD/IPU Description
PCIe
PCIERXN0
AJ14
I
PCIERXP0
AJ13
I
PCIERXN1
AH12
I
PCIERXP1
AH13
I
ADVANCE INFORMATION
PCIETXN0
AG14
O
PCIETXP0
AG13
O
PCIETXN1
AF12
O
PCIETXP1
AF13
O
RIORXN0
AJ11
I
PCIexpress Receive Data (2 links)
PCIexpress Transmit Data (2 links)
Serial RapidIO
RIORXP0
AJ10
I
RIORXN1
AH10
I
RIORXP1
AH9
I
RIORXN2
AJ7
I
RIORXP2
AJ8
I
RIORXN3
AH6
I
RIORXP3
AH7
I
RIOTXN0
AG11
O
RIOTXP0
AG10
O
RIOTXN1
AF9
O
RIOTXP1
AF10
O
RIOTXN2
AG7
O
RIOTXP2
AG8
O
RIOTXN3
AF6
O
RIOTXP3
AF7
O
Serial RapidIO Receive Data (4 links)
Serial RapidIO Transmit Data (4 links)
SGMII
SGMII0RXN
AH3
I
SGMII0RXP
AH4
I
SGMII1RXN
AJ4
I
SGMII1RXP
AJ5
I
SGMII0TXN
AF3
O
SGMII0TXP
AF4
O
SGMII1TXN
AG4
O
SGMII1TXP
AG5
O
VCL
Y4
IOZ
Voltage Control I C Clock
VD
W4
IOZ
Voltage Control I C Data
VCNTL0
AB4
OZ
VCNTL1
AB3
OZ
VCNTL2
AA4
OZ
VCNTL3
AB1
OZ
Ethernet MAC SGMII Receive Data (2 links)
Ethernet MAC SGMII Transmit Data (2 links)
SmartReflex
44
Device Overview
2
2
Voltage Control Outputs to variable core power supply
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Table 2-15
Signal Name
Terminal Functions — Signals and Control by Function (Part 11 of 12)
Ball No. Type IPD/IPU Description
SPI
SPISCS0
AH21
OZ
Up
SPI Interface Enable 0
SPISCS1
AJ22
OZ
Up
SPI Interface Enable 1
SPICLK
AG21
OZ
Down
SPI Clock
SPIDIN
AH22
I
Down
SPI Data In
SPIDOUT
AJ21
OZ
Down
SPI Data Out
TIMI0
AJ23
I
Down
TIMI1
AG23
I
Down
TIMO0
AH23
OZ
Down
TIMO1
AF23
OZ
Down
ADVANCE INFORMATION
Timer
Timer Inputs
Timer Outputs
UART
UARTRXD
AF24
I
Down
UART Serial Data In
UARTTXD
AJ24
OZ
Down
UART Serial Data Out
UARTCTS
AH24
I
Down
UART Clear To Send
UARTRTS
AG24
OZ
Down
UART Request TO Send
Reserved
RSV01
AJ25
IOZ
Down
Reserved - Connect to GND
RSV03
AC23
OZ
Down
Reserved - leave unconnected
RSV04
Y27
O
Reserved - leave unconnected
RSV05
W27
O
Reserved - leave unconnected
RSV06
J28
O
Reserved - leave unconnected
RSV07
H28
O
Reserved - leave unconnected
RSV08
J24
A
Reserved - leave unconnected
RSV09
J25
A
Reserved - leave unconnected
RSV10
H23
A
Reserved - leave unconnected
RSV11
J23
A
Reserved - leave unconnected
RSV12
AD22
A
Reserved - leave unconnected
RSV13
AC22
A
Reserved - leave unconnected
RSV14
V4
A
Reserved - leave unconnected
RSV15
AE8
A
Reserved - leave unconnected
RSV16
AE14
A
Reserved - leave unconnected
RSV17
AE5
A
Reserved - leave unconnected
RSV18
AA24
A
Reserved - leave unconnected
RSV19
G27
A
Reserved - leave unconnected
RSV20
AB26
OZ
Down
Reserved - leave unconnected
RSV21
G26
OZ
Down
Reserved - leave unconnected
RSV22
AE16
OZ
Down
Reserved - leave unconnected
RSV23
AD16
A
Reserved - leave unconnected
RSV24
AG17
O
Reserved - leave unconnected
RSV25
AF17
O
Reserved - leave unconnected
Copyright 2010 Texas Instruments Incorporated
Device Overview
45
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 2-15
www.ti.com
Terminal Functions — Signals and Control by Function (Part 12 of 12)
Signal Name
Ball No. Type IPD/IPU Description
RSV26
U25
A
Reserved - leave unconnected
RSV27
L25
A
Reserved - leave unconnected
End of Table 2-15
Table 2-16
Terminal Functions — Power and Ground
ADVANCE INFORMATION
Supply
Ball No.
Volts
Description
AVDDA1
W24
1.8
PLL Supply: CORE_PLL
AVDDA2
J26
1.8
PLL Supply: DDR3_PLL
AVDDA3
AB15
1.8
PLL Supply: PASS_PLL.
CVDD
0.9
H11, H13, H15, H17, H19, H21, J12, J18, K11, K19, L12, L18, M11, M13, M15 M17,
to
M19, N8, N10, N12, N14, N16, N18, N20, N22, P9, P11, P13, P15, P17, P19, P21, R8,
R10, R12, R14, R16, R18, R20, R22, T9, T11, T13, T15, T17, T19, T21, U8, U10, U12, U14, 1.1
U16, U18, U20, U22, V9, V11, V13, V15, V17, V19, V21, V23, W8, W10, W18, W20, W22,
Y9, Y19, Y21, Y23, AA8, AA10, AA12, AA14, AA16, AA18, AA20, AA22, AB23
SmartReflex core supply voltage
CVDD1
G6, H1, H3, H5, H7, H9, J2, J4, J6, J8, J10, J14, J16, J20, J22, K7, K9, K13, K15, K17, K21, 1.0
L8, L10, L14, L16, L20, L22, M9, M21, W12, W14, W16, Y11, Y13, Y15, Y17, AD1, AD3,
AE2, AF1, AG2, AH1, AJ2
Fixed core supply voltage
DVDD15
A2, A11, A17, A28, B1, B29, C14, C25, D5, D8, D20, D23, E3, F5, F7, F9, F11, F17, F19,
F27, G2, G4, G8, G10, G12, G14, G16 G18, G20, G22, G24
1.5
DDR IO supply
DVDD18
G28, H25, V5, Y5, Y25, AB5, AB17, AB19, AB21, AC2, AC4, AE24, AE27, AF19, AF22,
AH26, AH29, AJ28
1.8
IO supply
VDDR1
K6
1.5
HyperLink SerDes regulator supply
VDDR2
AE15
1.5
PCIe SerDes regulator supply
VDDR3
AE6
1.5
SGMII SerDes regulator supply
VDDR4
AE11
1.5
SRIO SerDes regulator supply
VDDR5
R25
VDDR6
N25
1.5
AIF SerDes regulator supply
VDDT1
M7, N6, P7, R6, T7, V7, W6, Y7
1.0
HyperLink SerDes termination supply
VDDT2
AC6, AC8, AC10, AC12, AC14, AD5, AD7, AD9, AD11, AD13, AE4, AE10, AE12
1.0
SGMII/SRIO/PCIe SerDes termination supply
VDDT3
K25, L24, M23, M25, N24, P23, P25, R24, T23, T25, U24, V25
VREFSSTL E14
VSS
1.0
AIF SerDes termination supply
0.75
DDR3 reference voltage
A1, A29, B11, B17, B25, C8, C23, D3, D14, D18, E5, E20, F6, F8, F10, F12, F16, F18, F26, Gnd
F28, F29, G1, G3, G5, G7, G9, G11, G13, G15, G17, G19, G21, G23, G25, H2, H4, H6, H8,
H10, H12, H14, H16, H18, H20, H22, J1, J3, J5, J7, J9, J11, J13, J15, J17, J19, J21, J27,
J29, K1, K2, K3, K4, K5, K8, K10, K12, K14, K16, K18, K20, K22, K26, K28, L2, L3,L5, L6,
L7, L9, L11, L13, L15, L17, L19, L21, L23, M3, M6, M8, M10, M12, M14, M16, M18, M20,
M22, M24, M27, M29, N1, N3, N4, N7, N9, N11, N13, N15, N17, N19, N21, N23, N26,
N28, P2, P3, P5, P6, P8, P10, P12, P14, P16, P18, P20, P22, P24, R3, R7, R9, R11, R13,
R15, R17, R19, R21, R23, R27, R29, T1, T3, T4, T6, T8, T10, T12, T14, T16, T18, T20, T22,
T24, T26, T28, U1, U2, U3, U4, U5, U6, U7, U9, U11, U13, U15, U17, U19, U21, U23, V6,
V8, V10, V12, V14, V16, V18, V20, V22, V24, V27, V29, W5, W7, W9, W11, W13, W15,
W17, W19, W21, W23, W25, W26, W28, W29, Y6, Y8, Y10, Y12, Y14, Y16, Y18, Y20,
Y22, Y24, Y26, AA5, AA6, AA7, AA9, AA11, AA13, AA15, AA17, AA19, AA21, AA23,
AA25, AB2, AB6, AB7, AB8, AB9, AB10, AB11, AB12, AB13, AB14, AB16, AB18, AB20,
AB22, AB24, AC1, AC3, AC5, AC7, AC9, AC11, AC13, AC15, AD2, AD4, AD6, AD8,
AD10, AD12, AD14, AD24, AD27, AE1, AE3, AE7, AE9, AE13, AF2, AF5, AF8, AF11,
AF14, AF15, AF20, AG1, AG3, AG6, AG9, AG12, AG15, AG22, AG26, AH2, AH5, AH8,
AH11, AH14, AJ1, AJ3, AJ6, AJ9, AJ12, AJ15, AJ29
Ground
End of Table 2-16
46
Device Overview
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 2-17
Terminal Functions
— By Signal Name
(Part 1 of 11)
Table 2-17
Terminal Functions
— By Signal Name
(Part 2 of 11)
Table 2-17
Terminal Functions
— By Signal Name
(Part 3 of 11)
Ball Number
Signal Name
Ball Number
Signal Name
Ball Number
AIFRXN0
L28
BOOTMODE12 †
AF21
DDRA15
C17
AIFRXN1
K29
CORECLKSEL
AB25
DDRBA0
A13
AIFRXN2
R28
CORESEL0
AH15
DDRBA1
B13
AIFRXN3
P29
CORESEL1
AC16
DDRBA2
C13
AIFRXN4
T29
CORESEL2
AD15
DDRCAS
D12
AIFRXN5
U28
CVDD
H11, H13, H15, H17,
H19, H21, J12, J18,
K11, K19, L12, L18,
M11, M13, M15
M17, M19, N8, N10,
N12, N14, N16, N18,
N20, N22, P9, P11,
P13, P15, P17, P19
DDRCB00
E19
DDRCB01
C20
DDRCB02
D19
DDRCB03
B20
DDRCB04
C19
DDRCB05
C18
Signal Name
AIFRXP0
M28
AIFRXP1
L29
AIFRXP2
P28
AIFRXP3
N29
AIFRXP4
U29
AIFRXP5
V28
AIFTXN0
L26
AIFTXN1
L27
AIFTXN2
R26
AIFTXN3
P27
AIFTXN4
U27
AIFTXN5
U26
AIFTXP0
M26
AIFTXP1
K27
AIFTXP2
P26
AIFTXP3
N27
AIFTXP4
T27
AIFTXP5
V26
ALTCORECLKN
AB28
ALTCORECLKP
AB29
CVDD
CVDD
CVDD1
P21, R8, R10, R12,
R14, R16, R18, R20,
R22, T9, T11, T13,
T15, T17, T19, T21,
U8, U10, U12, U14,
U16, U18, U20, U22,
V9, V11, V13, V15,
V17, V19, V21, V23
DDRCB06
B18
DDRCB07
A18
DDRCE0
C11
DDRCE1
C12
DDRCKE0
D11
W8, W10, W18, W20,
W22, Y9, Y19, Y21,
Y23, AA8, AA10,
AA12, AA14, AA16,
AA18, AA20, AA22,
AB23
DDRCKE1
E18
DDRCLKN
H29
DDRCLKOUTN0
B12
DDRCLKOUTN1
B16
G6, H1, H3, H5, H7,
H9, J2, J4, J6, J8, J10,
J14, J16, J20, J22, K7,
K9, K13, K15, K17,
K21, L8, L10, L14,
L16, L20, L22, M9,
M21, W12, W14,
W16, Y11, Y13, Y15,
Y17, AD1, AD3, AE2,
AF1, AG2, AH1, AJ2
DDRCLKOUTP0
A12
DDRCLKOUTP1
A16
DDRCLKP
G29
DDRD00
E28
DDRD01
D29
DDRD02
E27
DDRD03
D28
AVDDA1
W24
AVDDA2
J26
DDRA00
A14
DDRD04
D27
AVDDA3
AB15
DDRA01
B14
DDRD05
B28
BOOTCOMPLETE
AC21
DDRA02
F14
DDRD06
E26
BOOTMODE00 †
AG18
DDRA03
F13
DDRD07
F25
BOOTMODE01 †
AD19
DDRA04
A15
DDRD08
F24
BOOTMODE02 †
AE19
DDRA05
C15
DDRD09
E24
BOOTMODE03 †
AF18
DDRA06
B15
DDRD10
E25
BOOTMODE04 †
AE18
DDRA07
D15
DDRD11
D25
BOOTMODE05 †
AG20
DDRA08
F15
DDRD12
D26
BOOTMODE06 †
AH19
DDRA09
E15
DDRD13
C26
BOOTMODE07 †
AJ19
DDRA10
E16
DDRD14
B26
BOOTMODE08 †
AE21
DDRA11
D16
DDRD15
A26
BOOTMODE09 †
AG19
DDRA12
E17
DDRD16
F23
BOOTMODE10 †
AD20
DDRA13
C16
DDRD17
F22
BOOTMODE11 †
AE20
DDRA14
D17
DDRD18
D24
Copyright 2010 Texas Instruments Incorporated
Device Overview
ADVANCE INFORMATION
www.ti.com
47
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 2-17
Terminal Functions
— By Signal Name
(Part 4 of 11)
Signal Name
www.ti.com
Table 2-17
Terminal Functions
— By Signal Name
(Part 5 of 11)
ADVANCE INFORMATION
Ball Number
Signal Name
DDRD19
E23
DDRD20
A23
DDRD21
B23
DDRD63
F1
DDRD22
C24
DDRDQM0
E29
DDRD23
E22
DDRDQM1
DDRD24
D21
DDRDQM2
DDRD25
F20
DDRDQM3
DDRD26
E21
DDRD27
Table 2-17
Terminal Functions
— By Signal Name
(Part 6 of 11)
Ball Number
Signal Name
Ball Number
DDRD61
F3
DVDD18
DDRD62
E1
G28, H25, V5, Y5,
Y25, AB5, AB17,
AB19, AB21, AC2,
AC4, AE24, AE27,
AF19, AF22, AH26,
AH29, AJ28
C27
EMU00
AE29
A25
EMU01
AF29
A22
EMU02
AE28
DDRDQM4
A10
EMU03
AF28
F21
DDRDQM5
A8
EMU04
AE26
DDRD28
D22
DDRDQM6
B5
EMU05
AD25
DDRD29
C21
DDRDQM7
B2
EMU06
AF25
DDRD30
B22
DDRDQM8
A20
EMU07
AE25
DDRD31
C22
DDRDQS0N
C29
EMU08
AF27
DDRD32
E10
DDRDQS0P
C28
EMU09
AG29
DDRD33
D10
DDRDQS1N
B27
EMU10
AF26
DDRD34
B10
DDRDQS1P
A27
EMU11
AG28
DDRD35
D9
DDRDQS2N
B24
EMU12
AG27
DDRD36
E9
DDRDQS2P
A24
EMU13
AG25
DDRD37
C9
DDRDQS3N
B21
EMU14
AH28
DDRD38
B8
DDRDQS3P
A21
EMU15
AJ27
DDRD39
E8
DDRDQS4N
B9
EMU16
AH27
DDRD40
A7
DDRDQS4P
A9
EMU17
AJ26
DDRD41
D7
DDRDQS5N
A6
EMU18
AH25
DDRD42
E7
DDRDQS5P
B6
EXTFRAMEEVENT
AE17
DDRD43
C7
DDRDQS6N
A3
GPIO00
AJ20
DDRD44
B7
DDRDQS6P
B3
GPIO01
AG18
DDRD45
E6
DDRDQS7N
C1
GPIO02
AD19
DDRD46
D6
DDRDQS7P
D1
GPIO03
AE19
DDRD47
C6
DDRDQS8N
B19
GPIO04
AF18
DDRD48
C5
DDRDQS8P
A19
GPIO05
AE18
DDRD49
A5
DDRODT0
D13
GPIO06
AG20
DDRD50
B4
DDRODT1
E13
GPIO07
AH19
DDRD51
A4
DDRRAS
C10
GPIO08
AJ19
DDRD52
D4
DDRRESET
E11
GPIO09
AE21
DDRD53
E4
DDRSLRATE0
H27
GPIO10
AG19
DDRD54
C4
DDRSLRATE1
H26
GPIO11
AD20
DDRD55
C3
DDRWE
E12
GPIO12
AE20
DDRD56
F4
DVDD15
GPIO13
AF21
DDRD57
D2
DDRD58
E2
DDRD59
C2
DDRD60
F2
A2, A11, A17, A28,
B1, B29, C14, C25,
D5, D8, D20, D23,
E3, F5, F7, F9, F11,
F17, F19, F27, G2,
G4, G8, G10, G12,
G14, G16 G18, G20,
G22, G24
48
Device Overview
GPIO14
AH20
GPIO15
AD21
HOUT
AC18
LENDIAN
AJ20 †
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 2-17
Terminal Functions
— By Signal Name
(Part 7 of 11)
Table 2-17
Signal Name
Ball Number
Signal Name
LRESETNMIEN
AC20
LRESET
AE22
MCMCLKN
MCMCLKP
Terminal Functions
— By Signal Name
(Part 8 of 11)
Table 2-17
Terminal Functions
— By Signal Name
(Part 9 of 11)
Ball Number
Signal Name
PCIESSMODE0 †
AH20
RSV0A
K24
PCIESSMODE1 †
AD21
RSV0B
K23
W2
PCIESSEN †
AJ23
RSV10
H23
W1
PCIETXN0
AG14
RSV11
J23
MCMREFCLKOUTN
V1
PCIETXN1
AF12
RSV12
AD22
MCMREFCLKOUTP
V2
PCIETXP0
AG13
RSV13
AC22
MCMRXFLCLK
V3
PCIETXP1
AF13
RSV14
V4
MCMRXFLDAT
W3
PHYSYNC
AB27
RSV15
AE8
MCMRXN0
T2
POR
AC19
RSV16
AE14
MCMRXN1
P1
PTV15
H24
RSV17
AE5
MCMRXN2
L1
RADSYNC
AA27
RSV18
AA24
MCMRXN3
N2
RESETFULL
AE23
RSV19
G27
MCMRXP0
R2
RESETSTAT
AD18
RSV20
AB26
MCMRXP1
R1
RESET
AC24
RSV21
G26
MCMRXP2
M1
RIORXN0
AJ11
RSV22
AE16
MCMRXP3
M2
RIORXN1
AH10
RSV23
AD16
MCMRXPMCLK
AA3
RIORXN2
AJ7
RSV24
AG17
MCMRXPMDAT
Y3
RIORXN3
AH6
RSV25
AF17
MCMTXFLCLK
Y1
RIORXP0
AJ10
RSV26
U25
MCMTXFLDAT
Y2
RIORXP1
AH9
RSV27
L25
MCMTXN0
T5
RIORXP2
AJ8
SCL
AC17
MCMTXN1
R4
RIORXP3
AH7
SDA
AD17
MCMTXN2
L4
RIOTXN0
AG11
SGMII0RXN
AH3
MCMTXN3
M5
RIOTXN1
AF9
SGMII0RXP
AH4
MCMTXP0
R5
RIOTXN2
AG7
SGMII0TXN
AF3
MCMTXP1
P4
RIOTXN3
AF6
SGMII0TXP
AF4
MCMTXP2
M4
RIOTXP0
AG10
SGMII1RXN
AJ4
MCMTXP3
N5
RIOTXP1
AF10
SGMII1RXP
AJ5
MCMTXPMCLK
AA2
RIOTXP2
AG8
SGMII1TXN
AG4
MCMTXPMDAT
AA1
RIOTXP3
AF7
SGMII1TXP
AG5
MDCLK
AF16
RP1CLKN
AA28
SPICLK
AG21
MDIO
AG16
RP1CLKP
Y28
SPIDIN
AH22
NMI
AC25
RP1FBN
AA29
SPIDOUT
AJ21
PACLKSEL
AD23
RP1FBP
Y29
SPISCS0
AH21
PASSCLKN
AH18
RSV01
AJ25
SPISCS1
AJ22
PASSCLKP
AJ18
RSV03
AC23
SRIOSGMIICLKN
AH16
PCIECLKN
AJ17
RSV04
Y27
SRIOSGMIICLKP
AJ16
PCIECLKP
AH17
RSV05
W27
SYSCLKN
AC28
PCIERXN0
AJ14
RSV06
J28
SYSCLKOUT
AA26
PCIERXN1
AH12
RSV07
H28
SYSCLKP
AC29
PCIERXP0
AJ13
RSV08
J24
TCK
AD29
PCIERXP1
AH13
RSV09
J25
TDI
AD28
Copyright 2010 Texas Instruments Incorporated
Ball Number
Device Overview
ADVANCE INFORMATION
www.ti.com
49
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 2-17
Terminal Functions
— By Signal Name
(Part 10 of 11)
Signal Name
www.ti.com
Table 2-17
Terminal Functions
— By Signal Name
(Part 11 of 11)
ADVANCE INFORMATION
Ball Number
Signal Name
Ball Number
TDO
AC27
VSS
TIMI0
AJ23
K22, K26, K28, L2,
L3,L5, L6, L7, L9, L11,
L13, L15, L17, L19,
L21, L23, M3, M6,
M8, M10, M12, M14,
M16, M18, M20,
M22, M24, M27,
M29, N1, N3, N4, N7
VSS
N9, N11, N13, N15,
N17, N19, N21, N23,
N26, N28, P2, P3, P5,
P6, P8, P10, P12,
P14, P16, P18, P20,
P22, P24, R3, R7, R9,
R11, R13, R15, R17,
R19, R21, R23, R27
VSS
R29, T1, T3, T4, T6,
T8, T10, T12, T14,
T16, T18, T20, T22,
T24, T26, T28, U1,
U2, U3, U4, U5, U6,
U7, U9, U11, U13,
U15, U17, U19, U21,
U23, V6, V8, V10
VSS
V12, V14, V16, V18,
V20, V22, V24, V27,
V29, W5, W7, W9,
W11, W13, W15,
W17, W19, W21,
W23, W25, W26,
W28, W29, Y6, Y8,
Y10, Y12, Y14, Y16
VSS
Y18, Y20, Y22, Y24,
Y26, AA5, AA6, AA7,
AA9, AA11, AA13,
AA15, AA17, AA19,
AA21, AA23, AA25,
AB2, AB6, AB7, AB8,
AB9, AB10, AB11,
AB12, AB13, AB14
VSS
AB16, AB18, AB20,
AB22, AB24, AC1,
AC3, AC5, AC7, AC9,
AC11, AC13, AC15,
AD2, AD4, AD6,
AD8, AD10, AD12,
AD14, AD24, AD27,
AE1, AE3, AE7, AE9
VSS
AE13, AF2, AF5, AF8,
AF11, AF14, AF15,
AF20, AG1, AG3,
AG6, AG9, AG12,
AG15, AG22, AG26,
AH2, AH5, AH8,
AH11, AH14, AJ1,
AJ3, AJ6, AJ9, AJ12
VSS
AJ15, AJ29
TIMI1
AG23
TIMO0
AH23
TIMO1
AF23
TMS
AC26
TRST
AD26
UARTCTS
AH24
UARTRTS
AG24
UARTRXD
AF24
UARTTXD
AJ24
VCL
Y4
VCNTL0
AB4
VCNTL1
AB3
VCNTL2
AA4
VCNTL3
AB1
VD
W4
VDDR1
K6
VDDR2
AE15
VDDR3
AE6
VDDR4
AE11
VDDR5
R25
VDDR6
N25
VDDT1
M7, N6, P7, R6, T7,
V7, W6, Y7
VDDT2
AC6, AC8, AC10,
AC12, AC14, AD5,
AD7, AD9, AD11,
AD13, AE4, AE10,
AE12
VDDT3
K25, L24, M23, M25,
N24, P23, P25, R24,
T23, T25, U24, V25
VREFSSTL
E14
VSS
A1, A29, B11, B17,
B25, C8, C23, D3,
D14, D18, E5, E20,
F6, F8, F10, F12, F16,
F18, F26, F28, F29,
G1, G3, G5, G7, G9,
G11, G13, G15, G17,
G19, G21, G23, G25
VSS
50
H2, H4, H6, H8, H10,
H12, H14, H16, H18,
H20, H22, J1, J3, J5,
J7, J9, J11, J13, J15,
J17, J19, J21, J27,
J29, K1, K2, K3, K4,
K5, K8, K10, K12,
K14, K16, K18, K20
Device Overview
End of Table 2-17
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 2-18
Terminal Functions
— By Ball Number
(Part 1 of 21)
Table 2-18
Terminal Functions
— By Ball Number
(Part 2 of 21)
Table 2-18
Terminal Functions
— By Ball Number
(Part 3 of 21)
Signal Name
Ball Number
Signal Name
Ball Number
Signal Name
A1
VSS
B14
DDRA01
C27
DDRDQM1
A2
DVDD15
B15
DDRA06
C28
DDRDQS0P
A3
DDRDQS6N
B16
DDRCLKOUTN1
C29
DDRDQS0N
A4
DDRD51
B17
VSS
D1
DDRDQS7P
A5
DDRD49
B18
DDRCB06
D2
DDRD57
A6
DDRDQS5N
B19
DDRDQS8N
D3
VSS
A7
DDRD40
B20
DDRCB03
D4
DDRD52
A8
DDRDQM5
B21
DDRDQS3N
D5
DVDD15
A9
DDRDQS4P
B22
DDRD30
D6
DDRD46
A10
DDRDQM4
B23
DDRD21
D7
DDRD41
A11
DVDD15
B24
DDRDQS2N
D8
DVDD15
A12
DDRCLKOUTP0
B25
VSS
D9
DDRD35
A13
DDRBA0
B26
DDRD14
D10
DDRD33
A14
DDRA00
B27
DDRDQS1N
D11
DDRCKE0
A15
DDRA04
B28
DDRD05
D12
DDRCAS
A16
DDRCLKOUTP1
B29
DVDD15
D13
DDRODT0
A17
DVDD15
C1
DDRDQS7N
D14
VSS
A18
DDRCB07
C2
DDRD59
D15
DDRA07
A19
DDRDQS8P
C3
DDRD55
D16
DDRA11
A20
DDRDQM8
C4
DDRD54
D17
DDRA14
A21
DDRDQS3P
C5
DDRD48
D18
VSS
A22
DDRDQM3
C6
DDRD47
D19
DDRCB02
A23
DDRD20
C7
DDRD43
D20
DVDD15
A24
DDRDQS2P
C8
VSS
D21
DDRD24
A25
DDRDQM2
C9
DDRD37
D22
DDRD28
A26
DDRD15
C10
DDRRAS
D23
DVDD15
A27
DDRDQS1P
C11
DDRCE0
D24
DDRD18
A28
DVDD15
C12
DDRCE1
D25
DDRD11
A29
VSS
C13
DDRBA2
D26
DDRD12
B1
DVDD15
C14
DVDD15
D27
DDRD04
B2
DDRDQM7
C15
DDRA05
D28
DDRD03
B3
DDRDQS6P
C16
DDRA13
D29
DDRD01
B4
DDRD50
C17
DDRA15
E1
DDRD62
B5
DDRDQM6
C18
DDRCB05
E2
DDRD58
B6
DDRDQS5P
C19
DDRCB04
E3
DVDD15
B7
DDRD44
C20
DDRCB01
E4
DDRD53
B8
DDRD38
C21
DDRD29
E5
VSS
B9
DDRDQS4N
C22
DDRD31
E6
DDRD45
B10
DDRD34
C23
VSS
E7
DDRD42
B11
VSS
C24
DDRD22
E8
DDRD39
B12
DDRCLKOUTN0
C25
DVDD15
E9
DDRD36
B13
DDRBA1
C26
DDRD13
E10
DDRD32
Ball Number
Copyright 2010 Texas Instruments Incorporated
Device Overview
ADVANCE INFORMATION
www.ti.com
51
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 2-18
Terminal Functions
— By Ball Number
(Part 4 of 21)
Ball Number
www.ti.com
Table 2-18
Terminal Functions
— By Ball Number
(Part 5 of 21)
Table 2-18
Terminal Functions
— By Ball Number
(Part 6 of 21)
ADVANCE INFORMATION
Signal Name
Ball Number
Signal Name
Ball Number
E11
DDRRESET
F24
DDRD08
H8
VSS
E12
DDRWE
F25
DDRD07
H9
CVDD1
E13
DDRODT1
F26
VSS
H10
VSS
E14
VREFSSTL
F27
DVDD15
H11
CVDD
E15
DDRA09
F28
VSS
H12
VSS
E16
DDRA10
F29
VSS
H13
CVDD
E17
DDRA12
G1
VSS
H14
VSS
E18
DDRCKE1
G2
DVDD15
H15
CVDD
E19
DDRCB00
G3
VSS
H16
VSS
E20
VSS
G4
DVDD15
H17
CVDD
E21
DDRD26
G5
VSS
H18
VSS
E22
DDRD23
G6
CVDD1
H19
CVDD
E23
DDRD19
G7
VSS
H20
VSS
E24
DDRD09
G8
DVDD15
H21
CVDD
E25
DDRD10
G9
VSS
H22
VSS
E26
DDRD06
G10
DVDD15
H23
RSV10
E27
DDRD02
G11
VSS
H24
PTV15
E28
DDRD00
G12
DVDD15
H25
DVDD18
E29
DDRDQM0
G13
VSS
H26
DDRSLRATE1
F1
DDRD63
G14
DVDD15
H27
DDRSLRATE0
F2
DDRD60
G15
VSS
H28
RSV07
F3
DDRD61
G16
DVDD15
H29
DDRCLKN
F4
DDRD56
G17
VSS
J1
VSS
F5
DVDD15
G18
DVDD15
J2
CVDD1
F6
VSS
G19
VSS
J3
VSS
F7
DVDD15
G20
DVDD15
J4
CVDD1
F8
VSS
G21
VSS
J5
VSS
F9
DVDD15
G22
DVDD15
J6
CVDD1
F10
VSS
G23
VSS
J7
VSS
F11
DVDD15
G24
DVDD15
J8
CVDD1
F12
VSS
G25
VSS
J9
VSS
F13
DDRA03
G26
RSV21
J10
CVDD1
F14
DDRA02
G27
RSV19
J11
VSS
F15
DDRA08
G28
DVDD18
J12
CVDD
F16
VSS
G29
DDRCLKP
J13
VSS
F17
DVDD15
H1
CVDD1
J14
CVDD1
F18
VSS
H2
VSS
J15
VSS
F19
DVDD15
H3
CVDD1
J16
CVDD1
F20
DDRD25
H4
VSS
J17
VSS
F21
DDRD27
H5
CVDD1
J18
CVDD
F22
DDRD17
H6
VSS
J19
VSS
F23
DDRD16
H7
CVDD1
J20
CVDD1
52
Device Overview
Signal Name
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 2-18
Terminal Functions
— By Ball Number
(Part 7 of 21)
Table 2-18
Terminal Functions
— By Ball Number
(Part 8 of 21)
Table 2-18
Terminal Functions
— By Ball Number
(Part 9 of 21)
Ball Number
Signal Name
Ball Number
Signal Name
Ball Number
J21
VSS
L5
VSS
M18
VSS
J22
CVDD1
L6
VSS
M19
CVDD
J23
RSV11
L7
VSS
M20
VSS
J24
RSV08
L8
CVDD1
M21
CVDD1
J25
RSV09
L9
VSS
M22
VSS
J26
AVDDA2
L10
CVDD1
M23
VDDT3
J27
VSS
L11
VSS
M24
VSS
J28
RSV06
L12
CVDD
M25
VDDT3
J29
VSS
L13
VSS
M26
AIFTXP0
K1
VSS
L14
CVDD1
M27
VSS
K2
VSS
L15
VSS
M28
AIFRXP0
K3
VSS
L16
CVDD1
M29
VSS
K4
VSS
L17
VSS
N1
VSS
K5
VSS
L18
CVDD
N2
MCMRXN3
K6
VDDR1
L19
VSS
N3
VSS
K7
CVDD1
L20
CVDD1
N4
VSS
K8
VSS
L21
VSS
N5
MCMTXP3
K9
CVDD1
L22
CVDD1
N6
VDDT1
K10
VSS
L23
VSS
N7
VSS
K11
CVDD
L24
VDDT3
N8
CVDD
K12
VSS
L25
RSV27
N9
VSS
K13
CVDD1
L26
AIFTXN0
N10
CVDD
K14
VSS
L27
AIFTXN1
N11
VSS
K15
CVDD1
L28
AIFRXN0
N12
CVDD
K16
VSS
L29
AIFRXP1
N13
VSS
K17
CVDD1
M1
MCMRXP2
N14
CVDD
K18
VSS
M2
MCMRXP3
N15
VSS
K19
CVDD
M3
VSS
N16
CVDD
K20
VSS
M4
MCMTXP2
N17
VSS
K21
CVDD1
M5
MCMTXN3
N18
CVDD
K22
VSS
M6
VSS
N19
VSS
K23
RSV0B
M7
VDDT1
N20
CVDD
K24
RSV0A
M8
VSS
N21
VSS
K25
VDDT3
M9
CVDD1
N22
CVDD
K26
VSS
M10
VSS
N23
VSS
K27
AIFTXP1
M11
CVDD
N24
VDDT3
K28
VSS
M12
VSS
N25
VDDR6
K29
AIFRXN1
M13
CVDD
N26
VSS
L1
MCMRXN2
M14
VSS
N27
AIFTXP3
L2
VSS
M15
CVDD
N28
VSS
L3
VSS
M16
VSS
N29
AIFRXP3
L4
MCMTXN2
M17
CVDD
P1
MCMRXN1
Copyright 2010 Texas Instruments Incorporated
Signal Name
Device Overview
ADVANCE INFORMATION
www.ti.com
53
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 2-18
Terminal Functions
— By Ball Number
(Part 10 of 21)
www.ti.com
Table 2-18
Terminal Functions
— By Ball Number
(Part 11 of 21)
Table 2-18
Terminal Functions
— By Ball Number
(Part 12 of 21)
ADVANCE INFORMATION
Ball Number
Signal Name
Ball Number
Signal Name
Ball Number
Signal Name
P2
VSS
R15
VSS
T28
VSS
P3
VSS
R16
CVDD
T29
AIFRXN4
P4
MCMTXP1
R17
VSS
U1
VSS
P5
VSS
R18
CVDD
U2
VSS
P6
VSS
R19
VSS
U3
VSS
P7
VDDT1
R20
CVDD
U4
VSS
P8
VSS
R21
VSS
U5
VSS
P9
CVDD
R22
CVDD
U6
VSS
P10
VSS
R23
VSS
U7
VSS
P11
CVDD
R24
VDDT3
U8
CVDD
P12
VSS
R25
VDDR5
U9
VSS
P13
CVDD
R26
AIFTXN2
U10
CVDD
P14
VSS
R27
VSS
U11
VSS
P15
CVDD
R28
AIFRXN2
U12
CVDD
P16
VSS
R29
VSS
U13
VSS
P17
CVDD
T1
VSS
U14
CVDD
P18
VSS
T2
MCMRXN0
U15
VSS
P19
CVDD
T3
VSS
U16
CVDD
P20
VSS
T4
VSS
U17
VSS
P21
CVDD
T5
MCMTXN0
U18
CVDD
P22
VSS
T6
VSS
U19
VSS
P23
VDDT3
T7
VDDT1
U20
CVDD
P24
VSS
T8
VSS
U21
VSS
P25
VDDT3
T9
CVDD
U22
CVDD
P26
AIFTXP2
T10
VSS
U23
VSS
P27
AIFTXN3
T11
CVDD
U24
VDDT3
P28
AIFRXP2
T12
VSS
U25
RSV26
P29
AIFRXN3
T13
CVDD
U26
AIFTXN5
R1
MCMRXP1
T14
VSS
U27
AIFTXN4
R2
MCMRXP0
T15
CVDD
U28
AIFRXN5
R3
VSS
T16
VSS
U29
AIFRXP4
R4
MCMTXN1
T17
CVDD
V1
MCMREFCLKOUTN
R5
MCMTXP0
T18
VSS
V2
MCMREFCLKOUTP
R6
VDDT1
T19
CVDD
V3
MCMRXFLCLK
R7
VSS
T20
VSS
V4
RSV14
R8
CVDD
T21
CVDD
V5
DVDD18
R9
VSS
T22
VSS
V6
VSS
R10
CVDD
T23
VDDT3
V7
VDDT1
R11
VSS
T24
VSS
V8
VSS
R12
CVDD
T25
VDDT3
V9
CVDD
R13
VSS
T26
VSS
V10
VSS
R14
CVDD
T27
AIFTXP4
V11
CVDD
54
Device Overview
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 2-18
Terminal Functions
— By Ball Number
(Part 13 of 21)
Table 2-18
Terminal Functions
— By Ball Number
(Part 14 of 21)
Table 2-18
Terminal Functions
— By Ball Number
(Part 15 of 21)
Ball Number
Signal Name
Ball Number
Signal Name
Ball Number
Signal Name
V12
VSS
W25
VSS
AA9
VSS
V13
CVDD
W26
VSS
AA10
CVDD
V14
VSS
W27
RSV05
AA11
VSS
V15
CVDD
W28
VSS
AA12
CVDD
V16
VSS
W29
VSS
AA13
VSS
V17
CVDD
Y1
MCMTXFLCLK
AA14
CVDD
V18
VSS
Y2
MCMTXFLDAT
AA15
VSS
V19
CVDD
Y3
MCMRXPMDAT
AA16
CVDD
V20
VSS
Y4
VCL
AA17
VSS
V21
CVDD
Y5
DVDD18
AA18
CVDD
V22
VSS
Y6
VSS
AA19
VSS
V23
CVDD
Y7
VDDT1
AA20
CVDD
V24
VSS
Y8
VSS
AA21
VSS
V25
VDDT3
Y9
CVDD
AA22
CVDD
V26
AIFTXP5
Y10
VSS
AA23
VSS
V27
VSS
Y11
CVDD1
AA24
RSV18
V28
AIFRXP5
Y12
VSS
AA25
VSS
V29
VSS
Y13
CVDD1
AA26
SYSCLKOUT
W1
MCMCLKP
Y14
VSS
AA27
RADSYNC
W2
MCMCLKN
Y15
CVDD1
AA28
RP1CLKN
W3
MCMRXFLDAT
Y16
VSS
AA29
RP1FBN
W4
VD
Y17
CVDD1
AB1
VCNTL3
W5
VSS
Y18
VSS
AB2
VSS
W6
VDDT1
Y19
CVDD
AB3
VCNTL1
W7
VSS
Y20
VSS
AB4
VCNTL0
W8
CVDD
Y21
CVDD
AB5
DVDD18
W9
VSS
Y22
VSS
AB6
VSS
W10
CVDD
Y23
CVDD
AB7
VSS
W11
VSS
Y24
VSS
AB8
VSS
W12
CVDD1
Y25
DVDD18
AB9
VSS
W13
VSS
Y26
VSS
AB10
VSS
W14
CVDD1
Y27
RSV04
AB11
VSS
W15
VSS
Y28
RP1CLKP
AB12
VSS
W16
CVDD1
Y29
RP1FBP
AB13
VSS
W17
VSS
AA1
MCMTXPMDAT
AB14
VSS
W18
CVDD
AA2
MCMTXPMCLK
AB15
AVDDA3
W19
VSS
AA3
MCMRXPMCLK
AB16
VSS
W20
CVDD
AA4
VCNTL2
AB17
DVDD18
W21
VSS
AA5
VSS
AB18
VSS
W22
CVDD
AA6
VSS
AB19
DVDD18
W23
VSS
AA7
VSS
AB20
VSS
W24
AVDDA1
AA8
CVDD
AB21
DVDD18
Copyright 2010 Texas Instruments Incorporated
Device Overview
ADVANCE INFORMATION
www.ti.com
55
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 2-18
Terminal Functions
— By Ball Number
(Part 16 of 21)
Ball Number
www.ti.com
Table 2-18
Terminal Functions
— By Ball Number
(Part 17 of 21)
Table 2-18
Terminal Functions
— By Ball Number
(Part 18 of 21)
ADVANCE INFORMATION
Signal Name
Ball Number
Signal Name
Ball Number
Signal Name
AB22
VSS
AD6
VSS
AE16
RSV22
AB23
CVDD
AD7
VDDT2
AE17
EXTFRAMEEVENT
AB24
VSS
AD8
VSS
AE18
GPIO05
AB25
CORECLKSEL
AD9
VDDT2
AE18 †
BOOTMODE04
AB26
RSV20
AD10
VSS
AE19
GPIO03
AB27
PHYSYNC
AD11
VDDT2
AE19 †
BOOTMODE02
AB28
ALTCORECLKN
AD12
VSS
AE20
GPIO12
AB29
ALTCORECLKP
AD13
VDDT2
AE20 †
BOOTMODE11
AC1
VSS
AD14
VSS
AE21
GPIO09
AC2
DVDD18
AD15
CORESEL2
AE22
LRESET
AC3
VSS
AD16
RSV23
AE23
RESETFULL
AC4
DVDD18
AD17
SDA
AE24
DVDD18
AC5
VSS
AD18
RESETSTAT
AE25
EMU07
AC6
VDDT2
AD19
GPIO02
AE26
EMU04
AC7
VSS
AD19 †
BOOTMODE01
AE27
DVDD18
AC8
VDDT2
AD20
GPIO11
AE28
EMU02
AC9
VSS
AD20 †
BOOTMODE10
AE29
EMU00
AC10
VDDT2
AD21
GPIO15
AF1
CVDD1
AC11
VSS
AD21 †
PCIESSMODE1
AF2
VSS
AC12
VDDT2
AD22
RSV12
AF3
SGMII0TXN
AC13
VSS
AD23
PACLKSEL
AF4
SGMII0TXP
AC14
VDDT2
AD24
VSS
AF5
VSS
AC15
VSS
AD25
EMU05
AF6
RIOTXN3
AC16
CORESEL1
AD26
TRST
AF7
RIOTXP3
AC17
SCL
AD27
VSS
AF8
VSS
AC18
HOUT
AD28
TDI
AF9
RIOTXN1
AC19
POR
AD29
TCK
AF10
RIOTXP1
AC20
LRESETNMIEN
AE1
VSS
AF11
VSS
AC21
BOOTCOMPLETE
AE2
CVDD1
AF12
PCIETXN1
AC22
RSV13
AE3
VSS
AF13
PCIETXP1
AC23
RSV03
AE4
VDDT2
AF14
VSS
AC24
RESET
AE5
RSV17
AF15
VSS
AC25
NMI
AE6
VDDR3
AF16
MDCLK
AC26
TMS
AE7
VSS
AF17
RSV25
AC27
TDO
AE8
RSV15
AF18
GPIO04
AC28
SYSCLKN
AE9
VSS
AF18 †
BOOTMODE03
AC29
SYSCLKP
AE10
VDDT2
AF19
DVDD18
AD1
CVDD1
AE11
VDDR4
AF20
VSS
AD2
VSS
AE12
VDDT2
AF21
GPIO13
AD3
CVDD1
AE13
VSS
AF21 †
BOOTMODE12
AD4
VSS
AE14
RSV16
AF22
DVDD18
AD5
VDDT2
AE15
VDDR2
AF23
TIMO1
56
Device Overview
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Terminal Functions
— By Ball Number
(Part 19 of 21)
Table 2-18
Terminal Functions
— By Ball Number
(Part 20 of 21)
Table 2-18
Terminal Functions
— By Ball Number
(Part 21 of 21)
Ball Number
Signal Name
Ball Number
Signal Name
Ball Number
Signal Name
AF24
UARTRXD
AH6
RIORXN3
AJ17
PCIECLKN
AF25
EMU06
AH7
RIORXP3
AJ18
PASSCLKP
AF26
EMU10
AH8
VSS
AJ19
GPIO08
AF27
EMU08
AH9
RIORXP1
AJ19 †
BOOTMODE07
AF28
EMU03
AH10
RIORXN1
AJ20
GPIO00
AF29
EMU01
AH11
VSS
AJ20 †
LENDIAN
AG1
VSS
AH12
PCIERXN1
AJ21
SPIDOUT
AG2
CVDD1
AH13
PCIERXP1
AJ22
SPISCS1
AG3
VSS
AH14
VSS
AJ23
TIMI0
AG4
SGMII1TXN
AH15
CORESEL0
AJ23 †
PCIESSEN
AG5
SGMII1TXP
AH16
SRIOSGMIICLKN
AJ24
UARTTXD
AG6
VSS
AH17
PCIECLKP
AJ25
RSV01
AG7
RIOTXN2
AH18
PASSCLKN
AJ26
EMU17
AG8
RIOTXP2
AH19
GPIO07
AJ27
EMU15
AG9
VSS
AH19 †
BOOTMODE06
AJ28
DVDD18
AG10
RIOTXP0
AH20
GPIO14
AJ29
VSS
AG11
RIOTXN0
AH20 †
PCIESSMODE0
End of Table 2-18
AG12
VSS
AH21
SPISCS0
AG13
PCIETXP0
AH22
SPIDIN
AG14
PCIETXN0
AH23
TIMO0
AG15
VSS
AH24
UARTCTS
AG16
MDIO
AH25
EMU18
AG17
RSV24
AH26
DVDD18
AG18
GPIO01
AH27
EMU16
AG18 †
BOOTMODE00
AH28
EMU14
AG19
GPIO10
AH29
DVDD18
AG20
GPIO06
AJ1
VSS
AG20 †
BOOTMODE05
AJ2
CVDD1
AG21
SPICLK
AJ3
VSS
AG22
VSS
AJ4
SGMII1RXN
AG23
TIMI1
AJ5
SGMII1RXP
AG24
UARTRTS
AJ6
VSS
AG25
EMU13
AJ7
RIORXN2
AG26
VSS
AJ8
RIORXP2
AG27
EMU12
AJ9
VSS
AG28
EMU11
AJ10
RIORXP0
AG29
EMU09
AJ11
RIORXN0
AH1
CVDD1
AJ12
VSS
AH2
VSS
AJ13
PCIERXP0
AH3
SGMII0RXN
AJ14
PCIERXN0
AH4
SGMII0RXP
AJ15
VSS
AH5
VSS
AJ16
SRIOSGMIICLKP
Copyright 2010 Texas Instruments Incorporated
Device Overview
ADVANCE INFORMATION
Table 2-18
57
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
2.9 Development
2.9.1 Development Support
In case the customer would like to develop their own features and software on the C6670 device, TI offers an
extensive line of development tools for the TMS320C6000™ DSP platform, including tools to evaluate the
performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug
software and hardware modules. The tool's support documentation is electronically available within the Code
Composer Studio™ Integrated Development Environment (IDE).
ADVANCE INFORMATION
The following products support development of C6000™ DSP-based applications:
• Software Development Tools:
– Code Composer Studio™ Integrated Development Environment (IDE), including Editor C/C++/Assembly
Code Generation, and Debug plus additional development tools
– Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target software
needed to support any DSP application.
• Hardware Development Tools:
– Extended Development System (XDS™) Emulator (supports C6000™ DSP multiprocessor system debug)
– EVM (Evaluation Module)
2.9.2 Device Support
2.9.2.1 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices
and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g.,
TMX320CMH). Texas Instruments recommends two of three possible prefix designators for its support tools:
TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering
prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
• TMX: Experimental device that is not necessarily representative of the final device's electrical specifications
• TMP: Final silicon die that conforms to the device's electrical specifications but has not completed quality and
reliability verification
• TMS: Fully qualified production device
Support tool development evolutionary flow:
• TMDX: Development-support product that has not yet completed Texas Instruments internal qualification
testing.
• TMDS: Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped with the following disclaimer:
Developmental product is intended for internal evaluation purposes.
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of
the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
58
Device Overview
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Related Documentation from Texas Instruments
64-bit Timer (Timer 64) for KeyStone Devices User Guide
SPRUGV5
Antenna Interface 2 (AIF2) for KeyStone Devices User Guide
SPRUGV7
Bootloader for the C66x DSP User Guide
SPRUGY5
C66x CorePac User Guide
SPRUGW0
C66x CPU and Instruction Set Reference Guide
SPRUGH7
C66x DSP Cache User Guide
SPRUGY8
DDR3 Design Guide for KeyStone Devices
SPRABI1
Emulation and Trace Headers Technical Reference
SPRU655
Enhanced Direct Memory Access 3 (EDMA3) for KeyStone Devices User Guide
SPRUGS5
Ethernet Media Access Control (EMAC) for KeyStone Devices User Guide
SPRUGV9
Fast Fourier Transform Coprocessor (FFTC) for KeyStone Devices User Guide
SPRUGS2
General Purpose Input/Output (GPIO) for KeyStone Devices User Guide
SPRUGV1
Hardware Design Guide for KeyStone Devices
SPRABI2
HyperLink for KeyStone Devices User Guide
SPRUGW8
2
Inter Integrated Circuit (I C) for KeyStone Devices User Guide
SPRUGV3
Interrupt Controller (INTC) for KeyStone Devices User Guide
SPRUGW4
Memory Protection Unit (MPU) for KeyStone Devices User Guide
SPRUGW5
Multicore Navigator for KeyStone Devices User Guide
SPRUGR9
Multicore Shared Memory Controller (MSMC) for KeyStone Devices User Guide
SPRUGW7
Packet Accelerator (PA) for KeyStone Devices User Guide
SPRUGS4
Peripheral Component Interconnect Express (PCIe) for KeyStone Devices User Guide
SPRUGS6
Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide
SPRUGV2
Power Management for KeyStone Devices
SPRABH0
Power Sleep Controller (PSC) for KeyStone Devices User Guide
SPRUGV4
Rake Search Accelerator (RSA) for KeyStone Devices User Guide
SPRUGY7
Serial Peripheral Interface (SPI) for KeyStone Devices User Guide
SPRUGP2
Serial RapidIO (SRIO) for KeyStone Devices User Guide
SPRUGW1
Turbo Decoder Coprocessor 3 (TCP3d) for KeyStone Devices User Guide
SPRUGS0
Turbo Encoder Coprocessor 3 (TCP3e) for KeyStone Devices User Guide
SPRUGS1
Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices User Guide
SPRUGP1
Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded Microprocessor Systems
SPRA387
Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs
SPRA753
Using IBIS Models for Timing Analysis
SPRA839
Viterbi Coprocessor (VCP2) for KeyStone Devices User Guide
SPRUGV6
Copyright 2010 Texas Instruments Incorporated
Device Overview
ADVANCE INFORMATION
These documents describe the TMS320C6670 Multicore Fixed and Floating-Point System-on-Chip. Copies of these
documents are available on the Internet at www.ti.com
59
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
3 Device Configuration
On the TMS320C6670 device, certain device configurations like boot mode and endianess, are selected at device
power-on reset. The status of the peripherals (enabled/disabled) is determined after device power-on reset. By
default, the peripherals on the device are disabled and need to be enabled by software before being used.
3.1 Device Configuration at Device Reset
ADVANCE INFORMATION
Table 3-1 describes the device configuration pins. The logic level is latched at power-on reset to determine the device
configuration. The logic level on the device configuration pins can be set by using external pullup/pulldown resistors
or by using some control device (e.g., FPGA/CPLD) to intelligently drive these pins. When using a control device,
care should be taken to ensure there is no contention on the lines when the device is out of reset. The device
configuration pins are sampled during power-on reset and are driven after the reset is removed. To avoid
contention, the control device must stop driving the device configuration pins of the DSP.
Note—If a configuration pin must be routed out from the device and it is not driven (Hi-Z state), the internal
pullup/pulldown (IPU/IPD) resistor should not be relied upon. TI recommends the use of an external
pullup/pulldown resistor. For more detailed information on pullup/pulldown resistors and situations in
which external pullup/pulldown resistors are required, see Section 3.4 ‘‘Pullup/Pulldown Resistors’’ on
page 76.
Table 3-1
TMS320C6670 Device Configuration Pins
Configuration Pin
Pin No.
IPD/IPU
(1)
Functional Description
(1) (2)
AJ20
IPU
Device endian mode (LENDIAN).
0 = Device operates in big endian mode
1 = Device operates in little endian mode
BOOTMODE[12:0] (1) (2)
AF21, AE20, AD20,
AG19, AE21, AJ19,
AH19, AG20, AE18,
AF18, AE19, AD19,
AG18
IPD
Method of boot.
See ‘‘Boot Modes Supported and PLL Settings’’ on page 27 for more details. See the
Bootloader for the C66x DSP User Guide in ‘‘Related Documentation from Texas
Instruments’’ on page 59 for detailed information on boot configuration
AD21, AH20
IPD
PCIe Subsystem mode selection.
00 = PCIe in end point mode
01 = PCIe legacy end point (no support for MSI)
10 = PCIe in root complex mode
11 = Reserved
(1) (2)
AJ23
IPD
PCIe subsystem enable/disable.
0 = PCIE Subsystem is disabled
1 = PCIE Subsystem is enabled
CORECLKSEL
(1)
AB25
IPD
Core clock select.
0 = SYSCLK is used as the input to Main PLL
1 = ALTCORECLK is used as the input to Main PLL
PACLKSEL(1)
AD23
IPD
Packet accelerator subsystem clock select.
0 = SYSCLK / ALTCORECLK (controlled by CORECLKSEL pin) is used as the input to PA_SS
PLL
1 = PASSCLK is used as the input to PASS PLL
LENDIAN
PCIESSMODE[1:0]
PCIESSEN
(1) (2)
End of Table 3-1
1 Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can be used to oppose the IPD/IPU. For more detailed information on
pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see Section 3.4 ‘‘Pullup/Pulldown Resistors’’ on page 76.
2 These signal names are the secondary functions of these pins.
60
Device Configuration
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
3.2 Peripheral Selection After Device Reset
Several of the peripherals on the TMS320C6670 are controlled by the Power Sleep Controller (PSC). By default, the
PCIe, SRIO, HyperLink, FFTC, AIF2, TCP3d, TCP3e, and VCP are held in reset and clock-gated. The memories in
these modules are also in a low-leakage sleep mode. Software is required to turn these memories on. Then, the
software enables the modules (turns on clocks and de-asserts reset) before these modules can be used.
All other modules come up enabled by default and there is no special software sequence to enable. For more detailed
information on the PSC usage, see the Power Sleep Controller (PSC) for KeyStone Devices User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 59.
3.3 Device State Control Registers
The TMS320C6670 device has a set of registers that are used to control the status of its peripherals. These registers
are shown in Table 3-2.
Table 3-2
Device State Control Registers (Part 1 of 3)
Address Start
Address End
Size
Acronym
0x02620000
0x02620007
8B
Reserved
0x02620008
0x02620017
16B
Reserved
0x02620018
0x0262001B
4B
JTAGID
0x0262001C
0x0262001F
4B
Reserved
0x02620020
0x02620023
4B
DEVSTAT
Description
See section 3.3.3
See section 3.3.1
0x02620024
0x02620037
20B
Reserved
0x02620038
0x0262003B
4B
KICK0
0x0262003C
0x0262003F
4B
KICK1
0x02620040
0x02620043
4B
DSP_BOOT_ADDR0
The boot address for C66x DSP CorePac 0
0x02620044
0x02620047
4B
DSP_BOOT_ADDR1
The boot address for C66x DSP CorePac 1
0x02620048
0x0262004B
4B
DSP_BOOT_ADDR2
The boot address for C66x DSP CorePac 2
The boot address for C66x DSP CorePac 3
See section 3.3.4
0x0262004C
0x0262004F
4B
DSP_BOOT_ADDR3
0x02620050
0x02620053
4B
Reserved
0x02620054
0x02620057
4B
Reserved
0x02620058
0x0262005B
4B
Reserved
0x0262005C
0x0262005F
4B
Reserved
0x02620060
0x026200DF
128B
Reserved
0x026200E0
0x0262010F
48B
Reserved
0x02620110
0x02620117
8B
MACID
0x02620118
0x0262012F
24B
Reserved
0x02620130
0x02620133
4B
LRSTNMIPINSTAT_CLR
See section 3.3.6
See section 3.3.8
0x02620134
0x02620137
4B
RESET_STAT_CLR
0x02620138
0x0262013B
4B
Reserved
0x0262013C
0x0262013F
4B
BOOTCOMPLETE
0x02620140
0x02620143
4B
Reserved
See section 7.19 ‘‘Ethernet MAC (EMAC)’’ on page 190
See section 3.3.9
0x02620144
0x02620147
4B
RESET_STAT
See section 3.3.7
0x02620148
0x0262014B
4B
LRSTNMIPINSTAT
See section 3.3.5
0x0262014C
0x0262014F
4B
DEVCFG
See section 3.3.2
Copyright 2010 Texas Instruments Incorporated
Device Configuration
61
ADVANCE INFORMATION
If one of the above modules is used in the selected ROM boot mode, the ROM code will automatically enable the
module.
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 3-2
www.ti.com
Device State Control Registers (Part 2 of 3)
ADVANCE INFORMATION
Address Start
Address End
Size
Acronym
Description
0x02620150
0x02620153
4B
PWRSTATECTL
See section 3.3.10
0x02620154
0x0262017F
44B
Reserved
0x02620180
0x02620183
4B
Reserved
0x02620184
0x0262018F
12B
Reserved
0x02620190
0x02620193
4B
Reserved
0x02620194
0x02620197
4B
Reserved
0x02620198
0x0262019B
4B
Reserved
0x0262019C
0x0262019F
4B
Reserved
0x026201A0
0x026201A3
4B
Reserved
0x026201A4
0x026201A7
4B
Reserved
0x026201A8
0x026201AB
4B
Reserved
0x026201AC
0x026201AF
4B
Reserved
0x026201B0
0x026201B3
4B
Reserved
0x026201B4
0x026201B7
4B
Reserved
0x026201B8
0x026201BB
4B
Reserved
0x026201BC
0x026201BF
4B
Reserved
0x026201C0
0x026201C3
4B
Reserved
0x026201C4
0x026201C7
4B
Reserved
0x026201C8
0x026201CB
4B
Reserved
0x026201CC
0x026201CF
4B
Reserved
0x026201D0
0x026201FF
48B
Reserved
0x02620200
0x02620203
4B
NMIGR0
0x02620204
0x02620207
4B
NMIGR1
0x02620208
0x0262020B
4B
NMIGR2
0x0262020C
0x0262020F
4B
NMIGR3
0x02620210
0x02620213
4B
Reserved
0x02620214
0x02620217
4B
Reserved
0x02620218
0x0262021B
4B
Reserved
0x0262021C
0x0262021F
4B
Reserved
0x02620220
0x0262023F
32B
Reserved
0x02620240
0x02620243
4B
IPCGR0
0x02620244
0x02620247
4B
IPCGR1
0x02620248
0x0262024B
4B
IPCGR2
0x0262024C
0x0262024F
4B
IPCGR3
0x02620250
0x02620253
4B
Reserved
0x02620254
0x02620257
4B
Reserved
0x02620258
0x0262025B
4B
Reserved
0x0262025C
0x0262025F
4B
Reserved
0x02620260
0x0262027B
28B
Reserved
0x0262027C
0x0262027F
4B
IPCGRH
62
Device Configuration
See section 3.3.11
See section 3.3.12
See section 3.3.14
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Device State Control Registers (Part 3 of 3)
Address Start
Address End
Size
Acronym
Description
0x02620280
0x02620283
4B
IPCAR0
See section 3.3.13
0x02620284
0x02620287
4B
IPCAR1
0x02620288
0x0262028B
4B
IPCAR2
0x0262028C
0x0262028F
4B
IPCAR3
0x02620290
0x02620293
4B
Reserved
0x02620294
0x02620297
4B
Reserved
0x02620298
0x0262029B
4B
Reserved
0x0262029C
0x0262029F
4B
Reserved
0x026202A0
0x026202BB
28B
Reserved
0x026202BC
0x026202BF
4B
IPCARH
0x026202C0
0x026202FF
64B
Reserved
See section 3.3.15
0x02620300
0x02620303
4B
TINPSEL
See section 3.3.16
0x02620304
0x02620307
4B
TOUTPSEL
See section 3.3.17
See section 3.3.18
0x02620308
0x0262030B
4B
RSTMUX0
0x0262030C
0x0262030F
4B
RSTMUX1
0x02620310
0x02620313
4B
RSTMUX2
0x02620314
0x02620317
4B
RSTMUX3
0x02620318
0x0262031B
4B
Reserved
0x0262031C
0x0262031F
4B
Reserved
0x02620320
0x02620323
4B
Reserved
0x02620324
0x02620327
4B
Reserved
ADVANCE INFORMATION
Table 3-2
0x02620328
0x0262032B
4B
MAINPLLCTL0
0x0262032C
0x0262032F
4B
Reserved
0x02620330
0x02620333
4B
DDR3PLLCTL0
0x02620334
0x02620337
4B
Reserved
0x02620338
0x0262033B
4B
PAPLLCTL0
0x0262033C
0x026203FF
196B
Reserved
See section 7.8 ‘‘Main PLL and the PLL Controller’’ on page 160
See section 7.9 ‘‘DDR3 PLL’’ on page 173
See section 7.10 ‘‘PASS PLL’’ on page 174
0x02620400
0x02620403
4B
PKTDMA_PRI_ALLOC
0x02620404
0x02620467
100B
Reserved
See section 4.4 ‘‘Bus Priorities’’ on page 80
End of Table 3-2
3.3.1 Device Status Register
The Device Status Register depicts the device configuration selected upon a power-on reset by either the POR or
RESETFULL pin. Once set, these bits will remain set until a power-on reset. The Device Status Register is shown in
Figure 3-1 and described in Table 3-3.
Figure 3-1
Device Status Register
31
18
Reserved
17
16
PACLKSEL
PCIESSEN
PCIESSMODE[1:0
BOOTMODE[12:0]
R-x
R/W-xx
R/W-xxxxxxxxxxxx
R-0
15
14
13
1
0
LENDIAN
R-x
(1)
Legend: R = Read only; RW = Read/Write; -n = value after reset
1 x indicates the bootstrap value latched via the external pin
Copyright 2010 Texas Instruments Incorporated
Device Configuration
63
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 3-3
www.ti.com
Device Status Register Field Descriptions
ADVANCE INFORMATION
Bit
Field
Description
31-18
Reserved
Reserved. Read only, writes have no effect.
17
PACLKSEL
PA Clock select to select the reference clock for PA Sub-System PLL
0 = Selects PASSCLKP/N
1 = Selects output of Main PLL MUX (SYSCLK vs. ALTCORECLK - depending on CORECLKSEL pin)
16
PCIESSEN
PCIe module enable
0 = PCIe module disabled
1 = PCIe module enabled
15-14
PCIESSMODE[1:0]
PCIe Mode selection pins
00b = PCIe in End-point mode
01b = PCIe in Legacy End-point mode (no support for MSI)
10b = PCIe in Root complex mode
11b = Reserved
13-1
BOOTMODE[12:0]
Determines the bootmode configured for the device. For more information on bootmode, see Section 2.5 ‘‘Boot Modes
Supported and PLL Settings’’ on page 27 and see the Bootloader for the C66x DSP User Guide in ‘‘Related Documentation
from Texas Instruments’’ on page 59.
0
LENDIAN
Device Endian mode (LENDIAN) — Shows the status of whether the system is operating in Big Endian mode or Little
Endian mode (default).
0 = System is operating in Big Endian mode
1 = System is operating in Little Endian mode (default)
End of Table 3-3
3.3.2 Device Configuration Register
The Device Configuration Register is one-time writeable through software. The register is reset on all hard resets
and is locked after the first write. The Device Configuration Register is shown in Figure 3-2 and described in
Table 3-4.
Figure 3-2
Device Configuration Register (DEVCFG)
31
1
0
Reserved
SYSCLKOUTEN
R-0
R/W-1
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-4
Bit
31:1
0
Device Configuration Register Field Descriptions
Field
Description
Reserved
Reserved. Read only, writes have no effect.
SYSCLKOUTEN
SYSCLKOUT Enable
0 = No clock output
1 = Clock output enabled (default)
End of Table 3-4
64
Device Configuration
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
3.3.3 JTAG ID (JTAGID) Register Description
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the device, the
JTAG ID register resides at address location 0x02620018. The JTAG ID Register is shown in Figure 3-3 and
described in Table 3-5.
Figure 3-3
JTAG ID (JTAGID) Register
31
28
27
12
11
1
0
VARIANT
PART NUMBER
MANUFACTURER
LSB
R-0000
R-0000 0000 1001 1101
0000 0010 111b
R-1
Table 3-5
JTAG ID Register Field Descriptions
Bit
Acronym
Value
Description
31-28
VARIANT
0000b
Variant (4-Bit) value. The value of this field depends on the silicon revision being used.
27-12
PART NUMBER
0000 0000 1001 1101b
Part Number for boundary scan
11-1
MANUFACTURER
0000 0010 111b
Manufacturer
LSB
1b
This bit is read as a 1 for TMS320C6670
0
End of Table 3-5
3.3.4 Kicker Mechanism (KICK0 and KICK1) Register
The Bootcfg module contains a kicker mechanism to prevent any spurious writes from changing any of the Bootcfg
MMR values. When the kicker is locked (which it is initially after power on reset) none of the Bootcfg MMRs are
writable (they are only readable). This mechanism requires two MMR writes to the KICK0 and KICK1 registers with
exact data values before the kicker lock mechanism is un-locked. See Table 3-2 ‘‘Device State Control Registers’’ on
page 61 for the address location. Once released then all the Bootcfg MMRs having “write” permissions are writable
(the read only MMRs are still read only). The first KICK0 data is 0x83e70b13. The second KICK1 data is 0x95a4f1e0.
Writing any other data value to either of these kick MMRs will lock the kicker mechanism and block any writes to
Bootcfg MMRs. In order to ensure protection to all Bootcfg MMRs, software must always re-lock the kicker
mechanism after completing the MMR writes.
3.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
The LRSTNMIPINSTAT Register is created in Boot Configuration to latch the status of LRESET and NMI based on
CORESEL. The LRESETNMI PIN Status Register is shown in Figure 3-4 and described in Table 3-6.
Figure 3-4
LRESETNMI PIN Status Register (LRSTNMIPINSTAT)
31
20
19
18
17
16
Reserved
NMI3
NMI2
NMI1
NMI0
R, +000000000000
R-0
R-0
R-0
R-0
15
4
3
2
1
0
Reserved
LR3
LR2
LR1
LR0
R, +000000000000
R-0
R-0
R-0
R-0
Legend: R = Read only; -n = value after reset
Table 3-6
Bit
31-20
LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions (Part 1 of 2)
Field
Description
Reserved
Reserved
19
NMI3
CorePac 3 in NMI
18
NMI2
CorePac 2 in NMI
Copyright 2010 Texas Instruments Incorporated
Device Configuration
65
ADVANCE INFORMATION
Legend: RW = Read/Write; R = Read only; -n = value after reset
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 3-6
Bit
Field
17
Description
NMI1
16
www.ti.com
LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions (Part 2 of 2)
CorePac 1 in NMI
NMI0
CorePac 0 in NMI
Reserved
Reserved
3
LR4
CorePac 3 in Local Reset
2
LR3
CorePac 2 in Local Reset
1
LR31
CorePac 1 in Local Reset
0
LR0
CorePac 0 in Local Reset
15-4
End of Table 3-6
ADVANCE INFORMATION
3.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
The LRSTNMIPINSTAT_CLR Register is used to clear the status of LRESET and NMI based on CORESEL[2:0]. The
LRESETNMI PIN Status Clear Register is shown in Figure 3-5 and described in Table 3-7.
Figure 3-5
LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR)
31
20
19
Reserved
NMI3
R,+000000000000
WC,+0
(1)
18
17
16
NMI2
NMI1
NMI0
WC,+0
WC,+0
WC,+0
15
4
3
2
1
0
Reserved
LR3
LR2
LR1
LR0
R,+000000000000
WC,+0
WC,+0
WC,+0
WC,+0
Legend: R = Read only; -n = value after reset; WC = Write 1 to Clear
1 RC: Write one to clear.
Table 3-7
Bit
LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions
Field
31-20
Description
Reserved
Reserved
19
NMI3
CorePac 3 in NMI Clear
18
NMI2
CorePac 2 in NMI Clear
17
NMI1
CorePac 1 in NMI Clear
16
NMI0
CorePac 0 in NMI Clear
Reserved
Reserved
3
LR3
CorePac 3 in Local Reset Clear
2
LR2
CorePac 2 in Local Reset Clear
1
LR1
CorePac 1 in Local Reset Clear
0
LR0
CorePac 0 in Local Reset Clear
15-4
End of Table 3-7
3.3.7 Reset Status (RESET_STAT) Register
The reset status register (RESET_STAT) captures the status of Local reset (LRx) for each of the cores and also the
global device reset (GR). Software can use this information to take different device initialization steps, if desired.
• In case of Local reset: The LRx bits are written as 1 and GR bit is written as 0 only when the CorePac receives
an local reset without receiving a global reset.
• In case of Global reset: The LRx bits are written as 0 and GR bit is written as 1 only when a global reset is
asserted.
66
Device Configuration
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
The Reset Status Register is shown in Figure 3-6 and described in Table 3-8.
Figure 3-6
31
Reset Status Register (RESET_STAT)
30
4
3
2
1
0
GR
Reserved
LR3
LR2
LR1
LR0
R, +1
R, + 000 0000 0000 0000 0000 0000 0000
R,+0
R,+0
R,+0
R,+0
Legend: R = Read only; -n = value after reset
Reset Status Register (RESET_STAT) Field Descriptions
Bit
31
Field
Description
GR
Global reset status
0 = Device has not received a global reset.
1 = Device received a global reset.
Reserved
Reserved.
3
LR3
CorePac 3 reset status
0 = CorePac 3 has not received a local reset.
1 = CorePac 3 received a local reset.
2
LR2
CorePac 2 reset status
0 = CorePac 2 has not received a local reset.
1 = CorePac 2 received a local reset.
1
LR1
CorePac 1 reset status
0 = CorePac 1 has not received a local reset.
1 = CorePac 1 received a local reset.
0
LR0
CorePac 0 reset status
0 = CorePac 0 has not received a local reset.
1 = CorePac 0 received a local reset.
30-4
ADVANCE INFORMATION
Table 3-8
End of Table 3-8
3.3.8 Reset Status Clear (RESET_STAT_CLR) Register
The RESET_STAT bits can be cleared by writing 1 to the corresponding bit in the RESET_STAT_CLR register. The
Reset Status Clear Register is shown in Figure 3-7 and described in Table 3-9.
Figure 3-7
31
Reset Status Clear Register (RESET_STAT_CLR)
30
4
3
2
1
0
GR
Reserved
LR3
LR2
LR1
LR0
RW, +0
R, + 000 0000 0000 0000 0000 0000 0000
RW,+0
RW,+0
RW,+0
RW,+0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-9
Bit
31
30-4
3
Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions (Part 1 of 2)
Field
Description
GR
Global Reset Clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the GR bit clears the corresponding bit in the RESET_STAT register.
Reserved
Reserved.
LR3
CorePac 3 reset Clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR3 bit clears the corresponding bit in the RESET_STAT register.
Copyright 2010 Texas Instruments Incorporated
Device Configuration
67
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 3-9
Bit
www.ti.com
Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions (Part 2 of 2)
Field
Description
2
LR2
CorePac 2 reset Clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR2 bit clears the corresponding bit in the RESET_STAT register.
1
LR1
CorePac 1 reset Clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR1 bit clears the corresponding bit in the RESET_STAT register.
0
LR0
CorePac 0 reset Clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR0 bit clears the corresponding bit in the RESET_STAT register.
ADVANCE INFORMATION
End of Table 3-9
3.3.9 Boot Complete (BOOTCOMPLETE) Register
The BOOTCOMPLETE register controls the BOOTCOMPLETE pin status. The purpose is to indicate the
completion of the ROM booting process. The Boot Complete Register is shown in Figure 3-8 and described in
Table 3-10.
Figure 3-8
Boot Complete Register (BOOTCOMPLETE)
31
4
3
2
1
0
Reserved
BC3
BC
BC1
BC0
R, + 0000 0000 0000 0000 0000 0000 0000
RW,+0
RW,+0
RW,+0
RW,+0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-10
Bit
31-4
Boot Complete Register (BOOTCOMPLETE) Field Descriptions
Field
Description
Reserved
Reserved.
3
BC3
CorePac 4 boot status
0 = CorePac 4 boot NOT complete
1 = CorePac 4 boot complete
2
BC2
CorePac 3 boot status
0 = CorePac 3 boot NOT complete
1 = CorePac 3 boot complete
1
BC1
CorePac 2 boot status
0 = CorePac 2 boot NOT complete
1 = CorePac 2 boot complete
0
BC0
CorePac 1 boot status
0 = CorePac 1 boot NOT complete
1 = CorePac 1 boot complete
End of Table 3-10
The BCx bit indicates the boot complete status of the corresponding core. All BCx bits will be sticky bits — that is
they can be set only once by the software after device reset and they will be cleared to 0 on all device resets.
Boot ROM code will be implemented such that each core will set its corresponding BCx bit immediately before
branching to the predefined location in memory.
68
Device Configuration
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
3.3.10 Power State Control (PWRSTATECTL) Register
The PWRSTATECTL register is controlled by the software to indicate the power-saving mode. ROM code reads this
register to differentiate between the various power saving modes. This register is cleared only by POR and will
survive all other device resets. See the Hardware Design Guide for KeyStone Devices in‘‘Related Documentation from
Texas Instruments’’ on page 59 for more information. The Power State Control Register is shown in Figure 3-9 and
described in Table 3-11.
Power State Control Register (PWRSTATECTL)
31
3
2
1
0
GENERAL_PURPOSE
HIBERNATION_MODE
HIBERNATION
STANDBY
RW, +0000 0000 0000 0000 0000 0000 0000 0
RW,+0
RW,+0
RW,+0
Legend: RW = Read/Write; -n = value after reset
Table 3-11
Bit
Power State Control Register (PWRSTATECTL) Field Descriptions
Field
Description
GENERAL_PURPOSE
Used to provide a start address for execution out of the hibernation modes. See the Bootloader for the C66x DSP User
Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59.
2
HIBERNATION_MODE
Indicates whether the device is in hibernation mode 1 or mode 2.
0 = Hibernation mode 1
1 = Hibernation mode 2
1
HIBERNATION
Indicates whether the device is in hibernation mode or not.
0 = Not in hibernation mode
1 = Hibernation mode
0
STANDBY
Indicates whether the device is in standby mode or not.
0 = Not in standby mode
1 = Standby mode
31-3
End of Table 3-11
3.3.11 NMI Even Generation to CorePac (NMIGRx) Register
NMIGRx registers are used for generating NMI events to the corresponding CorePac. The C6670 has
four NMIGRx registers (NMIGR0 through NMIGR3). The NMIGR0 register generates an NMI event to CorePac0,
the NMIGR1 register generates an NMI event to CorePac1, and so on. Writing a 1 to the NMIG field generates a
NMI pulse. Writing a 0 has no effect and Reads return 0 and have no other effect. The NMI Even Generation to
CorePac Register is shown in Figure 3-10 and described in Table 3-12.
Figure 3-10
NMI Generation Register (NMIGRx)
31
1
0
GENERAL_PURPOSE
NMIG
R, +0000 0000 0000 0000 0000 0000 0000 000
RW,+0
Legend: RW = Read/Write; -n = value after reset
Copyright 2010 Texas Instruments Incorporated
Device Configuration
69
ADVANCE INFORMATION
Figure 3-9
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 3-12
Bit
NMI Generation Register (NMIGRx) Field Descriptions
Field
31-1
0
www.ti.com
Description
Reserved
Reserved
NMIG
Reads return 0
Writes:
0 = No effect
1 = Creates NMI pulse to the corresponding CorePac — CorePac0 for NMIGR0, etc.
End of Table 3-12
ADVANCE INFORMATION
3.3.12 IPC Generation (IPCGRx) Registers
IPCGRx are the IPC interrupt generation registers to facilitate inter CorePac interrupts.
The C6670 has four IPCGRx registers (IPCGR0 through IPCGR3) registers. This can be used by external hosts or
CorePacs to generate interrupts to other CorePacs. A write of 1 to IPCG field of IPCGRx register will generate an
interrupt pulse to CorePacx (0 <= x <= 3).
These registers also provide a Source ID facility by which up to 28 different sources of interrupts can be identified.
Allocation of source bits to source processor and meaning is entirely based on software convention. The register field
descriptions are given in the following tables. Virtually anything can be a source for these registers as this is
completely controlled by software. Any master that has access to BOOTCFG module space can write to these
registers. The IPC Generation Register is shown in Figure 3-11 and described in Table 3-13.
Figure 3-11
IPC Generation Registers (IPCGRx)
31
30
29
28
SRCS27
SRCS26
SRCS25
SRCS24
RW +0
RW +0
RW +0
RW +0
27
8
7
6
5
4
3
1
0
SRCS23 – SRCS4
SRCS3
SRCS2
RCS1
SRCS0
Reserved
IPCG
RW +0 (per bit field)
RW +0
RW +0
RW +0
RW +0
R, +000
RW +0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-13
Bit
31-4
IPC Generation Registers (IPCGRx) Field Descriptions
Field
Description
SRCSx
Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Sets both SRCSx and the corresponding SRCCx.
3-1
0
Reserved
Reserved
IPCG
Reads return 0.
Writes:
0 = No effect
1 = Creates an Inter-DSP interrupt.
End of Table 3-13
3.3.13 IPC Acknowledgement (IPCARx) Registers
IPCARx are the IPC interrupt-acknowledgement registers to facilitate inter-CorePac core interrupts.
70
Device Configuration
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
The C6670 has four IPCARx (IPCAR0 through IPCAR3) registers. These registers also provide a Source ID facility
by which up to 28 different sources of interrupts can be identified. Allocation of source bits to source processor and
meaning is entirely based on software convention. The register field descriptions are given in the following tables.
Virtually anything can be a source for these registers as this is completely controlled by software. Any master that
has access to BOOTCFG module space can write to these registers. The IPC Acknowledgement Register is shown in
Figure 3-12 and described in Table 3-14.
IPC Acknowledgement Registers (IPCARx)
31
30
29
28
SRCC27
SRCC26
SRCC25
SRCC24
RW +0
RW +0
RW +0
RW +0
27
8
7
6
5
4
3
0
SRCC23 – SRCC4
SRCC3
SRCC2
RCC1
SRCC0
Reserved
RW +0 (per bit field)
RW +0
RW +0
RW +0
RW +0
R, +0000
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-14
Bit
31-4
IPC Acknowledgement Registers (IPCARx) Field Descriptions
Field
Description
SRCCx
Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Clears both SRCCx and the corresponding SRCSx
3-0
Reserved
Reserved
End of Table 3-14
3.3.14 IPC Generation Host (IPCGRH) Register
IPCGRH register is provided to facilitate host CPU interrupt. Operation and use of IPCGRH is the same as other
IPCGR registers. Interrupt output pulse created by IPCGRH is driven on a device pin, host interrupt/event output
(HOUT).
The host interrupt output pulse should be stretched. It should be asserted for 4 bootcfg clock cycles (CPU/6)
followed by a deassertion of 4 bootcfg clock cycles. Generating the pulse will result in 8 CPU/6 cycle pulse blocking
window. Write to IPCGRH with IPCG bit (bit 0) set will only generate a pulse if they are beyond 8 CPU/6 cycle
period. The IPC Generation Host Register is shown in Figure 3-13 and described in Table 3-15.
Figure 3-13
IPC Generation Registers (IPCGRH)
31
30
29
28
SRCS27
SRCS26
SRCS25
SRCS24
RW +0
RW +0
RW +0
RW +0
27
8
7
6
5
4
3
1
0
SRCS23 – SRCS4
SRCS3
SRCS2
RCS1
SRCS0
Reserved
IPCG
RW +0 (per bit field)
RW +0
RW +0
RW +0
RW +0
R, +000
RW +0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Copyright 2010 Texas Instruments Incorporated
Device Configuration
71
ADVANCE INFORMATION
Figure 3-12
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 3-15
IPC Generation Registers (IPCGRH) Field Descriptions
Bit
Field
31-4
www.ti.com
Description
SRCSx
Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Sets both SRCSx and the corresponding SRCCx.
3-1
0
Reserved
Reserved
IPCG
Reads return 0.
ADVANCE INFORMATION
Writes:
0 = No effect
1 = Creates an interrupt pulse on device pin (host interrupt/event output in HOUT pin)
End of Table 3-15
3.3.15 IPC Acknowledgement Host (IPCARH) Register
IPCARH registers are provided to facilitate host CPU interrupt. Operation and use of IPCARH is the same as
other IPCAR registers. The IPC Acknowledgement Host Register is shown in Figure 3-14 and described in
Table 3-16.
Figure 3-14
IPC Acknowledgement Register (IPCARH)
31
30
29
28
27
SRCC27
SRCC26
SRCC25
SRCC24
RW +0
RW +0
RW +0
RW +0
8
7
6
5
4
3
0
SRCC23 – SRCC4
SRCC3
SRCC2
RCC1
SRCC0
Reserved
RW +0 (per bit field)
RW +0
RW +0
RW +0
RW +0
R, +0000
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-16
IPC Acknowledgement Register (IPCARH) Field Descriptions
Bit
Field
31-4
Description
SRCCx
Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Clears both SRCCx and the corresponding SRCSx
3-0
Reserved
Reserved
End of Table 3-16
3.3.16 Timer Input Selection Register (TINPSEL)
Timer input selection is handled within the control register TINPSEL. The Timer Input Selection Register is shown
in Figure 3-15 and described in Table 3-17.
Figure 3-15
Timer Input Selection Register (TINPSEL)
31
16
15
14
13
12
11
10
9
Reserved
TINPHSEL7
TINPLSEL7
TINPHSEL6
TINPLSEL6
TINPHSEL5
TINPLSEL5
TINPHSEL4
0
RW, +1
RW, +0
RW, +1
RW, +0
RW, +1
RW, +0
RW, +1
spacer
8
7
6
5
4
3
2
1
0
TINPLSEL4
TINPHSEL3
TINPLSEL3
TINPHSEL2
TINPLSEL2
TINPHSEL1
TINPLSEL1
TINPHSEL0
TINPLSEL0
RW, +0
RW, +1
RW, +0
RW, +1
RW, +0
RW, +1
RW, +1
RW, +1
RW, +0
Legend: R = Read only; RW = Read/Write; -n = value after reset
72
Device Configuration
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Bit
Timer Input Selection Field Description (TINPSEL)
Field
31-16 Reserved
Description
Reserved
15
TINPHSEL7
Input select for TIMER7 high.
0 = TIMI0
1 = TIMI1
14
TINPLSEL7
Input select for TIMER7 low.
0 = TIMI0
1 = TIMI1
13
TINPHSEL6
Input select for TIMER6 high.
0 = TIMI0
1 = TIMI1
12
TINPLSEL6
Input select for TIMER6 low.
0 = TIMI0
1 = TIMI1
11
TINPHSEL5
Input select for TIMER5 high.
0 = TIMI0
1 = TIMI1
10
TINPLSEL5
Input select for TIMER5 low.
0 = TIMI0
1 = TIMI1
9
TINPHSEL4
Input select for TIMER4 high.
0 = TIMI0
1 = TIMI1
8
TINPLSEL4
Input select for TIMER4 low.
0 = TIMI0
1 = TIMI1
7
TINPHSEL3
Input select for TIMER3 high.
0 = TIMI0
1 = TIMI1
6
TINPLSEL3
Input select for TIMER3 low.
0 = TIMI0
1 = TIMI1
5
TINPHSEL2
Input select for TIMER2 high.
0 = TIMI0
1 = TIMI1
4
TINPLSEL2
Input select for TIMER2 low.
0 = TIMI0
1 = TIMI1
3
TINPHSEL1
Input select for TIMER1 high.
0 = TIMI0
1 = TIMI1
2
TINPLSEL1
Input select for TIMER1 low.
0 = TIMI0
1 = TIMI1
1
TINPHSEL0
Input select for TIMER0 high.
0 = TIMI0
1 = TIMI1
0
TINPLSEL0
Input select for TIMER0 low.
0 = TIMI0
1 = TIMI1
ADVANCE INFORMATION
Table 3-17
End of Table 3-17
Copyright 2010 Texas Instruments Incorporated
Device Configuration
73
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
3.3.17 Timer Output Selection Register (TOUTPSEL)
The timer output selection is handled within the control register TOUTSEL. The Timer Output Selection Register
is shown in Figure 3-16 and described in Table 3-18.
Figure 3-16
Timer Output Selection Register (TOUTPSEL)
31
9
8
5
4
3
0
Reserved
TOUTPSEL1
Reserved
TOUTPSEL0
R,+0000000000000000000000000
RW,+0001
0
RW,+0000
Legend: R = Read only; RW = Read/Write; -n = value after reset
ADVANCE INFORMATION
Table 3-18
Timer Output Selection Field Description (TOUTPSEL)
Bit
Field
Description
31-9
Reserved
Reserved
8-5
TOUTPSEL1
Output select for TIMO1
0000: TOUTL0
0001: TOUTH0
0010: TOUTL1
0011: TOUTH1
0100: TOUTL2
0101: TOUTH2
0110: TOUTL3
0111: TOUTH3
4
Reserved
Reserved
3-0
TOUTPSEL0
Output select for TIMO0
0000: TOUTL0
0001: TOUTH0
0010: TOUTL1
0011: TOUTH1
0100: TOUTL2
0101: TOUTH2
0110: TOUTL3
0111: TOUTH3
1000: TOUTL4
1001: TOUTH4
1010: TOUTL5
1011: TOUTH5
1100: TOUTL6
1101: TOUTH6
1110: TOUTL7
1111: TOUTH7
1000: TOUTL4
1001: TOUTH4
1010: TOUTL5
1011: TOUTH5
1100: TOUTL6
1101: TOUTH6
1110: TOUTL7
1111: TOUTH7
End of Table 3-18
3.3.18 Reset Mux (RSTMUXx) Register
The software controls the Reset Mux block through the reset multiplex registers using RSTMUX0 through
RSTMUX3 for each of the four CorePacs on the C6670. These registers are located in Bootcfg memory space. The
Timer Output Selection Register is shown in Figure 3-17 and described in Table 3-19.
Figure 3-17
Reset Mux Register (RSTMUX0 through RSTMUX3)
31
10
9
8
7
5
4
3
1
0
Reserved
EVTSTATCLR
Reserved
DELAY
EVTSTAT
OMODE
LOCK
R, +0000 0000 0000 0000 0000 00
RC, +0
R, +0
RW, +100
R, +0
RW, +000
RW, +0
Legend: R = Read only; RW = Read/Write; -n = value after reset; RC = Read only and write 1 to clear
74
Device Configuration
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Bit
31-10
Reset Mux Register Field Descriptions
Field
Description
Reserved
Reserved
9
EVTSTATCLR
8
Reserved
7-5
0 = Writing O had no effect
1 = Writing 1 to this bit clears the EVTSTAT bit
Reserved
DELAY
000b = 256 CPU/6 cycles delay between NMI & Local reset, when OMODE = 100b
001b = 512 CPU/6 cycles delay between NMI & Local reset, when OMODE=100b
010b = 1024 CPU/6 cycles delay between NMI & Local reset, when OMODE=100b
011b = 2048 CPU/6 cycles delay between NMI & Local reset, when OMODE=100b
100b = 4096 CPU/6 cycles delay between NMI & Local reset, when OMODE=100b (Default)
101b = 8192 CPU/6 cycles delay between NMI & Local reset, when OMODE=100b
110b = 16384 CPU/6 cycles delay between NMI & Local reset, when OMODE=100b
111b = 32768 CPU/6 cycles delay between NMI & Local reset, when OMODE=100b
4
EVTSTAT
0 = No event received (Default)
1 = WD timer event received by Reset Mux block
3-1
OMODE
000b = WD Timer Event input to the Reset Mux block does not cause any output event (Default)
001b = Reserved
010b = WD Timer Event input to the Reset Mux block causes local reset input to CorePac
011b = WD Timer Event input to the Reset Mux block causes NMI input to CorePac
100b = WD Timer Event input to the Reset Mux block causes NMI input followed by Local reset input to CorePac. Delay
between NMI and local reset is set in DELAY bit field.
101b = WD Timer Event input to the Reset Mux block causes Device Reset to C6670
110b = Reserved
111b = Reserved
LOCK
0 = Register fields are not locked (Default)
1 = Register fields are locked until the next timer reset
0
ADVANCE INFORMATION
Table 3-19
End of Table 3-19
Copyright 2010 Texas Instruments Incorporated
Device Configuration
75
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
3.4 Pullup/Pulldown Resistors
Proper board design should ensure that input pins to the device always be at a valid logic level and not floating. This
may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and internal pulldown
(IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors.
An external pullup/pulldown resistor needs to be used in the following situations:
• Device Configuration Pins: If the pin is both routed out and are not driven (in Hi-Z state), an external
pullup/pulldown resistor must be used, even if the IPU/IPD matches the desired value/state.
• Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown
resistor to pull the signal to the opposite rail.
ADVANCE INFORMATION
For the device configuration pins (listed in Table 3-1), if they are both routed out and are not driven (in Hi-Z state),
it is strongly recommended that an external pullup/pulldown resistor be implemented. Although, internal
pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing
external connectivity can help ensure that valid logic levels are latched on these device configuration pins. In
addition, applying external pullup/pulldown resistors on the device configuration pins adds convenience to the user
in debugging and flexibility in switching operating modes.
Tips for choosing an external pullup/pulldown resistor:
• Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure to
include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown
resistors.
• Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of all inputs
connected to the net. For a pullup resistor, this should be above the highest VIH level of all inputs on the net.
A reasonable choice would be to target the VOL or VOH levels for the logic family of the limiting device; which,
by definition, have margin to the VIL and VIH levels.
• Select a pullup/pulldown resistor with the largest possible value that can still ensure that the net will reach the
target pulled value when maximum current from all devices on the net is flowing through the resistor. The
current to be considered includes leakage current plus, any other internal and external pullup/pulldown
resistors on the net.
• For bidirectional nets, there is an additional consideration that sets a lower limit on the resistance value of the
external resistor. Verify that the resistance is small enough that the weakest output buffer can drive the net to
the opposite logic level (including margin).
• Remember to include tolerances when selecting the resistor value.
• For pullup resistors, also remember to include tolerances on the DVDD rail.
For most systems:
• A 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above criteria. Users should confirm this
resistor value is correct for their specific application.
• A 20-kΩ resistor can be used to compliment the IPU/IPD on the device configuration pins while meeting the
above criteria. Users should confirm this resistor value is correct for their specific application.
For more detailed information on input current (II), and the low-level/high-level input voltages (VIL and VIH) for
the TMS320C6670 device, see Section 6.3 ‘‘Electrical Characteristics’’ on page 92.
To determine which pins on the device include internal pullup/pulldown resistors, see Table 2-16 ‘‘Terminal
Functions — Power and Ground’’ on page 46.
76
Device Configuration
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
www.ti.com
SPRS689—November 2010
4 System Interconnect
On the TMS320C6670 device, the C66x CorePac, the EDMA3 transfer controllers, and the system peripherals are
interconnected through two switch fabrics. The switch fabrics allow for low-latency, concurrent data transfers
between master peripherals and slave peripherals. The switch fabrics also allow for seamless arbitration between the
system masters when accessing system slaves.
Two types of buses exist in the device: data buses and configuration buses. Some peripherals have both a data bus
and a configuration bus interface, while others only have one type of interface. Furthermore, the bus interface width
and speed varies from peripheral to peripheral. Configuration buses are mainly used to access the register space of
a peripheral and the data buses are used mainly for data transfers. However, in some cases, the configuration bus is
also used to transfer data. For example, data is transferred to the VCP2 via its configuration bus. Similarly, the data
bus can also be used to access the register space of a peripheral. For example, the DDR3 memory controller registers
are accessed through their data bus interface.
The C66x CorePac, the EDMA3 traffic controllers, and the various system peripherals can be classified into two
categories: masters and slaves.
Masters are capable of initiating read and write transfers in the system and do not rely on the EDMA3 for their data
transfers. Slaves on the other hand rely on the EDMA3 to perform transfers to and from them. Examples of masters
2
include the EDMA3 traffic controllers, SRIO, and EMAC. Examples of slaves include the SPI, UART, and I C.
The device contains two switch fabrics (the TeraNet) through which masters and slaves communicate. The data
switch fabric, known as the data switched central resource (SCR), is a high-throughput interconnect mainly used to
move data across the system (for more information, see Section 4.2 ‘‘Data Switch Fabric Connections’’). The data
SCR is further divided into two smaller SCRs. One connects very high speed masters to slaves via 256-bit data buses
running at a CPU/2 frequency. The other connects masters to slaves via 128-bit data buses running at a CPU/3
frequency. Peripherals that match the native bus width of the SCR it’s connected to can connect directly to the data
SCR; other peripherals require a bridge.
The configuration switch fabric, also known as the configuration switch central resource (SCR), is mainly used to
access peripheral registers (for more information, see Section 4.3 ‘‘Configuration Switch Fabric’’). The
configuration SCR connects the C66x CorePac and masters on the data switch fabric to slaves via
32-bit configuration buses running at a CPU/3 frequency. As with the data SCR, some peripherals require the use of
a bridge to interface to the configuration SCR.
Bridges perform a variety of functions:
• Conversion between configuration bus and data bus.
• Width conversion between peripheral bus width and SCR bus width.
• Frequency conversion between peripheral bus frequency and SCR bus frequency.
Copyright 2010 Texas Instruments Incorporated
System Interconnect
77
ADVANCE INFORMATION
4.1 Internal Buses, Bridges, and Switch Fabrics
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
4.2 Data Switch Fabric Connections
A detailed figure will be added here for a future release. Connection information is shown in the tables below.
Table 4-1
CPU/2 Data SCR Connection Matrix
Slave
To CPU/3 Data SCR
Masters
TPCC0 TC0_RD
HyperLink_Slave
MSMC_SMS
MSMC_SES
Br_1
Br_2
Br_3
Br_4
Y
Y
Y
N
Y
N
N
ADVANCE INFORMATION
TPCC0 TC0_WR
Y
Y
Y
N
Y
N
N
TPCC0 TC1_RD
Y
Y
Y
N
N
Y
N
TPCC0 TC1_WR
Y
Y
Y
N
N
Y
N
HyperLink_Master
N
Y
Y
Y
N
N
N
MSMC_master
Y
N
N
N
N
N
Y
From CPU/3 Data SCR Br_5
Y
Y
Y
N
N
N
N
From CPU/3 Data SCR Br_6
Y
Y
Y
N
N
N
N
From CPU/3 Data SCR Br_7
Y
Y
Y
N
N
N
N
From CPU/3 Data SCR Br_8
Y
Y
Y
N
N
N
N
From CPU/3 Data SCR Br_9
Y
Y
Y
N
N
N
N
From CPU/3 Data SCR Br_10
Y
Y
Y
N
N
N
N
End of Table 4-1
78
System Interconnect
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Table 4-2
CPU/3 Data SCR Connection
Br_9 (to CPU/2 Data SCR)
Br_10 (to CPU/2 Data SCR)
Br_12 (to Config SCR)
Br_13 (to Config SCR)
Br_14 (to Config SCR)
N
N
N
N
N
N
Y
N
N
Y
Y
Y
Y
Y
N
N
N
N
N
N
Y
N
N
N
N
N
N
TPCC0 TC1
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
Y
N
N
N
N
N
N
TPCC1_TC0_RD
Y
Y
Y
Y
Y
Y
Y
N
Y
N
N
N
N
N
Y
N
N
N
N
N
N
TPCC1_TC0_WR
Y
Y
Y
Y
Y
Y
Y
N
Y
N
N
N
N
N
Y
N
N
N
N
N
N
TPCC1_TC1_RD
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
N
N
N
N
N
Y
N
N
N
N
N
TPCC1_TC1_WR
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
N
N
N
N
N
Y
N
N
N
N
N
TPCC1_TC2_RD
Y
Y
Y
Y
Y
Y
Y
N
N
N
Y
N
N
N
N
N
Y
N
N
N
N
TPCC1_TC2_WR
Y
Y
Y
Y
Y
Y
Y
N
N
N
Y
N
N
N
N
N
Y
N
N
N
N
TPCC1_TC3_RD
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
Y
N
N
Y
N
N
N
N
N
N
TPCC1_TC3_WR
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
Y
N
N
Y
N
N
N
N
N
N
TPCC2_TC0_RD
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
Y
N
Y
N
N
Y
Y
Y
Y
TPCC2_TC0_WR
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
Y
N
Y
N
N
Y
Y
Y
Y
TPCC2_TC1_RD
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
Y
N
Y
N
Y
Y
Y
Y
TPCC2_TC1_WR
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
Y
N
Y
N
Y
Y
Y
Y
TPCC2_TC2_RD
Y
Y
Y
Y
Y
Y
Y
N
Y
N
N
N
N
N
Y
N
N
Y
Y
N
N
TPCC2_TC2_WR
Y
Y
Y
Y
Y
Y
Y
N
Y
N
N
N
N
N
Y
N
N
Y
Y
N
N
TPCC2_TC3_RD
Y
Y
Y
Y
Y
Y
Y
N
N
Y
N
N
N
N
N
N
Y
Y
N
Y
Y
TPCC2_TC3_WR
Y
Y
Y
Y
Y
Y
Y
N
N
Y
N
N
N
N
N
N
Y
Y
N
Y
Y
SRIO Messaging
Y
Y
Y
Y
N
N
N
Y
N
N
N
N
Y
N
N
N
N
N
N
N
N
SRIO Data
Y
Y
Y
Y
N
Y
N
Y
N
N
Y
N
N
N
Y
N
N
Y
Y
Y
Y
PCIe_Master
Y
Y
Y
Y
N
Y
N
Y
N
N
Y
N
N
N
Y
N
N
Y
Y
Y
Y
Packet Accelerator_Data_Master
Y
Y
Y
Y
N
N
N
Y
N
N
N
N
N
Y
N
N
N
N
N
N
N
Br_4(MSMC_Data_Master)
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
Y
N
N
Y
Y
Y
Y
Queue Manager
Y
Y
Y
Y
N
N
N
Y
N
N
N
Y
N
N
N
N
N
N
N
N
N
FFTC_B
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
Y
Y
N
N
Y
Y
Y
Y
AIF
Y
Y
Y
Y
N
N
N
Y
N
N
Y
N
N
N
N
N
N
N
N
N
N
FFTC_A
Y
Y
Y
Y
N
N
N
Y
N
Y
N
N
N
N
N
N
N
N
N
N
N
End of Table 4-2
4.3 Configuration Switch Fabric
A detailed figure will be added here for a future release. All masters can talk to all slaves on the configuration switch
fabric.
Copyright 2010 Texas Instruments Incorporated
System Interconnect
79
ADVANCE INFORMATION
TCP3e_WR
Br_8 (to CPU/2 Data SCR)
Y
Y
TCP3e_RD
Br_7 (to CPU/2 Data SCR)
Y
Y
TCP3d
Br_6 (to CPU/2 Data SCR)
Y
Y
VCP2
Br_5 (to CPU/2 Data SCR)
Y
Y
PCIe_Slave
Y
Y
SRIO_Data_Slave
Y
Y
CorePac3_SDMA
Y
Y
CorePac2_SDMA
Y
TPCC0 TC0
CorePac1_SDMA
HyperLink Master
SCR_3_A Masters
CorePac0_SDMA
QM_Slave
Br_11 for (boot_ROM, SPI)
Slaves
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
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4.4 Bus Priorities
The priority level of all master peripheral traffic is defined at the TeraNet boundary. User programmable priority
registers will be present to allow software configuration of the data traffic through the TeraNet. Note that a lower
number means higher priority - PRI = 000b = urgent, PRI = 111b = low.
All other masters provide their priority directly and do not need a default priority setting. Examples include the
CorePacs, whose priorities are set through software in the UMC control registers. All the Packet DMA based
peripherals also have internal registers to define the priority level of their initiated transactions.
ADVANCE INFORMATION
The Packet DMA secondary port is one master port that does not have priority allocation register inside the IP. The
priority level for transaction from this master port is described by PKTDMA_PRI_ALLOC register in Figure 4-1 and
Table 4-3.
Figure 4-1
Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC)
31
16
15
10
9
8
7
4
3
2
0
Reserved
PKTDMA_PRI
R/W-00000000000000000000001000011
RW-000
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 4-3
Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC) Field Descriptions
Bit
Acronym
Description
31-10
Reserved
Reserved.
2-0
PKDTDMA_PRI
Control the priority level for the transactions from Packet DMA Master port, which access the external linking
RAM.
End of Table 4-3
For all other modules, see the respective User Guides in ‘‘Related Documentation from Texas Instruments’’ on
page 59 for programmable priority registers.
80
System Interconnect
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
The C66x CorePac consists of several components:
• The C66x DSP core
• Level-one and level-two memories (L1P, L1D, L2)
• RSA accelerator (on cores 1 and 2 only)
• Data Trace Formatter (DTF)
• Embedded Trace Buffer (ETB)
• Interrupt controller
• Power-down controller
• External memory controller
• Extended memory controller
• A dedicated power/sleep controller (LPSC)
The C66x CorePac also provides support for memory protection and bandwidth management (for resources local
to the CorePac). Figure 5-1 shows a block diagram of the C66x CorePac.
C66x CorePac Block Diagram
66xx
Memory Controller (PMC) With
Memory Protect/Bandwidth Mgmt
C66x DSP Core
Interrupt and Exception Controller
Instruction Fetch
16-/32-bit Instruction Dispatch
Control Registers
In-Circuit Emulation
Instruction Decode
Data Path B
Data Path A
PLLC
LPSC
A Register File
B Register File
A31-A16
A15-A0
B31-B16
B15-B0
.M1
xx
xx
.M2
xx
xx
GPSC
.L1
.S1
.D1
.D2
.S2
.L2
Data Memory Controller (DMC) With
Memory Protect/Bandwidth Mgmt
RSA
Cores 1 & 2
only
Copyright 2010 Texas Instruments Incorporated
32KB L1D
L2 Cache/
SRAM
1024KB
MSM
SRAM
2048KB
DDR3
SRAM
DMA Switch
Fabric
External Memory
Controller (EMC)
Boot
Controller
Unified Memory
Controller (UMC)
32KB L1P
Extended Memory
Controller (XMC)
Figure 5-1
CFG Switch
Fabric
RSA
Cores 1 & 2
only
C66x CorePac
81
ADVANCE INFORMATION
5 C66x CorePac
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
For more detailed information on the C66x CorePac in the C6670 device, see the C66x CorePac User Guide
in ‘‘Related Documentation from Texas Instruments’’ on page 59.
5.1 Memory Architecture
Each core of the TMS320C6670 device contains a 1024KB level-2 memory (L2), a 32KB level-1 program memory
(L1P), and a 32KB level-1 data memory (L1D). The device also contain a 2048KB multicore shared memory (MSM).
All memory on the C6670 has a unique location in the memory map (see Table 2-2 ‘‘TMS320C6670 Memory Map
Summary’’ on page 18.
ADVANCE INFORMATION
After device reset, L1P and L1D cache are configured as all cache, by default. The L1P and L1D cache can be
reconfigured via software through the L1PMODE field of the L1P Configuration Register (L1PMODE) and the
L1DMODE field of the L1D Configuration Register (L1DCFG) of the C66x CorePac. L1D is a two-way
set-associative cache, while L1P is a direct-mapped cache.
The on-chip bootloader changes the reset configuration for L1P and L1D. For more information, see the Bootloader
for the C66x DSP User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59.
For more information on the operation L1 and L2 caches, see the C66x DSP Cache User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 59.
5.1.1 L1P Memory
The L1P memory configuration for the C6670 device is as follows:
• Region 0 size is 0K bytes (disabled)
• Region 1 size is 32K bytes with no wait states
Figure 5-2 shows the available SRAM/cache configurations for L1P.
Figure 5-2
TMS320C6670 L1P Memory Configurations
L1P mode bits
000
001
010
011
100
1/2
SRAM
All
SRAM
7/8
SRAM
L1P memory
Block base
address
00E0 0000h
16K bytes
3/4
SRAM
direct
mapped
cache
00E0 4000h
8K bytes
dm
cache
82
C66x CorePac
direct
mapped
cache
direct
mapped
cache
00E0 6000h
4K bytes
00E0 7000h
4K bytes
00E0 8000h
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
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5.1.2 L1D Memory
The L1D memory configuration for the C6670 device is as follows:
• Region 0 size is 0K bytes (disabled)
• Region 1 size is 32K bytes with no wait states
Figure 5-3 shows the available SRAM/cache configurations for L1D.
Figure 5-3
TMS320C6670 L1D Memory Configurations
L1D mode bits
001
010
011
100
1/2
SRAM
All
SRAM
7/8
SRAM
L1D memory
Block base
address
00F0 0000h
ADVANCE INFORMATION
000
16K bytes
3/4
SRAM
2-way
cache
00F0 4000h
8K bytes
2-way
cache
00F0 6000h
4K bytes
2-way
cache
2-way
cache
Copyright 2010 Texas Instruments Incorporated
00F0 7000h
4K bytes
00F0 8000h
C66x CorePac
83
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Multicore Fixed and Floating-Point System-on-Chip
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5.1.3 L2 Memory
The L2 memory configuration for the C6670 device is as follows:
• Total memory size is 4096KB
• Each core contains 1024KB of memory
• Local starting address for each core is 0080 0000h
L2 memory can be configured as all SRAM, all 4-way set-associative cache, or a mix of the two. The amount of L2
memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration Register
(L2CFG) of the C66x CorePac. Figure 5-4 shows the available SRAM/cache configurations for L2. By default, L2 is
configured as all SRAM after device reset.
ADVANCE INFORMATION
Figure 5-4
TMS320C6670 L2 Memory Configurations
C6497-8
000
L2 mode bits
001
010
011
100
101
110
L2 memory
Block base
address
0080 0000h
512Kbytes
1/2
SRAM
31/32
SRAM
ALL
SRAM
15/16
SRAM
7/8
SRAM
3/4
SRAM
0088 0000h
4-way
cache
256Kbytes
008C 0000h
128Kbytes
4-way
cache
4-way
cache
84
C66x CorePac
4-way
cache
4-way
cache
4-way
cache
008E 0000h
64Kbytes
32Kbytes
008F 0000h
008F 8000h
32Kbytes
008F FFFFh
Copyright 2010 Texas Instruments Incorporated
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Multicore Fixed and Floating-Point System-on-Chip
www.ti.com
SPRS689—November 2010
5.1.4 MSM SRAM
The MSM SRAM configuration for the C6670 device is as follows:
• Memory size is 2048KB
• The MSM can be configured as shared L2 or shared L3 memory
• Allows extension of external addresses from 2GB to up to 8GB
• Has built in memory protection features
The MSM SRAM is always configured as all SRAM. When configured as a shared L2, its contents can be cached in
L1P and L1D. When configured in shared L3 mode, it’s contents can be cached in L2 also. For more details on
external memory address extension and memory protection features, see the Multicore Shared Memory Controller
(MSMC) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59.
5.1.5 L3 Memory
The L3 ROM on the device is 128KB. The ROM contains software used to boot the device. There is no requirement
to block accesses from this portion to the ROM.
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ADVANCE INFORMATION
Global addresses that are accessible to all masters in the system are in all memory local to the processors. In addition,
local memory can be accessed directly by the associated processor through aliased addresses, where the eight MSBs
are masked to 0. The aliasing is handled within the CorePac and allows for common code to be run unmodified on
multiple cores. For example, address location 0x10800000 is the global base address for CorePac 0's L2 memory.
CorePac 0 can access this location by either using 0x10800000 or 0x00800000. Any other master on the device must
use 0x10800000 only. Conversely, 0x00800000 can by used by any of the four CorePacs as their own L2 base
addresses. For CorePac 0, as mentioned, this is equivalent to 0x10800000, for CorePac 1 this is equivalent to
0x11800000, and for CorePac 2 this is equivalent to 0x12800000. Local addresses should be used only for shared code
or data, allowing a single image to be included in memory. Any code/data targeted to a specific core, or a memory
region allocated during run-time by a particular CorePac should always use the global address only.
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Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
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5.2 Memory Protection
Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2
memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16 pages of L1P (2KB
each), 16 pages of L1D (2KB each), and 32 pages of L2 (32KB each). The L1D, L1P, and L2 memory controllers in
the C66x CorePac are equipped with a set of registers that specify the permissions for each memory page.
ADVANCE INFORMATION
Each page may be assigned with fully orthogonal user and supervisor read, write, and execute permissions. In
addition, a page may be marked as either (or both) locally accessible or globally accessible. A local access is a direct
DSP access to L1D, L1P, and L2, while a global access is initiated by a DMA (either IDMA or the EDMA3) or by
other system masters. Note that EDMA or IDMA transfers programmed by the DSP count as global accesses. On a
secure device, pages can be restricted to secure access only (default) or opened up for public, non-secure access.
The DSP and each of the system masters on the device are all assigned a privilege ID. It is only possible to specify
whether memory pages are locally or globally accessible.
The AIDx and LOCAL bits of the memory protection page attribute registers specify the memory page protection
scheme, see Table 5-1.
Table 5-1
AIDx
(1)
Bit
Available Memory Page Protection Schemes
Local Bit
Description
0
0
No access to memory page is permitted.
0
1
Only direct access by DSP is permitted.
1
0
Only accesses by system masters and IDMA are permitted (includes EDMA and IDMA accesses initiated by the DSP).
1
1
All accesses permitted.
End of Table 5-1
1 x = 0, 1, 2, 3, 4, 5
Faults are handled by software in an interrupt (or an exception, programmable within the CorePac interrupt
controller) service routine. A DSP or DMA access to a page without the proper permissions will:
• Block the access — reads return 0, writes are ignored
• Capture the initiator in a status register — ID, address, and access type are stored
• Signal event to DSP interrupt controller
The software is responsible for taking corrective action to respond to the event and resetting the error status in the
memory controller. For more information on memory protection for L1D, L1P, and L2, see the C66x CorePac User
Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59.
86
C66x CorePac
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Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
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5.3 Bandwidth Management
The priority level for operations initiated within the C66x CorePac are declared through registers in the CorePac.
These operations are:
• DSP-initiated transfers
• User-programmed cache coherency operations
• IDMA-initiated transfers
The priority level for operations initiated outside the CorePac by system peripherals is declared through the Priority
Allocation Register (PRI_ALLOC), see Section 4.4 ‘‘Bus Priorities’’ on page 80. System peripherals with no fields
in PRI_ALLOC have their own registers to program their priorities.
More information on the bandwidth management features of the CorePac can be found in the C66x CorePac
Reference Guide (literature number SPRUGW0.)
5.4 Power-Down Control
The C66x CorePac supports the ability to power-down various parts of the CorePac. The power-down controller
(PDC) of the CorePac can be used to power down L1P, the cache control hardware, the DSP, and the entire CorePac.
These power-down features can be used to design systems for lower overall system power requirements.
Note—The C6670 does not support power-down modes for the L2 memory at this time.
More information on the power-down features of the C66x CorePac can be found in the C66x CorePac Reference
Guide (literature number SPRUGW0).
5.5 CorePac Resets
Table 5-2 shows the reset types supported on the C6670 device and how they affect the resetting of the CorePac,
either both globally or just locally.
Table 5-2
Reset Type
CorePac Reset (Global or Local)
Global CorePac Reset
Local CorePac Reset
Y
Y
Power-On Reset
Hard Reset
Y
Y
Soft Reset
Y
Y
Local Reset
N
Y
End of Table 5-2
For more detailed information on the global and local CorePac resets, see the C66x CorePac User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 59. And for more detailed information on device resets, see
Section 7.7 ‘‘Reset Controller’’ on page 153.
Copyright 2010 Texas Instruments Incorporated
C66x CorePac
87
ADVANCE INFORMATION
When multiple requestors contend for a single C66x CorePac resource, the conflict is resolved by granting access to
the highest priority requestor. The following four resources are managed by the Bandwidth Management control
hardware:
• Level 1 Program (L1P) SRAM/Cache
• Level 1 Data (L1D) SRAM/Cache
• Level 2 (L2) SRAM/Cache
• Memory-mapped registers configuration bus
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
5.6 CorePac Revision
The version and revision of the C66x CorePac can be read from the CorePac Revision ID Register (MM_REVID)
located at address 0181 2000h. The MM_REVID register is shown in Table 5-3 and described in Table 5-4. The C66x
CorePac revision is dependant on the silicon revision being used.
Table 5-3
CorePac Revision ID Register (MM_REVID)
Address - 0181 2000h
Bit
31
30
29
28
27
26
25
(1)
ADVANCE INFORMATION
Bit
22
21
20
19
18
17
16
6
5
4
3
2
1
0
R-h
15
14
13
12
11
10
9
8
7
REVISION
Acronym
Reset
23
VERSION
Acronym
Reset
24
(1)
R-n
1 R/W = Read/Write; R = Read only; -n = value after reset
Table 5-4
CorePac Revision ID Register (MM_REVID) Field Descriptions
Bit
Acronym
Value
31:16
VERSION
-
Version of the C66x CorePac implemented on the device.
Description
15:0
REVISION
-
Revision of the C66x CorePac version implemented on the device.
End of Table 5-4
5.7 C66x CorePac Register Descriptions
See the C66x CorePac User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59 for register
offsets and definitions.
88
C66x CorePac
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Multicore Fixed and Floating-Point System-on-Chip
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ADVANCE INFORMATION
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C66x CorePac
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Multicore Fixed and Floating-Point System-on-Chip
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6 Device Operating Conditions
6.1 Absolute Maximum Ratings
Table 6-1
Absolute Maximum Ratings (1)
Over Operating Case Temperature Range (Unless Otherwise Noted)
ADVANCE INFORMATION
Supply voltage range (2):
CVDD
-0.3 V to TBD V
CVDD1
-0.3 V to TBD V
DVDD15
-0.3 V to TBD V
DVDD18
-0.3 V to TBD V
VREFSSTL
0.49 × DVDD15 to 0.51 × DVDD15
VDDT1, VDDT2, VDDT3
-0.3 V to TBD V
VDDT4, VDDT5, VDDT6
VDDR1, VDDR2, VDDR3
-0.3 V to TBD V
AVDDA1, AVDDA2, AVDDA3
-0.3 V to TBD V
VSS Ground
0V
LVCMOS (1.8V)
-0.3 V to TBD V
DDR3
-0.3 V to TBD V
2
Input voltage (VI) range:
Output voltage (VO) range:
IC
-0.3 V to TBD V
LVDS
-0.3 V to TBD V
LJCB
-0.3 V to TBD V
SERDES
-0.3 V to TBD V
LVCMOS (1.8V)
-0.3 V to TBD V
DDR3
-0.3 V to TBD V
2
IC
-0.3 V to TBD V
SERDES
-0.3 V to TBD V
Commercial
Operating case temperature range, TC:
Extended
1-GHz CPU
1.2-GHz CPU
1-GHz CPU
1.2-GHz CPU
0°C to 100°C
0°C to 95°C
-40°C to 100°C
-40°C to 95°C
LVCMOS (1.8V)
Overshoot/undershoot
(3)
DDR3
2
20% Overshoot/Undershoot for 20% of
Signal Duty Cycle
IC
Storage temperature range, Tstg:
-65°C to 150°C
End of Table 6-1
1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability.
2 All voltage values are with respect to VSS.
3 Overshoot/Undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8-V LVCMOS signals is DVDD18 + 0.20 × DVDD18 and
maximum undershoot value would be VSS - 0.20 × DVDD18
90
Device Operating Conditions
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
6.2 Recommended Operating Conditions
(2)
Min
Nom
1-GHz CPU
0.855
1
Max Unit
1.05
1.2-GHz CPU
0.855
1
1.05
CVDD
SR Core Supply
V
CVDD1
Core Supply
0.95
1
1.05
V
DVDD18
1.8-V supply I/O voltage
1.71
1.8
1.89
V
DVDD15
1.5-V supply I/O voltage
1.425
1.5
1.575
V
VREFSSTL
DDR3 reference voltage
0.49 × DVDD15
0.5 × DVDD15
0.51 × DVDD15
V
SerDes regulator supply
(3)
1.425
1.5
1.575
V
VDDAx
PLL analog supply
1.71
1.8
1.89
V
VDDTx
SerDes termination supply
0.95
1
1.05
V
VSS
Ground
0
0
0
V
VDDRx
LVCMOS (1.8 V)
VIH
High-level input voltage
2
IC
DDR3 EMIF
0.65 × DVDD18
V
0.7 × DVDD18
V
VREFSSTL + 0.1
V
LVCMOS (1.8 V)
VIL
Low-level input voltage
DDR3 EMIF
-0.3
2
IC
Commercial
TC
Operating case temperature
Extended
1-GHz CPU
1.2-GHz CPU
0
0.35 × DVDD18
V
VREFSSTL - 0.1
V
0.3 × DVDD18
V
100
°C
0
95
°C
1-GHz CPU
-40
100
°C
1.2-GHz CPU
-40
95
°C
ADVANCE INFORMATION
Recommended Operating Conditions (1)
Table 6-2
End of Table 6-2
1 All differential clock inputs comply with the LVDS Electrical Specification, IEEE 1596.3-1996 and all SERDES I/Os comply with the XAUI Electrical Specification, IEEE
802.3ae-2002.
2 All SERDES I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002.
3 Where x = 1, 2, 3, 4... to indicate all supplies of the same kind.
Copyright 2010 Texas Instruments Incorporated
Device Operating Conditions
91
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
6.3 Electrical Characteristics
Table 6-3
Electrical Characteristics
Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
Parameter
LVCMOS (1.8 V)
VOH
High-level output voltage
Test Conditions
(1)
IO = IOH
Min
Typ
Max Unit
DVDD18 - 0.45
DDR3
DVDD15 - 0.4
V
2 (2)
IC
LVCMOS (1.8 V)
VOL
Low-level output voltage
IO = IOL
0.45
DDR3
ADVANCE INFORMATION
2
IC
0.4
IO = 3 mA, pulled up to 1.8 V
No IPD/IPU
LVCMOS (1.8 V)
II
(3)
Input current [DC]
Internal pulldown
2
IC
IOH High-level output current [DC]
Low-level output current [DC]
IOL
-5
Internal pullup
0.1 × DVDD18 V < VI < 0.9 ×
DVDD18 V
(4)
Off-state output current [DC]
5
50
100
170
-170
-100
-50
-10
10
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
IOZ
LVCMOS (1.8 V)
V
0.4
μA
μA
mA
mA
TBD
-2
2
μA
End of Table 6-3
1 For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.
2 I2C uses open collector IOs and does not have a VOH Minimum.
3 II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II includes input leakage current and
off-state (Hi-Z) output leakage current.
4 IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
92
Device Operating Conditions
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Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
7 TMS320C6670 Peripheral Information and Electrical Specifications
This chapter covers the various peripherals on the TMS320C6670 device. Peripheral-specific information, timing
diagrams, electrical specifications, and register memory maps are described in this chapter.
7.1 Parameter Information
The data manual provides timing at the device pin. For output analysis, the transmission line and associated
parasitics (vias, multiple nodes, etc.) must also be taken into account. The transmission line delay varies depending
on the trace length. An approximate range for output delays can vary from 176 ps to 2 ns depending on the end
product design. For recommended transmission line lengths, see the appropriate application notes, user guides, and
design guides. A transmission line delay of 2 ns was used for all output measurements, except the DDR3, which was
evaluated using a 528-ps delay.
2
Figure 7-1 represents all device outputs, except differential or I C.
Figure 7-1
Test Load Circuit for AC Timing Measurements
Device
DDR3 Output Test Load
Transmission Line
Zo = 50 W
4 pF
Data Manual Timing
Reference Point
(Device Terminal)
Device
Output Test Load Excluding DDR3
Transmission Line
Zo = 50 W
5 pF
The load capacitance value stated is for characterization and measurement of AC timing signals only. This load
capacitance value does not indicate the maximum load the device is capable of driving.
Copyright 2010 Texas Instruments Incorporated
TMS320C6670 Peripheral Information and Electrical Specifications
93
ADVANCE INFORMATION
This section describes the conditions used to capture the electrical data seen in this chapter.
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
7.1.1 1.8-V Signal Transition Levels
All input and output timing parameters are referenced to 0.9 V for both 0 and 1 logic levels.
Figure 7-2
Input and Output Voltage Reference Levels for AC Timing Measurements
Vref = 0.9 V
All rise and fall transition timing parameters are reference to VIL MAX and VIH MIN for input clocks.
ADVANCE INFORMATION
Figure 7-3
Rise and Fall Transition Time Voltage Reference Levels
Vref = VIH MIN (or VOH MIN)
7.1.2 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a good board
design practice, such delays must always be taken into account. Timing values may be adjusted by
increasing/decreasing such delays. TI recommends using the available I/O buffer information specification (IBIS)
models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis
for a given system, see the Using IBIS Models for Timing Analysis application report in ‘‘Related Documentation
from Texas Instruments’’ on page 59. If needed, external logic hardware such as buffers may be used to compensate
any timing differences.
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and
from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin,
but also tends to improve the input hold time margins (Table 7-1 and Figure 7-4).
Table 7-1
Board-Level Timing Example
(see Figure 7-4)
No.
Description
1
Clock route delay
2
Minimum DSP hold time
3
Minimum DSP setup time
4
External device hold time requirement
5
External device setup time requirement
6
Control signal route delay
7
External device hold time
8
External device access time
9
DSP hold time requirement
10
DSP setup time requirement
11
Data route delay
End of Table 7-1
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Figure 7-4 shows a general transfer between the DSP and an external device. The figure also shows board route
delays and how they are perceived by the DSP and the external device
Figure 7-4
Board-Level Input/Output Timings
AECLKOUT
(Output from DSP)
1
AECLKOUT
(Input to External Device)
2
3
Control Signals
(Input to External Device)
6
5
4
ADVANCE INFORMATION
Control Signals (A)
(Output from DSP)
7
8
(B)
Data Signals
(Output from External Device)
10
(B)
Data Signals
(Input to DSP)
9
11
(A) Control signals include data for writes.
(B) Data signals are generated during reads from an external device.
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7.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
7.3 Power Supplies
The following sections describe the proper power-supply sequencing and timing needed to properly power on the
C6670. The various power supply rails and their primary function is listed in Table 7-2 below.
Table 7-2
ADVANCE INFORMATION
Name
Power Supply Rails on TMS320C6670
Primary Function
Voltage
Notes
CVDD
SmartReflex core supply voltage
0.9 - 1.1 V Includes core voltage for DDR3 module
CVDD1
Core supply voltage for memory
array
1.0 V
Fixed supply at 1.0 V
VDDT1
HyperLink SerDes termination
supply
1.0 V
Filtered version of CVDD1. Special considerations for noise. Filter is not needed if
HyperLink is not in use.
VDDT3
AIF SerDes termination supply
1.0 V
Filtered version of CVDD1. Special considerations for noise. Filter is not needed if AIF is
not in use.
VDDT2
SGMII/SRIO/PCIE SerDes
termination supply
1.0 V
Filtered version of CVDD1. Special considerations for noise. Filter is not needed if
SGMII/SRIO/PCIE is not in use.
DVDD15
1.5-V DDR3 IO supply
1.5 V
VDDR1
HyperLink SerDes regulator supply
1.5 V
Filtered version of DVDD15. Special considerations for noise. Filter is not needed if
HyperLink is not in use.
VDDR2
PCIE SerDes regulator supply
1.5 V
Filtered version of DVDD15. Special considerations for noise. Filter is not needed if PCIE
is not in use.
VDDR3
SGMII SerDes regulator supply
1.5 V
Filtered version of DVDD15. Special considerations for noise. Filter is not needed if
SGMII is not in use.
VDDR4
SRIO SerDes regulator supply
1.5 V
Filtered version of DVDD15. Special considerations for noise. Filter is not needed if SRIO
is not in use.
1.5 V
Filtered version of DVDD15. Special considerations for noise. Filter is not needed if AIF
is not in use.
VDDR5
AIF SerDes regulator supply
VDDR6
DVDD18
1.8-V IO supply
1.8V
AVDDA1
Main PLL supply
1.8 V
Filtered version of DVDD18. Special considerations for noise.
AVDDA2
DDR3 PLL supply
1.8 V
Filtered version of DVDD18. Special considerations for noise.
AVDDA3
PASS PLL supply
1.8 V
Filtered version of DVDD18. Special considerations for noise.
VREFSSTL
0.75-V DDR3 reference voltage
0.75 V
Should track the 1.5-V supply. Use 1.5 V as source.
VSS
Ground
GND
End of Table 7-2
7.3.1 Power-Up Sequencing
This section defines the requirements for a power up sequencing from a Power-on reset condition. There are two
acceptable power sequences for the device. The first sequence stipulates the core voltages starting before the IO
voltages as shown below.
1. CVDD
2. CVDD1, VDDT1-3
3. DVDD18, AVDD1, AVDD2 (HHV)
4. DVDD15, VDDR1-6
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The device initialization is broken into two phases. The first phase consists of the time period from the activation of
the first power supply until the point in which all supplies are active and at a valid voltage level. Either of the
sequencing scenarios described above can be implemented during this phase. The figures below show both the
core-before-IO voltage sequence and the IO-before-core voltage sequence. POR must be held low for the entire
power stabilization phase.
This is followed by the device initialization phase. Either POR or RESETFULL may be used to trigger the end of the
initialization phase, but both must be inactive for the initialization to complete. The differences between
POR-controlled initialization and RESETFULL initialization are described below. The following section has a
mention of REFCLK in many places. REFCLK here refers to the clock input that has been selected as the source for
the Main PLL. See Figure 7-23 for more details.
7.3.1.1 POR-Controlled Device Initialization
The timing diagrams in the figures below show the power sequencing and reset control of the device when
RESETFULL is held high and POR is used to control the device initialization. In this mode, POR must be held low
until the power has been stable for the required 100 μsec and the device initialization requirements have been met.
On the rising edge of POR, the HHV signal will go inactive allowing the core to control the state of the output buffers
and pulls. The POR must be held for the 100 μsec after the power has stabilized plus the time period between that100
μsec and when the clock is active in addition to the 16 μsecs following the active clock. If the clock becomes active
before the 100 μsec stabilization period has expired, only the additional 16 μsecs of POR is required to complete
initialization.
Note—REFCLK must always be active before POR can be removed.
7.3.1.1.1 Core-Before-IO Power Sequencing
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ADVANCE INFORMATION
The second sequence provides compatibility with other TI processors with the IO voltage starting before the core
voltages as shown below.
1. DVDD18, AVDD1, AVDD2 (HHV)
2. CVDD
3. CVDD1, VDDT1-3
4. DVDD15, VDDR1-6
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Multicore Fixed and Floating-Point System-on-Chip
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The timing diagram for core-before-IO power sequencing is shown in Figure 7-5 and defined in Table 7-3.
Figure 7-5
POR-Controlled Power Sequencing — Core Before IO
Pow er Stabilization Phase
C hip Initialization Phase
POR z
R ESETFULLz
ADVANCE INFORMATION
t4b
RESET z
t1
C VD D(core AVS)
t2a
t5
CVDD1 (core constant)
t6
t7
t3
DVDD18 (1.8V)
t2b
DVDD15 (1.5V)
t4a
t2c
REFC LKP&N
D DRC LKP&N
RESET STATz
PORz Controlled Reset Sequencing – Core before IO
Table 7-3
POR-Controlled Power Sequencing — Core Before IO (Part 1 of 2)
Time
System State
t1
Begin Power Stabilization Phase
• CVDD (core AVS) ramps up.
• POR must be held low through the power stabilization phase. Because POR is low, all the core logic that has async reset (created from
POR) is put into the reset state.
t2a
• CVDD1 (core constant) ramps at the same time or shortly following CVDD. Although ramping CVDD1 and CVDD simultaneously is
permitted, the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.
• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 (core constant) should trail CVDD
(core AVS) as this will ensure that the WLs in the memories are turned off and there is no current through the memory bit cells. If,
however, CVDD1 (core constant) ramps up before CVDD (core AVS), then the worst-case current could be on the order of twice the
specified draw of CVDD1.
t2b
• Once CVDD is valid, the clock drivers should be enabled. Although the clock inputs are not necessary at this time, they should either be
driven with a valid clock or be held in a static state with one leg high and one leg low.
t2c
• The DDRCLK and REFCLK may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR goes high
specified by t7.
t3
• DVDD18 (1.8 V) supply is ramped up followed coincidentally by HHV (1.8 V).
• Filtered versions of 1.8 V can ramp simultaneously with DVDD18.
• RESETSTAT is driven low once the DVDD18 supply is available.
• All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin
before DVDD18 is valid could cause damage to the device.
t4a
• DVDD15 (1.5 V) supply is ramped up following DVDD18. Although ramping DVDD18 and DVDD15 simultaneously is permitted, the
voltage for DVDD15 must never exceed DVDD18.
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Table 7-3
POR-Controlled Power Sequencing — Core Before IO (Part 2 of 2)
Time
System State
t4b
• RESETFULL and RESET may be driven high anytime after DVDD18 is at a valid level. In a POR controlled boot both RESETFULL and RESET
must be high before POR is driven high.
t5
• POR must continue to remain low for at least 100 μs after power has stabilized.
End Power Stabilization Phase
t6
• Device initialization requires 500 REFCLK periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec, so a delay
of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire 16 μs.
t7
• The rising edge of POR will remove the reset to the efuse farm, allowing the scan to begin.
• Once device initialization and the efuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be 10000 to 50000
clock cycles.
ADVANCE INFORMATION
End Device Initialization Phase
End of Table 7-3
7.3.1.1.2 IO-Before-Core Power Sequencing
The timing diagram for IO-before-core power sequencing is shown in Figure 7-6 and defined in Table 7-4.
Figure 7-6
POR-Controlled Power Sequencing — IO Before Core
Power Stabilization Phase
C hip Initialization Phase
PORz
RESETF ULLz
R ESETz
t2a
CVDD(core AVS)
t3a
t2b
CVD D1 (core constant)
t6
t1
t4
DVDD18 (1.8V)
DVDD15 (1.5V)
t7
t5
t3c
t3b
REFCLKP&N
D DRCLKP&N
RESETST ATz
PORz Controlled Reset Sequencing – IO before Core
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Multicore Fixed and Floating-Point System-on-Chip
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Table 7-4
www.ti.com
POR-Controlled Power Sequencing — IO Before Core
ADVANCE INFORMATION
Time
System State
t1
Begin Power Stabilization Phase
• DVDD18 (1.8 V) supply is ramped up followed coincidentally by HHV (1.8 V).
• Since POR is low all the core logic having async reset (created from POR) are put into reset state once the core supply ramps. POR must
remain low through Power Stabilization Phase.
• Filtered versions of 1.8V can ramp simultaneously with DVDD18.
• RESETSTAT is driven low once the DVDD18 supply is available.
• All input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before
DVDD18 could cause damage to the device.
t2a
• RESETFULL and RESET may be driven high anytime after DVDD18 is at a valid level. In a POR-controlled boot both RESETFULL and RESET
must be high before POR is driven high.
t2b
• CVDD (core AVS) ramps up.
t3a
• CVDD1 (core constant) ramps at the same time or following CVDD. Although ramping CVDD1 and CVDD simultaneously is permitted the
voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.
• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 (core constant) should trail CVDD
(core AVS) as this will ensure that the WLs in the memories are turned off and there is no current through the memory bit cells. If,
however, CVDD1 (core constant) ramps up before CVDD (core AVS) then the worst case current could be on the order of twice the
specified draw of CVDD1.
t3b
• Once CVDD is valid the clock drivers should be enabled. Although the clock inputs are not necessary at this time they should either be
driven with a valid clock or held is a static state with one leg high and one leg low.
t3c
• The DDRCLK and REFCLK may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR goes high
specified by t7.
t4
• DVDD15 (1.5 V) supply is ramped up following CVDD1.
t5
• POR must continue to remain low for at least 100 μs after power has stabilized.
End Power Stabilization Phase
t6
Begin Device Initialization
• Device initialization requires 500 REFCLK periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec so a delay
of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire 16 μs.
• POR must remain low.
t7
• The rising edge of the POR will remove the reset to the efuse farm allowing the scan to begin.
• Once device initialization and the efuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be 10000 to 50000
clock cycles.
End Device Initialization Phase
End of Table 7-4
7.3.1.2 RESETFULL-Controlled Device Initialization
The timing diagrams in the figures below show the power sequencing and reset control of the device when
RESETFULL is used to extend device initialization. In this mode, POR may be removed after the power has been
stable for the required 100 μsec, but RESETFULL may be held low until the device initialization requirements have
been met. On the rising edge of POR, the HHV signal will go inactive.
Note—REFCLK must always be active before POR can be removed.
7.3.1.2.1 Core-Before-IO Power Sequencing
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The timing diagram for core-before-IO power sequencing is shown in Figure 7-7 and defined in Table 7-5.
Figure 7-7
RESETFULL-Controlled Device Initialization — Core Before IO
Power Stabilization Phase
Chip Initialization Phase
PORz
t7
RESET FULLz
R ESETz
t1
t4b
CVDD(core AVS)
CVDD1 (core constant)
t6
t3
D VD D18 (1.8V)
t2b
t4a
t8
t2c
DVDD15 (1.5V)
R EF CLKP&N
DD RCLKP&N
RESET STATz
RESETFULLz Controlled Reset Sequencing – Core before IO
Table 7-5
RESETFULL-Controlled Device Initialization — Core Before IO (Part 1 of 2)
Time
System State
t1
Begin Power Stabilization Phase
• CVDD (core AVS) ramps up.
• POR must be held low through the power stabilization phase. Because POR is low, all the core logic that has async reset (created from
POR) is put into the reset state.
t2a
• CVDD1 (core constant) ramps at the same time or shortly following CVDD. Although ramping CVDD1 and CVDD simultaneously is
permitted, the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.
• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 (core constant) should trail CVDD
(core AVS) as this will ensure that the WLs in the memories are turned off and there is no current through the memory bit cells. If,
however, CVDD1 (core constant) ramps up before CVDD (core AVS), then the worst-case current could be on the order of twice the
specified draw of CVDD1.
t2b
• Once CVDD is valid the clock drivers should be enabled. Although the clock inputs are not necessary at this time, they should either be
driven with a valid clock or held is a static state with one leg high and one leg low.
t2c
• The DDRCLK and REFCLK may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR goes high
specified by t7.
t3
• DVDD18 (1.8 V) supply is ramped up followed coincidentally by HHV (1.8 V).
• Filtered versions of 1.8 V can ramp simultaneously with DVDD18.
• RESETSTAT is driven low once the DVDD18 supply is available.
• All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin
before DVDD18 is valid could cause damage to the device
t4a
• DVDD15 (1.5 V) supply is ramped up following DVDD18. Although ramping DVDD18 and DVDD15 simultaneously is permitted, the
voltage for DVDD15 must never exceed DVDD18.
t4b
• RESET may be driven high anytime after DVDD18 is at a valid level. In a RESETFULL-controlled boot, both POR
and RESET must be high before RESETFULL is driven high.
t5
• POR must continue to remain low for at least 100 μs after power has stabilized.
End Power Stabilization Phase
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ADVANCE INFORMATION
t5
t2a
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
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Table 7-5
www.ti.com
RESETFULL-Controlled Device Initialization — Core Before IO (Part 2 of 2)
Time
System State
t6
Begin Device Initialization Phase
• Device initialization requires 500 REFCLK periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec, so a delay
of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire 16 μs. In RESETFULL-controlled
boot, the RESETFULL signal will continue to be low after POR transitions high.
t7
• RESETFULL is held low for some period after POR has transitioned high.
t8
• The rising edge of the RESETFULL will remove the reset to the efuse farm, allowing the scan to begin.
• Once device initialization and the efuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be 10000 to 50000
clock cycles.
End Device Initialization Phase
ADVANCE INFORMATION
End of Table 7-5
7.3.1.2.2 IO-Before-Core Power Sequencing
The timing diagram for core-before-IO power sequencing is shown in Figure 7-8 and defined in Table 7-6.
Figure 7-8
RESETFULL-Controlled Device Initialization — IO Before Core
Pow er Stabilization Phase
C hip Initialization Phase
POR z
t7
R ESETFULLz
RESET z
C VD D(core AVS)
t5
t3a
t2b
t6
t2a
CVDD1 (core constant)
DVDD18 (1.8V)
t4
t8
t1
t3c
DVDD15 (1.5V)
t3b
REFC LKP&N
D DRC LKP&N
RESET STATz
RESETFULLz Controlled Reset Sequencing – IO before Core
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RESETFULL-Controlled Device Initialization — IO Before Core
Time
System State
t1
Begin Power Stabilization Phase
• DVDD18 (1.8 V) supply is ramped up followed coincidentally by HHV (1.8 V).
• Because POR is low, all the core logic that has async reset (created from POR) is put into the reset state once the core supply ramps. POR
must remain low through the Power Stabilization Phase.
• Filtered versions of 1.8V can ramp simultaneously with DVDD18.
• RESETSTAT is driven low once the DVDD18 supply is available.
• All input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before
DVDD18 could cause damage to the device.
t2a
• RESET may be driven high anytime after DVDD18 is at a valid level. In a RESETFULL-controlled boot both POR and RESET must be high
before RESETFULL is driven high.
t2b
• CVDD (core AVS) ramps up.
t3a
CVDD1 (core constant) ramps at the same time or following CVDD. Although ramping CVDD1 and CVDD simultaneously is permitted the
voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.
The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 (core constant) should trail CVDD
(core AVS) as this will ensure that the WLs in the memories are turned off and there is no current through the memory bit cells. If,
however, CVDD1 (core constant) ramps up before CVDD (core AVS) then the worst case current could be on the order of twice the
specified draw of CVDD1.
t3b
• Once CVDD is valid, the clock drivers should be enabled. Although the clock inputs are not necessary at this time, they should either be
driven with a valid clock or held is a static state with one leg high and one leg low.
t3c
• The DDRCLK and REFCLK may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR goes high
specified by t7.
t4
• DVDD15 (1.5 V) supply is ramped up following CVDD1.
t5
• POR must continue to remain low for at least 100 μs after power has stabilized.
End Power Stabilization Phase
t6
Begin Device Initialization
• Device initialization requires 500 REFCLK periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec so a delay
of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire 16 μs.
• POR must remain low.
t7
• RESETFULL is held low for some period after POR has transitioned high.
• The rising edge of the RESETFULL will remove the reset to the efuse farm allowing the scan to begin.
t8
• The rising edge of the RESETFULL will remove the reset to the efuse farm allowing the scan to begin.
• Once device initialization and the efuse farm scan are complete the RESETSTAT signal is driven high. This delay will be 10000 to 50000
clock cycles.
End Device Initialization Phase
End of Table 7-6
7.3.1.3 Prolonged Resets
Holding the device in POR, RESETFULL, or RESET for long periods of time will affect the long term reliability of
the part. The device should not be held in a reset for times exceeding one hour and should not be held in reset for
more the 5% of the time during which power is applied. Exceeding these limits will cause a gradual reduction in the
reliability of the part. This can be avoided by allowing the DSP to boot and then configuring it to enter a hibernation
state soon after power is applied. This will satisfy the reset requirement while limiting the power consumption of the
device.
7.3.2 Power-Down Sequence
The power down sequence is the exact reverse of the power-up sequence described above. The goal is to prevent a
large amount of static current and to prevent overstress of the device. A power-good circuit that monitors all the
supplies for the device should be used in all designs. If a catastrophic power supply failure occurs on any voltage rail,
POR should transition to low to prevent over-current conditions that could possibly impact device reliability.
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ADVANCE INFORMATION
Table 7-6
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
A system power monitoring solution is needed to shut down power to the board if a power supply fails. Long-term
exposure to an environment in which one of the power supply voltages is no longer present will affect the reliability
of the device. Holding the device in reset is not an acceptable solution because prolonged periods of time with an
active reset can also affect long term reliability.
Some of the clock inputs are required to be present for the device to initialize correctly, but behavior of many of the
clocks is contingent on the state of the boot configuration pins. Table 7-7 describes the clock sequencing and the
conditions that affect the clock operation. Note that all clock drivers should be in a high-impedance state until
CVDD is at a valid level and that all clock inputs either be active or in a static state with one leg pulled low and the
other connected to CVDD.
ADVANCE INFORMATION
Table 7-7
Clock Sequencing
Clock
Condition
Sequencing
DDRCLK
None
Must be present 16 μsec before POR transitions high.
SYSCLK
ALTCORECLK
PASSCLK
CORECLKSEL = 0
SYSCLK used to clock the core PLL. It must be present 16 μsec before POR transitions high.
CORECLKSEL = 1
SYSCLK used only for AIF. Clock most be present before the reset to the AIF is removed.
CORECLKSEL = 0
ALTCORECLK is not used and should be tied to a static state.
CORECLKSEL = 1
ALTCORECLK is used to clock the core PLL. It must be present 16 μsec before POR transitions high.
PASSCLKSEL = 0
PASSCLK is not used and should be tied to a static state.
PASSCLKSEL = 1
PASSCLK is used as a source for the PA_SS PLL. It must be present before the PA_SS PLL is removed from
reset and programmed.
An SGMII port will be used.
SRIOSGMIICLK must be present 16 μsec before POR transitions high.
SGMII will not be used. SRIO SRIOSGMIICLK must be present 16 μsec before POR transitions high.
will be used as a boot device.
SRIOSGMIICLK SGMII will not be used. SRIO
will be used after boot.
PCIECLK
MCMCLK
SRIOSGMIICLK is used as a source to the SRIO SERDES PLL. It must be present before the SRIO is
removed from reset and programmed.
SGMII will not be used. SRIO
will not be used.
SRIOSGMIICLK is not used and should be tied to a static state.
PCIE will be used as a boot
device.
PCIECLK must be present 16 μsec before POR transitions high.
PCIE will be used after boot.
PCIECLK is used as a source to the PCIE SERDES PLL. It must be present before the PCIE is removed from
reset and programmed.
PCIE will not be used.
PCIECLK is not used and should be tied to a static state.
HyperLink will be used as a
boot device.
MCMCLK must be present 16 μsec before POR transitions high.
HyperLink will be used after
boot.
MCMCLK is used as a source to the HyperLink SERDES PLL. It must be present before the HyperLink is
removed from reset and programmed.
HyperLink will not be used.
MCMCLK is not used and should be tied to a static state.
End of Table 7-7
7.3.3 Power Supply Decoupling and Bulk Capacitors
In order to properly decouple the supply planes on the PCB from system noise, decoupling and bulk capacitors are
required. Bulk capacitors are used to minimize the effects of low frequency current transients and decoupling or
bypass capacitors are used to minimize higher frequency noise. For recommendations on selection of Power Supply
Decoupling and Bulk capacitors see the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation
from Texas Instruments’’ on page 59.
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7.3.4 SmartReflex
Texas Instruments' SmartReflex technology is used to decrease both static and dynamic power consumption while
maintaining the device performance. SmartReflex in the TMS320C6670 device is a feature that allows the core
voltage to be optimized based on the process corner of the device. This requires a voltage regulator for each
TMS320C6670 device.
To guarantee maximizing performance and minimizing power consumption of the device, SmartReflex is required
to be implemented whenever the TMS320C6670 device is used. The voltage selection is done using 4 VCNTL pins
which are used to select the output voltage of the core voltage regulator.
For information on implementation of SmartReflex see the Power Management for KeyStone Devices application
report and the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation from Texas Instruments’’
on page 59.
Table 7-8
SmartReflex 4-Pin VID Interface Switching Characteristics
(see Figure 7-9)
No.
Parameter
Min
Max
Unit
1
tosu(Bn-SELECTL)
Setup Time - VCNTL[2:0] (B[2:0]]) valid before VCNTL[3] (Select) low
35.00
μs
2
toh(SELECTL-Bn)
Hold Time - VCNTL[2:0] (B[2:0]]) valid after VCNTL[3] (Select) low
35.00
μs
3
tosu(Bn-SELECTH)
Setup Time - VCNTL[2:0] (B[2:0]]) valid before VCNTL[3] (Select) high
35.00
μs
4
toh(SELECTH-Bn)
Hold Time - VCNTL[2:0] (B[2:0]]) valid after VCNTL[3] (Select) high
35.00
μs
End of Table 7-8
Figure 7-9
SmartReflex 4-Pin VID Interface Timing
2
1
4
3
VCNTL[3] (Select)
VCNTL[2:0] (B[2:0])
Table 7-9
LSB VID[2:0]
SmartReflex I2C Interface Timing Requirements
(1)
MSB VID[5:3]
(Part 1 of 2)
(see Figure 7-10)
Standard Mode
No.
Min
Max
Fast Mode
Min
Max
Unit
s
1
tc(VCL)
Cycle time, VCL
10
2.5
μs
2
tsu(VCLH-VDL)
Setup Time, VCL high before VD low (for a repeated START condition)
4.7
0.6
μs
4
0.6
μs
4.7
1.3
μs
4
0.6
μs
250
100 (2)
ns
3
th(VDL-VCLL)
Hold time, VCL low after VD low (for a START and a repeated START condition
4
tw(VCLL)
Pulse duration, VCL low
5
tw(VCLH)
Pulse duration, VCL high
6
tsu(VDV-VCLH) Setup time, VD valid before VCL high
Copyright 2010 Texas Instruments Incorporated
TMS320C6670 Peripheral Information and Electrical Specifications
105
ADVANCE INFORMATION
Increasing the device complexity increases its power consumption and with the smaller transistor structures
responsible for higher achievable clock rates and increased performance, comes an inevitable penalty, increasing the
leakage currents. Leakage currents are present in any active circuit, independently of clock rates and usage scenarios.
This static power consumption is mainly determined by transistor type and process technology. Higher clock rates
also increase dynamic power, the power used when transistors switch. The dynamic power depends mainly on a
specific usage scenario, clock rates, and I/O activity.
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
SmartReflex I2C Interface Timing Requirements
Table 7-9
(1)
(Part 2 of 2)
(see Figure 7-10)
Standard Mode
No.
Min
Max
Min
Max
Unit
s
3.45
0 (3)
0.9 (4)
μs
th(VCLL-VD)
Hold time, VD valid after VCL low (for IIC bus devices)
0 (3)
8
tw(VDH)
Pulse duration, VD high between STOP and START conditions
4.7
9
tr(SDA)
Rise time, SDA
7
Fast Mode
1.3
1000
μs
20 + 0.1Cb
(5)
300
μs
10
tr(SCL)
Rise time, SCL
1000
20 + 0.1Cb
(5)
300
ns
11
tf(SDA)
Fall time, SDA
300
20 + 0.1Cb
(5)
300
ns
20 + 0.1Cb
(5)
300
ns
Fall time, SCL
300
ADVANCE INFORMATION
12
tf(SCL)
13
tsu(VCLH-VDH) Setup time, high before VD high (for STOP condition)
4
tw(SP)
0
14
Cb
Pulse duration, spike (must be suppressed)
(5)
0.6
50
Capacitive load for each bus line
μs
0
400
50
ns
400
pF
End of Table 7-9
1 The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down
2
2
2 A Fast-mode I C-bus™ device can be used in a Standard-mode I C-bus™ system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the
case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
3 A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of
SCL.
4 The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
5 Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
SmartReflex I2C Interface Receive Timings
Figure 7-10
11
9
SDA
8
6
4
14
13
5
10
SCL
12
1
3
7
2
3
Stop
Table 7-10
Start
Repeated
Start
SmartReflex I2C Interface Switching Characteristics
(1)
Stop
(Part 1 of 2)
(see Figure 7-11)
Standard Mode
No.
16
Parameter
tc(VCL)
17
tosu(VCLH-VDL) Setup Time, VCL high before VD low (for a repeated START condition)
18
toh(VDL-VCLL)
Hold time, VCL low after VD low (for a START and a repeated START condition
19
tw(VCLL)
Pulse duration, VCL low
20
tw(VCLH)
Pulse duration, VCL high
21
tosu(VDV-VCLH) Setup time, VD valid before VCL high
22
toh(VCLL-VD)
Hold time, VD valid after VCL low (for IIC bus devices)
23
tw(VDH)
Pulse duration, VD high between STOP and START conditions
106
Min
Cycle time, VCL
TMS320C6670 Peripheral Information and Electrical Specifications
Max
Fast Mode
Min
Max Unit
10
2.5
ms
4.7
0.6
ms
4
0.6
ms
4.7
1.3
ms
4
0.6
ms
250
100
0
0
4.7
1.3
ns
0.9
ms
ms
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
2
Table 7-10
SmartReflex I C Interface Switching Characteristics
(1)
(Part 2 of 2)
(see Figure 7-11)
Standard Mode
No.
24
Parameter
tr(SDA)
Min
Rise time, SDA
Fast Mode
Max
Min
Max Unit
1000 20 + 0.1Cb (1)
300
ns
25
tr(SCL)
Rise time, SCL
1000 20 + 0.1Cb
(1)
300
ns
26
tf(SDA)
Fall time, SDA
300 20 + 0.1Cb
(1)
300
ns
300 20 + 0.1Cb
(1)
300
tf(SCL)
Fall time, SCL
28
tsu(VCLH-VDH)
Setup time, high before VD high (for STOP condition)
Cp
Capacitance for each I C pin
4
2
0.6
10
ns
ms
10
pF
ADVANCE INFORMATION
27
End of Table 7-10
1 Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
Figure 7-11
SmartReflex I2C Interface Transmit Timings
24
26
SDA
23
21
19
28
20
25
SCL
27
16
18
22
17
18
Stop
Start
Copyright 2010 Texas Instruments Incorporated
Repeated
Start
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7.4 Enhanced Direct Memory Access (EDMA3) Controller
The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-mapped
slave endpoints on the device. The EDMA3 services software-driven paging transfers (e.g., data movement between
external memory and internal memory), performs sorting or subframe extraction of various data structures, services
event driven peripherals, and offloads data transfers from the device CPU.
There are 3 EDMA Channel Controllers on the device, TPCC0, TPCC1, and TPCC2. TPCC0 is optimized to be used
for transfers to/from/within the MSMC and DDR-3 Subsytems. The others are to be used for the remaining traffic.
ADVANCE INFORMATION
Each EDMA3 Channel Controller includes the following features:
• Fully orthogonal transfer description
– 3 transfer dimensions:
› Array (multiple bytes)
› Frame (multiple arrays)
› Block (multiple frames)
– Single event can trigger transfer of array, frame, or entire block
– Independent indexes on source and destination
• Flexible transfer definition:
– Increment or FIFO transfer addressing modes
– Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous
transfers, all with no CPU intervention
– Chaining allows multiple transfers to execute with one event
• 128 PaRAM entries for TPCC0, 512 each for TPCC1 and TPCC2
– Used to define transfer context for channels
– Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry
• 16 DMA channels for TPCC0, 64 each for TPCC1 and TPCC2
– Manually triggered (CPU writes to channel controller register), external event triggered, and chain
triggered (completion of one transfer triggers another)
• 8 Quick DMA (QDMA) channels per TPCCx
– Used for software-driven transfers
– Triggered upon writing to a single PaRAM set entry
• 2 transfer controllers and 2 event queues with programmable system-level priority for TPCC0, 4 transfer
controllers and 4 event queues with programmable system-level priority for each of TPCC1 and TPCC2
• Interrupt generation for transfer completion and error conditions
• Debug visibility
– Queue watermarking/threshold allows detection of maximum usage of event queues
– Error and status recording to facilitate debug
In the context of this document, TPTCs associated with TPCC0 are referred to as TPCC0 TPTC0 and1. TPTCs
associated with TPCC1 and 2 are each referred to as TPCCx TPTC0 - 3, where x is 1 or 2. Each of the transfer
controllers has a direct connection to the switched central resource (SCR). Table 4-1 ‘‘SCR Connection Matrix’’ lists
the peripherals that can be accessed by the transfer controllers.
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7.4.1 EDMA3 Device-Specific Information
For the range of memory addresses that include EDMA3 Channel Controller (TPCC) Control Registers and
EDMA3 Transfer Controller (TPTC) Control Register see Section 2.3 ‘‘Memory Map Summary’’ on page 18. For
memory offsets and other details on TPCC and TPTC Control Registers entries, see the Enhanced Direct Memory
Access 3 (EDMA3) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on
page 59. Refer to Table 7-11 for offset addresses on Parameter RAM (PaRAM) registers.
Table 7-11
EDMA3 Parameter RAM Contents
(1)
PaRAM Set Number
Offset Address
Parameters
0
4000h to 401Fh
PaRAM set 0
1
4020h to 403Fh
PaRAM set 1
2
4040h to 405Fh
PaRAM set 2
3
4060h to 407Fh
PaRAM set 3
4
4080h to 409Fh
PaRAM set 4
5
40A0h to 40BFh
PaRAM set 5
6
40C0h to 40DFh
PaRAM set 6
7
40E0h to 40FFh
PaRAM set 7
8
4100h to 411Fh
PaRAM set 8
9
4120h to 413Fh
PaRAM set 9
...
...
...
63
47E0h to 47FFh
PaRAM set 63
64
4800h to 481Fh
PaRAM set 64
65
4820h to 483Fh
PaRAM set 65
...
...
...
254
5FC0h to 5FDFh
PaRAM set 254
255
5FE0h to 5FFFh
PaRAM set 255
...
...
...
510
7FC0h to 7FDFh
PaRAM set 254
511
7FE0h to 7FFFh
PaRAM set 255
1 A PaRAM set can be configured for use with either DMA channel, QDMA channel, or as a reload link set.
Copyright 2010 Texas Instruments Incorporated
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ADVANCE INFORMATION
The EDMA supports two addressing modes: constant addressing and increment addressing mode. Constant
addressing mode is applicable to a very limited set of use cases; for most applications increment mode can be used.
On the C6670 DSP, the EDMA can use constant addressing mode only with the Enhanced Viterbi-Decoder
Coprocessor (VCP) and the Enhanced Turbo Decoder Coprocessor (TCP). Constant addressing mode is not
supported by any other peripheral or internal memory in the DSP. Note that increment mode is supported by all
peripherals, including VCP and TCP. For more information on these two addressing modes, see the Enhanced Direct
Memory Access 3 (EDMA3) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’
on page 59.
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
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7.4.2 EDMA3 Channel Synchronization Events
The EDMA3 supports up to 16 DMA channels for TPCC0, 64 each for TPCC1 and TPCC2 that can be used to
service system peripherals and to move data between system memories. DMA channels can be triggered by
synchronization events generated by system peripherals. The following tables lists the source of the synchronization
event associated with each of the EDMA TPCC DMA channels. On the C6670, the association of each
synchronization event and DMA channel is fixed and cannot be reprogrammed.
For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured, processed,
prioritized, linked, chained, and cleared, etc., see the Enhanced Direct Memory Access 3 (EDMA3) for KeyStone
Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59.
ADVANCE INFORMATION
Table 7-12
TPCC0 Events for C6670
Event Number
Event
0~5
Reserved
Event Description
6
INTC2_OUT40
Interrupt Controller Output
7
INTC2_OUT41
Interrupt Controller Output
8
INTC2_OUT0
Interrupt Controller Output
9
INTC2_OUT1
Interrupt Controller Output
10
INTC2_OUT2
Interrupt Controller Output
11
INTC2_OUT3
Interrupt Controller Output
12
INTC2_OUT4
Interrupt Controller Output
13
INTC2_OUT5
Interrupt Controller Output
14
INTC2_OUT6
Interrupt Controller Output
15
INTC2_OUT7
Interrupt Controller Output
End of Table 7-12
Table 7-13
TPCC1 Events for C6670 (Part 1 of 2)
Event Number
Event
Event Description
0
SPIINT0
SPI interrupt
1
SPIINT1
SPI interrupt
2
SPIXEVT
Transmit event
3
SPIREVT
Receive event
4
I2CREVT
I2C Receive event
5
I2CXEVT
I2C Transmit event
6
GPINT0
GPIO Interrupt
7
GPINT1
GPIO Interrupt
8
GPINT2
GPIO Interrupt
9
GPINT3
GPIO Interrupt
10
AIF_SEVT0
AIF radio timing sync event 0
11
AIF_SEVT1
AIF radio timing sync event 1
12
AIF_SEVT2
AIF radio timing sync event 2
13
AIF_SEVT3
AIF radio timing sync event 3
14
AIF_SEVT4
AIF radio timing sync event 4
15
AIF_SEVT5
AIF radio timing sync event 5
16
AIF_SEVT6
AIF radio timing sync event 6
17
AIF_SEVT7
AIF radio timing sync event 7
18
SEMINT0
Semaphore interrupt
19
SEMINT1
Semaphore interrupt
110
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Multicore Fixed and Floating-Point System-on-Chip
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TPCC1 Events for C6670 (Part 2 of 2)
Event Number
Event
Event Description
20
SEMINT2
Semaphore interrupt
21
SEMINT3
Semaphore interrupt
22
TINT4L
Timer interrupt low
23
TINT4H
Timer interrupt high
24
TINT5L
Timer interrupt low
25
TINT5H
Timer interrupt high
26
TINT6L
Timer interrupt low
27
TINT6H
Timer interrupt high
28
TINT7L
Timer interrupt low
29
TINT7H
Timer interrupt high
30 - 44
Reserved
45
INTC1_OUT2
Interrupt Controller Output
46
INTC1_OUT3
Interrupt Controller Output
47
INTC1_OUT4
Interrupt Controller Output
48
INTC1_OUT5
Interrupt Controller Output
49
INTC1_OUT6
Interrupt Controller Output
50
INTC1_OUT7
Interrupt Controller Output
51
INTC1_OUT8
Interrupt Controller Output
52
INTC1_OUT9
Interrupt Controller Output
53
INTC1_OUT10
Interrupt Controller Output
54
INTC1_OUT11
Interrupt Controller Output
55
INTC1_OUT12
Interrupt Controller Output
56
INTC1_OUT13
Interrupt Controller Output
57
INTC1_OUT14
Interrupt Controller Output
58
INTC1_OUT15
Interrupt Controller Output
59
INTC1_OUT16
Interrupt Controller Output
60
INTC1_OUT17
Interrupt Controller Output
61
INTC1_OUT18
Interrupt Controller Output
62
INTC1_OUT19
Interrupt Controller Output
63
INTC1_OUT20
Interrupt Controller Output
ADVANCE INFORMATION
Table 7-13
End of Table 7-13
Table 7-14
TPCC2 Events for C6670 (Part 1 of 3)
Event Number
Event
Event Description
0
TCP3D_AREVT0
TCP3D_A Receive event0
1
TCP3D_AREVT1
TCP3D_A Receive event1
2
TCP3EREVT
TCP3e read event
3
TCP3EWEVT
TCP3e Write event
4
URXEVT
UART Receive Event
5
UTXEVT
UART Transmit Event
6
GPINT0
GPIO Interrupt
7
GPINT1
GPIO Interrupt
8
GPINT2
GPIO Interrupt
9
GPINT3
GPIO Interrupt
Copyright 2010 Texas Instruments Incorporated
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Multicore Fixed and Floating-Point System-on-Chip
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Table 7-14
www.ti.com
TPCC2 Events for C6670 (Part 2 of 3)
Event Number
Event
Event Description
10
VCPAREVT
Receive event
11
VCPAXEVT
Transmit event
12
VCPBREVT
Receive event
13
VCPBXEVT
Transmit event
14
VCPCREVT
Receive event
15
VCPCXEVT
Transmit event
16
VCPDREVT
Receive event
ADVANCE INFORMATION
17
VCPDXEVT
Transmit event
18
SEMINT0
Semaphore interrupt
19
SEMINT1
Semaphore interrupt
20
SEMINT2
Semaphore interrupt
21
SEMINT3
Semaphore interrupt
22
TINT4L
Timer interrupt low
23
TINT4H
Timer interrupt high
24
TINT5L
Timer interrupt low
25
TINT5H
Timer interrupt high
26
TINT6L
Timer interrupt low
27
TINT6H
Timer interrupt high
28
TINT7L
Timer interrupt low
29
TINT7H
Timer interrupt high
30
SPIXEVT
SPI Transmit event
31
SPIREVT
SPI Receive event
32
I2CREVT
I2C Receive event
33
I2CXEVT
I2C Transmit event
34
TCP3D_BREVT0
TCP3D_B Receive event0
35
TCP3D_BREVT1
TCP3D_B Receive event1
36
INTC1_OUT23
Interrupt Controller Output
37
INTC1_OUT24
Interrupt Controller Output
38
INTC1_OUT25
Interrupt Controller Output
39
INTC1_OUT26
Interrupt Controller Output
40
INTC1_OUT27
Interrupt Controller Output
41
INTC1_OUT28
Interrupt Controller Output
42
INTC1_OUT29
Interrupt Controller Output
43
INTC1_OUT30
Interrupt Controller Output
44
INTC1_OUT31
Interrupt Controller Output
45
INTC1_OUT32
Interrupt Controller Output
46
INTC1_OUT33
Interrupt Controller Output
47
INTC1_OUT34
Interrupt Controller Output
48
INTC1_OUT35
Interrupt Controller Output
49
INTC1_OUT36
Interrupt Controller Output
50
INTC1_OUT37
Interrupt Controller Output
51
INTC1_OUT38
Interrupt Controller Output
52
INTC1_OUT39
Interrupt Controller Output
53
INTC1_OUT40
Interrupt Controller Output
112
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Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Table 7-14
TPCC2 Events for C6670 (Part 3 of 3)
Event Number
Event
Event Description
54
INTC1_OUT41
Interrupt Controller Output
55
INTC1_OUT42
Interrupt Controller Output
56
INTC1_OUT43
Interrupt Controller Output
57
INTC1_OUT44
Interrupt Controller Output
58 - 63
Reserved
ADVANCE INFORMATION
End of Table 7-14
Copyright 2010 Texas Instruments Incorporated
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7.5 Interrupts
7.5.1 Interrupt Sources and Interrupt Controller
The CPU interrupts on the C6670 device are configured through the C66x CorePac interrupt controller. The
interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU interrupt inputs
(CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced emulation logic. The 128 system
events consist of both internally-generated events (within the CorePac) and chip-level events.
ADVANCE INFORMATION
Additional system events are routed to each of the C66x CorePacs to provide chip-level events that are not required
as CPU interrupts/exceptions to be routed to the interrupt controller as emulation events. In addition, error-class
events or infrequently used events are also routed through the system event router to offload the C66x CorePac
interrupt selector. This is accomplished through INTC blocks, INTC[2:0], with one controller per C66x CorePac.
This is clocked using CPU/6.
The event controllers consist of simple combination logic to provide additional events to each C66x CorePac, plus
the TPCC. INTC0 provides 16 additional events to each of the C66x CorePacs, INTC1 provides 21 and 30 additional
events to TPCC1 and TPCC2 respectively, and INTC provides 8 and 32 additional events to TPCC0 and HyperLink
respectively.
The events that are routed to the C66x CorePacs for AET purposes, from those TPCC and FSYNC events that are
not otherwise provided to each C66x CorePac. For more details on the INTC features, please see the Interrupt
Controller (INTC) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on
page 59.
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Figure 7-12 shows the C6670 interrupt topology.
Figure 7-12
TMS320C6670 Interrupt Topology
8 Broadcast Events from AIF
6 Reserved Secondary Events
65 Primary Events
Core0
INTC0
119 Core-only Secondary Events
18 Secondary Events
65 Primary Events
Core1
83 Common Events
ADVANCE INFORMATION
18 Secondary Events
65 Primary Events
Core2
18 Secondary Events
65 Primary Events
Core3
18 Secondary Events
8 Broadcast Events from INTC0
12 Reserved Secondary Events
83 Common Events
45 Primary Events
INTC1
5 Reserved Secondary Events
19 Secondary Events
42 Primary Events
72 TPCC-only Events
22 Secondary Events
32 Queue Events
5 Reserved Secondary Events
CPU/3
TPCC1
CPU/3
TPCC2
HyperLink
32 Secondary Events
59 Events
INTC2
6 Primary Events
10 Secondary Events
CPU/2
TPCC0
6670
Table 7-15 shows the mapping of system events. For more information on the Interrupt Controller, see the C66x
CorePac User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59.
Table 7-15
TMS320C6670 System Event Mapping — C66x CorePac Primary Interrupts (Part 1 of 4)
Event Number
Interrupt Event
Description
0
EVT0
Event combiner 0 output
1
EVT1
Event combiner 1 output
2
EVT2
Event combiner 2 output
3
EVT3
4
TETBHFULLINTn
Event combiner 3 output
1
5
TETBFULLINTn
6
TETBACQINTn1
1
TETB is half full
TETB is full
Acquisition has been completed
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Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 7-15
Event Number
7
www.ti.com
TMS320C6670 System Event Mapping — C66x CorePac Primary Interrupts (Part 2 of 4)
Interrupt Event
TETBOVFLINTn
Description
1
Overflow Condition Interrupt
1
Underflow Condition Interrupt
8
TETBUNFLINTn
9
EMU_DTDMA
10
MSMC_mpf_errorn
11
Reserved
Emulation interrupt for:
1. Host scan access
2. DTDMA transfer complete
3. AET interrupt
4
Memory protection fault indicators for local CorePac
ADVANCE INFORMATION
12
Reserved
13
IDMA0
14
IDMA1
15
SEMERRn
2
Semaphore Error Interrupt
16
SEMINTn
2
Semaphore Interrupt
17
PCIEXpress_MSI_INTn3
IDMA Channel 0 Interrupt
IDMA Channel 1 Interrupt
Message Signaled Interrupt Mode
3
18
PCIEXpress_MSI_INTn+1
19
Reserved
20
INTDST(n+16)10
21
INTDST(n+20)
Message Signaled Interrupt Mode
SRIO Interrupt
10
SRIO Interrupt
7
Interrupt Controller Output
7
Interrupt Controller Output
24
7
INTC0_OUT(64+2+10*n)
Interrupt Controller Output
25
INTC0_OUT(64+3+10*n)7
Interrupt Controller Output
26
7
INTC0_OUT(64+4+10*n)
Interrupt Controller Output
27
INTC0_OUT(64+5+10*n)
7
Interrupt Controller Output
7
Interrupt Controller Output
7
Interrupt Controller Output
30
7
INTC0_OUT(64+8+10*n)
Interrupt Controller Output
31
INTC0_OUT(64+9+10*n)7
Interrupt Controller Output
22
INTC0_OUT(64+0+10*n)
23
INTC0_OUT(64+1+10*n)
28
INTC0_OUT(64+6+10*n)
29
INTC0_OUT(64+7+10*n)
32
QM_INT_LOW_0
QM Interrupt for 0~31 Queues
33
QM_INT_LOW_1
QM Interrupt for 32~63 Queues
34
QM_INT_LOW_2
QM Interrupt for 64~95 Queues
35
QM_INT_LOW_3
QM Interrupt for 96~127 Queues
36
QM_INT_LOW_4
QM Interrupt for 128~159 Queues
37
QM_INT_LOW_5
QM Interrupt for 160~191 Queues
38
QM_INT_LOW_6
QM Interrupt for 192~223 Queues
39
QM_INT_LOW_7
QM Interrupt for 224~255 Queues
40
QM_INT_LOW_8
QM Interrupt for 256~287 Queues
41
QM_INT_LOW_9
QM Interrupt for 288~319 Queues
42
QM_INT_LOW_10
QM Interrupt for 320~351 Queues
43
QM_INT_LOW_11
QM Interrupt for 352~383 Queues
44
QM_INT_LOW_12
QM Interrupt for 384~415 Queues
45
QM_INT_LOW_13
QM Interrupt for 416~447 Queues
46
QM_INT_LOW_14
QM Interrupt for 448~479 Queues
47
QM_INT_LOW_15
QM Interrupt for 480~511 Queues
48
9
116
QM_INT_HIGH_n
QM Interrupt for Queue 704+n
TMS320C6670 Peripheral Information and Electrical Specifications
9
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Event Number
TMS320C6670 System Event Mapping — C66x CorePac Primary Interrupts (Part 3 of 4)
Interrupt Event
49
QM_INT_HIGH_(n+4)
9
50
QM_INT_HIGH_(n+8)
9
Description
QM Interrupt for Queue 708+n
9
QM Interrupt for Queue 712+n
9
9
QM Interrupt for Queue 716+n9
9
QM Interrupt for Queue 720+n
9
9
9
51
QM_INT_HIGH_(n+12)
52
QM_INT_HIGH_(n+16)
53
QM_INT_HIGH_(n+20)
QM Interrupt for Queue 724+n
54
QM_INT_HIGH_(n+24)9
QM Interrupt for Queue 728+n9
55
9
QM_INT_HIGH_(n+28)
QM Interrupt for Queue 732+n
56
INTC0_OUT0
Interrupt Controller Output
57
INTC0_OUT1
Interrupt Controller Output
58
INTC0_OUT2
Interrupt Controller Output
59
INTC0_OUT3
Interrupt Controller Output
60
INTC0_OUT4
Interrupt Controller Output
61
INTC0_OUT5
Interrupt Controller Output
62
INTC0_OUT6
Interrupt Controller Output
63
INTC0_OUT7
Interrupt Controller Output
6
9
Local Timer interrupt low
64
TINTLn
65
TINTHn6
Local Timer interrupt high
66
TINT4L
Timer 4 interrupt low
67
TINT4H
Timer 4 interrupt high
68
TINT5L
Timer 5 interrupt low
69
TINT5H
Timer 5 interrupt high
70
TINT6L
Timer 6 interrupt low
71
TINT6H
Timer 6 interrupt high
72
TINT7L
Timer 7 interrupt low
73
TINT7H
Timer 7 interrupt high
7
74
INTC0_OUT(8+16*n)
75
INTC0_OUT(9+16*n)
Interrupt Controller Output
7
Interrupt Controller Output
76
7
INTC0_OUT(10+16*n)
Interrupt Controller Output
77
INTC0_OUT(11+16*n)7
Interrupt Controller Output
78
GPINT4
Local GPIO Interrupt
79
GPINT5
Local GPIO Interrupt
80
GPINT6
Local GPIO Interrupt
81
GPINT7
Local GPIO Interrupt
82
GPINT8
Local GPIO Interrupt
83
GPINT9
Local GPIO Interrupt
84
GPINT10
Local GPIO Interrupt
85
GPINT11
Local GPIO Interrupt
86
GPINT12
Local GPIO Interrupt
87
GPINT13
Local GPIO Interrupt
88
GPINT14
Local GPIO Interrupt
89
GPINT15
Local GPIO Interrupt
90
IPC_LOCAL
Inter DSP Interrupt from IPCGRn
91
GPINTn
92
ADVANCE INFORMATION
Table 7-15
5
Local GPIO Interrupt
7
INTC0_OUT(12+16*n)
Interrupt Controller Output
Copyright 2010 Texas Instruments Incorporated
TMS320C6670 Peripheral Information and Electrical Specifications
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TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 7-15
www.ti.com
TMS320C6670 System Event Mapping — C66x CorePac Primary Interrupts (Part 4 of 4)
Event Number
Interrupt Event
Description
7
Interrupt Controller Output
94
7
INTC0_OUT(14+16*n)
Interrupt Controller Output
95
INTC0_OUT(15+16*n)7
Interrupt Controller Output
93
INTC0_OUT(13+16*n)
ADVANCE INFORMATION
96
INTERR
Dropped CPU interrupt event
97
EMC_IDMAERR
Invalid IDMA parameters
98
Reserved
99
Reserved
100
EFIINTA
EFI Interrupt from Side A
101
EFIINTB
EFI Interrupt from Side B
102
AIF_SEVT0
AIF System Event
103
AIF_SEVT0
AIF System Event
104
AIF_SEVT0
AIF System Event
105
AIF_SEVT0
AIF System Event
106
AIF_SEVT0
AIF System Event
107
AIF_SEVT0
AIF System Event
108
AIF_SEVT0
AIF System Event
109
AIF_SEVT0
AIF System Event
110
MDMAERREVT
VbusM error event
111
Reserved
112
TPCC0_EDMACC_AETEVT
TPCC0 AET Event
113
PMC_ED
Single bit error detected during DMA read
114
TPCC1_EDMACC_AETEVT
TPCC1 AET Event
115
TPCC2_EDMACC_AETEVT
TPCC2 AET Event
116
UMC_ED1
Corrected bit error detected
117
UMC_ED2
Uncorrected bit error detected
118
PDC_INT
Power Down sleep interrupt
119
SYS_CMPA
SYS CPU MP fault event
120
PMC_CMPA
CPU memory protection fault
121
PMC_DMPA
DMA memory protection fault
122
DMC_CMPA
CPU memory protection fault
123
DMC_DMPA
DMA memory protection fault
124
UMC_CMPA
CPU memory protection fault
125
UMC_DMPA
DMA memory protection fault
126
EMC_CMPA
CPU memory protection fault
127
EMC_BUSERR
Bus Error Interrupt
End of Table 7-15
1.
2.
3.
4.
5.
6.
7.
9.
10.
118
Core [n] will receive TETBHFULLINTn, TETBFULLINTn, TETBACQINTn, TETBOVFLINTn and TETBUNFLINTn.
Core [n] will receive SEMINTn and SEMERRn.
Core [n] will receive PCIEXpress_MSI_INTn and PCIEXpress_MSI_INTn+1.
Core [n] will receive MSMC_mpf_errorn.
Core [n] will receive GPINTn.
Core [n] will receive TINTLn and TINTHn.
For Core 0~3, it is INTC(interrupt number+17*n).
n is core number.
Core [n] will receive INTDST(n+16) and INTDST(n+20).
TMS320C6670 Peripheral Information and Electrical Specifications
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
INTC0 Event Inputs — C66x CorePac Secondary Interrupts (Part 1 of 5)
Input Event# on INTC System Interrupt
Description
0
TPCC1 EDMACC_ERRINT
TPCC1 Error Interrupt
1
TPCC1 EDMACC_MPINT
TPCC1 Memory Protection Interrupt
2
TPCC1 EDMATC_ERRINT0
TPCC1 TPTC0 Error Interrupt
3
TPCC1 EDMATC_ERRINT1
TPCC1 TPTC1 Error Interrupt
4
TPCC1 EDMATC_ERRINT2
TPCC1 TPTC2 Error Interrupt
5
TPCC1 EDMATC_ERRINT3
TPCC1 TPTC3 Error Interrupt
6
TPCC1 EDMACC_GINT
TPCC1 GINT
7
Reserved
8
TPCC1 TPCCINT0
TPCC1 Individual Completion Interrupt
9
TPCC1 TPCCINT1
TPCC1 Individual Completion Interrupt
10
TPCC1 TPCCINT2
TPCC1 Individual Completion Interrupt
11
TPCC1 TPCCINT3
TPCC1 Individual Completion Interrupt
12
TPCC1 TPCCINT4
TPCC1 Individual Completion Interrupt
13
TPCC1 TPCCINT5
TPCC1 Individual Completion Interrupt
14
TPCC1 TPCCINT6
TPCC1 Individual Completion Interrupt
15
TPCC1 TPCCINT7
TPCC1 Individual Completion Interrupt
16
TPCC2 EDMACC_ERRINT
TPCC2 Error Interrupt
17
TPCC2 EDMACC_MPINT
TPCC2 Memory Protection Interrupt
18
TPCC2 EDMATC_ERRINT0
TPCC2 TPTC0 Error Interrupt
19
TPCC2 EDMATC_ERRINT1
TPCC2 TPTC1 Error Interrupt
20
TPCC2 EDMATC_ERRINT2
TPCC2 TPTC2 Error Interrupt
21
TPCC2 EDMATC_ERRINT3
TPCC2 TPTC3 Error Interrupt
22
TPCC2 EDMACC_GINT
TPCC2 GINT
23
Reserved
24
TPCC2 TPCCINT0
TPCC2 Individual Completion Interrupt
25
TPCC2 TPCCINT1
TPCC2 Individual Completion Interrupt
26
TPCC2 TPCCINT2
TPCC2 Individual Completion Interrupt
27
TPCC2 TPCCINT3
TPCC2 Individual Completion Interrupt
28
TPCC2 TPCCINT4
TPCC2 Individual Completion Interrupt
29
TPCC2 TPCCINT5
TPCC2 Individual Completion Interrupt
30
TPCC2 TPCCINT6
TPCC2 Individual Completion Interrupt
31
TPCC2 TPCCINT7
TPCC2 Individual Completion Interrupt
32
TPCC0 EDMACC_ERRINT
TPCC0 Error Interrupt
33
TPCC0 EDMACC_MPINT
TPCC0 Memory Protection Interrupt
34
TPCC0 EDMATC_ERRINT0
TPCC0 TPTC0 Error Interrupt
35
TPCC0 EDMATC_ERRINT1
TPCC0 TPTC1 Error Interrupt
36
TPCC0 EDMACC_GINT
TPCC0 GINT
37
Reserved
38
TPCC0INT0
TPCC0 Individual Completion Interrupt
39
TPCC0INT1
TPCC0 Individual Completion Interrupt
40
TPCC0INT2
TPCC0 Individual Completion Interrupt
41
TPCC0INT3
TPCC0 Individual Completion Interrupt
42
TPCC0INT4
TPCC0 Individual Completion Interrupt
43
TPCC0INT5
TPCC0 Individual Completion Interrupt
Copyright 2010 Texas Instruments Incorporated
TMS320C6670 Peripheral Information and Electrical Specifications
ADVANCE INFORMATION
Table 7-16
119
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 7-16
www.ti.com
INTC0 Event Inputs — C66x CorePac Secondary Interrupts (Part 2 of 5)
Input Event# on INTC System Interrupt
Description
44
TPCC0INT6
TPCC0 Individual Completion Interrupt
45
TPCC0INT7
TPCC0 Individual Completion Interrupt
46
Reserved
ADVANCE INFORMATION
47
Reserved
48
PCIEXpress_ERR_INT
Protocol Error Interrupt
49
PCIEXpress_PM_INT
Power Management Interrupt
50
PCIEXpress_Legacy_INTA
Legacy Interrupt Mode
51
PCIEXpress_Legacy_INTB
Legacy Interrupt Mode
52
PCIEXpress_Legacy_INTC
Legacy Interrupt Mode
53
PCIEXpress_Legacy_INTD
Legacy Interrupt Mode
54
SPIINT0
SPI Interrupt0
55
SPIINT1
SPI Interrupt1
56
SPIXEVT
SPI Transmit event
57
SPIREVT
SPI Receive event
58
I2CINT
I2C interrupt
59
I2CREVT
I C Receive event
60
I2CXEVT
I2C Transmit event
61
Reserved
62
Reserved
63
TETBHFULLINT
TETB is half full
64
TETBFULLINT
TETB is full
65
TETBACQINT
Acquisition has been completed
66
TETBOVFLINT
Overflow condition occur
67
TETBUNFLINT
Underflow condition occur
68
mdio_link_intr0
Packet Accelerator Subsystem mdio Interrupt
2
69
mdio_link_intr1
Packet Accelerator Subsystem mdio Interrupt
70
mdio_user_intr0
Packet Accelerator Subsystem mdio Interrupt
71
mdio_user_intr1
Packet Accelerator Subsystem mdio Interrupt
72
misc_intr
Packet Accelerator Subsystem misc Interrupt
73
Tracer_core_0_INTD
Tracer sliding time window interrupt for individual core
74
Tracer_core_1_INTD
Tracer sliding time window interrupt for individual core
75
Tracer_core_2_INTD
Tracer sliding time window interrupt for individual core
76
Tracer_core_3_INTD
Tracer sliding time window interrupt for individual core
77
Tracer_DDR_INTD
Tracer sliding time window interrupt for DDR3 EMIF1
78
Tracer_MSMC_0_INTD
Tracer sliding time window interrupt for MSMC SRAM Bank0
79
Tracer_MSMC_1_INTD
Tracer sliding time window interrupt for MSMC SRAM Bank1
80
Tracer_MSMC_2_INTD
Tracer sliding time window interrupt for MSMC SRAM Bank2
81
Tracer_MSMC_3_INTD
Tracer sliding time window interrupt for MSMC SRAM Bank3
82
Tracer_CFG_INTD
Tracer sliding time window interrupt for CFG0 SCR
83
Tracer_QM_SS_CFG_INTD
Tracer sliding time window interrupt for QM_SS CFG
84
Tracer_QM_SS_DMA_INTD
Tracer sliding time window interrupt for QM_SS Slave
85
Tracer_SEM_INTD
Tracer sliding time window interrupt for Semaphore
86
PSC_ALLINT
Power & Sleep Controller Interrupt
87
MSMC_scrub_cerror
Correctable (1-bit) soft error detected during scrub cycle
120
TMS320C6670 Peripheral Information and Electrical Specifications
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
INTC0 Event Inputs — C66x CorePac Secondary Interrupts (Part 3 of 5)
Input Event# on INTC System Interrupt
Description
88
Chip-level MMR Error Register
BOOTCFG_INTD
89
Reserved
90
MPU0_INTD
(MPU0_ADDR_ERR_INT and
MPU0_PROT_ERR_INT combined)
91
Reserved
92
MPU1_INTD
(MPU1_ADDR_ERR_INT and
MPU1_PROT_ERR_INT combined)
93
Reserved
94
MPU2_INTD
(MPU2_ADDR_ERR_INT and
MPU2_PROT_ERR_INT combined)
95
Reserved
96
MPU3_INTD
(MPU3_ADDR_ERR_INT and
MPU3_PROT_ERR_INT combined)
97
Reserved
98
MSMC_dedc_cerror
MPU0 addressing violation interrupt and protection violation interrupt.
MPU1 addressing violation interrupt and protection violation interrupt.
MPU2 addressing violation interrupt and protection violation interrupt.
MPU3 addressing violation interrupt and protection violation interrupt.
Correctable (1-bit) soft error detected on SRAM read
99
MSMC_dedc_nc_error
Non-correctable (2-bit) soft error detected on SRAM read
100
MSMC_scrub_nc_error
Non-correctable (2-bit) soft error detected during scrub cycle
101
MSMC_mpax_addr_error
SES MPAX setup error causing extended address to be out of EMIF range
102
MSMC_mpf_error8
Memory protection fault indicators for each system master PrivID
103
MSMC_mpf_error9
Memory protection fault indicators for each system master PrivID
104
MSMC_mpf_error10
Memory protection fault indicators for each system master PrivID
105
MSMC_mpf_error11
Memory protection fault indicators for each system master PrivID
106
MSMC_mpf_error12
Memory protection fault indicators for each system master PrivID
107
MSMC_mpf_error13
Memory protection fault indicators for each system master PrivID
108
MSMC_mpf_error14
Memory protection fault indicators for each system master PrivID
109
MSMC_mpf_error15
Memory protection fault indicators for each system master PrivID
110
DDR3_ERR
DDR3_EMIF Error Interrupt
111
vusr_int_o
HyperLink Interrupt
112
INTDST0
RapidIO Interrupt
113
INTDST1
RapidIO Interrupt
114
INTDST2
RapidIO Interrupt
115
INTDST3
RapidIO Interrupt
116
INTDST4
RapidIO Interrupt
117
INTDST5
RapidIO Interrupt
118
INTDST6
RapidIO Interrupt
119
INTDST7
RapidIO Interrupt
120
INTDST8
RapidIO Interrupt
121
INTDST9
RapidIO Interrupt
122
INTDST10
RapidIO Interrupt
123
INTDST11
RapidIO Interrupt
124
INTDST12
RapidIO Interrupt
125
INTDST13
RapidIO Interrupt
126
INTDST14
RapidIO Interrupt
Copyright 2010 Texas Instruments Incorporated
ADVANCE INFORMATION
Table 7-16
TMS320C6670 Peripheral Information and Electrical Specifications
121
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 7-16
www.ti.com
INTC0 Event Inputs — C66x CorePac Secondary Interrupts (Part 4 of 5)
Input Event# on INTC System Interrupt
Description
127
RapidIO Interrupt
INTDST15
ADVANCE INFORMATION
128 - 132
Reserved
133
AIF_INTD
AIF CPU error interrupt and AIF CPU alarm interrupt and Starvation interrupt
134
QM_INT_PASS_TXQ_PEND_22
Queue Manager (Packet Accelerator) Pend Event
135
QM_INT_PASS_TXQ_PEND_23
Queue Manager (Packet Accelerator) Pend Event
136
QM_INT_PASS_TXQ_PEND_24
Queue Manager (Packet Accelerator) Pend Event
137
QM_INT_PASS_TXQ_PEND_25
Queue Manager (Packet Accelerator) Pend Event
138
QM_INT_PASS_TXQ_PEND_26
Queue Manager (Packet Accelerator) Pend Event
139
QM_INT_PASS_TXQ_PEND_27
Queue Manager (Packet Accelerator) Pend Event
140
QM_INT_PASS_TXQ_PEND_28
Queue Manager (Packet Accelerator) Pend Event
141
QM_INT_PASS_TXQ_PEND_29
Queue Manager (Packet Accelerator) Pend Event
142
QM_INT_PASS_TXQ_PEND_30
Queue Manager (Packet Accelerator) Pend Event
143
VCP0INT
Error interrupt
144
VCP1INT
Error interrupt
145
VCP2INT
Error interrupt
146
VCP3INT
Error interrupt
147
VCP0REVT
Receive event
148
VCP0XEVT
Transmit event
149
VCP1REVT
Receive event
150
VCP1XEVT
Transmit event
151
VCP2REVT
Receive event
152
VCP2XEVT
Transmit event
153
VCP3REVT
Receive event
154
VCP3XEVT
Transmit event
155
TCP3D_A_INTD
TCP3d_A Error interrupt TCP3DINT0 and TCP3DINT1
156
TCP3D_B_INTD
TCP3d_B Error interrupt TCP3DINT0 and TCP3DINT1
157
TCP3D_AREVT0
TCP3d_A Receive event0
158
TCP3D_AREVT1
TCP3d_A Receive event1
159
TCP3E_INTD
Error interrupt TCP3EINT
160
TCP3EREVT
TCP3e read event
161
TCP3EWEVT
TCP3e Write event
162
TCP3D_BREVT0
TCP3d_B Receive event0
163
TCP3D_BREVT1
TCP3d_B Receive event1
164
UARTINT
UART Interrupt
165
URXEVT
UART Receive Event
166
UTXEVT
UART Transmit Event
167 - 169
Reserved
170
MSMC_mpf_error4
Memory protection fault indicators for each system master PrivID
171
MSMC_mpf_error5
Memory protection fault indicators for each system master PrivID
172
MSMC_mpf_error6
Memory protection fault indicators for each system master PrivID
173
MSMC_mpf_error7
Memory protection fault indicators for each system master PrivID
174
Reserved
175
QM_INT_PASS_TXQ_PEND_31
Queue Manager (Packet Accelerator) Pend Event
176
QM_INT_CDMA_0
QM Interrupt for CDMA Starvation
122
TMS320C6670 Peripheral Information and Electrical Specifications
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
INTC0 Event Inputs — C66x CorePac Secondary Interrupts (Part 5 of 5)
Input Event# on INTC System Interrupt
Description
177
QM_INT_CDMA_1
QM Interrupt for CDMA Starvation
178
RapidIO_INT_CDMA_0
RapidIO Interrupt for CDMA Starvation
179
PASS_INT_CDMA_0
PASS Interrupt for CDMA Starvation
180
Reserved
181
SmartReflex_intrreq0
SmartReflex sensor interrupt
182
SmartReflex_intrreq
SmartReflex sensor interrupt
183
SmartReflex_intrreq2
SmartReflex sensor interrupt
184
SmartReflex_intrreq3
SmartReflex sensor interrupt
185
VPNoSMPSAck
VPVOLTUPDATE has been asserted but SMPS has not been responded in a defined time
interval
186
VPEqValue
SRSINTERUPTZ is asserted, but the new voltage is not different from the current SMPS
voltage.
187
VPMaxVdd
the new voltage required is equal to or greater than MaxVdd.
188
VPMinVdd
the new voltage required is equal to or less than MinVdd.
189
VPINIDLE
Indicating that the FSM of Voltage Processor is in idle.
190
VPOPPChangeDone
Indicating that the average frequency error is within the desired limit.
191
Reserved
192
FFTC_A_INTD0
FFTC_A error event and FFTC_A debug event
193
FFTC_A_INTD1
FFTC_A error event and FFTC_A debug event
194
FFTC_A_INTD2
FFTC_A error event and FFTC_A debug event
195
FFTC_A_INTD3
FFTC_A error event and FFTC_A debug event
196
FFTC_B_INTD0
FFTC_B error event and FFTC_B debug event
197
FFTC_B_INTD1
FFTC_B error event and FFTC_B debug event
198
FFTC_B_INTD2
FFTC_B error event and FFTC_B debug event
199
FFTC_B_INTD3
FFTC_B error event and FFTC_B debug event
200 - 207
Reserved
Reserved inputs
End of Table 7-16
Table 7-17
INTC1 Event Inputs (Secondary Events for TPCC1 and TPCC2) (Part 1 of 5)
Input Event # on INTC System Interrupt
Description
0
GPINT8
GPIO Interrupt
1
GPINT9
GPIO Interrupt
2
GPINT10
GPIO Interrupt
3
GPINT11
GPIO Interrupt
4
GPINT12
GPIO Interrupt
5
GPINT13
GPIO Interrupt
6
GPINT14
GPIO Interrupt
7
GPINT15
GPIO Interrupt
8
TETBHFULLINT
TETB is half full
9
TETBFULLINT
TETB is full
10
TETBACQINT
Acquisition has been completed
11
TETBHFULLINT0
TETB is half full
12
TETBFULLINT0
TETB is full
13
TETBACQINT0
Acquisition has been completed
Copyright 2010 Texas Instruments Incorporated
TMS320C6670 Peripheral Information and Electrical Specifications
123
ADVANCE INFORMATION
Table 7-16
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 7-17
www.ti.com
INTC1 Event Inputs (Secondary Events for TPCC1 and TPCC2) (Part 2 of 5)
ADVANCE INFORMATION
Input Event # on INTC System Interrupt
Description
14
TETBHFULLINT1
TETB is half full
15
TETBFULLINT1
TETB is full
16
TETBACQINT1
Acquisition has been completed
17
TETBHFULLINT2
TETB is half full
18
TETBFULLINT2
TETB is full
19
TETBACQINT2
Acquisition has been completed
20
TETBHFULLINT3
TETB is half full
21
TETBFULLINT3
TETB is full
22
TETBACQINT3
Acquisition has been completed
23
Reserved
24
QM_INT_HIGH_16
QM Interrupt for IPC_core_0
25
QM_INT_HIGH_17
QM Interrupt for IPC_core_1
26
QM_INT_HIGH_18
QM Interrupt for IPC_core_2
27
QM_INT_HIGH_19
QM Interrupt for IPC_core_3
28
QM_INT_HIGH_20
QM Interrupt for IPC_core_0
29
QM_INT_HIGH_21
QM Interrupt for IPC_core_1
30
QM_INT_HIGH_22
QM Interrupt for IPC_core_2
31
QM_INT_HIGH_23
QM Interrupt for IPC_core_3
32
QM_INT_HIGH_24
QM Interrupt for IPC_core_0
33
QM_INT_HIGH_25
QM Interrupt for IPC_core_1
34
QM_INT_HIGH_26
QM Interrupt for IPC_core_2
35
QM_INT_HIGH_27
QM Interrupt for IPC_core_3
36
QM_INT_HIGH_28
QM Interrupt for IPC_core_0
37
QM_INT_HIGH_29
QM Interrupt for IPC_core_1
38
QM_INT_HIGH_30
QM Interrupt for IPC_core_2
39
QM_INT_HIGH_31
QM Interrupt for IPC_core_3
40
mdio_link_intr0
PASS_mdio Interrupt
41
mdio_link_intr1
PASS_mdio Interrupt
42
mdio_user_intr0
PASS_mdio Interrupt
43
mdio_user_intr1
PASS_mdio Interrupt
44
misc_intr
PASS_misc Interrupt
45
Tracer_core_0_INTD
Tracer sliding time window interrupt for individual core
46
Tracer_core_1_INTD
Tracer sliding time window interrupt for individual core
47
Tracer_core_2_INTD
Tracer sliding time window interrupt for individual core
48
Tracer_core_3_INTD
Tracer sliding time window interrupt for individual core
49
Tracer_DDR_INTD
Tracer sliding time window interrupt for DDR3 EMIF1
50
Tracer_MSMC_0_INTD
Tracer sliding time window interrupt for MSMC SRAM Bank0
51
Tracer_MSMC_1_INTD
Tracer sliding time window interrupt for MSMC SRAM Bank1
52
Tracer_MSMC_2_INTD
Tracer sliding time window interrupt for MSMC SRAM Bank2
53
Tracer_MSMC_3_INTD
Tracer sliding time window interrupt for MSMC SRAM Bank3
54
Tracer_CFG_INTD
Tracer sliding time window interrupt for CFG0 SCR
55
Tracer_QM_SS_CFG_INTD
Tracer sliding time window interrupt for QM_SS CFG
56
Tracer_QM_SS_DMA_INTD
Tracer sliding time window interrupt for QM_SS Slave port
57
Tracer_SEM_INTD
Tracer sliding time window interrupt for Semaphore
124
TMS320C6670 Peripheral Information and Electrical Specifications
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
INTC1 Event Inputs (Secondary Events for TPCC1 and TPCC2) (Part 3 of 5)
Input Event # on INTC System Interrupt
Description
58
SEMERR0
Semaphore interrupt
59
SEMERR1
Semaphore interrupt
60
SEMERR2
Semaphore interrupt
61
SEMERR3
Semaphore interrupt
62
BOOTCFG_INTD
Chip-level MMR Interrupt
63
PASS_INT_CDMA_0
PASS Interrupt for CDMA Starvation
64
MPU0_INTD
(MPU0_ADDR_ERR_INT and
MPU0_PROT_ERR_INT combined)
MPU0 Addressing violation interrupt and Protection violation interrupt.
65
MSMC_scrub_cerror
Correctable (1-bit) soft error detected during scrub cycle
66
MPU1_INTD
(MPU1_ADDR_ERR_INT and
MPU1_PROT_ERR_INT combined)
MPU1 Addressing violation interrupt and Protection violation interrupt.
67
RapidIO_INT_CDMA_0
RapidIO Interrupt for CDMA Starvation
68
MPU2_INTD
(MPU2_ADDR_ERR_INT and
MPU2_PROT_ERR_INT combined)
MPU2 Addressing violation interrupt and Protection violation interrupt.
69
QM_INT_CDMA_0
QM Interrupt for CDMA Starvation
70
MPU3_INTD
(MPU3_ADDR_ERR_INT and
MPU3_PROT_ERR_INT combined)
MPU3 Addressing violation interrupt and Protection violation interrupt.
71
QM_INT_CDMA_1
QM Interrupt for CDMA Starvation
72
MSMC_dedc_cerror
Correctable (1-bit) soft error detected on SRAM read
73
MSMC_dedc_nc_error
Non-correctable (2-bit) soft error detected on SRAM read
74
MSMC_scrub_nc_error
Non-correctable (2-bit) soft error detected during scrub cycle
75
Reserved
76
MSMC_mpf_error0
Memory protection fault indicators for each system master PrivID
77
MSMC_mpf_error1
Memory protection fault indicators for each system master PrivID
78
MSMC_mpf_error2
Memory protection fault indicators for each system master PrivID
79
MSMC_mpf_error3
Memory protection fault indicators for each system master PrivID
80
MSMC_mpf_error4
Memory protection fault indicators for each system master PrivID
81
MSMC_mpf_error5
Memory protection fault indicators for each system master PrivID
82
MSMC_mpf_error6
Memory protection fault indicators for each system master PrivID
83
MSMC_mpf_error7
Memory protection fault indicators for each system master PrivID
84
MSMC_mpf_error8
Memory protection fault indicators for each system master PrivID
85
MSMC_mpf_error9
Memory protection fault indicators for each system master PrivID
86
MSMC_mpf_error10
Memory protection fault indicators for each system master PrivID
87
MSMC_mpf_error11
Memory protection fault indicators for each system master PrivID
88
MSMC_mpf_error12
Memory protection fault indicators for each system master PrivID
89
MSMC_mpf_error13
Memory protection fault indicators for each system master PrivID
90
MSMC_mpf_error14
Memory protection fault indicators for each system master PrivID
91
MSMC_mpf_error15
Memory protection fault indicators for each system master PrivID
92
Reserved
93
INTDST0
RapidIO Interrupt
94
INTDST1
RapidIO Interrupt
95
INTDST2
RapidIO Interrupt
96
INTDST3
RapidIO Interrupt
Copyright 2010 Texas Instruments Incorporated
TMS320C6670 Peripheral Information and Electrical Specifications
ADVANCE INFORMATION
Table 7-17
125
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 7-17
www.ti.com
INTC1 Event Inputs (Secondary Events for TPCC1 and TPCC2) (Part 4 of 5)
ADVANCE INFORMATION
Input Event # on INTC System Interrupt
Description
97
INTDST4
RapidIO Interrupt
98
INTDST5
RapidIO Interrupt
99
INTDST6
RapidIO Interrupt
100
INTDST7
RapidIO Interrupt
101
INTDST8
RapidIO Interrupt
102
INTDST9
RapidIO Interrupt
103
INTDST10
RapidIO Interrupt
104
INTDST11
RapidIO Interrupt
105
INTDST12
RapidIO Interrupt
106
INTDST13
RapidIO Interrupt
107
INTDST14
RapidIO Interrupt
108
INTDST15
RapidIO Interrupt
109
INTDST16
RapidIO Interrupt
110
INTDST17
RapidIO Interrupt
111
INTDST18
RapidIO Interrupt
112
INTDST19
RapidIO Interrupt
113
INTDST20
RapidIO Interrupt
114
INTDST21
RapidIO Interrupt
115
INTDST22
RapidIO Interrupt
116
INTDST23
RapidIO Interrupt
117
AIF_INTD
AIF CPU error interrupt and AIF CPU alarm interrupt and Starvation interrupt
118
Reserved
119
VCPAINT
Error interrupt
120
VCPBINT
Error interrupt
121
VCPCINT
Error interrupt
122
VCPDINT
Error interrupt
123
TCP3D_A_INTD
Error interrupt TCP3DINT0 and TCP3DINT1
124
TCP3D_B_INTD
Error interrupt TCP3DINT0 and TCP3DINT1
125
TCP3E_INTD
Error interrupt TCP3EINT
126
FFTC_B_INTD0
FFTC_B error event and FFTC_B debug event
127
FFTC_B_INTD1
FFTC_B error event and FFTC_B debug event
128
GPINT4
GPIO Interrupt
129
GPINT5
GPIO Interrupt
130
GPINT6
GPIO Interrupt
131
GPINT7
GPIO Interrupt
132
Reserved
133
Reserved
134
Reserved
135
Reserved
136
Reserved
137
QM_INT_HIGH_0
QM Interrupt for SRIO_core_0
138
QM_INT_HIGH_1
QM Interrupt for SRIO_core_1
139
QM_INT_HIGH_2
QM Interrupt for SRIO_core_2
140
QM_INT_HIGH_3
QM Interrupt for SRIO_core_3
126
TMS320C6670 Peripheral Information and Electrical Specifications
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
INTC1 Event Inputs (Secondary Events for TPCC1 and TPCC2) (Part 5 of 5)
Input Event # on INTC System Interrupt
Description
141
QM_INT_HIGH_4
QM Interrupt for FFTC_core_0
142
QM_INT_HIGH_5
QM Interrupt for FFTC_core_1
143
QM_INT_HIGH_6
QM Interrupt for FFTC_core_2
144
QM_INT_HIGH_7
QM Interrupt for FFTC_core_3
145
QM_INT_HIGH_8
QM Interrupt for PA_SS_core_0
146
QM_INT_HIGH_9
QM Interrupt for PA_SS_core_1
147
QM_INT_HIGH_10
QM Interrupt for PA_SS_core_2
148
QM_INT_HIGH_11
QM Interrupt for PA_SS_core_3
149
QM_INT_HIGH_12
QM Interrupt for IPC_core_0
150
QM_INT_HIGH_13
QM Interrupt for IPC_core_1
151
QM_INT_HIGH_14
QM Interrupt for IPC_core_2
152
QM_INT_HIGH_15
QM Interrupt for IPC_core_3
153
FFTC_A_INTD0
FFTC_A error event and FFTC_A debug event
154
FFTC_A_INTD1
FFTC_A error event and FFTC_A debug event
155
FFTC_A_INTD2
FFTC_A error event and FFTC_A debug event
156
FFTC_A_INTD3
FFTC_A error event and FFTC_A debug event
157
FFTC_B_INTD2
FFTC_B error event and FFTC_B debug event
158
FFTC_B_INTD3
FFTC_B error event and FFTC_B debug event
159
Reserved
Reserved inputs
ADVANCE INFORMATION
Table 7-17
End of Table 7-17
Table 7-18
INTC2 Event Inputs (Secondary Events for TPCC0 and HyperLink) (Part 1 of 3)
Input Event # on INTC System Interrupt
Description
0
GPINT0
GPIO Interrupt
1
GPINT1
GPIO Interrupt
2
GPINT2
GPIO Interrupt
3
GPINT3
GPIO Interrupt
4
GPINT4
GPIO Interrupt
5
GPINT5
GPIO Interrupt
6
GPINT6
GPIO Interrupt
7
GPINT7
GPIO Interrupt
8
GPINT8
GPIO Interrupt
9
GPINT9
GPIO Interrupt
10
GPINT10
GPIO Interrupt
11
GPINT11
GPIO Interrupt
12
GPINT12
GPIO Interrupt
13
GPINT13
GPIO Interrupt
14
GPINT14
GPIO Interrupt
15
GPINT15
GPIO Interrupt
16
TETBHFULLINT
System TETB is half full
17
TETBFULLINT
System TETB is full
18
TETBACQINT
System Acquisition has been completed
19
TETBHFULLINT0
TETB0 is half full
Copyright 2010 Texas Instruments Incorporated
TMS320C6670 Peripheral Information and Electrical Specifications
127
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 7-18
www.ti.com
INTC2 Event Inputs (Secondary Events for TPCC0 and HyperLink) (Part 2 of 3)
ADVANCE INFORMATION
Input Event # on INTC System Interrupt
Description
20
TETBFULLINT0
TETB0 is full
21
TETBACQINT0
TETB0 Acquisition has been completed
22
TETBHFULLINT1
TETB1 is half full
23
TETBFULLINT1
TETB1 is full
24
TETBACQINT1
TETB1 Acquisition has been completed
25
TETBHFULLINT2
TETB2 is half full
26
TETBFULLINT2
TETB2 is full
27
TETBACQINT2
TETB2 Acquisition has been completed
28
TETBHFULLINT3
TETB3 is half full
29
TETBFULLINT3
TETB3 is full
30
TETBACQINT3
TETB3 Acquisition has been completed
31
Tracer_core_0_INTD
Tracer sliding time window interrupt for individual core
32
Tracer_core_1_INTD
Tracer sliding time window interrupt for individual core
33
Tracer_core_2_INTD
Tracer sliding time window interrupt for individual core
34
Tracer_core_3_INTD
Tracer sliding time window interrupt for individual core
35
Tracer_DDR_INTD
Tracer sliding time window interrupt for DDR3 EMIF1
36
Tracer_MSMC_0_INTD
Tracer sliding time window interrupt for MSMC SRAM Bank0
37
Tracer_MSMC_1_INTD
Tracer sliding time window interrupt for MSMC SRAM Bank1
38
Tracer_MSMC_2_INTD
Tracer sliding time window interrupt for MSMC SRAM Bank2
39
Tracer_MSMC_3_INTD
Tracer sliding time window interrupt for MSMC SRAM Bank3
40
Tracer_CFG_INTD
Tracer sliding time window interrupt for CFG0 SCR
41
Tracer_QM_SS_CFG_INTD
Tracer sliding time window interrupt for QM_SS CFG
42
Tracer_QM_SS_DMA_INTD
Tracer sliding time window interrupt for QM_SS Slave port
43
Tracer_SEM_INTD
Tracer sliding time window interrupt for Semaphore
44
vusr_int_o
HyperLink Interrupt
45
Reserved
46
Reserved
47
Reserved
48
Reserved
49
TINT4L
Timer64_4 Interrupt Low
50
TINT4H
Timer64_4 Interrupt High
51
TINT5L
Timer64_5 Interrupt Low
52
TINT5H
Timer64_5 Interrupt High
53
TINT6L
Timer64_6 Interrupt Low
54
TINT6H
Timer64_6 Interrupt High
55
TINT7L
Timer64_7 Interrupt Low
56
TINT7H
Timer64_7 Interrupt High
57
Reserved
58
Reserved
59
Reserved
60
Reserved
61
DDR3_ERR
128
DDR3 EMIF Error Interrupt
TMS320C6670 Peripheral Information and Electrical Specifications
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Table 7-18
INTC2 Event Inputs (Secondary Events for TPCC0 and HyperLink) (Part 3 of 3)
Input Event # on INTC System Interrupt
62
Reserved
63
Reserved
Description
End of Table 7-18
7.5.2 INTC Registers
This section includes the INTC memory map information and registers.
Table 7-19
ADVANCE INFORMATION
7.5.2.1 INTC0 Register Map
INTC0 Registers (Part 1 of 3)
Address Offset
Register Mnemonic
Register Name
0x0
REVISION_REG
Revision Register
0x4
CONTROL_REG
Control Register
0xc
HOST_CONTROL_REG
Host Control Register
0x10
GLOBAL_ENABLE_HINT_REG
Global Host Int Enable Register
0x20
STATUS_SET_INDEX_REG
Status Set Index Register
0x24
STATUS_CLR_INDEX_REG
Status Clear Index Register
0x28
ENABLE_SET_INDEX_REG
Enable Set Index Register
0x2c
ENABLE_CLR_INDEX_REG
Enable Clear Index Register
0x34
HINT_ENABLE_SET_INDEX_REG
Host Int Enable Set Index Register
0x38
HINT_ENABLE_CLR_INDEX_REG
Host Int Enable Clear Index Register
0x200
RAW_STATUS_REG0
Raw Status Register 0
0x204
RAW_STATUS_REG1
Raw Status Register 1
0x208
RAW_STATUS_REG2
Raw Status Register 2
0x20c
RAW_STATUS_REG3
Raw Status Register 3
0x210
RAW_STATUS_REG4
Raw Status Register 4
0x214
RAW_STATUS_REG5
Raw Status Register 5
0x218
RAW_STATUS_REG6
Raw Status Register 6
0x280
ENA_STATUS_REG0
Enabled Status Register 0
0x284
ENA_STATUS_REG1
Enabled Status Register 1
0x288
ENA_STATUS_REG2
Enabled Status Register 2
0x28c
ENA_STATUS_REG3
Enabled Status Register 3
0x290
ENA_STATUS_REG4
Enabled Status Register 4
0x294
ENA_STATUS_REG5
Enabled Status Register 5
0x298
ENA_STATUS_REG6
Enabled Status Register 6
0x300
ENABLE_REG0
Enable Register 0
0x304
ENABLE_REG1
Enable Register 1
0x308
ENABLE_REG2
Enable Register 2
0x30c
ENABLE_REG3
Enable Register 3
0x310
ENABLE_REG4
Enable Register 4
0x314
ENABLE_REG5
Enable Register 5
0x318
ENABLE_REG6
Enable Register 6
0x380
ENABLE_CLR_REG0
Enable Clear Register 0
0x384
ENABLE_CLR_REG1
Enable Clear Register 1
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TMS320C6670 Peripheral Information and Electrical Specifications
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TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 7-19
www.ti.com
INTC0 Registers (Part 2 of 3)
ADVANCE INFORMATION
Address Offset
Register Mnemonic
Register Name
0x388
ENABLE_CLR_REG2
Enable Clear Register 2
0x38c
ENABLE_CLR_REG3
Enable Clear Register 3
0x390
ENABLE_CLR_REG4
Enable Clear Register 4
0x394
ENABLE_CLR_REG5
Enable Clear Register 5
0x398
ENABLE_CLR_REG6
Enable Clear Register 6
0x400
CH_MAP_REG0
Interrupt Channel Map Register for 0 to 0+3
0x404
CH_MAP_REG1
Interrupt Channel Map Register for 4 to 4+3
0x408
CH_MAP_REG2
Interrupt Channel Map Register for 8 to 8+3
0x40c
CH_MAP_REG3
Interrupt Channel Map Register for 12 to 12+3
0x410
CH_MAP_REG4
Interrupt Channel Map Register for 16 to 16+3
0x414
CH_MAP_REG5
Interrupt Channel Map Register for 20 to 20+3
0x418
CH_MAP_REG6
Interrupt Channel Map Register for 24 to 24+3
0x41c
CH_MAP_REG7
Interrupt Channel Map Register for 28 to 28+3
0x420
CH_MAP_REG8
Interrupt Channel Map Register for 32 to 32+3
0x424
CH_MAP_REG9
Interrupt Channel Map Register for 36 to 36+3
0x428
CH_MAP_REG10
Interrupt Channel Map Register for 40 to 40+3
0x42c
CH_MAP_REG11
Interrupt Channel Map Register for 44 to 44+3
0x430
CH_MAP_REG12
Interrupt Channel Map Register for 48 to 48+3
0x434
CH_MAP_REG13
Interrupt Channel Map Register for 52 to 52+3
0x438
CH_MAP_REG14
Interrupt Channel Map Register for 56 to 56+3
0x43c
CH_MAP_REG15
Interrupt Channel Map Register for 60 to 60+3
0x440
CH_MAP_REG16
Interrupt Channel Map Register for 64 to 64+3
0x444
CH_MAP_REG17
Interrupt Channel Map Register for 68 to 68+3
0x448
CH_MAP_REG18
Interrupt Channel Map Register for 72 to 72+3
0x44c
CH_MAP_REG19
Interrupt Channel Map Register for 76 to 76+3
0x450
CH_MAP_REG20
Interrupt Channel Map Register for 80 to 80+3
0x454
CH_MAP_REG21
Interrupt Channel Map Register for 84 to 84+3
0x458
CH_MAP_REG22
Interrupt Channel Map Register for 88 to 88+3
0x45c
CH_MAP_REG23
Interrupt Channel Map Register for 92 to 92+3
0x460
CH_MAP_REG24
Interrupt Channel Map Register for 96 to 96+3
0x464
CH_MAP_REG25
Interrupt Channel Map Register for 100 to 100+3
0x468
CH_MAP_REG26
Interrupt Channel Map Register for 104 to 104+3
0x46c
CH_MAP_REG27
Interrupt Channel Map Register for 108 to 108+3
0x470
CH_MAP_REG28
Interrupt Channel Map Register for 112 to 112+3
0x474
CH_MAP_REG29
Interrupt Channel Map Register for 116 to 116+3
0x478
CH_MAP_REG30
Interrupt Channel Map Register for 120 to 120+3
0x47c
CH_MAP_REG31
Interrupt Channel Map Register for 124 to 124+3
0x480
CH_MAP_REG32
Interrupt Channel Map Register for 128 to 128+3
0x484
CH_MAP_REG33
Interrupt Channel Map Register for 132 to 132+3
0x488
CH_MAP_REG34
Interrupt Channel Map Register for 136 to 136+3
0x48c
CH_MAP_REG35
Interrupt Channel Map Register for 140 to 140+3
0x490
CH_MAP_REG36
Interrupt Channel Map Register for 144 to 144+3
0x494
CH_MAP_REG37
Interrupt Channel Map Register for 148 to 148+3
0x498
CH_MAP_REG38
Interrupt Channel Map Register for 152 to 152+3
130
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Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
INTC0 Registers (Part 3 of 3)
Address Offset
Register Mnemonic
Register Name
0x49c
CH_MAP_REG39
Interrupt Channel Map Register for 156 to 156+3
0x4a0
CH_MAP_REG40
Interrupt Channel Map Register for 160 to 160+3
0x4a4
CH_MAP_REG41
Interrupt Channel Map Register for 164 to 164+3
0x4a8
CH_MAP_REG42
Interrupt Channel Map Register for 168 to 168+3
0x4ac
CH_MAP_REG43
Interrupt Channel Map Register for 172 to 172+3
0x4b0
CH_MAP_REG44
Interrupt Channel Map Register for 176 to 176+3
0x4b4
CH_MAP_REG45
Interrupt Channel Map Register for 180 to 180+3
0x4b8
CH_MAP_REG46
Interrupt Channel Map Register for 184 to 184+3
0x4bc
CH_MAP_REG47
Interrupt Channel Map Register for 188 to 188+3
0x4c0
CH_MAP_REG48
Interrupt Channel Map Register for 192 to 192+3
0x4c4
CH_MAP_REG49
Interrupt Channel Map Register for 196 to 196+3
0x4c8
CH_MAP_REG50
Interrupt Channel Map Register for 200 to 200+3
0x4cc
CH_MAP_REG51
Interrupt Channel Map Register for 204 to 204+3
0x800
HINT_MAP_REG0
Host Interrupt Map Register for 0 to 0+3
0x804
HINT_MAP_REG1
Host Interrupt Map Register for 4 to 4+3
0x808
HINT_MAP_REG2
Host Interrupt Map Register for 8 to 8+3
0x80c
HINT_MAP_REG3
Host Interrupt Map Register for 12 to 12+3
0x810
HINT_MAP_REG4
Host Interrupt Map Register for 16 to 16+3
0x814
HINT_MAP_REG5
Host Interrupt Map Register for 20 to 20+3
0x818
HINT_MAP_REG6
Host Interrupt Map Register for 24 to 24+3
0x81c
HINT_MAP_REG7
Host Interrupt Map Register for 28 to 28+3
0x820
HINT_MAP_REG8
Host Interrupt Map Register for 32 to 32+3
0x824
HINT_MAP_REG9
Host Interrupt Map Register for 36 to 36+3
0x828
HINT_MAP_REG10
Host Interrupt Map Register for 40 to 40+3
0x82c
HINT_MAP_REG11
Host Interrupt Map Register for 44 to 44+3
0x830
HINT_MAP_REG12
Host Interrupt Map Register for 48 to 48+3
0x834
HINT_MAP_REG13
Host Interrupt Map Register for 52 to 52+3
0x838
HINT_MAP_REG14
Host Interrupt Map Register for 56 to 56+3
0x83c
HINT_MAP_REG15
Host Interrupt Map Register for 60 to 60+3
0x840
HINT_MAP_REG16
Host Interrupt Map Register for 64 to 64+3
0x844
HINT_MAP_REG17
Host Interrupt Map Register for 68 to 68+3
0x848
HINT_MAP_REG18
Host Interrupt Map Register for 72 to 72+3
0x84c
HINT_MAP_REG19
Host Interrupt Map Register for 76 to 76+3
0x1500
ENABLE_HINT_REG0
Host Int Enable Register 0
0x1504
ENABLE_HINT_REG1
Host Int Enable Register 1
0x1508
ENABLE_HINT_REG2
Host Int Enable Register 2
ADVANCE INFORMATION
Table 7-19
End of Table 7-19
Copyright 2010 Texas Instruments Incorporated
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7.5.2.2 INTC1 Register Map
Table 7-20
INTC1 Registers (Part 1 of 2)
ADVANCE INFORMATION
Address Offset
Register Mnemonic
Register Name
0x0
REVISION_REG
Revision Register
0x10
GLOBAL_ENABLE_HINT_REG
Global Host Int Enable Register
0x20
STATUS_SET_INDEX_REG
Status Set Index Register
0x24
STATUS_CLR_INDEX_REG
Status Clear Index Register
0x28
ENABLE_SET_INDEX_REG
Enable Set Index Register
0x2c
ENABLE_CLR_INDEX_REG
Enable Clear Index Register
0x34
HINT_ENABLE_SET_INDEX_REG
Host Int Enable Set Index Register
0x38
HINT_ENABLE_CLR_INDEX_REG
Host Int Enable Clear Index Register
0x200
RAW_STATUS_REG0
Raw Status Register 0
0x204
RAW_STATUS_REG1
Raw Status Register 1
0x208
RAW_STATUS_REG2
Raw Status Register 2
0x20c
RAW_STATUS_REG3
Raw Status Register 3
0x210
RAW_STATUS_REG4
Raw Status Register 4
0x280
ENA_STATUS_REG0
Enabled Status Register 0
0x284
ENA_STATUS_REG1
Enabled Status Register 1
0x288
ENA_STATUS_REG2
Enabled Status Register 2
0x28c
ENA_STATUS_REG3
Enabled Status Register 3
0x290
ENA_STATUS_REG4
Enabled Status Register 4
0x300
ENABLE_REG0
Enable Register 0
0x304
ENABLE_REG1
Enable Register 1
0x308
ENABLE_REG2
Enable Register 2
0x30c
ENABLE_REG3
Enable Register 3
0x310
ENABLE_REG4
Enable Register 4
0x380
ENABLE_CLR_REG0
Enable Clear Register 0
0x384
ENABLE_CLR_REG1
Enable Clear Register 1
0x388
ENABLE_CLR_REG2
Enable Clear Register 2
0x38c
ENABLE_CLR_REG3
Enable Clear Register 3
0x390
ENABLE_CLR_REG4
Enable Clear Register 4
0x400
CH_MAP_REG0
Interrupt Channel Map Register for 0 to 0+3
0x404
CH_MAP_REG1
Interrupt Channel Map Register for 4 to 4+3
0x408
CH_MAP_REG2
Interrupt Channel Map Register for 8 to 8+3
0x40c
CH_MAP_REG3
Interrupt Channel Map Register for 12 to 12+3
0x410
CH_MAP_REG4
Interrupt Channel Map Register for 16 to 16+3
0x414
CH_MAP_REG5
Interrupt Channel Map Register for 20 to 20+3
0x418
CH_MAP_REG6
Interrupt Channel Map Register for 24 to 24+3
0x41c
CH_MAP_REG7
Interrupt Channel Map Register for 28 to 28+3
0x420
CH_MAP_REG8
Interrupt Channel Map Register for 32 to 32+3
0x424
CH_MAP_REG9
Interrupt Channel Map Register for 36 to 36+3
0x428
CH_MAP_REG10
Interrupt Channel Map Register for 40 to 40+3
0x42c
CH_MAP_REG11
Interrupt Channel Map Register for 44 to 44+3
0x430
CH_MAP_REG12
Interrupt Channel Map Register for 48 to 48+3
0x434
CH_MAP_REG13
Interrupt Channel Map Register for 52 to 52+3
132
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Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
INTC1 Registers (Part 2 of 2)
Address Offset
Register Mnemonic
Register Name
0x438
CH_MAP_REG14
Interrupt Channel Map Register for 56 to 56+3
0x43c
CH_MAP_REG15
Interrupt Channel Map Register for 60 to 60+3
0x440
CH_MAP_REG16
Interrupt Channel Map Register for 64 to 64+3
0x444
CH_MAP_REG17
Interrupt Channel Map Register for 68 to 68+3
0x448
CH_MAP_REG18
Interrupt Channel Map Register for 72 to 72+3
0x44c
CH_MAP_REG19
Interrupt Channel Map Register for 76 to 76+3
0x450
CH_MAP_REG20
Interrupt Channel Map Register for 80 to 80+3
0x454
CH_MAP_REG21
Interrupt Channel Map Register for 84 to 84+3
0x458
CH_MAP_REG22
Interrupt Channel Map Register for 88 to 88+3
0x45c
CH_MAP_REG23
Interrupt Channel Map Register for 92 to 92+3
0x460
CH_MAP_REG24
Interrupt Channel Map Register for 96 to 96+3
0x464
CH_MAP_REG25
Interrupt Channel Map Register for 100 to 100+3
0x468
CH_MAP_REG26
Interrupt Channel Map Register for 104 to 104+3
0x46c
CH_MAP_REG27
Interrupt Channel Map Register for 108 to 108+3
0x470
CH_MAP_REG28
Interrupt Channel Map Register for 112 to 112+3
0x474
CH_MAP_REG29
Interrupt Channel Map Register for 116 to 116+3
0x478
CH_MAP_REG30
Interrupt Channel Map Register for 120 to 120+3
0x47c
CH_MAP_REG31
Interrupt Channel Map Register for 124 to 124+3
0x480
CH_MAP_REG32
Interrupt Channel Map Register for 128 to 128+3
0x484
CH_MAP_REG33
Interrupt Channel Map Register for 132 to 132+3
0x488
CH_MAP_REG34
Interrupt Channel Map Register for 136 to 136+3
0x48c
CH_MAP_REG35
Interrupt Channel Map Register for 140 to 140+3
0x490
CH_MAP_REG36
Interrupt Channel Map Register for 144 to 144+3
0x494
CH_MAP_REG37
Interrupt Channel Map Register for 148 to 148+3
0x498
CH_MAP_REG38
Interrupt Channel Map Register for 152 to 152+3
0x49c
CH_MAP_REG39
Interrupt Channel Map Register for 156 to 156+3
0x800
HINT_MAP_REG0
Host Interrupt Map Register for 0 to 0+3
0x804
HINT_MAP_REG1
Host Interrupt Map Register for 4 to 4+3
0x808
HINT_MAP_REG2
Host Interrupt Map Register for 8 to 8+3
0x80c
HINT_MAP_REG3
Host Interrupt Map Register for 12 to 12+3
0x810
HINT_MAP_REG4
Host Interrupt Map Register for 16 to 16+3
0x814
HINT_MAP_REG5
Host Interrupt Map Register for 20 to 20+3
0x818
HINT_MAP_REG6
Host Interrupt Map Register for 24 to 24+3
0x81c
HINT_MAP_REG7
Host Interrupt Map Register for 28 to 28+3
0x820
HINT_MAP_REG8
Host Interrupt Map Register for 32 to 32+3
0x824
HINT_MAP_REG9
Host Interrupt Map Register for 36 to 36+3
0x828
HINT_MAP_REG10
Host Interrupt Map Register for 40 to 40+3
0x82c
HINT_MAP_REG11
Host Interrupt Map Register for 44 to 44+3
0x830
HINT_MAP_REG12
Host Interrupt Map Register for 48 to 48+3
0x834
HINT_MAP_REG13
Host Interrupt Map Register for 52 to 52+3
0x1500
ENABLE_HINT_REG0
Host Int Enable Register 0
0x1504
ENABLE_HINT_REG1
Host Int Enable Register 1
ADVANCE INFORMATION
Table 7-20
End of Table 7-20
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7.5.2.3 INTC2 Register Map
Table 7-21
INTC2 Registers (Part 1 of 2)
ADVANCE INFORMATION
Address Offset
Register Mnemonic
Register Name
0x0
REVISION_REG
Revision Register
0x10
GLOBAL_ENABLE_HINT_REG
Global Host Int Enable Register
0x20
STATUS_SET_INDEX_REG
Status Set Index Register
0x24
STATUS_CLR_INDEX_REG
Status Clear Index Register
0x28
ENABLE_SET_INDEX_REG
Enable Set Index Register
0x2c
ENABLE_CLR_INDEX_REG
Enable Clear Index Register
0x34
HINT_ENABLE_SET_INDEX_REG
Host Int Enable Set Index Register
0x38
HINT_ENABLE_CLR_INDEX_REG
Host Int Enable Clear Index Register
0x200
RAW_STATUS_REG0
Raw Status Register 0
0x204
RAW_STATUS_REG1
Raw Status Register 1
0x280
ENA_STATUS_REG0
Enabled Status Register 0
0x284
ENA_STATUS_REG1
Enabled Status Register 1
0x300
ENABLE_REG0
Enable Register 0
0x304
ENABLE_REG1
Enable Register 1
0x380
ENABLE_CLR_REG0
Enable Clear Register 0
0x384
ENABLE_CLR_REG1
Enable Clear Register 1
0x400
CH_MAP_REG0
Interrupt Channel Map Register for 0 to 0+3
0x404
CH_MAP_REG1
Interrupt Channel Map Register for 4 to 4+3
0x408
CH_MAP_REG2
Interrupt Channel Map Register for 8 to 8+3
0x40c
CH_MAP_REG3
Interrupt Channel Map Register for 12 to 12+3
0x410
CH_MAP_REG4
Interrupt Channel Map Register for 16 to 16+3
0x414
CH_MAP_REG5
Interrupt Channel Map Register for 20 to 20+3
0x418
CH_MAP_REG6
Interrupt Channel Map Register for 24 to 24+3
0x41c
CH_MAP_REG7
Interrupt Channel Map Register for 28 to 28+3
0x420
CH_MAP_REG8
Interrupt Channel Map Register for 32 to 32+3
0x424
CH_MAP_REG9
Interrupt Channel Map Register for 36 to 36+3
0x428
CH_MAP_REG10
Interrupt Channel Map Register for 40 to 40+3
0x42c
CH_MAP_REG11
Interrupt Channel Map Register for 44 to 44+3
0x430
CH_MAP_REG12
Interrupt Channel Map Register for 48 to 48+3
0x434
CH_MAP_REG13
Interrupt Channel Map Register for 52 to 52+3
0x438
CH_MAP_REG14
Interrupt Channel Map Register for 56 to 56+3
0x43c
CH_MAP_REG15
Interrupt Channel Map Register for 60 to 60+3
0x800
HINT_MAP_REG0
Host Interrupt Map Register for 0 to 0+3
0x804
HINT_MAP_REG1
Host Interrupt Map Register for 4 to 4+3
0x808
HINT_MAP_REG2
Host Interrupt Map Register for 8 to 8+3
0x80c
HINT_MAP_REG3
Host Interrupt Map Register for 12 to 12+3
0x810
HINT_MAP_REG4
Host Interrupt Map Register for 16 to 16+3
0x814
HINT_MAP_REG5
Host Interrupt Map Register for 20 to 20+3
0x818
HINT_MAP_REG6
Host Interrupt Map Register for 24 to 24+3
0x81c
HINT_MAP_REG7
Host Interrupt Map Register for 28 to 28+3
0x820
HINT_MAP_REG8
Host Interrupt Map Register for 32 to 32+3
0x824
HINT_MAP_REG9
Host Interrupt Map Register for 36 to 36+3
134
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TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Table 7-21
INTC2 Registers (Part 2 of 2)
Address Offset
Register Mnemonic
Register Name
0x828
HINT_MAP_REG10
Host Interrupt Map Register for 40 to 40+3
0x1500
ENABLE_HINT_REG0
Host Int Enable Register 0
0x1504
ENABLE_HINT_REG1
Host Int Enable Register 1
End of Table 7-21
7.5.3 Inter-Processor Register Map
IPC Generation Registers (IPCGRx)
Address Start
Address End
Size
Register Name
Description
0x02620200
0x02620203
4B
NMIGR0
NMI Event Generation Register for Core 0
0x02620204
0x02620207
4B
NMIGR1
NMI Event Generation Register for Core 1
0x02620208
0x0262020B
4B
NMIGR2
NMI Event Generation Register for Core 2
0x0262020C
0x0262020F
4B
NMIGR3
NMI Event Generation Register for Core 3
0x02620210
0x02620213
4B
Reserved
Reserved
0x02620214
0x02620217
4B
Reserved
Reserved
0x02620218
0x0262021B
4B
Reserved
Reserved
0x0262021C
0x0262021F
4B
Reserved
Reserved
0x02620220
0x0262023F
32B
Reserved
Reserved
0x02620240
0x02620243
4B
IPCGR0
IPC Generation Register for Core 0
0x02620244
0x02620247
4B
IPCGR1
IPC Generation Register for Core 1
0x02620248
0x0262024B
4B
IPCGR2
IPC Generation Register for Core 2
0x0262024C
0x0262024F
4B
IPCGR3
IPC Generation Register for Core 3
0x02620250
0x02620253
4B
Reserved
Reserved
0x02620254
0x02620257
4B
Reserved
Reserved
0x02620258
0x0262025B
4B
Reserved
Reserved
0x0262025C
0x0262025F
4B
Reserved
Reserved
0x02620260
0x0262027B
28B
Reserved
Reserved
0x0262027C
0x0262027F
4B
IPCGRH
IPC Generation Register for Host
0x02620280
0x02620283
4B
IPCAR0
IPC Acknowledgement Register for Core 0
0x02620284
0x02620287
4B
IPCAR1
IPC Acknowledgement Register for Core 1
0x02620288
0x0262028B
4B
IPCAR2
IPC Acknowledgement Register for Core 2
0x0262028C
0x0262028F
4B
IPCAR3
IPC Acknowledgement Register for Core 3
0x02620290
0x02620293
4B
Reserved
Reserved
0x02620294
0x02620297
4B
Reserved
Reserved
0x02620298
0x0262029B
4B
Reserved
Reserved
0x0262029C
0x0262029F
4B
Reserved
Reserved
0x026202A0
0x026202BB
28B
Reserved
Reserved
0x026202BC
0x026202BF
4B
IPCARH
IPC Acknowledgement Register for Host
ADVANCE INFORMATION
Table 7-22
End of Table 7-22
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Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
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7.5.4 NMI and LRESET
The Non-Maskable Interrupts (NMI) can be generated by chip-level registers and the LRESET can be generated by
software writing into LPSC registers. LRESET and NMI can also be asserted by device pins or Watch Dog Timers.
There is one NMI pin and one LRESET pin on the device and CORESEL[2:0] is used to select the CorePac that needs
to be acted upon the assertion of this pin. The configuration is shown in Table 7-23.
Table 7-23
LRESET and NMI Decoding
ADVANCE INFORMATION
CORESEL[2:0] Pin Input LRESET Pin Input NMI Pin Input
LRESETNMIEN Pin Input
Reset Mux Block Output
XXX
X
X
1
No local reset or NMI assertion
000
0
X
0
Assert local reset to CorePac 0
001
0
X
0
Assert local reset to CorePac 1
010
0
X
0
Assert local reset to CorePac 2
011
0
X
0
Assert local reset to CorePac 3.
1xx
0
X
0
Assert local reset to all CorePac s
000
1
1
0
De-assert local reset & NMI to CorePac 0
001
1
1
0
De-assert local reset & NMI to CorePac 1
010
1
1
0
De-assert local reset & NMI to CorePac 2
011
1
1
0
De-assert local reset & NMI to CorePac 3
1xx
1
1
0
De-assert local reset & NMI to all CorePac s
000
1
0
0
Assert NMI to CorePac 0
001
1
0
0
Assert NMI to CorePac 1
010
1
0
0
Assert NMI to CorePac 2
011
1
0
0
Assert NMI to CorePac 3
1xx
1
0
0
Assert NMI to all CorePac s
End of Table 7-23
136
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Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
7.5.5 External Interrupts Electrical Data/Timing
Table 7-24
NMI and LRESET Timing Requirements
(1)
(see Figure 7-13)
Min
Max
Unit
1
tsu(LRESET-LRESETNMIENL)
Setup Time - LRESET valid before LRESETNMIEN low
TBD
μs
1
tsu(NMI-LRESETNMIENL)
Setup Time - NMI valid before LRESETNMIEN low
TBD
μs
1
tsu(CORESELn-LRESETNMIENL)
Setup Time - CORESEL[2:0] valid before LRESETNMIEN low
TBD
μs
2
th(LRESETNMIENL-LRESET)
Hold Time - LRESET valid after LRESETNMIEN low
TBD
μs
2
th(LRESETNMIENL-NMI)
Hold Time - NMI valid after LRESETNMIEN low
TBD
μs
2
th(LRESETNMIENL-CORESELn)
Hold Time - CORESEL[2:0] valid after LRESETNMIEN low
TBD
μs
3
tw(LRESETNMIEN)
Pulse Width - LRESETNMIEN low width
TBD
μs
4
tc(LRESETNMIENL-LRESETNMIENL)
Cycle Time - time between LRESETNMIEN low
TBD
μs
End of Table 7-24
1 P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
Figure 7-13
NMI and LRESET Timing
1
2
CORESEL[2:0]/
LRESET/
NMI
3
LRESETNMIEN
4
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ADVANCE INFORMATION
No.
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Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
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7.6 Memory Protection Unit (MPU)
The C6670 supports four MPUs:
• One MPU is used to protect main CORE/3 CFG TeraNet (CFG space of all slave devices on the TeraNet is
protected by the MPU).
• Two MPUs are used for packet DMA (one for DATA PORT and another is for CFG PORT).
• One MPU is used for Semaphore.
This section contains MPU register map and details of device-specific MPU registers only. For MPU features and
details of generic MPU registers, see the Memory Protection Unit (MPU) for KeyStone Devices User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 59.
ADVANCE INFORMATION
The following tables show the configuration of each MPU and the memory regions protected by each MPU.
Table 7-25
MPU Default Configuration
MPU0
Main CFG SCR
Setting
MPU1
(QM_SS DATA PORT)
MPU2
(QM_SS CFG PORT)
MPU3
Semaphore
Default permission
Assume allowed
Assume allowed
Assume allowed
Assume allowed
Number of allowed IDs supported
16
16
16
16
Number of programmable ranges supported
16
4
16
1
Compare width
1KB granularity
1KB granularity
1KB granularity
1KB granularity
End of Table 7-25
Table 7-26
MPU Memory Regions
Memory Protection
Start Address
End Address
MPU0
Main CFG SCR
0x01D00000
0x026203FF
MPU1
QM_SS DATA PORT
0x34000000
0x340BFFFF
MPU2
QM_SS CFG PORT
0x02A00000
0x02ABFFFF
MPU3
Semaphore
0x02640000
0x026407FF
End of Table 7-26
Table 7-27 shows the privilege ID of each CORE and every mastering peripheral. Table 7-27 also shows the privilege
level (supervisor vs. user), security level (secure vs. non-secure), and access type (instruction read vs. data/DMA read
or write) of each master on the device. In some cases, a particular setting depends on software being executed at the
time of the access or the configuration of the master peripheral.
Table 7-27
Device Master Settings (Part 1 of 2)
Privilege ID
Master
Privilege Level
Security Level
Access Type
0
CorePac0
SW dependant, driven by MSMC
SW dependant
DMA
1
CorePac1
SW dependant, driven by MSMC
SW dependant
DMA
2
CorePac2
SW dependant, driven by MSMC
SW dependant
DMA
3
CorePac3
SW dependant, driven by MSMC
SW dependant
DMA
4
AIF
User
Non-secure
DMA
5
Reserved
6
Reserved
7
FFTC
User
Non-secure
DMA
8
PA_SS
User
Non-secure
DMA
9
SRIO_CPPI/SRIO_M
User/Driven by SRIO block, User mode and supervisor mode is determined Non-secure
by per transaction basis. Only the transaction with source ID matching the
value in SupervisorID register is granted supervisor mode.
DMA
138
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Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Table 7-27
Device Master Settings (Part 2 of 2)
Privilege ID
Master
Privilege Level
Security Level
Access Type
10
QM_CDMA/QM_second
User
Non-secure
DMA
11
PCIe
Supervisor
Non-secure
DMA
12
DAP
Driven by debug_SS
Driven by
debug_SS
DMA
13
Reserved
Supervisor
Non-secure
DMA
14
Reserved
Supervisor
Non-secure
DMA
15
Reserved
User
Non-secure
DMA
ADVANCE INFORMATION
End of Table 7-27
7.6.1 MPU Registers
This section includes the offsets for MPU registers and definitions for device specific MPU registers.
7.6.1.1 MPU Register Map
Table 7-28
MPU0 Registers (Part 1 of 2)
Offset
Name
Description
0h
REVID
Revision ID
4h
CONFIG
Configuration
10h
IRAWSTAT
Interrupt raw status/set
14h
IENSTAT
Interrupt enable status/clear
18h
IENSET
Interrupt enable
1Ch
IENCLR
Interrupt enable clear
20h
EOI
End of interrupt
200h
PROG1_MPSAR
Programmable range 1, start address
204h
PROG1_MPEAR
Programmable range 1, end address
208h
PROG1_MPPA
Programmable range 1, memory page protection attributes
210h
PROG2_MPSAR
Programmable range 2, start address
214h
PROG2_MPEAR
Programmable range 2, end address
218h
PROG2_MPPA
Programmable range 2, memory page protection attributes
220h
PROG3_MPSAR
Programmable range 3, start address
224h
PROG3_MPEAR
Programmable range 3, end address
228h
PROG3_MPPA
Programmable range 3, memory page protection attributes
230h
PROG4_MPSAR
Programmable range 4, start address
234h
PROG4_MPEAR
Programmable range 4, end address
238h
PROG4_MPPA
Programmable range 4, memory page protection attributes
240h
PROG5_MPSAR
Programmable range 5, start address
244h
PROG5_MPEAR
Programmable range 5, end address
248h
PROG5_MPPA
Programmable range 5, memory page protection attributes
250h
PROG6_MPSAR
Programmable range 6, start address
254h
PROG6_MPEAR
Programmable range 6, end address
258h
PROG6_MPPA
Programmable range 6, memory page protection attributes
260h
PROG7_MPSAR
Programmable range 7, start address
264h
PROG7_MPEAR
Programmable range 7, end address
268h
PROG7_MPPA
Programmable range 7, memory page protection attributes
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Multicore Fixed and Floating-Point System-on-Chip
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Table 7-28
www.ti.com
MPU0 Registers (Part 2 of 2)
ADVANCE INFORMATION
Offset
Name
Description
270h
PROG8_MPSAR
Programmable range 8, start address
274h
PROG8_MPEAR
Programmable range 8, end address
278h
PROG8_MPPA
Programmable range 8, memory page protection attributes
280h
PROG9_MPSAR
Programmable range 9, start address
284h
PROG9_MPEAR
Programmable range 9, end address
288h
PROG9_MPPA
Programmable range 9, memory page protection attributes
290h
PROG10_MPSAR
Programmable range 10, start address
294h
PROG10_MPEAR
Programmable range 10, end address
298h
PROG10_MPPA
Programmable range 10, memory page protection attributes
2A0h
PROG11_MPSAR
Programmable range 11, start address
2A4h
PROG11_MPEAR
Programmable range 11, end address
2A8h
PROG11_MPPA
Programmable range 11, memory page protection attributes
2B0h
PROG12_MPSAR
Programmable range 12, start address
2B4h
PROG12_MPEAR
Programmable range 12, end address
2B8h
PROG12_MPPA
Programmable range 12, memory page protection attributes
2C0h
PROG13_MPSAR
Programmable range 13, start address
2C4h
PROG13_MPEAR
Programmable range 13, end address
2C8h
PROG13_MPPA
Programmable range 13, memory page protection attributes
2D0h
PROG14_MPSAR
Programmable range 14, start address
2D4h
PROG14_MPEAR
Programmable range 14, end address
2Dh
PROG14_MPPA
Programmable range 14, memory page protection attributes
2E0h
PROG15_MPSAR
Programmable range 15, start address
2E4h
PROG15_MPEAR
Programmable range 15, end address
2E8h
PROG15_MPPA
Programmable range 15, memory page protection attributes
2F0h
PROG16_MPSAR
Programmable range 16, start address
2F4h
PROG16_MPEAR
Programmable range 16, end address
2F8h
PROG16_MPPA
Programmable range 16, memory page protection attributes
300h
FLTADDRR
Fault address
304h
FLTSTAT
Fault status
308h
FLTCLR
Fault clear
End of Table 7-28
Table 7-29
MPU1 Registers (Part 1 of 2)
Offset
Name
Description
0h
REVID
Revision ID
4h
CONFIG
Configuration
10h
IRAWSTAT
Interrupt raw status/set
14h
IENSTAT
Interrupt enable status/clear
18h
IENSET
Interrupt enable
1Ch
IENCLR
Interrupt enable clear
20h
EOI
End of interrupt
200h
PROG1_MPSAR
Programmable range 1, start address
204h
PROG1_MPEAR
Programmable range 1, end address
140
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Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
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MPU1 Registers (Part 2 of 2)
Offset
Name
Description
208h
PROG1_MPPA
Programmable range 1, memory page protection attributes
210h
PROG2_MPSAR
Programmable range 2, start address
214h
PROG2_MPEAR
Programmable range 2, end address
218h
PROG2_MPPA
Programmable range 2, memory page protection attributes
220h
PROG3_MPSAR
Programmable range 3, start address
224h
PROG3_MPEAR
Programmable range 3, end address
228h
PROG3_MPPA
Programmable range 3, memory page protection attributes
230h
PROG4_MPSAR
Programmable range 4, start address
234h
PROG4_MPEA
Programmable range 4, end address
238h
PROG4_MPPA
Programmable range 4, memory page protection attributes
300h
FLTADDRR
Fault address
304h
FLTSTAT
Fault status
308h
FLTCLR
Fault clear
ADVANCE INFORMATION
Table 7-29
End of Table 7-29
Table 7-30
MPU2 Registers (Part 1 of 2)
Offset
Name
Description
0h
REVID
Revision ID
4h
CONFIG
Configuration
10h
IRAWSTAT
Interrupt raw status/set
14h
IENSTAT
Interrupt enable status/clear
18h
IENSET
Interrupt enable
1Ch
IENCLR
Interrupt enable clear
20h
EOI
End of interrupt
200h
PROG1_MPSAR
Programmable range 1, start address
204h
PROG1_MPEAR
Programmable range 1, end address
208h
PROG1_MPPA
Programmable range 1, memory page protection attributes
210h
PROG2_MPSAR
Programmable range 2, start address
214h
PROG2_MPEAR
Programmable range 2, end address
218h
PROG2_MPPA
Programmable range 2, memory page protection attributes
220h
PROG3_MPSAR
Programmable range 3, start address
224h
PROG3_MPEAR
Programmable range 3, end address
228h
PROG3_MPPA
Programmable range 3, memory page protection attributes
230h
PROG4_MPSAR
Programmable range 4, start address
234h
PROG4_MPEAR
Programmable range 4, end address
238h
PROG4_MPPA
Programmable range 4, memory page protection attributes
240h
PROG5_MPSAR
Programmable range 5, start address
244h
PROG5_MPEAR
Programmable range 5, end address
248h
PROG5_MPPA
Programmable range 5, memory page protection attributes
250h
PROG6_MPSAR
Programmable range 6, start address
254h
PROG6_MPEAR
Programmable range 6, end address
258h
PROG6_MPPA
Programmable range 6, memory page protection attributes
260h
PROG7_MPSAR
Programmable range 7, start address
Copyright 2010 Texas Instruments Incorporated
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141
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 7-30
www.ti.com
MPU2 Registers (Part 2 of 2)
Offset
Name
Description
264h
PROG7_MPEAR
Programmable range 7, end address
268h
PROG7_MPPA
Programmable range 7, memory page protection attributes
270h
PROG8_MPSAR
Programmable range 8, start address
ADVANCE INFORMATION
274h
PROG8_MPEAR
Programmable range 8, end address
278h
PROG8_MPPA
Programmable range 8, memory page protection attributes
280h
PROG9_MPSAR
Programmable range 9, start address
284h
PROG9_MPEAR
Programmable range 9, end address
288h
PROG9_MPPA
Programmable range 9, memory page protection attributes
290h
PROG10_MPSAR
Programmable range 10, start address
294h
PROG10_MPEAR
Programmable range 10, end address
298h
PROG10_MPPA
Programmable range 10, memory page protection attributes
2A0h
PROG11_MPSAR
Programmable range 11, start address
2A4h
PROG11_MPEAR
Programmable range 11, end address
2A8h
PROG11_MPPA
Programmable range 11, memory page protection attributes
2B0h
PROG12_MPSAR
Programmable range 12, start address
2B4h
PROG12_MPEAR
Programmable range 12, end address
2B8h
PROG12_MPPA
Programmable range 12, memory page protection attributes
2C0h
PROG13_MPSAR
Programmable range 13, start address
2C4h
PROG13_MPEAR
Programmable range 13, end address
2C8h
PROG13_MPPA
Programmable range 13, memory page protection attributes
2D0h
PROG14_MPSAR
Programmable range 14, start address
2D4h
PROG14_MPEAR
Programmable range 14, end address
2Dh
PROG14_MPPA
Programmable range 14, memory page protection attributes
2E0h
PROG15_MPSAR
Programmable range 15, start address
2E4h
PROG15_MPEAR
Programmable range 15, end address
2E8h
PROG15_MPPA
Programmable range 15, memory page protection attributes
2F0h
PROG16_MPSAR
Programmable range 16, start address
2F4h
PROG16_MPEAR
Programmable range 16, end address
2F8h
PROG16_MPPA
Programmable range 16, memory page protection attributes
300h
FLTADDRR
Fault address
304h
FLTSTAT
Fault status
308h
FLTCLR
Fault clear
End of Table 7-30
Table 7-31
Offset
MPU3 Registers (Part 1 of 2)
Name
Description
0h
REVID
Revision ID
4h
CONFIG
Configuration
10h
IRAWSTAT
Interrupt raw status/set
14h
IENSTAT
Interrupt enable status/clear
18h
IENSET
Interrupt enable
1Ch
IENCLR
Interrupt enable clear
20h
EOI
End of interrupt
142
TMS320C6670 Peripheral Information and Electrical Specifications
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Table 7-31
MPU3 Registers (Part 2 of 2)
Offset
Name
Description
200h
PROG1_MPSAR
Programmable range 1, start address
204h
PROG1_MPEAR
Programmable range 1, end address
208h
PROG1_MPPA
Programmable range 1, memory page protection attributes
300h
FLTADDRR
Fault address
304h
FLTSTAT
Fault status
308h
FLTCLR
Fault clear
ADVANCE INFORMATION
End of Table 7-31
Copyright 2010 Texas Instruments Incorporated
TMS320C6670 Peripheral Information and Electrical Specifications
143
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
7.6.1.2 Device-Specific MPU Registers
7.6.1.2.1 Configuration Register (CONFIG)
The configuration register (CONFIG) contains the configuration value of the MPU.
Figure 7-14
Configuration Register (CONFIG)
31
MPU0
24
23
20
19
16
15
12
11
1
0
ADDR_WIDTH
NUM_FIXED
NUM_PROG
NUM_AIDS
Reserved
ASSUME_ALLOWED
R-0
R-0
R-4
R-16
R-0
R-1
MPU1
R-16
MPU2
R-1
MPU3
R-16
Reset Values
ADVANCE INFORMATION
Legend: R = Read only; -n = value after reset
Table 7-32
Configuration Register (CONFIG) Field Descriptions
Bits
Field
Description
31 – 24
ADDR_WIDTH
Address alignment for range checking
0 = 1KB alignment
6 = 64KB alignment
23 – 20
NUM_FIXED
Number of fixed address ranges
19 – 16
NUM_PROG
Number of programmable address ranges
15 – 12
NUM_AIDS
Number of supported AIDs
11 – 1
Reserved
Reserved. Always reads as 0.
0
ASSUME_ALLOWED
Assume allowed bit. When an address is not covered by any MPU protection range, this bit determines whether the
transfer is assumed to be allowed or not.
0 = Assume disallowed
1 = Assume allowed
7.6.2 MPU Programmable Range Registers
7.6.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
The programmable address start register holds the start address for the range. This register is writeable by a
supervisor entity only. If NS = 0 (non-secure mode) in the associated MPPA register, then the register is also
writeable only by a secure entity.
The start address must be aligned on a page boundary. The size of the page is 1K byte. The size of the page determines
the width of the address field in MPSAR and MPEAR.
Figure 7-15
Programmable Range n Start Address Register (PROGn_MPSAR)
31
10
9
0
START_ADDR
Reserved
R/W
R
Legend: R = Read only; R/W = Read/Write
144
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Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Register
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Register 8
Register 9
Register 10
Register 11
Register 12
Register 13
Register 14
Register 15
Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions (MPU0)
Bits
Name
Reset Value
Range
Programmable
31 – 10
START_ADDR
0x7400
9–0
Reserved
000h
Description
Start address for range 0.
Reserved. Always reads as 0.
31 – 10
START_ADDR
0x7C00
9–0
Reserved
000h
Programmable
Start address for range 1.
Reserved. Always reads as 0.
31 – 10
START_ADDR
0x8000
9–0
Reserved
000h
Programmable
Start address for range 2.
Reserved. Always reads as 0.
31 – 10
START_ADDR
0x8600
9–0
Reserved
000h
Programmable
Start address for range 3.
Reserved. Always reads as 0.
31 – 10
START_ADDR
0x8700
9–0
Reserved
000h
Programmable
ADVANCE INFORMATION
Table 7-33
Start address for range 4.
Reserved. Always reads as 0.
31 – 10
START_ADDR
0x87C0
9–0
Reserved
000h
Programmable
Start address for range 5.
Reserved. Always reads as 0.
31 – 10
START_ADDR
0x8800
9–0
Reserved
000h
Programmable
Start address for range 6.
Reserved. Always reads as 0.
31 – 10
START_ADDR
0x8C40
9–0
Reserved
000h
Programmable
Start address for range 7.
Reserved. Always reads as 0.
31 – 10
START_ADDR
0x8C80
9–0
Reserved
000h
Programmable
Start address for range 8.
Reserved. Always reads as 0.
31 – 10
START_ADDR
0x8CC0
9–0
Reserved
000h
31 – 10
START_ADDR
0x8D40
9–0
Reserved
000h
Programmable
Start address for range 9.
Reserved. Always reads as 0.
Programmable
Start address for range 10.
Reserved. Always reads as 0.
31 – 10
START_ADDR
0x9000
9–0
Reserved
000h
Programmable
Start address for range 11.
Reserved. Always reads as 0.
31 – 10
START_ADDR
0x9400
9–0
Reserved
000h
Programmable
Start address for range 12.
Reserved. Always reads as 0.
31 – 10
START_ADDR
0x94C0
9–0
Reserved
000h
Programmable
Start address for range 13.
Reserved. Always reads as 0.
31 – 10
START_ADDR
0x9800
9–0
Reserved
000h
Programmable
Start address for range 14.
Reserved. Always reads as 0.
31 – 10
START_ADDR
0x9880
9–0
Reserved
000h
Programmable
Start address for range 15.
Reserved. Always reads as 0.
End of Table 7-33
Table 7-34
Register
Register 0
Register 1
Register 2
Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions (MPU1) (Part 1 of 2)
Bits
Name
Reset Value
Range
Programmable
31 – 10
START_ADDR
0xD0000
9–0
Reserved
000h
31 – 10
START_ADDR
0xD0080
9–0
Reserved
000h
31 – 10
START_ADDR
0xD0180
9–0
Reserved
000h
Copyright 2010 Texas Instruments Incorporated
Description
Start address for range 0.
Reserved. Always reads as 0.
Programmable
Start address for range 1.
Reserved. Always reads as 0.
Programmable
Start address for range 2.
Reserved. Always reads as 0.
TMS320C6670 Peripheral Information and Electrical Specifications
145
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 7-34
www.ti.com
Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions (MPU1) (Part 2 of 2)
Register
Register 3
Register 4
Register 5
Bits
Name
Reset Value
Range
Description
31 – 10
START_ADDR
0xD01A0
Programmable
Start address for range 3.
9–0
Reserved
000h
31 – 10
START_ADDR
0xD02E0
Programmable
Start address for range 4.
9–0
Reserved
000h
31 – 10
START_ADDR
0xD0200
9–0
Reserved
000h
Reserved. Always reads as 0.
Reserved. Always reads as 0.
Programmable
Start address for range 5.
Reserved. Always reads as 0.
End of Table 7-34
ADVANCE INFORMATION
Table 7-35
Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions (MPU2)
Register
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Register 8
Register 9
Register 10
Register 11
Register 12
Register 13
Register 14
Register 15
Bits
Name
Reset Value
Range
Description
Programmable
Start address for range 0.
31 – 10
START_ADDR
0xA800
9–0
Reserved
000h
31 – 10
START_ADDR
0xA880
9–0
Reserved
000h
31 – 10
START_ADDR
0xA900
9–0
Reserved
000h
31 – 10
START_ADDR
0xA980
9–0
Reserved
000h
31 – 10
START_ADDR
0xA9A0
9–0
Reserved
000h
31 – 10
START_ADDR
0xA9A4
9–0
Reserved
000h
31 – 10
START_ADDR
0xA9A8
9–0
Reserved
000h
31 – 10
START_ADDR
0xA9AC
9–0
Reserved
000h
31 – 10
START_ADDR
0xA9B0
9–0
Reserved
000h
31 – 10
START_ADDR
0xA9B8
9–0
Reserved
000h
31 – 10
START_ADDR
0xAA00
9–0
Reserved
000h
31 – 10
START_ADDR
0xAA40
9–0
Reserved
000h
31 – 10
START_ADDR
0xAA80
9–0
Reserved
000h
31 – 10
START_ADDR
0xAAA0
9–0
Reserved
000h
31 – 10
START_ADDR
0xAAD0
9–0
Reserved
000h
31 – 10
START_ADDR
0xAAE0
9–0
Reserved
000h
Reserved. Always reads as 0.
Programmable
Start address for range 1.
Reserved. Always reads as 0.
Programmable
Start address for range 2.
Reserved. Always reads as 0.
Programmable
Start address for range 3.
Reserved. Always reads as 0.
Programmable
Start address for range 4.
Reserved. Always reads as 0.
Programmable
Start address for range 5.
Reserved. Always reads as 0.
Programmable
Start address for range 6.
Reserved. Always reads as 0.
Programmable
Start address for range 7.
Reserved. Always reads as 0.
Programmable
Start address for range 8.
Reserved. Always reads as 0.
Programmable
Start address for range 9.
Reserved. Always reads as 0.
Programmable
Start address for range 10.
Reserved. Always reads as 0.
Programmable
Start address for range 11.
Reserved. Always reads as 0.
Programmable
Start address for range 12.
Reserved. Always reads as 0.
Programmable
Start address for range 13.
Reserved. Always reads as 0.
Programmable
Start address for range 14.
Reserved. Always reads as 0.
Programmable
Start address for range 15.
Reserved. Always reads as 0.
End of Table 7-35
146
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Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Table 7-36
Register
Register 0
Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions (MPU3)
Bits
Name
Reset Value
Range
Description
31 – 16
START_ADDR
0x9900
Programmable
9–0
Reserved
000h
Start address for range 0.
Reserved. Always reads as 0.
End of Table 7-36
The programmable address end register holds the end address for the range. This register is writeable by a supervisor
entity only. If NS = 0 (non-secure mode) in the associated MPPA register then the register is also only writeable by
a secure entity.
The end address must be aligned on a page boundary. The size of the page depends on the MPU number. The page
size for MPU1 is 1K byte and for MPU2 it is 64K bytes. The size of the page determines the width of the address field
in MPSAR and MPEAR
Figure 7-16
Programmable Range n End Address Register (PROGn_MPEAR)
31
10
9
0
END_ADDR
Reserved
R/W
R
Legend: R = Read only; R/W = Read/Write
Table 7-37
Register
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Register 8
Register 9
Register 10
Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions (MPU0)
Bits
Name
Reset Value
Range
Description
31 – 10
END_ADDR
0x75E0
Programmable
End address for range 0.
9–0
Reserved
3FFh
31 – 10
END_ADDR
0x7DFF
Programmable
End address for range 1.
9–0
Reserved
3FFh
31 – 10
END_ADDR
0x827F
Programmable
End address for range 2.
9–0
Reserved
3FFh
31 – 10
END_ADDR
0x86BF
Programmable
End address for range 3.
9–0
Reserved
3FFh
31 – 10
END_ADDR
0x8783
Programmable
End address for range 4.
9–0
Reserved
3FFh
31 – 10
END_ADDR
0x87DF
Programmable
End address for range 5.
9–0
Reserved
3FFh
31 – 10
END_ADDR
0x89C0
Programmable
End address for range 6.
9–0
Reserved
3FFh
31 – 10
END_ADDR
0x8C40
Programmable
End address for range 7.
9–0
Reserved
3FFh
31 – 10
END_ADDR
0x8C80
Programmable
End address for range 8.
9–0
Reserved
3FFh
31 – 10
END_ADDR
0x8CC0
Programmable
End address for range 9.
9–0
Reserved
3FFh
31 – 10
END_ADDR
0x8D43
Programmable
End address for range 10.
9–0
Reserved
3FFh
Copyright 2010 Texas Instruments Incorporated
Reserved. Always reads as 0.
Reserved. Always reads as 0.
Reserved. Always reads as 0.
Reserved. Always reads as 0.
Reserved. Always reads as 0.
Reserved. Always reads as 0.
Reserved. Always reads as 0.
Reserved. Always reads as 0.
Reserved. Always reads as 0.
Reserved. Always reads as 0.
Reserved. Always reads as 0.
TMS320C6670 Peripheral Information and Electrical Specifications
147
ADVANCE INFORMATION
7.6.2.2 Programmable Range n - End Address Register (PROGn_MPEAR)
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 7-37
Register
Register 11
Register 12
Register 13
Register 14
ADVANCE INFORMATION
Register 15
www.ti.com
Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions (MPU0)
Bits
Name
Reset Value
Range
Description
31 – 10
END_ADDR
91CF
Programmable
End address for range 11.
9–0
Reserved
3FFh
31 – 10
END_ADDR
0x9480
Programmable
End address for range 12.
9–0
Reserved
3FFh
31 – 10
END_ADDR
0x9500
Programmable
End address for range 13.
9–0
Reserved
3FFh
31 – 10
END_ADDR
0x982F
Programmable
End address for range 14.
9–0
Reserved
3FFh
31 – 10
END_ADDR
0x9881
Programmable
End address for range 15.
9–0
Reserved
3FFh
Reserved. Always reads as 0.
Reserved. Always reads as 0.
Reserved. Always reads as 0.
Reserved. Always reads as 0.
Reserved. Always reads as 0.
End of Table 7-37
Table 7-38
Register
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions (MPU1)
Bits
Name
Reset Value
Range
31 – 10
END_ADDR
0xD007F
Programmable
9–0
Reserved
3FFh
31 – 10
END_ADDR
0xD017F
9–0
Reserved
3FFh
31 – 10
END_ADDR
0xD019F
9–0
Reserved
3FFh
31 – 10
END_ADDR
0xD02DF
9–0
Reserved
3FFh
31 – 10
END_ADDR
0xD02FF
9–0
Reserved
3FFh
31 – 10
END_ADDR
0xD02FF
9–0
Reserved
3FFh
Description
End address for range 0.
Reserved. Always reads as 0.
Programmable
End address for range 1.
Reserved. Always reads as 0.
Programmable
End address for range 2.
Reserved. Always reads as 0.
Programmable
End address for range 3.
Reserved. Always reads as 0.
Programmable
End address for range 4.
Reserved. Always reads as 0.
Programmable
End address for range 5.
Reserved. Always reads as 0.
End of Table 7-38
Table 7-39
Register
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
148
Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions (MPU2) (Part 1 of 2)
Bits
Name
Reset Value
Range
Description
31 – 10
END_ADDR
0xA87F
Programmable
End address for range 0.
9–0
Reserved
3FFh
31 – 10
END_ADDR
0xA8FF
9–0
Reserved
3FFh
31 – 10
END_ADDR
0xA97F
9–0
Reserved
3FFh
31 – 10
END_ADDR
0xA99F
9–0
Reserved
3FFh
31 – 10
END_ADDR
0xA9A3
9–0
Reserved
3FFh
31 – 10
END_ADDR
0xA9A7
9–0
Reserved
3FFh
Reserved. Always reads as 0.
Programmable
End address for range 1.
Reserved. Always reads as 0.
Programmable
End address for range 2.
Reserved. Always reads as 0.
Programmable
End address for range 3.
Reserved. Always reads as 0.
Programmable
End address for range 4.
Reserved. Always reads as 0.
Programmable
TMS320C6670 Peripheral Information and Electrical Specifications
End address for range 5.
Reserved. Always reads as 0.
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions (MPU2) (Part 2 of 2)
Register
Register 6
Register 7
Register 8
Register 9
Register 10
Register 11
Register 12
Register 13
Register 14
Register 15
Bits
Name
Reset Value
Range
Description
31 – 10
END_ADDR
0xA9AB
Programmable
End address for range 6.
Programmable
End address for range 7.
Programmable
End address for range 8.
Programmable
End address for range 9.
Programmable
End address for range 10.
Programmable
End address for range 11.
Programmable
End address for range 12.
Programmable
End address for range 13.
Programmable
End address for range 14.
Programmable
End address for range 15.
9–0
Reserved
3FFh
31 – 10
END_ADDR
0xA9AF
9–0
Reserved
3FFh
31 – 10
END_ADDR
0xA9B7
9–0
Reserved
3FFh
31 – 10
END_ADDR
0xA9BF
9–0
Reserved
3FFh
31 – 10
END_ADDR
0xAA3F
9–0
Reserved
3FFh
31 – 10
END_ADDR
0xAA7F
9–0
Reserved
3FFh
31 – 10
END_ADDR
0xAA9F
9–0
Reserved
3FFh
31 – 10
END_ADDR
0xAACF
9–0
Reserved
3FFh
31 – 10
END_ADDR
0xAADE
9–0
Reserved
3FFh
31 – 10
END_ADDR
0xAAFF
9–0
Reserved
3FFh
Reserved. Always reads as 0.
Reserved. Always reads as 0.
Reserved. Always reads as 0.
Reserved. Always reads as 0.
ADVANCE INFORMATION
Table 7-39
Reserved. Always reads as 0.
Reserved. Always reads as 0.
Reserved. Always reads as 0.
Reserved. Always reads as 0.
Reserved. Always reads as 0.
Reserved. Always reads as 0.
End of Table 7-39
Table 7-40
Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions (MPU3)
Register
Bits
Register 0
Name
Reset Value
Range
Programmable
31 – 16
END_ADDR
9901h
9–0
Reserved
3FFh
Description
End address for range 0.
Reserved. Always reads as 0.
End of Table 7-40
7.6.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)
The programmable address memory protection page attribute register holds the permissions for the region. This
register is writeable only by a non-debug supervisor entity. If NS = 0 (secure mode) then the register is also only
writeable by a non-debug secure entity. The NS bit is only writeable by a non-debug secure entity. For debug
accesses, the register is writeable only when NS = 1 or EMU = 1.
Figure 7-17
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)
31
26
25
24
23
22
21
20
19
18
17
16
15
Reserved
AID15
AID14
AID13
AID12
AID11
AID10
AID9
AID8
AID7
AID6
AID5
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AID4
AID3
AID2
AID1
AID0
AIDX
Reserved
NS
EMU
SR
SW
SX
UR
UW
UX
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Legend: R = Read only; R/W = Read/Write
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Table 7-41
www.ti.com
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions
(Part 1 of 2)
ADVANCE INFORMATION
Bits
Name
Description
31 – 26
Reserved
Reserved. Always reads as 0.
25
AID15
Controls access from ID = 15
0 = Access denied.
1 = Access granted.
24
AID14
Controls access from ID = 14
0 = Access denied.
1 = Access granted.
23
AID13
Controls access from ID = 13
0 = Access denied.
1 = Access granted.
22
AID12
Controls access from ID = 12
0 = Access denied.
1 = Access granted.
21
AID11
Controls access from ID = 11
0 = Access denied.
1 = Access granted.
20
AID10
Controls access from ID = 10
0 = Access denied.
1 = Access granted.
19
AID9
Controls access from ID = 9
0 = Access denied.
1 = Access granted.
18
AID8
Controls access from ID = 8
0 = Access denied.
1 = Access granted.
17
AID7
Controls access from ID = 7
0 = Access denied.
1 = Access granted.
16
AID6
Controls access from ID = 6
0 = Access denied.
1 = Access granted.
15
AID5
Controls access from ID = 5
0 = Access denied.
1 = Access granted.
14
AID4
Controls access from ID = 4
0 = Access denied.
1 = Access granted.
13
AID3
Controls access from ID = 3
0 = Access denied.
1 = Access granted.
12
AID2
Controls access from ID = 2
0 = Access denied.
1 = Access granted.
11
AID1
Controls access from ID = 1
0 = Access denied.
1 = Access granted.
10
AID0
Controls access from ID = 0
0 = Access denied.
1 = Access granted.
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Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions
(Part 2 of 2)
Bits
Name
Description
9
AIDX
Controls access from ID > 15
0 = Access denied.
1 = Access granted.
8
Reserved
Reserved. Always reads as 0.
7
NS
Non-secure access permission
0 = Only secure access allowed.
1 = Non-secure access allowed.
6
EMU
Emulation (debug) access permission. This bit is ignored if NS = 1
0 = Debug access not allowed.
1 = Debug access allowed.
5
SR
Supervisor Read permission
0 = Access not allowed.
1 = Access allowed.
4
SW
Supervisor Write permission
0 = Access not allowed.
1 = Access allowed.
3
SX
Supervisor Execute permission
0 = Access not allowed.
1 = Access allowed.
2
UR
User Read permission
0 = Access not allowed.
1 = Access allowed
1
UW
User Write permission
0 = Access not allowed.
1 = Access allowed.
0
UX
User Execute permission
ADVANCE INFORMATION
Table 7-41
0 = Access not allowed.
1 = Access allowed.
End of Table 7-411
Table 7-42
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Reset Values (Part 1 of 2)
Register
MPU0
MPU1
MPU2
MPU3
Register 0
0X0003_FCB6
0X03FF_FC80
0x03FF_FCA4
0X0003_FCB6
Register 1
0X0003_FCB6
0X0003_FCB6
0X0003_FCB6
N/A
Register 2
0X0003_FCB6
0X0003_FCB4
0X0003_FCB6
N/A
Register 3
0X0003_FCB6
0X0003_FC80
0X0003_FCB4
N/A
Register 4
0X0003_FCB6
0X0003_FCB6
0X0003_FCB4
N/A
Register 5
0X0003_FCB6
N/A
0X0003_FCB4
N/A
Register 6
0X0003_FCB6
N/A
0X0003_FCB4
N/A
Register 7
0X0003_FCB4
N/A
0X0003_FCB4
N/A
Register 8
0X0003_FCB4
N/A
0X0003_FCB4
N/A
Register 9
0X0003_FCB4
N/A
0X0003_FCB4
N/A
Register 10
0X0003_FCB4
N/A
0X0003_FCA4
N/A
Register 11
0X0003_FCB6
N/A
0X0003_FCB4
N/A
Register 12
0X0003_FCB4
N/A
0X0003_FCB4
N/A
Register 13
0X0003_FCB6
N/A
0X0003_FCB4
N/A
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Table 7-42
www.ti.com
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Reset Values (Part 2 of 2)
Register
MPU0
MPU1
MPU2
MPU3
Register 14
0X0003_FCB4
N/A
0X0003_FCB4
N/A
Register 15
0X0003_FCB4
N/A
0X0003_FCB6
N/A
End of Table 7-42
ADVANCE INFORMATION
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7.7 Reset Controller
The reset controller detects the different type of resets supported on the TMS320C6670 device and manages the
distribution of those resets throughout the device.
Table 7-43 explains further the types of reset, the reset initiator, and the effects of each reset on the device. For more
information on the effects of each reset on the PLL controllers and their clocks, see Section 7.7.7 ‘‘Reset Electrical
Data/Timing’’ on page 156.
Table 7-43
Reset Types
Type
Power-on Reset
Initiator
POR pin
RESETFULL pin
RESET pin
Hard Reset
Soft Reset
PLLCTL (1) register (RSCTRL)
Watchdog Timers
Resets the entire chip including the test and emulation logic. The device configuration pins are
latched only during Power-on Reset.
Hard Reset resets everything except for test, emulation logic and reset isolation modules. This
reset is also different from Power-on Reset in that the PLLCTL assumes power and clocks are stable
when Hard Reset is asserted. The device configurations pins are not re-latched.
Emulation initiated reset is always a Hard Reset.
Emulation
By default these initiators are configured as Hard reset, but can be configured (Except Emulation)
as Soft reset in the RSCFG register of PLLCTL. Contents of DDR3 SDRAM memory can be retained
during a Hard Reset if the SDRAM is placed in self-refresh mode.
RESET pin
Soft Reset will behave like Hard Reset except that PCIe MMRs and DDR3 EMIF MMRs contents are
retained.
PLLCTL register (RSCTRL)
Watchdog Timers
Local Reset
Effect(s)
LRESET pin
Watchdog Timer timeout
By default these initiators are configured as Hard reset, but can be configured as Soft reset in the
RSCFG register of PLLCTL. Contents of DDR3 SDRAM memory can be retained during a Soft Reset if
the SDRAM is placed in self-refresh mode.
Resets the CorePac, without destroying clock alignment or memory contents. The device
configuration pins are not re-latched.
LPSC MMRs
End of Table 7-43
1 All masters in the device have access to the PLLCTL registers.
7.7.1 Power-on Reset
Power-on reset is used to reset the entire device, including the test and emulation logic.
Power-on reset is initiated by the following
1. POR pin
2. RESETFULL pin
During power-up, the POR pin must be asserted (driven low) until the power supplies have reached their normal
operating conditions. A RESETFULL pin is also provided to allow the on-board host to reset the entire device
including the reset isolated logic. The assumption is that, device is already powered up and hence unlike POR,
RESETFULL pin will be driven by the on-board host control other than the power good circuitry. For power-on
reset, the Main PLL controller comes up in bypass mode and the PLL is not enabled. Other resets do not affect the
state of the PLL or the dividers in the PLL controller.
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The device has the following types of resets:
• Power-on Reset
• Hard Reset
• Soft Reset
• Local Reset
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ADVANCE INFORMATION
The following sequence must be followed during a power-on reset:
1. Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted (driven
low). While POR is asserted, all pins except RESETSTAT will be set to high-impedance. After the POR pin is
de-asserted (driven high), all Z group pins, low group pins, and high group pins are set to their reset state and
will remain at their reset state until otherwise configured by their respective peripheral. All peripherals that are
power managed, are disabled after a Power-on Reset and must be enabled through the Device State Control
registers (for more details, see Section Table 3-2 ‘‘Device State Control Registers’’ on page 61).
2. Clocks are reset, and they are propagated throughout the chip to reset any logic that was using reset
synchronously. All logic is now reset and RESETSTAT will be driven low indicating that the device is in reset.
3. POR must be held active until all supplies on the board are stable then for at least an additional time for the
Chip level PLLs to lock.
4. The POR pin can now be de-asserted. Reset sampled pin values are latched at this point. The Chip level PLLs
is taken out of reset and begins its locking sequence, and all power-on device initialization also begins.
5. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high). By this time, DDR3
PLL has already completed its locking sequence and is outputting a valid clock. The system clocks of both PLL
controllers are allowed to finish their current cycles and then paused for 10 cycles of their respective system
reference clocks. After the pause, the system clocks are restarted at their default divide by settings.
6. The device is now out of reset and device execution begins as dictated by the selected boot mode.
Note—To most of the device, reset is de-asserted only when the POR and RESET pins are both de-asserted
(driven high). Therefore, in the sequence described above, if the RESET pin is held low past the low period
of the POR pin, most of the device will remain in reset. The RESET pin should not be tied together with the
POR pin.
7.7.2 Hard Reset
A Hard reset will reset everything on the device except the PLLs, test, emulation logic and reset isolation modules.
POR should also remain de-asserted during this time.
Hard reset is initiated by the following
• RESET pin
• RSCTRL register in PLLCTL
• Watchdog Timer
• Emulation
All the above initiators by default are configured to act as Hard reset. Except Emulation all the other 3 initiators can
be configured as Soft resets in the RSCFG register in PLLCTL.
The following sequence must be followed during a Hard reset:
1. The RESET pin is pulled active low for a minimum of 24 CLKIN1 cycles. During this time the RESET signal is
able to propagate to all modules (except those specifically mentioned above). All I/O are Hi-Z for modules
affected by RESET, to prevent off-chip contention during the warm reset.
2. Once all logic is reset, RESETSTAT is driven active to denote that the device is in reset.
3. The RESET pin can now be released. A minimal device initialization begins to occur. Note that configuration
pins are not re-latched and clocking is unaffected within the device.
4. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high).
Note—The POR pin should be held inactive (high) throughout the warm reset sequence. Otherwise, if POR
is activated (brought low), the minimum POR pulse width must be met. The RESET pin should not be tied
together with the POR pin.
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7.7.3 Soft Reset
Soft reset is initiated by the following
• RESET pin
• RSCTRL register in PLLCTL
• Watchdog Timer
• Emulation
All the above initiators by default are configured to act as Hard reset. Except Emulation all the other 3 initiators can
be configured as Soft resets in the RSCFG register in PLLCTL.
In the case of a soft reset, the clock logic or the power control logic of the peripherals are not affected, and, therefore,
the enabled/disabled state of the peripherals is not affected. The following external memory contents are maintained
during a soft reset:
• DDR3 MMRs: The DDR3 Memory Controller registers are not reset. In addition, the DDR3 SDRAM memory
content is retained if the user places the DDR3 SDRAM in self-refresh mode before invoking the soft reset.
• PCIe MMRs: The contents of the memory connected to the EMIFA are retained. The EMIFA registers are not
reset.
During a soft reset, the following happens:
1. The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset is allowed to propagate
through the system. Internal system clocks are not affected. PLLs also remain locked.
2. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). In addition, the PLL
controllers pause their system clocks for about 8 cycles.
At this point:
› The state of the peripherals before the soft reset is not changed.
› The I/O pins are controlled as dictated by the DEVSTAT register.
› The DDR3 MMRs and PCIe MMRs retain their previous values. Only the DDR3 Memory Controller
and PCIe state machines are reset by the soft reset.
› The PLL controllers are operating in the mode prior to soft reset. System clocks are unaffected.
The boot sequence is started after the system clocks are restarted. Since the configuration pins are not latched with
a System Reset, the previous values, as shown in the DEVSTAT register, are used to select the boot mode.
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ADVANCE INFORMATION
A soft reset will behave like a hard reset except that the PCIe MMRs and DDR3 EMIF MMRs contents are retained.
POR should also remain de-asserted during this time.
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Multicore Fixed and Floating-Point System-on-Chip
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7.7.4 Local Reset
The local reset can be used to reset a particular CorePac without resetting any other chip components.
ADVANCE INFORMATION
Local reset is initiated by the following (for more details see the Phase Locked Loop (PLL) Controller for KeyStone
Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59):
• LRESET pin
• Watchdog Timer should cause one of the below based on the setting of the CORESEL[2:0] and RSTCFG
registers in the PLL controller. See ‘‘Reset Configuration Register (RSTCFG)’’ on page 168 and ‘‘INTC
Registers’’ on page 129.
– Local Reset
– NMI
– NMI followed by a time delay and then a local reset for the core selected
– Hard Reset by requesting reset via PLLCTL
• LPSC MMRs
7.7.5 Reset Priority
If any of the above reset sources occur simultaneously, the PLLCTL processes only the highest priority reset request.
The reset request priorities are as follows (high to low):
• Power-on reset
• Hard/Soft reset
7.7.6 Reset Controller Register
The reset controller register are part of the PLLCTL MMRs. All C6670 device-specific MMRs are covered in Section
7.8.2 ‘‘PLL Controller Memory Map’’ on page 162. For more details on these registers and how to program them,
see the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in ‘‘Related Documentation from Texas
Instruments’’ on page 59.
7.7.7 Reset Electrical Data/Timing
Table 7-44
Reset Timing Requirements (1) (2) (Part 1 of 2)
(see Figure 7-18, Figure 7-19, Figure 7-20 and Figure 7-21)
No.
Min
Max
Unit
POR Pin Reset
1
th(PORL)
Hold Time - POR low after VDDS15 stable and input clocks valid
500C + 100
μs
2
tsu(RESETH-PORH)
Setup Time - RESET high before POR high
500C + 100
μs
2
tsu(RESETFULLH-PORH)
Setup Time - RESETFULLhigh before POR high
500C + 100
μs
RESETFULL Pin Reset
4
td(PORH-RESETFULLL)
Delay Time - POR high before RESETFULL low
500C + 100
μs
5
tw(RESETFULLL)
Pulse Width - Pulse width RESETFULL low
500C + TBD
μs
6
td(RESETH-RESETFULLL)
Delay Time - RESET high before RESETFULL low
500C + 100
μs
Hard-Reset
4
td(PORH-RESETL)
Delay Time - POR high before RESET low
500C + 100
μs
9
tw(RESETL)
Pulse Width - Pulse width RESET low
500C + TBD
μs
6
td(RESETFULLH-RESETL)
Delay Time - RESETFULL high before RESET low
500C + 100
μs
500C + 100
μs
Soft Reset
12
156
td(PORH-RESETL)
Delay Time - POR high before RESET low
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Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
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Table 7-44
Reset Timing Requirements
(1) (2)
(Part 2 of 2)
(see Figure 7-18, Figure 7-19, Figure 7-20 and Figure 7-21)
No.
Min
Max
Unit
13
tw(RESETL)
Pulse Width - Pulse width RESET low
500C + TBD
μs
14
td(RESETFULLH-RESETL)
Delay Time - RESETFULL high before RESET low
500C + 100
μs
End of Table 7-44
1 If CORECLKSEL = 0, C = 1 ÷ CORECLK(N|P) frequency in ns.
2 If CORECLKSEL = 1, C = 1 ÷ ALTCORECLK frequency in ns.
Reset Switching Characteristics Over Recommended Operating Conditions
(see Figure 7-18, Figure 7-19, Figure 7-20 and Figure 7-21)
No.
Parameter
Min
Max
Unit
POR Pin Reset
3
td(PORH-RESETSTATH)
Delay Time - RESETSTAT high after POR high
TBD μs
RESETFULL Pin Reset
7
td(RESETFULLH-RESETSTATH)
Delay Time - RESETSTAT high after RESETFULL high
TBD μs
Hard Reset
11
td(RESETH-RESETSTATH)
Delay Time - RESETSTAT high after RESET high
15
td(RESETH-RESETSTATH)
Delay Time - RESETSTAT high after RESET high
TBD μs
Soft Reset
TBD μs
End of Table 7-45
Figure 7-18
POR Reset Timing
1
2
VDDS15 Stable +
Clocks Valid
(internal signal)
POR
RESET
RESETFULL
3
RESETSTAT
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Table 7-45
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Figure 7-19
www.ti.com
RESETFULL Reset Timing
5
4
6
RESETFULL
RESET
7
RESETSTAT
ADVANCE INFORMATION
POR
Figure 7-20
Hard-Reset Timing
9
8
10
RESET
RESETFULL
11
RESETSTAT
POR
Figure 7-21
Soft-Reset Timing
13
12
14
RESET
RESETFULL
15
RESETSTAT
POR
158
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Table 7-46
Boot Configuration Timing Requirements
(1) (2)
See Figure 7-22)
No.
Min
Max
Unit
1
tsu(GPIOn-POR)
Setup Time - GPIO valid before POR asserted
12C
ns
2
th(POR-GPIOn)
Hold Time - GPIO valid after POR asserted
12C
ns
End of Table 7-46
1 If CORECLKSEL = 0, C = 1 ÷ CORECLK(N|P) frequency in ns.
2 If CORECLKSEL = 1, C = 1 ÷ ALTCORECLK frequency in ns.
Figure 7-22
Boot Configuration Timing
ADVANCE INFORMATION
1
POR
GPIO[15:0]
2
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7.8 Main PLL and the PLL Controller
This section provides a description of the Main PLL and the PLL controller. For details on the operation of the PLL
controller module, see the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 59.
Note—The Main PLL controller registers can be accessed by any master in the device.
ADVANCE INFORMATION
The Main PLL is controlled by the standard PLL controller. The PLL controller manages the clock ratios, alignment,
and gating for the system clocks to the device. Figure 7-23 shows a block diagram of the main PLL controller. The
following paragraphs define the clocks and PLL controller parameters.
Figure 7-23
Main PLL and PLL Controller
AIF Module
Main PLL Controller
SYSCLK(N|P)
xM
/2
REFCLK
ALTCORECLK(N|P)
CORECLKSEL
Main PLL
C66x
CorePac
/x
SYSCLK2
/2
SYSCLK3
/3
SYSCLK4
/y
SYSCLK5
/64
SYSCLK6
/6
SYSCLK7
To Switch Fabric,
Peripherals,
Accelerators
/z
SYSCLK8
/12
SYSCLK9
/3
SYSCLK10
/6
SYSCLK11
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The inputs, multiply factor within the PLL, and post-division for each of the chip-level clocks from the PLL output.
The PLL controller also controls reset propagation through the chip, clock alignment, and test points. The PLL
controller monitors the PLL status and provides an output signal indicating when the PLL is locked.
The minimum SYSCLK rise and fall times should also be observed. For the input clock timing requirements, see
Section 7.8.4 ‘‘Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing’’.
CAUTION—The PLL controller module as described in the see the Phase Locked Loop (PLL) Controller for
KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59 includes a
superset of features, some of which are not supported on the TMS320C6670 device. The following sections
describe the registers that are supported; it should be assumed that any registers not included in these
sections is not supported by the device. Furthermore, only the bits within the registers described here are
supported. Avoid writing to any reserved memory location or changing the value of reserved bits.
7.8.1 Main PLL Controller Device-Specific Information
7.8.1.1 Internal Clocks and Maximum Operating Frequencies
The Main PLL, used to drive the CorePacs, the switch fabric, and a majority of the peripheral clocks (all but the
DDR3 and the PASS modules) requires a PLL controller to manage the various clock divisions, gating, and
synchronization. The Main PLL’s PLL controller has several SYSCLK outputs that are listed below, along with the
clock description. Each SYSCLK has a corresponding divider that divides down the output clock of the PLL. Note
that dividers are not programmable unless explicitly mentioned in the description below.
• REFCLK: Full-rate clock for CorePac 0~CorePac 3 and RSA.
• SYSCLK2: 1/x-rate clock for CorePac (emulation) and the ADTF module. Default rate for this will be 1/3. This
is programmable from /1 to /32, where this clock does not violate the max of 350 MHz. The SYSCLK2 can be
turned off by software.
• SYSCLK3: 1/2-rate clock used to clock the L2/MSMC, TCP3d, HyperLink, CPU/2 SCR, DDR EMIF and
CPU/2 EDMA.
• SYSCLK4: 1/3-rate clock for the switch fabrics and fast peripherals. The Debug_SS and ETBs will use this as
well.
• SYSCLK5: 1/y-rate clock for system trace module only. Default rate for this will be 1/5. It is configurable and
the max configurable clock is 210 MHz and min configuration clock is 32 MHz. The SYSCLK5 can be turned
off by software.
• SYSCLK6: 1/64-rate clock. 1/64 rate clock (emif_ptv) used to clock the PVT compensated buffers for DDR3
EMIF.
• SYSCLK7: 1/6-rate clock for slow peripherals and sources the SYSCLKOUT output pin.
• SYSCLK8: 1/z-rate clock. This clock is used as slow_sysclck in the system. Default for this will be 1/64. This is
programmable from /24 to /80.
• SYSCLK9: 1/12-rate clock for SmartReflex.
• SYSCLK10: 1/3-rate clock for SRIO only.
• SYSCLK11: 1/6-rate clock for PSC only.
Only SYSCLK2, SYSCLK5, and SYSCLK8 are programmable on TMS320C6670 device.
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ADVANCE INFORMATION
Main PLL power is supplied externally via the Main PLL power-supply pin (AVDDA1). An external EMI filter
circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone Devices in ‘‘Related
Documentation from Texas Instruments’’ on page 59 for detailed recommendations. For the best performance, TI
recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than those shown. For reduced PLL jitter, maximize the spacing between switching signal traces
and the PLL external components (C1, C2, and the EMI Filter).
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
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Note—In case any of the other programmable SYSCLKs are set slower than 1/64 rate, then SYSCLK8
(SLOW_SYSCLK) needs to be programmed to either match, or be slower than, the slowest SYSCLK in the
system.
7.8.1.2 Main PLL Controller Operating Modes
The Main PLL controller has two modes of operation: bypass mode and PLL mode. The mode of operation is
determined by the PLLEN bit of the PLL control register (PLLCTL). In PLL mode, REFCLK is generated from the
PLL output using the divider POSTDIV and the PLL multiplier PLLM. In bypass mode, PLL output is fed directly
to REFCLK.
ADVANCE INFORMATION
All hosts must hold off accesses to the DSP while the frequency of its internal clocks is changing. A mechanism must
be in place such that the DSP notifies the host when the PLL configuration has completed.
7.8.1.3 Main PLL Stabilization, Lock, and Reset Times
The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to become
stable after device powerup. The PLL should not be operated until this stabilization time has expired.
The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in order for the
PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the Main PLL reset time value,
see Table 7-47.
The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1 with
PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). The Main PLL lock time
is given in Table 7-47.
Table 7-47
Main PLL Stabilization, Lock, and Reset Times
Min
PLL stabilization time
Max
100
Unit
μs
2000 × C (1)
PLL lock time
PLL reset time
Typ
1000
ns
End of Table 7-47
1 C = SYSCLK(N|P) cycle time in ns.
7.8.2 PLL Controller Memory Map
The memory map of the PLL controller is shown in Table 7-48. TMS320C6670 specific PLL Controller register
definitions can be found in the sections following the Table 7-48, for other registers in the table, see the Phase Locked
Loop (PLL) Controller for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on
page 59.
CAUTION—Note that only registers documented here are accessible on the TMS320C6670. Other addresses
in the PLL controller memory map including the reserved registers should not be modified. Furthermore,
only the bits within the registers described here are supported. Avoid writing to any reserved memory
location or changing the value of reserved bits. It is recommended to use read-modify-write sequence to
make any changes to the valid bits in the register.
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PLL Controller Registers (Including Reset Controller)
Hex Address Range
Acronym
0231 0000 - 0231 00E3
-
Register Name
Reserved
0231 00E4
RSTYPE
Reset Type Status Register (Reset Controller)
0231 00E8
RSTCTRL
Software Reset Control Register (Reset Controller)
0231 00EC
RSTCFG
Reset Configuration Register (Reset Controller)
0231 00F0
RSISO
0231 00F0 - 0231 00FF
-
0231 0100
PLLCTL
0231 0104
-
0231 0108
SECCTL
0231 010C
-
0231 0110
PLLM
Reset isolation register (Reset Controller)
Reserved
PLL Control Register
ADVANCE INFORMATION
Table 7-48
Reserved
PLL Secondary Control Register
Reserved
PLL Multiplier Control Register
0231 0114
PREDIV
PLL pre-divider control register
0231 0118
PLLDIV1
Reserved
0231 011C
PLLDIV2
PLL controller divider 2 register
0231 0120
PLLDIV3
Reserved
0231 0124
-
Reserved
0231 0128
POSTDIV
PLL Post-Divider Register
0231 012C - 0231 0134
-
0231 0138
PLLCMD
Reserved
0231 013C
PLLSTAT
PLL Controller Status Register
0231 0140
ALNCTL
PLL Controller Clock Align Control Register
0231 0144
DCHANGE
0231 0148
CKEN
Reserved
0231 014C
CKSTAT
Reserved
0231 0150
SYSTAT
SYSCLK Status Register
PLL Controller Command Register
PLLDIV Ratio Change Status Register
0231 0154 - 0231 015C
-
Reserved
0231 0160
PLLDIV4
Reserved
0231 0164
PLLDIV5
PLL Controller Divider 5 Register
0231 0168
PLLDIV6
Reserved
0231 016C
PLLDIV7
Reserved
0231 0170
PLLDIV8
PLL Controller Divider 8 Register
0231 0174 - 0231 0193
PLLDIV9 - PLLDIV16
Reserved
0231 0194 - 0231 01FF
-
Reserved
End of Table 7-48
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7.8.2.1 PLL Secondary Control Register (SECCTL)
The PLL Secondary Control Register contains extra fields to control the Main PLL and is shown in Figure 7-24 and
described in Table 7-49.
Figure 7-24
PLL Secondary Control Register (SECCTL))
31
24
23
Reserved
BYPASS
R-0000 0000
RW-0
22
21
20
19
18
OUTPUT_DIVIDE
RW-0
RW-0
0
Reserved
RW-0
RW-1
RW-001 0000 0000 0000 0000
Legend: R/W = Read/Write; R = Read only; -n = value after reset
ADVANCE INFORMATION
Table 7-49
PLL Secondary Control Register (SECCTL) Field Descriptions
Bit
Field
Description
31-24
Reserved
Reserved
23
BYPASS
22-19
OUTPUT_DIVIDE
Output Divider ratio bits.
0h = ÷1. Divide frequency by 1.
1h = ÷2. Divide frequency by 2.
2h = ÷3. Divide frequency by 3.
3h = ÷4. Divide frequency by 4.
4h - Fh = ÷5 to ÷16. Divide frequency by 5 to divide frequency by 80.
18-0
Reserved
Reserved
Main PLL Bypass Enable
0 = Main PLL Bypass disabled
1 = Main PLL Bypass enabled
End of Table 7-49
7.8.2.2 PLL Controller Divider Register (PLLDIV2, PLLDIV5, PLLDIV8)
The PLL controller divider registers (PLLDIV2, PLLDIV5, PLLDIV8) are shown in Figure 7-25 and described in
Table 7-50. The default values of the RATIO field on a reset for PLLDIV2, PLLDIV5, and PLLDIV8 are different and
mentioned in the footnote of Figure 7-25.
Figure 7-25
PLL Controller Divider Register (PLLDIVn)
31
16
Reserved
15
Dn
R-0
(1)
14
EN
R/W-1
8
7
0
Reserved
RATIO
R-0
R/W-n (2)
Legend: R/W = Read/Write; R = Read only; -n = value after reset
1 D2EN for PLLDIV2; D5EN for PLLDIV5; D8EN for PLLDIV8
2 n=02h for PLLDIV2; n=04h for PLLDIV5; n=3Fh for PLLDIV8
Table 7-50
PLL Controller Divider Register (PLLDIVn) Field Descriptions
Bit
Field
Description
31-16
Reserved
Reserved.
15
DnEN
Divider Dn enable bit. (see footnote of Figure 7-25)
0 = Divider n is disabled.
1 = No clock output. Divider n is enabled.
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Multicore Fixed and Floating-Point System-on-Chip
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Table 7-50
PLL Controller Divider Register (PLLDIVn) Field Descriptions
Bit
Field
Description
14-8
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
7-0
RATIO
Divider ratio bits. (see footnote of Figure 7-25)
0h = ÷1. Divide frequency by 1.
1h = ÷2. Divide frequency by 2.
2h = ÷3. Divide frequency by 3.
3h = ÷4. Divide frequency by 4.
4h - 4Fh = ÷5 to ÷80. Divide frequency by 5 to divide frequency by 80.
ADVANCE INFORMATION
End of Table 7-50
7.8.2.3 PLL Controller Clock Align Control Register (ALNCTL)
The PLL controller clock align control register (ALNCTL) is shown in Figure 7-26 and described in Table 7-51.
Figure 7-26
PLL Controller Clock Align Control Register (ALNCTL)
31
8
7
6
5
4
3
2
1
0
Reserved
ALN8
Reserved
ALN5
Reserved
ALN2
Reserved
R-0
R/W-1
R-0
R/W-1
R-0
R/W-1
R-0
Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value
Table 7-51
Bit
PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
Field
Description
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
7
ALN8
4
ALN5
1
ALN2
SYSCLKn alignment. Do not change the default values of these fields.
0 = Do not align SYSCLKn to other SYSCLKs during GO operation. If SYSn in DCHANGE is set, SYSCLKn switches to the new
ratio immediately after the GOSET bit in PLLCMD is set.
1 = Align SYSCLKn to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set and SYSn in DCHANGE is 1.
The SYSCLKn rate is set to the ratio programmed in the RATIO bit in PLLDIVn.
31-8
6-5
3-2
0
End of Table 7-51
7.8.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
Whenever a different ratio is written to the PLLDIVn registers, the PLLCTL flags the change in the DCHANGE
status register. During the GO operation, the PLL controller will change only the divide ratio of the SYSCLKs with
the bit set in DCHANGE. Note that the ALNCTL register determines if that clock also needs to be aligned to other
clocks. The PLLDIV divider ratio change status register is shown in Figure 7-27 and described in Table 7-52.
Figure 7-27
PLLDIV Divider Ratio Change Status Register (DCHANGE)
31
8
7
6
5
4
3
2
1
0
Reserved
SYS8
Reserved
SYS5
Reserved
SYS2
Reserved
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
R-0
Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value
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Table 7-52
Bit
www.ti.com
PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions
Field
Description
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
7
SYS8
4
SYS5
1
SYS2
Identifies when the SYSCLKn divide ratio has been modified.
0 = SYSCLKn ratio has not been modified. When GOSET is set, SYSCLKn will not be affected.
1 = SYSCLKn ratio has been modified. When GOSET is set, SYSCLKn will change to the new ratio.
31-8
6-5
3-2
0
End of Table 7-52
ADVANCE INFORMATION
7.8.2.5 SYSCLK Status Register (SYSTAT)
The SYSCLK status register (SYSTAT) shows the status of SYSCLK[11:1]. SYSTAT is shown in Figure 7-28 and
described in Table 7-53.
Figure 7-28
SYSCLK Status Register (SYSTAT)
31
11
10
Reserved
9
SYS11ON SYS10ON
R-n
R-1
8
7
6
5
4
3
2
1
0
SYS9ON
SYS8ON
SYS7ON
SYS6ON
SYS5ON
SYS4ON
SYS3ON
SYS2ON
SYS1ON
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
Legend: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-53
SYSCLK Status Register (SYSTAT) Field Descriptions
Bit
Field
31-11
Reserved
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
(1)
SYS[N ]ON
10-0
SYSCLK[N] on status.
0 = SYSCLK[N] is gated.
1 = SYSCLK[N] is on.
End of Table 7-53
1 Where N = 1, 2, 3,....N (Not all these output clocks may be used on a specific device. For more information, see the device-specific data manual)
7.8.2.6 Reset Type Status Register (RSTYPE)
The reset type status (RSTYPE) register latches the cause of the last reset. If multiple reset sources occur
simultaneously, this register latches the highest priority reset source. The Reset Type Status register is shown in
Figure 7-29 and described in Table 7-54.
Figure 7-29
31
Reset Type Status Register (RSTYPE)
29
28
27
12
11
8
7
3
2
1
0
Reserved
EMU-RST
Reserved
WDRST[N]
Reserved
PLLCTRLRST
RESET
POR
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
Legend: R = Read only; -n = value after reset
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Multicore Fixed and Floating-Point System-on-Chip
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Bit
Reset Type Status Register (RSTYPE) Field Descriptions
Field
Description
31-29
Reserved
Reserved. Read only. Always reads as 0. Writes have no effect.
28
EMU-RST
Reset initiated by emulation.
0 = Not the last reset to occur.
1 = The last reset to occur.
27-12
Reserved
Reserved. Read only. Always reads as 0. Writes have no effect.
11
WDRST3
10
WDRST2
9
WDRST1
Reset initiated by Watchdog Timer[N].
0 = Not the last reset to occur.
1 = The last reset to occur.
8
WDRST0
7-3
Reserved
Reserved. Read only. Always reads as 0. Writes have no effect.
2
PLLCTLRST
Reset initiated by PLLCTL.
0 = Not the last reset to occur.
1 = The last reset to occur.
1
RESET
RESET reset.
0 = RESET was not the last reset to occur.
1 = RESET was the last reset to occur.
0
POR
Power-on reset.
0 = Power-on reset was not the last reset to occur.
1 = Power-on reset was the last reset to occur.
End of Table 7-54
7.8.2.7 Reset Control Register (RSTCTRL)
This register contains a key that enables writes to the MSB of this register and the RSTCFG register. The key value
is 0x5A69. A valid key will be stored as 0x000C, any other key value is invalid. When the RSTCTRL or the RSTCFG
is written, the key is invalidated. Every write must be set up with a valid key. The Software Reset Control register
(RSTCTRL) is shown in Figure 7-30 and described in Table 7-55.
Figure 7-30
Reset Control Register (RSTCTRL)
31
17
Reserved
R-0x0000
16
15
SWRST
R/W-0x
(1)
0
KEY
R/W-0x0003
Legend: R = Read only; -n = value after reset;
1 Writes are conditional based on valid key.
Table 7-55
Reset Control Register (RSTCTRL) Field Descriptions
Bit
Field
Description
31-17
Reserved
Reserved.
16
SWRST
Software reset
0 = Reset
1 = Not reset
15-0
KEY
Key used to enable writes to RSTCTRL and RSTCFG.
End of Table 7-55
Copyright 2010 Texas Instruments Incorporated
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167
ADVANCE INFORMATION
Table 7-54
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
7.8.2.8 Reset Configuration Register (RSTCFG)
This register is used to configure the type of reset initiated by RESET, Watchdog Timer and the PLL controller’s
RSTCTRL register; i.e., a Hard reset or a Soft reset. By default, these resets will be Hard resets. The Reset
Configuration register (RSTCFG) is shown in Figure 7-31 and described in Table 7-56.
Figure 7-31
Reset Configuration Register (RSTCFG)
31
16
15
Reserved
14
13
Reserved
R-0x0000
12
PLLCTLRSTTYPE
R-00
R/W-0
(2)
11
RESETTYPE
R/W-0
4
3
Reserved
2
0
(1)
WDTYPE[N
]
2
R-0x0
R/W-0x00
Legend: R = Read only; R/W = Read/Write; -n = value after reset
ADVANCE INFORMATION
1 Where N = 1, 2, 3,....N (Not all these output may be used on a specific device. For more information, see the device-specific data manual)
2 Writes are conditional based on valid key. For details, see Section 7.8.2.7 ‘‘Reset Control Register (RSTCTRL)’’.
Table 7-56
Reset Configuration Register (RSTCFG) Field Descriptions
Bit
Acronym
Description
31-14
Reserved
Reserved.
13
PLLCTLRSTTYPE
PLL controller initiates a software-driven reset of type:
0 = Hard reset (default)
1 = Soft reset
12
RESETTYPE
RESET initiates a reset of type:
0 = Hard Reset (default)
1 = Soft Reset
11-4
Reserved
Reserved.
3
WDTYPE3
2
WDTYPE2
1
WDTYPE1
Watchdog Timer [N] initiates a reset of type:
0 = Hard Reset (default)
1 = Soft Reset
0
WDTYPE0
End of Table 7-56
7.8.2.9 Reset Isolation Register (RSISO)
This register is used to select the module clocks that must maintain their clocking without pausing through non
Power-on reset. Setting any of these bits effectively blocks reset to all PLLCTL registers in order to maintain current
values of PLL multiplier, divide ratios and other settings. The Reset Isolation register (RSTCTRL) is shown in
Figure 7-32 and described in Table 7-57.
Figure 7-32
Reset Isolation Register (RSISO)
31
9
8
Reserved
16
15
Reserved
10
SRIOISO
SRISO
7
Reserved
4
AIF2ISO
3
Reserved
2
0
R-0x0000
R-0x00
R/W-0
R/W-0
R-0x0
R/W-0
R-000
Legend: R = Read only; R/W = Read/Write; -n = value after reset
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Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
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Bit
Reset Isolation Register (RSISO) Field Descriptions
Acronym
Description
31-10
Reserved
Reserved.
9
SRIOISO
Isolate SRIO module
0 = Not reset isolated
1 = Reset Isolated
8
SRISO
Isolate SmartReflex
0 = Not reset isolated
1 = Reset Isolated
7-4
Reserved
Reserved.
3
AIF2ISO
Isolate AIF2 module
0 = Not reset isolated
1 = Reset isolated
2-0
Reserved
Reserved.
End of Table 7-57
7.8.3 Main PLL Control Register
The Main PLL uses a chip-level register (MAINPLLCTL) along with the PLL controller for its configuration. This
MMR exists inside the Bootcfg space. To write to this register, software should go through an un-locking sequence
using KICK0/KICK1 registers. For valid configurable values into the MAINPLLCTL register see Section 2.5.3 ‘‘PLL
Settings’’ on page 33. See 3.3.4 ‘‘Kicker Mechanism (KICK0 and KICK1) Register’’ on page 65 for the address
location of the registers and locking and unlocking sequences for accessing the registers. This register is reset on
POR only.
Figure 7-33
Main PLL Control Register (MAINPLLCTL)
31
24
23
19
18
12
11
6
5
0
BWADJ[7:0]
Reserved
PLLM[12:6]
Reserved
PLLD
RW,+0000 0101
RW - 0000 0
RW,+0000000
RW, +000000
RW,+000000
Legend: RW = Read/Write; -n = value after reset
Table 7-58
Bit
Main PLL Control Register Field Descriptions
Field
Description
31-24
BWADJ[7:0]
BWADJ should be programmed to a value equal to half of PLLM[12:0]
23-19
Reserved
Reserved
18-12
PLLM[12:6]
A 13-bit bus that selects the values for the multiplication factor (see Note below)
11-6
Reserved
Reserved
5-0
PLLD
A 6-bit bus that selects the values for the reference divider
End of Table 7-58
Note—PLLM[5:0] bits of the multiplier is controlled by the PLLM register inside the PLL controller and
PLLM[12:6] bits are controlled by the above chip level register. MAINPLLCTL register PLLM[12:6] bits
should be written just before writing to PLLM register PLLM[5:0] bits in the controller to have the complete
13 bit value latched when the GO operation is initiated in the PLL controller. See the Phase Locked Loop
(PLL) Controller for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on
Copyright 2010 Texas Instruments Incorporated
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169
ADVANCE INFORMATION
Table 7-57
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
page 59 for the recommended programming sequence. Output Divide ratio and Bypass enable/disable of the
Main PLL is controlled by the SECCTL register in the PLL Controller. See the Phase Locked Loop (PLL)
Controller for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on
page 59 for more details.
7.8.4 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing
Table 7-59
Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements (1) (Part 1 of 2)
(see Figure 7-34 and Figure 7-35)
No.
Min
Max
Unit
SYSCLK[P:N]
ADVANCE INFORMATION
Cycle Time _ SYSCLKN cycle time
3.25 or 6.51 or 8.138 (2)
tc(SYSCLKP)
Cycle Time _ SYSCLKP cycle time
3.25 or 6.51 or 8.138
tw(SYSCLKN)
Pulse Width _ SYSCLKN high
0.45*tc
0.55*tc
2
tw(SYSCLKN)
Pulse Width _ SYSCLKN low
0.45*tc
0.55*tc
ns
2
tw(SYSCLKP)
Pulse Width _ SYSCLKP high
0.45*tc
0.55*tc
ns
3
tw(SYSCLKP)
Pulse Width _ SYSCLKP low
0.45*tc
0.55*tc
ns
4
tr(SYSCLKN_250mv)
Transition Time _ SYSCLKN Rise time (250mV)
50
350
ps
4
tf(SYSCLKN_250mv)
Transition Time _ SYSCLKN Fall time (250mV)
50
350
ps
4
tr(SYSCLKP_250mv)
Transition Time _ SYSCLKP Rise time (250mV)
50
350
ps
4
tf(SYSCLKP_250mv)
Transition Time _ SYSCLKP Fall time (250mV)
50
350
ps
5
tj(SYSCLKN)
Jitter, Peak_to_Peak _ Periodic SYSCLKN
100
ps
5
tj(SYSCLKP)
Jitter, Peak_to_Peak _ Periodic SYSCLKP
100
ps
1
tc(SYSCLKN)
1
3
ns
ns
ns
ALTCORECLK[P:N]
1
tc(ALTCORCLKN)
Cycle Time _ ALTCORECLKN cycle time
3.2
25
ns
1
tc(ALTCORECLKP)
Cycle Time _ ALTCORECLKP cycle time
3.2
25
ns
3
tw(ALTCORECLKN)
Pulse Width _ ALTCORECLKN high
0.45*tc(ALTCORECLKN)
0.55*tc(ALTCORECLKN)
ns
2
tw(ALTCORECLKN)
Pulse Width _ ALTCORECLKN low
0.45*tc(ALTCORECLKN)
0.55*tc(ALTCORECLKN)
ns
2
tw(ALTCORECLKP)
Pulse Width _ ALTCORECLKP high
0.45*tc(ALTCORECLKP)
0.55*tc(ALTCORECLKP)
ns
3
tw(ALTCORECLKP)
Pulse Width _ ALTCORECLKP low
0.45*tc(ALTCORECLKP)
0.55*tc(ALTCORECLKP)
ns
4
tr(ALTCORECLKN_250mv)
Transition Time _ ALTCORECLKN Rise time
(250mV)
50
350
ps
4
tf(ALTCORECLKN_250mv)
Transition Time _ ALTCORECLKN Fall time (250mV)
50
350
ps
4
tr(ALTCORECLKP_250mv)
Transition Time _ ALTCORECLKP Rise time
(250mV)
50
350
ps
4
tf(ALTCORECLKP_250mv)
Transition Time _ ALTCORECLKP Fall time (250mV)
50
350
ps
5
tj(ALTCORECLKN)
Jitter, Peak_to_Peak _ Periodic ALTCORECLKN
100
ps
5
tj(ALTCORECLKP)
Jitter, Peak_to_Peak _ Periodic ALTCORECLKP
100
ps
SRIOSGMIICLK[P:N]
1
tc(SRIOSMGMIICLKN)
Cycle Time _ SRIOSMGMIICLKN cycle time
3.2 or 4 or 6.4
ns
1
tc(SRIOSMGMIICLKP)
Cycle Time _ SRIOSMGMIICLKP cycle time
3.2 or 4 or 6.4
ns
3
tw(SRIOSMGMIICLKN)
Pulse Width _ SRIOSMGMIICLKN high
0.45*tc(SRIOSGMIICLKN) 0.55*tc(SRIOSGMIICLKN)
ns
2
tw(SRIOSMGMIICLKN)
Pulse Width _ SRIOSMGMIICLKN low
0.45*tc(SRIOSGMIICLKN) 0.55*tc(SRIOSGMIICLKN)
ns
2
tw(SRIOSMGMIICLKP)
Pulse Width _ SRIOSMGMIICLKP high
0.45*tc(SRIOSGMIICLKP) 0.55*tc(SRIOSGMIICLKP)
ns
3
tw(SRIOSMGMIICLKP)
Pulse Width _ SRIOSMGMIICLKP low
0.45*tc(SRIOSGMIICLKP) 0.55*tc(SRIOSGMIICLKP)
ns
4
tr(SRIOSMGMIICLKN_250mv) Transition Time _ SRIOSMGMIICLKN Rise time
(250mV)
50
350
ps
4
tf(SRIOSMGMIICLKN_250mv) Transition Time _ SRIOSMGMIICLKN Fall time
(250mV)
50
350
ps
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Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Table 7-59
Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements
(1)
(Part 2 of 2)
(see Figure 7-34 and Figure 7-35)
Min
Max
Unit
4
tr(SRIOSMGMIICLKP_250mv) Transition Time _ SRIOSMGMIICLKP Rise time
(250mV)
50
350
ps
4
tf(SRIOSMGMIICLKP_250mv) Transition Time _ SRIOSMGMIICLKP Fall time
(250mV)
50
350
ps
5
tj(SRIOSMGMIICLKN)
Jitter, Peak_to_Peak _ Periodic SRIOSMGMIICLKN
4 ps,RMS
5
tj(SRIOSMGMIICLKP)
Jitter, Peak_to_Peak _ Periodic SRIOSMGMIICLKP
4 ps,RMS
5
tj(SRIOSMGMIICLKN)
Jitter, Peak_to_Peak _ Periodic SRIOSMGMIICLKN
(SRIO Not Used)
8 ps,RMS
5
tj(SRIOSMGMIICLKP)
Jitter, Peak_to_Peak _ Periodic SRIOSMGMIICLKP
(SRIO Not Used)
8 ps,RMS
1
tc(MCMCLKN)
Cycle Time _ MCMCLKN cycle time
HyperLink CLK[P:N]
3.2 or 4 or 6.4
ns
3.2 or 4 or 6.4
ns
1
tc(MCMCLKP)
Cycle Time _ MCMCLKP cycle time
3
tw(MCMCLKN)
Pulse Width _ MCMCLKN high
0.45*tc(MCMCLKN)
0.55*tc(MCMCLKN)
2
tw(MCMCLKN)
Pulse Width _ MCMCLKN low
0.45*tc(MCMCLKN)
0.55*tc(MCMCLKN)
ns
2
tw(MCMCLKP)
Pulse Width _ MCMCLKP high
0.45*tc(MCMCLKP)
0.55*tc(MCMCLKP)
ns
3
tw(MCMCLKP)
Pulse Width _ MCMCLKP low
0.45*tc(MCMCLKP)
0.55*tc(MCMCLKP)
ns
4
tr(MCMCLKN_250mv)
Transition Time _ MCMCLKN Rise time (250 mV)
50
350
ps
4
tf(MCMCLKN_250mv)
Transition Time _ MCMCLKN Fall time (250 mV)
50
350
ps
4
tr(MCMCLKP_250mv)
Transition Time _ MCMCLKP Rise time (250 mV)
50
350
ps
4
tf(MCMCLKP_250mv)
Transition Time _ MCMCLKP Fall time (250 mV)
50
350
ps
5
tj(MCMCLKN)
Jitter, Peak_to_Peak _ Periodic MCMCLKN
4 ps,RMS
5
tj(MCMCLKP)
Jitter, Peak_to_Peak _ Periodic MCMCLKP
4 ps,RMS
ns
PCIECLK[P:N]
1
tc(PCIECLKN)
Cycle Time _ PCIECLKN cycle time
3.2 or 4 or 6.4 or 10
ns
1
tc(PCIECLKP)
Cycle Time _ PCIECLKP cycle time
3.2 or 4 or 6.4 or 10
ns
3
tw(PCIECLKN)
Pulse Width _ PCIECLKN high
0.45*tc(PCIECLKN)
0.55*tc(PCIECLKN)
ns
2
tw(PCIECLKN)
Pulse Width _ PCIECLKN low
0.45*tc(PCIECLKN)
0.55*tc(PCIECLKN)
ns
2
tw(PCIECLKP)
Pulse Width _ PCIECLKP high
0.45*tc(PCIECLKP)
0.55*tc(PCIECLKP)
ns
3
tw(PCIECLKP)
Pulse Width _ PCIECLKP low
0.45*tc(PCIECLKP)
0.55*tc(PCIECLKP)
ns
4
tr(PCIECLKN_250mv)
Transition Time _ PCIECLKN Rise time (250 mV)
50
350
ps
4
tf(PCIECLKN_250mv)
Transition Time _ PCIECLKN Fall time (250 mV)
50
350
ps
4
tr(PCIECLKP_250mv)
Transition Time _ PCIECLKP Rise time (250 mV)
50
350
ps
4
tf(PCIECLKP_250mv)
Transition Time _ PCIECLKP Fall time (250 mV)
50
350
ps
5
tj(PCIECLKN)
Jitter, Peak_to_Peak _ Periodic PCIECLKN
4 ps,RMS
5
tj(PCIECLKP)
Jitter, Peak_to_Peak _ Periodic PCIECLKP
4 ps,RMS
End of Table 7-59
1 If CORECLKSEL = 0, C = 1/SYSCLK(NIP) frequency, in ns. If CORECLKSEL = 1, C = 1/ALTCORECLK frequency, in ns.
2 If AIF2 is being used then SYSCLK(N|P) can only be programmed to fixed values, if AIF2 is not being used then any value in the range between the min and max values can be
used.
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No.
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Figure 7-34
www.ti.com
Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing
1
2
3
<CLK_NAME>CLKN
<CLK_NAME>CLKP
4
Figure 7-35
5
Main PLL Transition Time
ADVANCE INFORMATION
peak-to-peak differential input
voltage (250 mV to 2 V)
0
250 mV peak-to-peak
TR = 50 ps min to 350 ps max (10% to 90 %)
for the 250 mV peak-to-peak centered at zero crossing
172
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Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
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7.9 DDR3 PLL
The DDR3 PLL generates interface clocks for the DDR3 memory controller. When coming out of power-on reset,
DDR3 PLL is programmed to a valid frequency during the boot config before being enabled and used.
Figure 7-36
DDR3 PLL Block Diagram
DDR3 PLL
DDRCLK(N|P)
/2
PLLOUT
DDR3
PHY
xPLLM
7.9.1 DDR3 PLL Control Register
The DDR3 PLL, which is used to drive the DDR PHY for the EMIF, does not use a PLL controller. DDR3 PLL can
be controlled using the DDR3PLLCTL register located in the Bootcfg module. This MMR exists inside the Bootcfg
space. To write to this register, software should go through an un-locking sequence using KICK0/KICK1 registers.
For suggested configurable values see 2.5.3 ‘‘PLL Settings’’ on page 33. See 3.3.4 ‘‘Kicker Mechanism (KICK0 and
KICK1) Register’’ on page 65 for the address location of the registers and locking and unlocking sequences for
accessing the registers. This register is reset on POR only
.
DDR3 PLL Control Register (DDR3PLLCTL) (1)
Figure 7-37
31
24
23
22
19
18
6
5
0
Reserved
BYPASS
Reserved
PLLM
PLLD
RW,+0000 1001
RW,+0
RW,+0001
RW,+0000000010011
RW,+000000
Legend: RW = Read/Write; -n = value after reset
1 This register is Reset on POR only. The regreset, reset and bgreset from PLL are all tied to a common pll0_ctrl_rst_n The pwrdn, regpwrdn, bgpwrdn are all tied to common
pll0_ctrl_to_pll_pwrdn.
Table 7-60
Bit
DDR3 PLL Control Register Field Descriptions
Field
Description
31-24
Reserved
Reserved
23
BYPASS
Enable Bypass Mode
0 = Bypass Disabled
1 = Bypass Enabled
22-19
Reserved
Reserved
18-6
PLLM
A 13-bit bus that selects the values for the multiplication factor (see Note below)
5-0
PLLD
A 6-bit bus that selects the values for the reference divider
End of Table 7-60
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ADVANCE INFORMATION
DDR3 PLL power is supplied externally via the Main PLL power-supply pin (AVDDA2). An external EMI filter
circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone Devices in ‘‘Related
Documentation from Texas Instruments’’ on page 59 for detailed recommendations. For the best performance, TI
recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than those shown. For reduced PLL jitter, maximize the spacing between switching signal traces
and the PLL external components (C1, C2, and the EMI Filter).
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
7.9.2 DDR3 PLL Device-Specific Information
As shown in Figure 7-36, the output of DDR3 PLL (PLLOUT) is divided by 2 and directly fed to the DDR3 memory
controller. The DDR3 PLL is affected by power-on reset. During power-on resets, the internal clocks of the DDR3
PLL are affected as described in Section 7.7 ‘‘Reset Controller’’ on page 153. DDR3 PLL is unlocked only during the
power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any of the
other resets.
7.9.3 DDR3 PLL Input Clock Electrical Data/Timing
Table 7-61
DDR3 PLL DDRREFCLK(N|P) Timing Requirements
(see Figure 7-38 and Figure 7-35)
ADVANCE INFORMATION
No.
Min
Max
Unit
3.2
25
ns
DDRCLK[P:N]
1
tc(DDRCLKN)
Cycle Time _ DDRCLKN cycle time
1
tc(DDRCLKP)
Cycle Time _ DDRCLKP cycle time
3.2
25
ns
3
tw(DDRCLKN)
Pulse Width _ DDRCLKN high
0.45*tc(DDRCLKN)
0.55*tc(DDRCLKN)
ns
2
tw(DDRCLKN)
Pulse Width _ DDRCLKN low
0.45*tc(DDRCLKN)
0.55*tc(DDRCLKN)
ns
2
tw(DDRCLKP)
Pulse Width _ DDRCLKP high
0.45*tc(DDRCLKP)
0.55*tc(DDRCLKP)
ns
3
tw(DDRCLKP)
Pulse Width _ DDRCLKP low
0.45*tc(DDRCLKP)
0.55*tc(DDRCLKP)
ns
4
tr(DDRCLKN_250mv)
Transition Time _ DDRCLKN Rise time (250mV)
50
350
ps
4
tf(DDRCLKN_250mv)
Transition Time _ DDRCLKN Fall time (250mV)
50
350
ps
4
tr(DDRCLKP_250mv)
Transition Time _ DDRCLKP Rise time (250mV)
50
350
ps
4
tf(DDRCLKP_250mv)
Transition Time _ DDRCLKP Fall time (250mV)
50
350
ps
5
tj(DDRCLKN)
Jitter, Peak_to_Peak _ Periodic DDRCLKN
0.025*tc(DDRCLKN)
ps
5
tj(DDRCLKP)
Jitter, Peak_to_Peak _ Periodic DDRCLKP
0.025*tc(DDRCLKN)
ps
End of Table 7-61
Figure 7-38
DDR3 PLL DDRCLK Timing
1
2
3
DDRCLKN
DDRCLKP
4
5
7.10 PASS PLL
The PASS PLL generates interface clocks for the Packet Accelerator Subsystem. Using the PACLKSEL pin the user
can select the input source of PASS PLL as either the output of Main PLL mux or the PASSCLK clock reference
sources. When coming out of power-on reset, PASS PLL comes out in a bypass mode and needs to be programmed
to a valid frequency before being enabled and used.
PASS PLL power is supplied externally via the Main PLL power-supply pin (AVDDA3). An external EMI filter
circuit must be added to all PLL supplies. Please see the Hardware Design Guide for KeyStone Devices in ‘‘Related
Documentation from Texas Instruments’’ on page 59 for detailed recommendations. For the best performance, TI
recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than those shown. For reduced PLL jitter, maximize the spacing between switching signal traces
and the PLL external components (C1, C2, and the EMI Filter).
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SPRS689—November 2010
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Figure 7-39
PASS PLL Block Diagram
SYSCLK(P|N)
REFCLK
Main PLL and
PLL Controller
ALTCORECLK(P|N)
CORECLKSEL
PASS PLL
/2
PLLOUT
Packet
Accelerator
PASSCLK(P|N)
7.10.1 PASS PLL Control Register
The PASS PLL, which is used to drive the Packet Accelerator Sub-System, does not use a PLL controller. PASS PLL
can be controlled using the PAPLLCTL register located in Bootcfg module. This MMR exists inside the Bootcfg
space. To write to this register, software should go through an un-locking sequence using KICK0/KICK1 registers.
For suggested configurable values see 2.5.3 ‘‘PLL Settings’’ on page 33. See 3.3.4 ‘‘Kicker Mechanism (KICK0 and
KICK1) Register’’ on page 65 for the address location of the registers and locking and unlocking sequences for
accessing the registers. This register is reset on POR only
.
PASS PLL Control Register (PASSPLLCTL) (1)
Figure 7-40
31
24
23
22
19
18
6
5
0
Reserved
BYPASS
Reserved
PLLM
PLLD
RW,+0000 1001
RW,+0
RW,+0001
RW,+0000000010011
RW,+000000
Legend: RW = Read/Write; -n = value after reset
1 This register is Reset on POR only. The regreset, reset, and bgreset from PLL are all tied to a common pll0_ctrl_rst_n. The pwrdn, regpwrdn, and bgpwrdn are all tied to
common pll0_ctrl_to_pll_pwrdn.
Table 7-62
Bit
PASS PLL Control Register Field Descriptions
Field
Description
31-24
Reserved
Reserved
23
BYPASS
Enable Bypass Mode
0 = Bypass Disabled
1 = Bypass Enabled
22-19
Reserved
Reserved
18-6
PLLM
A 13-bit bus that selects the values for the multiplication factor (see Note below)
5-0
PLLD
A 6-bit bus that selects the values for the reference divider
End of Table 7-62
7.10.2 PASS PLL Device-Specific Information
As shown in Figure 7-39, the output of PASS PLL (PLLOUT) is divided by 2 and directly fed to the Packet
Accelerator Sub-System. The PASS PLL is affected by power-on reset. During power-on resets, the internal clocks
of the PASS PLL are affected as described in Section 7.7 ‘‘Reset Controller’’ on page 153. PASS PLL is unlocked only
during the power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during
any of the other resets.
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xPLLM
PACLKSEL
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Multicore Fixed and Floating-Point System-on-Chip
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7.10.3 PASS PLL Input Clock Electrical Data/Timing
Table 7-63
PASS PLL Timing Requirments
(See Figure 7-41 and Figure 7-35)
No.
Parameter
Min
Max
3.2
25
Unit
PASSCLK[P:N]
1
tc(PASSCLKN)
Cycle Time _ PASSCLKN cycle time
ns
1
tc(PASSCLKP)
Cycle Time _ PASSCLKP cycle time
3.2
25
ns
3
tw(PASSCLKN)
Pulse Width _ PASSCLKN high
0.45*tc(PASSCLKN)
0.55*tc(PASSCLKN)
ns
ADVANCE INFORMATION
2
tw(PASSCLKN)
Pulse Width _ PASSCLKN low
0.45*tc(PASSCLKN)
0.55*tc(PASSCLKN)
ns
2
tw(PASSCLKP)
Pulse Width _ PASSCLKP high
0.45*tc(PASSCLKP)
0.55*tc(PASSCLKP)
ns
3
tw(PASSCLKP)
Pulse Width _ PASSCLKP low
0.45*tc(PASSCLKP)
0.55*tc(PASSCLKP)
ns
4
tr(PASSCLKN_250mv) Transition Time _ PASSCLKN Rise time (250 mV)
50
350
ps
4
tf(PASSCLKN_250mv)
Transition Time _ PASSCLKN Fall time (250 mV)
50
350
ps
4
tr(PASSCLKP_250mv)
Transition Time _ PASSCLKP Rise time (250 mV)
50
350
ps
4
tf(PASSCLKP_250mv)
Transition Time _ PASSCLKP Fall time (250 mV)
50
350
ps
5
tj(PASSCLKN)
Jitter, Peak_to_Peak _ Periodic PASSCLKN
100
ps, pk-pk
5
tj(PASSCLKP)
Jitter, Peak_to_Peak _ Periodic PASSCLKP
100
ps, pk-pk
Figure 7-41
PASS PLL Timing
1
2
3
PASSCLKN
PASSCLKP
4
176
TMS320C6670 Peripheral Information and Electrical Specifications
5
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Multicore Fixed and Floating-Point System-on-Chip
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www.ti.com
7.11 DDR3 Memory Controller
The 64-bit DDR3 Memory Controller bus of the TMS320C6670 is used to interface to JEDEC standard-compliant
DDR3 SDRAM devices. The DDR3 external bus interfaces only to DDR3 SDRAM devices; it does not share the bus
with any other types of peripherals.
7.11.1 DDR3 Memory Controller Device-Specific Information
Due to the complicated nature of the interface, a limited number of topologies will be supported to provide a 16-bit,
32-bit, or 64-bit interface.
The DDR3 electrical requirements are fully specified in the DDR Jedec Specification JESD79-3C. Standard DDR3
SDRAMs are available in 8- and 16-bit versions, allowing for the following bank topologies to be supported by the
interface:
• 72-bit: Five 16-bit SDRAMs (including 8 bits of ECC)
• 72-bit: Nine 8-bit SDRAMs (including 8 bits of ECC)
• 36-bit: Three 16-bit SDRAMs (including 4 bits of ECC)
• 36-bit: Five 8-bit SDRAMs (including 4 bits of ECC)
• 64-bit: Four 16-bit SDRAMs
• 64-bit: Eight 8-bit SDRAMs
• 32-bit: Two 16-bit SDRAMs
• 32-bit: Four 8-bit SDRAMs
• 16-bit: One 16-bit SDRAM
• 16-bit: Two 8-bit SDRAM
The approach to specifying interface timing for the DDR3 memory bus is different than on other interfaces such as
I2C or SPI. For these other interfaces, the device timing was specified in terms of data manual specifications and I/O
buffer information specification (IBIS) models. For the DDR3 memory bus, the approach is to specify compatible
DDR3 devices and provide the printed circuit board (PCB) solution and guidelines directly to the user.
A race condition may exist when certain masters write data to the DDR3 memory controller. For example, if
master A passes a software message via a buffer in external memory and does not wait for indication that the write
completes, when master B attempts to read the software message, then the master B read may bypass the master A
write and, thus, master B may read stale data and, therefore, receive an incorrect message.
Some master peripherals (e.g., EDMA3 transfer controllers) will always wait for the write to complete before
signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have a hardware
specification of write-read ordering, it may be necessary to specify data ordering via software.
If master A does not wait for indication that a write is complete, it must perform the following workaround:
1. Perform the required write.
2. Perform a dummy write to the DDR3 memory controller module ID and revision register.
3. Perform a dummy read to the DDR3 memory controller module ID and revision register.
4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The completion of
the read in step 3 ensures that the previous write was done.
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ADVANCE INFORMATION
The TMS320C6670 includes one 64-bit wide 1.5-V DDR3 SDRAM EMIF interface. The DDR3 interface can operate
at 800 Mega Transfers per Second (MTS), 1033 MTS, 1333 MTS, and 1600 MTS
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
7.11.2 DDR3 Memory Controller Electrical Data/Timing
The DDR3 Implementation Guidelines application report in ‘‘Related Documentation from Texas Instruments’’ on
page 59 specifies a complete DDR3 interface solution as well as a list of compatible DDR3 devices. The DDR3
electrical requirements are fully specified in the DDR3 Jedec Specification JESD79-3C. TI has performed the
simulation and system characterization to ensure all DDR3 interface timings in this solution are met; therefore, no
electrical data/timing information is supplied here for this interface.
Note—TI supports only designs that follow the board design guidelines outlined in the application report.
7.12 I2C Peripheral
ADVANCE INFORMATION
The inter-integrated circuit (I2C) module provides an interface between DSP and other devices compliant with
2
2
Philips Semiconductors Inter-IC bus (I C bus) specification version 2.1 and connected by way of an I C bus.
External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DSP
through the I2C module.
2
7.12.1 I C Device-Specific Information
2
2
The TMS320C6670 device includes an I C peripheral module. NOTE: when using the I C module, ensure there are
external pullup resistors on the SDA and SCL pins.
2
The I C modules on the C6670 may be used by the DSP to control local peripheral ICs (DACs, ADCs, etc.) or may
be used to communicate with other controllers in a system or to implement a user interface.
2
The I C port supports:
2
• Compatible with Philips I C specification revision 2.1 (January 2000)
• Fast mode up to 400 Kbps (no fail-safe I/O buffers)
• Noise filter to remove noise 50 ns or less
• 7-bit and 10-bit device addressing modes
• Multi-master (transmit/receive) and slave (transmit/receive) functionality
• Events: DMA, interrupt, or polling
• Slew-rate limited open-drain output buffers
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Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
2
Figure 7-42 shows a block diagram of the I C module.
Figure 7-42
I2C Module Block Diagram
2
I C Module
Clock
Prescale
Peripheral Clock
(CPU/6)
2
I CPSC
Bit Clock
Generator
SCL
Noise
Filter
2
I C Clock
I COAR
Own
Address
I2CSAR
Slave
Address
I2CMDR
Mode
2
2
I CCLKH
ADVANCE INFORMATION
Control
I2CCLKL
2
I CCNT
Transmit
I2CXSR
2
I CDXR
Transmit
Shift
Extended
Mode
Transmit
Buffer
SDA
I2C Data
I2CEMDR
Data
Count
Interrupt/DMA
Noise
Filter
I2CDRR
2
I CRSR
2
Interrupt
Mask/Status
2
Interrupt
Status
I CIMR
Receive
Receive
Buffer
I CSTR
Receive
Shift
I CIVR
2
Interrupt
Vector
Shading denotes control/status registers.
2
7.12.2 I C Peripheral Register Description(s)
Table 7-64
I2C Registers (Part 1 of 2)
Hex Address Range
Acronym
02B0 4000
ICOAR
I2C own address register
02B0 4004
ICIMR
I C interrupt mask/status register
02B0 4008
ICSTR
I C interrupt status register
02B0 400C
ICCLKL
I2C clock low-time divider register
02B0 4010
ICCLKH
I C clock high-time divider register
02B0 4014
ICCNT
I C data count register
02B0 4018
ICDRR
I2C data receive register
02B0 401C
ICSAR
I C slave address register
02B0 4020
ICDXR
I C data transmit register
02B0 4024
ICMDR
I2C mode register
02B0 4028
ICIVR
I C interrupt vector register
02B0 402C
ICEMDR
I C extended mode register
02B0 4030
ICPSC
Copyright 2010 Texas Instruments Incorporated
Register Name
2
2
2
2
2
2
2
2
I2C prescaler register
TMS320C6670 Peripheral Information and Electrical Specifications
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TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
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Table 7-64
www.ti.com
I2C Registers (Part 2 of 2)
Hex Address Range
Acronym
02B0 4034
ICPID1
I2C peripheral identification register 1 [Value: 0x0000 0105]
Register Name
02B0 4038
ICPID2
I C peripheral identification register 2 [Value: 0x0000 0005]
02B0 403C - 02B0 405C
-
Reserved
02B0 4060 - 02B3 407F
-
Reserved
02B0 4080 - 02B3 FFFF
-
Reserved
2
End of Table 7-64
2
ADVANCE INFORMATION
7.12.3 I C Electrical Data/Timing
2
7.12.3.1 Inter-Integrated Circuits (I C) Timing
Table 7-65
I2C Timing Requirements
(1)
(see Figure 7-43)
Standard Mode
No.
1
2
3
Min
Max
Fast Mode
Min
tc(SCL)
Cycle time, SCL
10
2.5
μs
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a repeated START
condition)
4.7
0.6
μs
th(SDAL-SCLL)
Hold time, SCL low after SDA low (for a START and a repeated
START condition)
4
0.6
μs
4
tw(SCLL)
Pulse duration, SCL low
5
tw(SCLH)
Pulse duration, SCL high
6
tsu(SDAV-SCLH)
Setup time, SDA valid before SCL high
4.7
1.3
μs
4
0.6
μs
100
(2)
3.45
0
(3)
250
2
(3)
μs
(5)
300
ns
(5)
300
ns
300
20 + 0.1Cb (5)
300
ns
300
(5)
300
th(SCLL-SDAV)
Hold time, SDA valid after SCL low (for I C bus devices)
0
8
tw(SDAH)
Pulse duration, SDA high between STOP and START conditions
4.7
9
tr(SDA)
Rise time, SDA
1000
20 + 0.1Cb
10
tr(SCL)
Rise time, SCL
1000
20 + 0.1Cb
11
tf(SDA)
Fall time, SDA
12
tf(SCL)
Fall time, SCL
13
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high (for STOP condition)
tw(SP)
Cb
(5)
0.9
1.3
4
20 + 0.1Cb
μs
0.6
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
ns
(4)
7
14
Max Units
0
400
ns
μs
50
ns
400
pF
End of Table 7-65
1 The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down
2
2
2 A Fast-mode I C-bus™ device can be used in a Standard-mode I C-bus™ system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the
case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
3 A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge
of SCL.
4 The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
5 Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
180
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TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
2
Figure 7-43
I C Receive Timings
11
9
SDA
8
6
4
14
13
5
10
SCL
3
12
7
2
3
Stop
Table 7-66
Start
Repeated
Start
Stop
I2C Switching Characteristics (1)
(see Figure 7-44)
Standard Mode
No.
Parameter
Min
Max
Fast Mode
Min
Max Unit
16
tc(SCL)
Cycle time, SCL
10
2.5
ms
17
tsu(SCLH-SDAL)
Setup time, SCL high to SDA low (for a repeated START condition)
4.7
0.6
ms
18
th(SDAL-SCLL)
Hold time, SDA low after SCL low (for a START and a repeated START
condition)
4
0.6
ms
19
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
ms
20
tw(SCLH)
Pulse duration, SCL high
4
0.6
ms
21
td(SDAV-SDLH)
Delay time, SDA valid to SCL high
250
100
22
tv(SDLL-SDAV)
Valid time, SDA valid after SCL low (for I2C bus devices)
0
0
23
tw(SDAH)
Pulse duration, SDA high between STOP and START conditions
24
tr(SDA)
Rise time, SDA
4.7
ns
0.9
1.3
1000
ms
ms
20 + 0.1Cb
(1)
300
ns
25
tr(SCL)
Rise time, SCL
1000
20 + 0.1Cb
(1)
300
ns
26
tf(SDA)
Fall time, SDA
300
20 + 0.1Cb
(1)
300
ns
20 + 0.1Cb
(1)
300
27
tf(SCL)
Fall time, SCL
28
td(SCLH-SDAH)
Delay time, SCL high to SDA high (for STOP condition)
300
Cp
Capacitance for each I C pin
2
4
0.6
10
ns
ms
10
pF
End of Table 7-66
1 Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
Copyright 2010 Texas Instruments Incorporated
TMS320C6670 Peripheral Information and Electrical Specifications
181
ADVANCE INFORMATION
1
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Figure 7-44
www.ti.com
I2C Transmit Timings
26
24
SDA
23
21
19
28
20
25
SCL
16
18
27
22
17
ADVANCE INFORMATION
18
Stop
182
Start
TMS320C6670 Peripheral Information and Electrical Specifications
Repeated
Start
Stop
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
7.13 SPI Peripheral
The serial peripheral interconnect (SPI) module provides an interface between the DSP and other SPI-compliant
devices. The primary intent of this interface is to allow for connection to a SPI ROM for boot. The SPI module on
C6670 is supported only in Master mode. Additional chip-level components can also be included, such as
temperature sensors or an I/O expander.
7.13.1 SPI Electrical Data/Timing
7.13.1.1 SPI Timing
SPI Timing Requirements
See Figure 7-45)
No.
Min
Max
Unit
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
7
tsu(SOMI-SPC)
Input Setup Time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 0 Phase = 0
2
ns
7
tsu(SOMI-SPC)
Input Setup Time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 0 Phase = 1
2
ns
7
tsu(SOMI-SPC)
Input Setup Time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 1 Phase = 0
2
ns
7
tsu(SOMI-SPC)
Input Setup Time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 1 Phase = 1
2
ns
8
th(SPC-SOMI)
Input Hold Time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 0 Phase = 0
5
ns
8
th(SPC-SOMI)
Input Hold Time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 0 Phase = 1
5
ns
8
th(SPC-SOMI)
Input Hold Time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 1 Phase = 0
5
ns
8
th(SPC-SOMI)
Input Hold Time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 1 Phase = 1
5
ns
End of Table 7-67
Table 7-68
SPI Switching Characteristics (Part 1 of 2)
(See Figure 7-45 and Figure 7-46)
No.
Parameter
Min
Max
Unit
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
1
tc(SPC)
Cycle Time, SPIx_CLK, All Master Modes
1/66MHz
ns
2
tw(SPCH)
Pulse Width High, SPIx_CLK, All Master Modes
7
ns
3
tw(SPCL)
Pulse Width Low, SPIx_CLK, All Master Modes
7
4
td(SIMO-SPC)
Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK.
Polarity = 0, Phase = 0.
5
ns
4
td(SIMO-SPC)
Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK.
Polarity = 0, Phase = 1.
5
ns
4
td(SIMO-SPC)
Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK
Polarity = 1, Phase = 0
5
ns
4
td(SIMO-SPC)
Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK
Polarity = 1, Phase = 1
5
ns
5
td(SPC-SIMO)
Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on
SPIx_CLK. Polarity = 0 Phase = 0
5
ns
5
td(SPC-SIMO)
Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on
SPIx_CLK Polarity = 0 Phase = 1
5
ns
5
td(SPC-SIMO)
Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on
SPIx_CLK Polarity = 1 Phase = 0
5
ns
5
td(SPC-SIMO)
Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on
SPIx_CLK Polarity = 1 Phase = 1
5
ns
6
toh(SPC-SIMO)
Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for
final bit. Polarity = 0 Phase = 0
0.5*tc - 2
ns
6
toh(SPC-SIMO)
Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for
final bit. Polarity = 0 Phase = 1
0.5*tc - 2
ns
Copyright 2010 Texas Instruments Incorporated
ns
TMS320C6670 Peripheral Information and Electrical Specifications
183
ADVANCE INFORMATION
Table 7-67
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 7-68
www.ti.com
SPI Switching Characteristics (Part 2 of 2)
(See Figure 7-45 and Figure 7-46)
No.
Parameter
Min
Max
Unit
6
toh(SPC-SIMO)
Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for
final bit. Polarity = 1 Phase = 0
0.5*tc - 2
ns
6
toh(SPC-SIMO)
Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for
final bit. Polarity = 1 Phase = 1
0.5*tc - 2
ns
Additional SPI Master Timings — 4 Pin Mode with Chip Select Option
ADVANCE INFORMATION
19
td(SCS-SPC)
Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 0 Phase = 0
2*P2 - 5
19
td(SCS-SPC)
Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 0 Phase = 1
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns
2*P2 + 5
19
td(SCS-SPC)
Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 1 Phase = 0
2*P2 - 5
19
td(SCS-SPC)
Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 1 Phase = 1
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns
20
td(SPC-SCS)
Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 0
Phase = 0
1*P2 - 5
20
td(SPC-SCS)
Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 0
Phase = 1
0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5 ns
20
td(SPC-SCS)
Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 1
Phase = 0
1*P2 - 5
20
td(SPC-SCS)
Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 1
Phase = 1
0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5 ns
tw(SCSH)
Minimum inactive time on SPIx_SCS\ pin between two transfers when
SPIx_SCS\ is not held using the CSHOLD feature.
2*P2 - 5
2*P2 + 5
1*P2 + 5
1*P2 + 5
ns
ns
ns
ns
ns
End of Table 7-68
184
TMS320C6670 Peripheral Information and Electrical Specifications
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Figure 7-45
SPI Master Mode Timing Diagrams — Base Timings for 3-Pin Mode
1
2
MASTER MODE
POLARITY = 0 PHASE = 0
3
SPIx_CLK
5
4
MO(0)
7
SPIx_SOMI
6
MO(1)
MO(n-1)
MO(n)
8
MI(0)
MI(1)
MI(n-1)
MI(n)
ADVANCE INFORMATION
SPIx_SIMO
MASTER MODE
POLARITY = 0 PHASE = 1
4
SPIx_CLK
6
5
SPIx_SIMO
MO(0)
7
SPIx_SOMI
MO(1)
MO(n-1)
MI(1)
MI(n-1)
MO(n)
8
MI(0)
4
MI(n)
MASTER MODE
POLARITY = 1 PHASE = 0
SPIx_CLK
5
SPIx_SIMO
6
MO(0)
MO(1)
7
SPIx_SOMI
MO(n-1)
MO(n)
8
MI(0)
MI(1)
MI(n-1)
MI(n)
MASTER MODE
POLARITY = 1 PHASE = 1
SPIx_CLK
5
4
SPIx_SIMO
MO(0)
7
SPIx_SOMI
Figure 7-46
6
MO(1)
MO(n-1)
MI(1)
MI(n-1)
MO(n)
8
MI(0)
MI(n)
SPI Additional Timings for 4-Pin Master Mode with Chip Select Option
MASTER MODE 4 PIN WITH CHIP SELECT
19
20
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
MO(0)
MI(0)
MO(1)
MO(n-1)
MO(n)
MI(1)
MI(n-1)
MI(n)
SPIx_SCS
Copyright 2010 Texas Instruments Incorporated
TMS320C6670 Peripheral Information and Electrical Specifications
185
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
7.14 HyperLink Peripheral
The TMS320C6670 includes the HyperLink for companion chip/die interfaces. This is a four-lane SerDes interface
designed to operate at 12.5 Gbps per lane from pin-to-pin and at 18 Gbps per lane from die-to-die. The interface is
used to connect with external accelerators that are manufactured using TI libraries. The Hyperbridge links must be
connected with DC coupling.
The interface includes the Serial Station Management Interfaces used to send power management and flow messages
between devices. This consists of four LVCMOS inputs and four LVCMOS outputs configured as two 2-wire output
buses and two 2-wire input buses. Each 2-wire bus includes a data signal and a clock signal.
Table 7-69
HyperLink Peripheral Timing Requirements
ADVANCE INFORMATION
(see Figure 7-47, Figure 7-48 and Figure 7-49)
No.
Min
Max
Unit
FL Interface
1
tc(MCMTXFLCLK)
Clock Period - MCMTXFLCLK (C1)
2
tw(MCMTXFLCLKH)
High Pulse Width - MCMTXFLCLK
0.4*C1 0.6*C1
6
ns
ns
3
tw(MCMTXFLCLKL)
Low Pulse Width - MCMTXFLCLK
0.4*C1 0.6*C1
ns
6
tsu(MCMTXFLDAT-MCMTXFLCLKH)
Setup Time - MCMTXFLDAT valid before MCMTXFLCLK high
7
th(MCMTXFLCLKH-MCMTXFLDAT)
Hold Time - MCMTXFLDAT valid after MCMTXFLCLK high
1
ns
6
tsu(MCMTXFLDAT-MCMTXFLCLKL)
Setup Time - MCMTXFLDAT valid before MCMTXFLCLK low
1
ns
7
th(MCMTXFLCLKL-MCMTXFLDAT)
Hold Time - MCMTXFLDAT valid after MCMTXFLCLK low
1
ns
6
ns
1
ns
PM Interface
1
tc(MCMRXPMCLK)
Clock Period - MCMRXPMCLK (C3)
2
tw(MCMRXPMCLK)
High Pulse Width - MCMRXPMCLK
0.4*C3 0.6*C3
3
tw(MCMRXPMCLK)
Low Pulse Width - MCMRXPMCLK
0.4*C3 0.6*C3
6
tsu(MCMRXPMDAT-MCMRXPMCLKH) Setup Time - MCMRXPMDAT valid before MCMRXPMCLK high
7
th(MCMRXPMCLKH-MCMRXPMDAT)
Hold Time - MCMRXPMDAT valid after MCMRXPMCLK high
1
ns
6
tsu(MCMRXPMDAT-MCMRXPMCLKL)
Setup Time - MCMRXPMDAT valid before MCMRXPMCLK low
1
ns
7
th(MCMRXPMCLKL-MCMRXPMDAT)
Hold Time - MCMRXPMDAT valid after MCMRXPMCLK low
1
ns
1
ns
ns
ns
End of Table 7-69
Table 7-70
HyperLink Peripheral Switching Characteristics (Part 1 of 2)
(see Figure 7-47, Figure 7-48 and Figure 7-49)
No.
Parameter
Min
Max
Unit
FL Interface
1
tc(MCMRXFLCLK)
Clock Period - MCMRXFLCLK (C2)
6
ns
2
tw(MCMRXFLCLKH)
High Pulse Width - MCMRXFLCLK
0.4*C2
0.6*C2
ns
3
tw(MCMRXFLCLKL)
Low Pulse Width - MCMRXFLCLK
0.4*C2
0.6*C2
ns
4
tosu(MCMRXFLDAT-MCMRXFLCLKH)
Setup Time - MCMRXFLDAT valid before MCMRXFLCLK high
1.1
ns
5
toh(MCMRXFLCLKH-MCMRXFLDAT)
Hold Time - MCMRXFLDAT valid after MCMRXFLCLK high
1.1
ns
4
tosu(MCMRXFLDAT-MCMRXFLCLKL)
Setup Time - MCMRXFLDAT valid before MCMRXFLCLK low
1.1
ns
5
toh(MCMRXFLCLKL-MCMRXFLDAT)
Hold Time - MCMRXFLDAT valid after MCMRXFLCLK low
1.1
ns
1
tc(MCMTXPMCLK)
Clock Period - MCMTXPMCLK (C4)
6
ns
2
tw(MCMTXPMCLK)
High Pulse Width - MCMTXPMCLK
0.4*C4
0.6*C4
ns
3
tw(MCMTXPMCLK)
Low Pulse Width - MCMTXPMCLK
0.4*C4
0.6*C4
ns
4
tosu(MCMTXPMDAT-MCMTXPMCLKH) Setup Time - MCMTXPMDAT valid before MCMTXPMCLK high
PM Interface
186
TMS320C6670 Peripheral Information and Electrical Specifications
1.1
ns
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Table 7-70
HyperLink Peripheral Switching Characteristics (Part 2 of 2)
(see Figure 7-47, Figure 7-48 and Figure 7-49)
No.
Parameter
Min
Max
Unit
5
toh(MCMTXPMCLKH-MCMTXPMDAT)
Hold Time - MCMTXPMDAT valid after MCMTXPMCLK high
1.1
ns
4
tosu(MCMTXPMDAT-MCMTXPMCLKL)
Setup Time - MCMTXPMDAT valid before MCMTXPMCLK low
1.1
ns
5
toh(MCMTXPMCLKL-MCMTXPMDAT)
Hold Time - MCMTXPMDAT valid after MCMTXPMCLK low
1.1
ns
End of Table 7-70
HyperLink Station Management Clock Timing
ADVANCE INFORMATION
Figure 7-47
1
2
Figure 7-48
3
HyperLink Station Management Transmit Timing
4
5
4
5
6
7
?_CLK
?_DAT
Figure 7-49
HyperLink Station Management Receive Timing
6
7
?_CLK
?_DAT
Copyright 2010 Texas Instruments Incorporated
TMS320C6670 Peripheral Information and Electrical Specifications
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TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
7.15 UART Peripheral
The universal asynchronous receiver/transmitter (UART) module provides an interface between the DSP and
UART terminal interface or other UART based peripheral. UART is based on the industry standard TL16C550
asynchronous communications element, which in turn is a functional upgrade of the TL16C450. Functionally
similar to the TL16C450 on power up (single character or TL16C450 mode), the UART can be placed in an alternate
FIFO (TL16C550) mode. This relieves the DSP of excessive software overhead by buffering received and transmitted
characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per
byte for the receiver FIFO.
ADVANCE INFORMATION
The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial
conversion on data received from the DSP. The DSP can read the UART status at any time. The UART includes
control capability and a processor interrupt system that can be tailored to minimize software management of the
communications link. For more information on UART, see the Universal Asynchronous Receiver/Transmitter
(UART) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59.
Table 7-71
UART Timing Requirements
(see Figure 7-50 and Figure 7-51)
No.
Parameter
Min
Max
Unit
Receive Timing
4
tw(RXSTART)
Pulse width, receive start bit
0.96U
1.05U
ns
5
tw(RXH)
Pulse width, receive data/parity bit high
0.96U
1.05U
ns
5
tw(RXL)
Pulse width, receive data/parity bit low
0.96U
1.05U
ns
6
tw(RXSTOP1)
Pulse width, receive stop bit 1
0.96U
1.05U
ns
6
tw(RXSTOP15)
Pulse width, receive stop bit 1.5
0.96U
1.05U
ns
6
tw(RXSTOP2)
Pulse width, receive stop bit 2
0.96U
1.05U
ns
(1)
P
ns
Autoflow Timing Requirements
8
td(CTSL-TX)
Delay time, CTS asserted to START bit transmit
P
End of Table 7-71
1 P = CPU/6
Figure 7-50
UART Receive Timing Waveform
5
4
RXD
Stop/Idle
Figure 7-51
Start
5
Bit 0
Bit 1
Bit N-1
Bit N
6
Parity
Stop
Idle
Start
UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform
8
TXD
Bit N-1
Bit N
Stop
Start
Bit 0
CTS
188
TMS320C6670 Peripheral Information and Electrical Specifications
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
Table 7-72
UART Switching Characteristics
(See Figure 7-52 and Figure 7-53)
No.
Parameter
Min
Max
Unit
1
tw(TXSTART)
Pulse width, transmit start bit
U-2
U+2
ns
2
tw(TXH)
Pulse width, transmit data/parity bit high
U-2
U+2
ns
2
tw(TXL)
Pulse width, transmit data/parity bit low
U-2
U+2
ns
3
tw(TXSTOP1)
Pulse width, transmit stop bit 1
U-2
U+2
ns
3
tw(TXSTOP15)
Pulse width, transmit stop bit 1.5
1.5 * (U - 2) 1.5 * ('U + 2)
ns
3
tw(TXSTOP2)
Pulse width, transmit stop bit 2
2 * (U - 2)
2 * ('U + 2)
ns
P (1)
P
ns
Autoflow Timing Requirements
7
Delay time, STOP bit received to RTS deasserted
td(RX-RTSH)
End of Table 7-72
1 P = CPU/6
Figure 7-52
UART Transmit Timing Waveform
1
TXD
Figure 7-53
Start
Stop/Idle
2
Bit 0
2
Bit 1
Bit N-1
Bit N
Parity
3
Stop
Idle
Start
UART RTS (Request-to-Send Output) – Autoflow Timing Waveform
7
RXD
Bit N-1
Bit N
Stop
Start
CTS
7.16 PCIe Peripheral
The 2 lane PCI express (PCIe) module on TMS320C6670 provides an interface between the DSP and other PCIe
compliant devices. The PCI Express module provides low pin count, high reliability, and high-speed data transfer at
rates of 5.0 Gbps per lane on the serial links. For more information, see the Peripheral Component Interconnect
Express (PCIe) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59.
7.17 Packet Accelerator
The packet accelerator provides L2 to L4 classification functionalities. It supports classification for Ethernet, VLAN,
MPLS over Ethernet, IPv4/6, GRE over IP, and other session identification over IP such as TCP and UDP ports. It
maintains 8K multiple-in, multiple-out hardware queues. It also provides checksum capability as well as some QoS
capabilities. It enables a single IP address to be used for a multi-core device. It can process up to 1.5 M pps. For more
information, see the Packet Accelerator (PA) for KeyStone Devices User Guide in ‘‘Related Documentation from
Texas Instruments’’ on page 59.
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7.18 Security Accelerator
The security accelerator provides wire-speed processing on 1-Gbps Ethernet traffic on IPSec, SRTP, and 3GPP Air
interface security protocols. It functions on the packet level with the packet and the associated security context being
one of these above three types. The security accelerator is coupled with packet accelerator, and receives the packet
descriptor containing the security context in the buffer descriptor, and the data to be encrypted/decrypted in the
linked buffer descriptor.
7.19 Ethernet MAC (EMAC)
ADVANCE INFORMATION
The Ethernet media access controller (EMAC) modules provide an efficient interface between the TMS320C6670
DSP and the networked community. The EMAC supports 10Base-T (10 Mbits/second [Mbps]), and 100BaseTX
(100 Mbps), in half- or full-duplex mode, and 1000BaseT (1000 Mbps) in full-duplex mode, with hardware flow
control and quality-of-service (QOS) support. For more information, see the Ethernet Media Access Control (EMAC)
for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59.
Each device has a unique MAC address. There are two registers to hold these values, MACID1 (0x02620110) and
MACID2 (0x02600114). All bits of these registers are defined as follows:
Figure 7-54
MACID1 Register
31
0
MACID[31:0]
R,+xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
Legend: R = Read only; -x, value is indeterminate
Table 7-73
MACID1 Register Field Descriptions
Bit
Field
Description
31-0
MAC ID[31-0]
MAC ID. A range will be assigned to this device. Each device will consume only one MAC address.
End of Table 7-73
Figure 7-55
MACID2 Register
31
24
23
18
17
16
15
0
CRC
Reserved
FLOW
BCAST
MACID[47:32]
R+,cccc cccc
R,+rr rrrr
R,+z
R,+y
R,+xxxx xxxx xxxx xxxx
Legend: R = Read only; -x, value is indeterminate
Table 7-74
MACID2 Register Field Descriptions
Bit
Field
Description
31-24
Reserved
Variable
23-18
Reserved
000000
17
FLOW
MAC Flow Control
0 = Off
1 = On
16
BCAST
Default m/b-cast reception
0 = Broadcast
1 = Disabled
15-0
MAC ID[47-0]
MAC ID. A range will be assigned to this device. Each device will consume only one MAC address.
End of Table 7-74
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7.20 Management Data Input/Output (MDIO)
The management data input/output (MDIO) module implements the 802.3 serial management interface to
interrogate and controls up to 32 Ethernet PHY(s) connected to the device, using a shared two-wire bus. Application
software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the EMAC,
retrieve the negotiation results, and configure required parameters in the EMAC module for correct operation. The
module is designed to allow almost transparent operation of the MDIO interface, with very little maintenance from
the core processor. For more information, see the Ethernet Media Access Control (EMAC) for KeyStone Devices User
Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59.
Table 7-75
MDIO Timing Requirements
No.
1
Min
Max
ADVANCE INFORMATION
(see Figure 7-56)
Unit
tc(MDCLK)
Cycle time, MDCLK
400
ns
tw(MDCLKH)
Pulse duration, MDCLK high
180
ns
tw(MDCLKL)
Pulse duration, MDCLK low
180
ns
4
tsu(MDIO-MDCLKH)
Setup time, MDIO data input valid before MDCLK high
10
ns
5
th(MDCLKH-MDIO)
Hold time, MDIO data input valid after MDCLK high
10
tt(MDCLK)
Transition time, MDCLK
ns
5
ns
End of Table 7-75
Figure 7-56
MDIO Input Timing
1
MDCLK
4
5
MDIO
(Input)
Table 7-76
MDIO Switching Characteristics
(see Figure 7-57)
No.
7
Parameter
td(MDCLKL-MDIO)
Min
Delay time, MDCLK low to MDIO data output valid
Max
Unit
100
ns
End of Table 7-76
Figure 7-57
MDIO Output Timing
1
MDCLK
7
MDIO
(Ouput)
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7.21 Timers
The timers can be used to time events, count events, generate pulses, interrupt the CPU, and send synchronization
events to the EDMA3 channel controller.
7.21.1 Timers Device-Specific Information
The TMS320C6670 device has eight 64-bit timers in total. Of which Timer0 through Timer3 are dedicated to each
of the four CorePacs as a watchdog timer and can also be used as general-purpose timers. Each of other 4 timers can
also be configured as a general-purpose timer only, with each timer programmed as a 64-bit timer or as two separate
32-bit timers.
ADVANCE INFORMATION
When operating in 64-bit mode, the timer counts either VBUS clock cycles or input (TINPLx) pulses (rising edge)
and generates an output pulse/waveform (TOUTLx) plus an internal event (TINTLx) on a software-programmable
period.
When operating in 32-bit mode, the timer is split into two independent 32-bit timers. Each timer is made up of two
32-bit counters: a high counter and a low counter. The timer pins, TINPLx and TOUTLx are connected to the low
counter. The timer pins, TINPHx and TOUTHx are connected to the high counter.
When operating in Watchdog mode, the timer counts down to zero and generates an event. It is a requirement that
software writes to the timer before the count expires, after which the count begins again. If the count ever reaches
zero, the timer event output is asserted. Reset initiated by a watch dog timer can be set by programming ‘‘Reset Type
Status Register (RSTYPE)’’ on page 166 and the type of reset initiated can set by programming ‘‘Reset Configuration
Register (RSTCFG)’’ on page 168. For more information, see the 64-bit Timer (Timer 64) for KeyStone Devices User
Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59.
7.21.2 Timers Electrical Data/Timing
The tables and figures below describe the timing requirements and switching characteristics of Timer0 through
Timer7 peripherals.
Table 7-77
Timer Input Timing Requirements (1)
(see Figure 7-58)
No.
Min
Max
Unit
1
tw(TINPH)
Pulse duration, high
12C
ns
2
tw(TINPL)
Pulse duration, low
12C
ns
End of Table 7-77
1 If CORECLKSEL = 0, C = 1/CORECLK(NIP) frequency in ns. If CORECLKSEL = 1, C = 1/ALTCORECLK frequency in ns.
Table 7-78
Timer Output Switching Characteristics (1)
(2)
(see Figure 7-58)
No.
Parameter
Min
Max
Unit
3
tw(TOUTH)
Pulse duration, high
12C - 3
ns
4
tw(TOUTL)
Pulse duration, low
12C - 3
ns
End of Table 7-78
1 Over recommended operating conditions.
2 If CORECLKSEL = 0, C = 1/CORECLK(NIP) frequency in ns. If CORECLKSEL = 1, C = 1/ALTCORECLK frequency in ns.
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Figure 7-58
Timer Timing
1
2
TIMIx
3
4
ADVANCE INFORMATION
TIMOx
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7.22 Rake Search Accelerator (RSA)
There are four Rake Search Accelerators (RSAs) on the TMS320C6670 device. CorePac 1 and CorePac 2 each have
one set of directly-connected RSA pairs. The RSA is an extension of the C66x CPU. The CPU performs send/receive
to the RSAs via the .L and .S functional units. For more information, see the Rake Search Accelerator (RSA) for
KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59.
7.23 Enhanced Viterbi-Decoder Coprocessor (VCP2)
ADVANCE INFORMATION
The TMS320C6670 device has four high-performance embedded Viterbi-Decoder Coprocessor (VCP2) that
significantly speeds up channel-decoding operations on-chip. Each VCP2, operating at CPU clock divided-by-3, can
decode more than 694 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP2 supports
constraint lengths K = 5, 6, 7, 8, and 9, rates R = 3/4, 1/2, 1/3, 1/4, and 1/5, and flexible polynomials, while generating
hard decisions or soft decisions. Communications between the VCP2 and the CPU are carried out through the
EDMA3 controller. The VCP2 supports:
• Unlimited frame sizes
• Code rates 3/4, 1/2, 1/3, 1/4, and 1/5
• Constraint lengths 5, 6, 7, 8, and 9
• Programmable encoder polynomials
• Programmable reliability and convergence lengths
• Hard and soft decoded decisions
• Tail and convergent modes
• Yamamoto logic
• Tail biting logic
• Various input and output FIFO lengths
For more information, see the Viterbi Coprocessor (VCP2) for KeyStone Devices User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 59.
7.24 Third-Generation Turbo Decoder Coprocessor (TCP3d)
The C6670 device has two high-performance embedded Turbo-Decoder Coprocessor (TCP3d) that significantly
speed up channel-decoding operations on-chip for WCDMA, HSPA, HSPA+, TD-SCDMA, LTE, and WiMAX.
Operating at CPU clock divided-by-2, the TCP3d is capable of processing data channels at a throughput of >100
Mbps. For more information, see the Turbo Decoder Coprocessor 3 (TCP3d) for KeyStone Devices User Guide
in ‘‘Related Documentation from Texas Instruments’’ on page 59.
7.25 Turbo Encoder Coprocessor (TCP3e)
The C6670 device has a high-performance embedded Turbo-Encoder Coprocessor (TCP3e) that significantly
speeds up channel-encoding operations on-chip for WCDMA, HSPA, HSPA+, TD-SCDMA, LTE, and WiMAX.
Operating at CPU clock divided-by-3, the TCP3e is capable of processing data channels at a throughput of >200
Mbps. For more information, see the Turbo Encoder Coprocessor 3 (TCP3e) for KeyStone Devices User Guide
in ‘‘Related Documentation from Texas Instruments’’ on page 59.
7.26 Serial RapidIO (SRIO) Port
The SRIO port on the TMS320C6670 device is a high-performance, low pin-count interconnect aimed for
embedded markets. The use of the RapidIO interconnect in a baseband board design can create a homogeneous
interconnect environment, providing even more connectivity and control among the components. RapidIO is based
on the memory and device addressing concepts of processor buses where the transaction processing is managed
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completely by hardware. This enables the RapidIO interconnect to lower the system cost by providing lower latency,
reduced overhead of packet data processing, and higher system bandwidth, all of which are key for wireless
interfaces. For more information, see the Serial RapidIO (SRIO) for KeyStone Devices User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 59.
7.27 General-Purpose Input/Output (GPIO)
7.27.1 GPIO Device-Specific Information
7.27.2 GPIO Electrical Data/Timing
Table 7-79
GPIO Input Timing Requirements
(1)
(see Figure 7-59)
No.
Min
Max
Unit
1
tw(GPOH)
Pulse duration, GPOx high
12C
ns
2
tw(GPOL)
Pulse duration, GPOx low
12C
ns
End of Table 7-79
1 If CORECLKSEL = 0, C = 1 ÷ CORECLK(NIP) frequency, in ns. If CORECLKSEL = 1, C = 1 ÷ ALTCORECLK frequency, in ns.
Table 7-80
GPIO Output Switching Characteristics
(1) (2)
(see Figure 7-59)
No.
Parameter
Min
Max
Unit
1
tw(GPOH)
Pulse duration, GPOx high
36C - 8
ns
2
tw(GPOL)
Pulse duration, GPOx low
36C - 8
ns
End of Table 7-80
1 Over recommended operating conditions.
2 If CORECLKSEL = 0, C = 1 ÷ CORECLK(NIP) frequency, in ns. If CORECLKSEL = 1, C = 1 ÷ ALTCORECLK frequency, in ns.
Figure 7-59
GPIO Timing
1
2
GPIx
3
4
GPOx
7.28 Semaphore2
The device contains an enhanced Semaphore module for the management of shared resources of the DSP cores. The
Semaphore enforces atomic accesses to shared chip-level resources so that the read-modify-write sequence is not
broken. The semaphore block has unique interrupts to each of the cores to identify when that core has acquired the
resource.
Semaphore resources within the module are not tied to specific hardware resources. It is a software requirement to
allocate semaphore resources to the hardware resource(s) to be arbitrated.
The Semaphore module supports 3 masters and contains 32 semaphores to be used within the system.
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On the TMS320C6670, the GPIO peripheral pins GP[15:0] are also used to latch configuration pins. For more
detailed information on device/peripheral configuration and the C6670 device pin muxing, see ‘‘Device
Configuration’’ on page 60.
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Multicore Fixed and Floating-Point System-on-Chip
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There are two methods of accessing a semaphore resource:
• Direct Access: A core directly accesses a semaphore resource. If free, the semaphore will be granted. If not, the
semaphore is not granted.
• Indirect Access: A core indirectly accesses a semaphore resource by writing it. Once it is free, an interrupt
notifies the CPU that it is available.
7.29 Antenna Interface Subsystem 2
ADVANCE INFORMATION
The enhanced antenna interface subsystem (AIF2) consists of the antenna interface module and two SerDes macros.
The AIF2 relies on the performance SerDes macro (high-speed serial link) with a logic layer for the OBSAI RP3 and
CPRI protocols. The AIF is used to connect to the backplane for transmission and reception of antenna data, as well
as to connect to additional device peripherals.
The AIF2 has 11 timer synchronization events from the AIF2 Timer (AT) module. Timer synchronization events
0-7 are routed as primary events to the TPCC1 and also as secondary events to the C66x CorePacs via INTC0.
Table 7-81
AIF2 Timer Module Timing Requirements
See Figure 7-60, Figure 7-61, Figure 7-62, and Figure 7-63
No.
Min
Max
Unit
RP1 Clock and Frameburst
1
tc(RP1CLKN)
Cycle time, RP1CLK(N)
1
tc(RP1CLKP)
Cycle time, RP1CLK(P)
2
tw(RP1CLKNL)
Pulse duration, RP1CLK(N) low
3
tw(RP1CLKNH)
3
tw(RP1CLKPL)
2
tw(RP1CLKPH)
Pulse duration, RP1CLK(P) high
4
tr(RP1CLKN)
Rise Time - RP1CLKN 10% to 90%
32.55
32.55
ns
32.55
32.55
ns
(1)
0.6 * C1
ns
Pulse duration, RP1CLK(N) high
0.4 * C1
0.6 * C1
ns
Pulse duration, RP1CLK(P) low
0.4 * C1
0.6 * C1
ns
0.4 * C1
0.6 * C1
ns
350.00
ps
0.4 * C1
4
tf(RP1CLKN)
Fall Time - RP1CLKN 90% to 10%
350.00
ps
4
tr(RP1CLKP)
Rise Time - RP1CLKP 10% to 90%
350.00
ps
4
tf(RP1CLKP)
Fall Time - RP1CLKP 90% to 10%
350.00
ps
5
tj(RP1CLKN)
Period Jitter (peak-to-peak), RP1CLK(N)
600
ps
5
tj(RP1CLKP)
Period Jitter (peak-to-peak), RP1CLK(P)
6
tw(RP1FBN)
Bit Period, RP1FB(N)
8 * C1
6
tw(RP1FBP)
Bit Period, RP1FB(P)
8 * C1
7
tr(RP1CLKN)
Rise Time - RP1FBN 10% to 90%
7
tf(RP1CLKN)
Fall Time - RP1FBN 90% to 10%
350.00
ps
7
tr(RP1CLKP)
Rise Time - RP1FBP 10% to 90%
350.00
ps
7
tf(RP1CLKP)
Fall Time - RP1FBP 90% to 10%
350.00
ps
600
ps
8 * C1
ns
8 * C1
ns
350.00
ps
PHY Sync and Radio Sync Pulses
8
tw(PHYSYNCH)
Pulse duration, PHYSYNC high
6.50
13.00
ns
9
tw(PHYSYNCL)
Pulse duration, PHYSYNC low
6.50
13.00
ns
10
tc(PHYSYNC)
Cycle time, PHYSYNC pulse to PHYSYNC pulse
10.00
10.00
ms
11
tw(RADSYNCH)
Pulse duration, RADSYNC high
6.50
13.00
ns
12
tw(RADSYNCL)
Pulse duration, RADSYNC low
6.50
13.00
ns
13
tc(RADSYNC)
Cycle time, RADSYNC pulse to RADSYNC pulse
1.00
10.00
ms
End of Table 7-81
1 C1 = tc(RP1CLKN/P)
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Figure 7-60
AIF2 RP1 Frame Synchronization Clock Timing
1
2
3
RP1CLKN
RP1CLKP
5
4
Figure 7-61
AIF2 RP1 Frame Synchronization Burst Timing
6
RP1CLKN
RP1FBP/N
RP1 Frame Burst BIT 0
RP1 Frame Burst BIT 1
ADVANCE INFORMATION
RP1CLKP
RP1 Frame Burst BIT N
7
Figure 7-62
AIF2 Physical Layer Synchronization Pulse Timing
10
8
9
PHYSYNC
Figure 7-63
AIF2 Radio Synchronization Pulse Timing
13
11
12
RADSYNC
Table 7-82
AIF2 Timer Module Switching Characteristics
(see Figure 7-64)
No.
Parameter
Min
Max
Unit
External Frame Event
14
tw(EXTFRAMEEVENTH)
Pulse width, EXTFRAMEEVENT output high
4 * C1
15
tw(EXTFRAMEEVENTL)
Pulse width, EXTFRAMEEVENT output low
4 * C1
(1)
ns
ns
End of Table 7-82
1 C1 = tc(RP1CLKN/P)
Figure 7-64
AIF2 Timer External Frame Event Timing
14
15
EXT FRAME EVENT
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7.30 FFTC
There are two FFTC coprocessors intended to accelerate FFT, IFFT, DFT, and IDFT operations. For more
information, see the Fast Fourier Transform Coprocessor (FFTC) for KeyStone Devices User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 59.
7.31 Emulation Features and Capability
7.31.1 Advanced Event Triggering (AET)
ADVANCE INFORMATION
The TMS320C6670 device supports Advanced Event Triggering (AET). This capability can be used to debug
complex problems as well as understand performance characteristics of user applications. AET provides the
following capabilities:
• Hardware Program Breakpoints: specify addresses or address ranges that can generate events such as halting
the processor or triggering the trace capture.
• Data Watchpoints: specify data variable addresses, address ranges, or data values that can generate events
such as halting the processor or triggering the trace capture.
• Counters: count the occurrence of an event or cycles for performance monitoring.
• State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to precisely
generate events for complex sequences.
For more information on AET, see the following documents in ‘‘Related Documentation from Texas Instruments’’
on page 59:
• Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs application report
• Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded Microprocessor
Systems application report
7.31.2 Trace
The C6670 device supports Trace. Trace is a debug technology that provides a detailed, historical account of
application code execution, timing, and data accesses. Trace collects, compresses, and exports debug information
for analysis. Trace works in real-time and does not impact the execution of the system.
For more information on board design guidelines for Trace Advanced Emulation, see the Emulation and Trace
Headers Technical Reference in ‘‘Related Documentation from Texas Instruments’’ on page 59.
7.31.2.1 Trace Electrical Data/Timing
Table 7-83
Trace Switching Characteristics
(1)
(see Figure 7-65)
No.
Parameter
1
tw(DPnH)
1
2
Min
Pulse duration, DPn/EMUn high
Max Unit
2.4
ns
tw(DPnH)90% Pulse duration, DPn/EMUn high detected at 90% Voh
1.5
ns
tw(DPnL)
Pulse duration, DPn/EMUn low
2.4
ns
2
tw(DPnL)10%
Pulse duration, DPn/EMUn low detected at 10% Voh
3
tsko(DPn)
Output skew time, time delay difference between DPn/EMUn pins configured as trace
1.5
tskp(DPn)
Pulse skew, magnitude of difference between high-to-low (tphl) and low-to-high (tplh) propagation delays.
tσλδπ_ο(DPn)
Output slew rate DPn/EMUn
-500
ns
500
600
3.3
ps
ps
V/ns
End of Table 7-83
1 Over recommended operating conditions.
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Figure 7-65
Trace Timing
A
TPLH
TPHL
1
2
B
3
7.31.3 IEEE 1149.1 JTAG
The JTAG interface is used to support boundary scan and emulation of the device. The boundary scan supported
allows for an asynchronous TRST and only the 5 baseline JTAG signals (e.g., no EMU[1:0]) required for boundary
scan. Most interfaces on the device follow the Boundary Scan Test Specification (IEEE1149.1), while all of the SerDes
(SRIO and SGMII) support the AC-coupled net test defined in AC-Coupled Net Test Specification (IEEE1149.6).
It is expected that all compliant devices are connected through the same JTAG interface, in daisy-chain fashion, in
accordance with the specification. The JTAG interface uses 1.8-V LVCMOS buffers, compliant with the Power
Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit Specification (EAI/JESD8-5).
7.31.3.1 IEEE 1149.1 JTAG Compatibility Statement
For maximum reliability, the C6670 DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST
will always be asserted upon power up and the DSP's internal emulation logic will always be properly initialized
when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high. However, some
third-party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and externally drive TRST
high before attempting any emulation or boundary scan operations.
7.31.3.2 JTAG Electrical Data/Timing
Table 7-84
JTAG Test Port Timing Requirements
(see Figure 7-66)
No.
Min
1
tc(TCK)
Cycle time, TCK
1a
tw(TCKH)
Pulse duration, TCK high (40% of tc)
Max
Unit
20
ns
8
ns
1b
tw(TCKL)
Pulse duration, TCK low(40% of tc)
8
ns
3
tsu(TDI-TCK)
input setup time, TDI valid to TCK high
2
ns
3
tsu(TMS-TCK)
input setup time, TMS valid to TCK high
2
ns
4
th(TCK-TDI)
input hold time, TDI valid from TCK high
10
ns
4
th(TCK-TMS)
input hold time, TMS valid from TCK high
10
ns
End of Table 7-84
Table 7-85
JTAG Test Port Switching Characteristics
(1)
(see Figure 7-66)
No.
2
Parameter
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
Min
Max
8
Unit
ns
End of Table 7-85
1 Over recommended operating conditions.
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Figure 7-66
www.ti.com
JTAG Test-Port Timing
1
1b
1a
TCK
2
TDO
3
4
ADVANCE INFORMATION
TDI / TMS
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Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
8 Mechanical Data
8.1 Packaging Information
The following packaging information reflects the most current released data available for the designated device(s).
This data is subject to change without notice and without revision of this document.
ADVANCE INFORMATION
202
Mechanical Data
Copyright 2010 Texas Instruments Incorporated
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
www.ti.com
8.2 Package CYP
CYP (S–PBGA–N841) Plastic Ball Grid Array
ADVANCE INFORMATION
Figure 8-1
Copyright 2010 Texas Instruments Incorporated
Mechanical Data
203
PACKAGE OPTION ADDENDUM
www.ti.com
6-Nov-2010
PACKAGING INFORMATION
Orderable Device
TMX320C6670CYP
Status
(1)
ACTIVE
Package Type Package
Drawing
FCBGA
CYP
Pins
Package Qty
841
1
Eco Plan
TBD
(2)
Lead/
Ball Finish
Call TI
MSL Peak Temp
(3)
Samples
(Requires Login)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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Addendum-Page 1
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