8M x 36-Bit EDO - DRAM Module HYM 368025S/GS-50/-60 • SIMM modules with 8 388 608 words by 36-bit organization in two banks for PC main memory applications • Fast access and cycle time 50 ns access time 84 ns cycle time (-50 version) 60 ns access time 104 ns cycle time (-60 version) • Hyper Page Mode (EDO) capability 20 ns cycle time (-50 version) 25 ns cycle time (-60 version) • Single + 5 V (± 10 %) supply • Low power dissipation max. 6820 mW active (-50 version) max. 6160 mW active (-60 version) CMOS – 132 mW standby TTL –264 mW standby • CAS-before-RAS refresh RAS-only-refresh Hidden-refresh • Decoupling capacitors mounted on substrate • All inputs, outputs and clocks fully TTL compatible • 72 pin Single in-Line Memory Module (L-SIM-72-14) with 31.75 mm height • Utilizes sixteen 4Mx4-EDO-DRAMs and eight 4M x 1 EDO-DRAMs in 300 mil wide SOJ packages • 2048 refresh cycles / 32 ms • Optimized for use in byte-write parity applications • Tin-Lead contact pads (S- version) • Gold contact pads (GS - version) Semiconductor Group 1 4.97 HYM 368025S/GS-50/-60 8M × 36-Bit EDO-Module The HYM 368025S/GS-50/-60 is a 32 MByte DRAM module organized as 8 388 608 words by 36Bit in two banks in a 72-pin single-in-line package comprising sixteen HYB 5117405BJ 4M × 4 EDO-DRAMs and eight HYB 514105BJ 4M x 1 EDO-DRAMs in 300 mil wide SOJ-packages mounted together with decoupling capacitors on a PC board. Each HYB 5117405BJ and HYB 514105BJ is described in the data sheet and is fully electrical tested and processed according to SIEMENS standard quality procedure prior to module assembly. After assembly onto the board, a further set of electrical tests is performed. The speed of the module can be detected by the use of four presence detect pins. The common I/O feature on the HYM 368025S/GS-50/-60 dictates the use of early write cycles. Ordering Information Type Package Description HYM 368025S-50 L-SIM-72-14 EDO-DRAM Module (access time 50 ns) HYM 368025S-60 L-SIM-72-14 EDO-DRAM Module (access time 60 ns) HYM 368025GS-50 L-SIM-72-14 EDO-DRAM Module (access time 50 ns) HYM 368025GS-60 L-SIM-72-14 EDO-DRAM Module (access time 60 ns) Semiconductor Group Ordering Code 2 HYM 368025S/GS-50/-60 8M × 36-Bit EDO-Module Pin Configuration Pin Names VSS 1 DQ0 2 DQ18 3 DQ1 4 DQ19 5 DQ2 6 DQ20 7 DQ3 8 DQ21 9 VCC 10 N.C. 11 A0 12 A1 13 A2 14 A3 15 A4 16 A5 17 A6 18 A10 19 DQ4 20 DQ22 21 DQ5 22 DQ23 23 DQ6 24 DQ24 25 DQ7 26 DQ25 27 A7 28 N.C. 29 VCC 30 A8 31 A9 32 RAS3 33 RAS2 34 DQ26 35 DQ8 36 DQ17 37 DQ35 38 VSS 39 CAS0 40 CAS2 41 CAS3 42 CAS1 43 RAS0 44 RAS1 45 N.C. 46 WE 47 N.C. 48 DQ9 49 DQ27 50 DQ10 51 DQ28 52 DQ11 53 DQ29 54 DQ12 55 DQ30 56 DQ13 57 DQ31 58 VCC 59 DQ32 60 DQ14 61 DQ33 62 DQ15 63 DQ34 64 DQ16 65 N.C. 66 PD0 67 PD1 68 PD2 69 PD3 70 N.C. 71 VSS 72 Semiconductor Group A0-A10 Address Inputs DQ0-DQ35 Data Input/Output CAS0 - CAS3 Column Address Strobe RAS0- RAS3 Row Address Strobe WE Read/Write Input VCC Power (+ 5 V) VSS Ground PD Presence Detect Pin N.C. No Connection Presence Detect Pins 3 -50 -60 PD0 N.C. N.C. PD1 VSS VSS PD2 VSS N.C. PD3 VSS N.C. HYM 368025S/GS-50/-60 8M × 36-Bit EDO-Module RAS0 RAS1 CAS0 DQ0-DQ3 DQ4-DQ7 CAS RAS I/O1-I/O4 OE D0 CAS RAS I/O1-I/O4 OE D1 CAS RAS I/O1-I/O4 OE D3 CAS RAS I/O1-I/O4 D2 OE Di Do DQ8 CAS RAS Di Do M0 CAS RAS M1 CAS1 DQ9-DQ12 CAS RAS I/O1-I/O4 OE D4 CAS RAS I/O1-I/O4 OE D5 DQ13-DQ16 CAS RAS I/O1-I/O4 OE D7 CAS RAS I/O1-I/O4 D6 OE DQ17 Di Do CAS RAS Di Do M2 CAS RAS M3 RAS3 RAS2 CAS2 DQ18-DQ21 DQ22-DQ25 DQ26 CAS RAS I/O1-I/O4 OE D8 CAS RAS I/O1-I/O4 OE D9 CAS RAS I/O1-I/O4 OE D11 CAS RAS I/O1-I/O4 D10 OE Di Do CAS3 CAS RAS Di Do M4 CAS RAS M5 DQ27-DQ30 CAS RAS I/O1-I/O4 OE D12 CAS RAS I/O1-I/O4 OE D13 DQ31-DQ34 CAS RAS I/O1-I/O4 D15 OE CAS RAS I/O1-I/O4 D14 OE DQ35 Di Do A0-A10 WE CAS RAS M6 D0-D15, M0-M7 D0-D15, M0-M7 Block Diagram Semiconductor Group Di Do 4 VCC VSS CAS RAS M7 C0 - C23 HYM 368025S/GS-50/-60 8M × 36-Bit EDO-Module Absolute Maximum Ratings Operation temperature range ......................................................................................... 0 to + 70 °C Storage temperature range......................................................................................... – 55 to 125 °C Input/output voltage ............................................................................ –0.5V to min (Vcc+0.5, 7.0) V Power supply voltage...................................................................................................... – 1 to + 7 V Power dissipation................................................................................................................... 9.24 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 °C, VCC = 5 V ± 10 % Parameter Symbol Limit Values min. Unit max. Test Condition Input high voltage VIH 2.4 Vcc+0.5 V 1) Input low voltage VIL – 0.5 0.8 V 1) Output high voltage ( IOUT = – 5 mA) VOH 2.4 – V 1) Output low voltage ( IOUT = 4.2 mA) VOL – 0.4 V 1) Input leakage current (0 V < VIN < 6.5 V, all other pins = 0 V) II(L) – 20 20 µA 1) Output leakage current (DO is disabled, 0 V < VOUT < 5.5 V) IO(L) – 20 20 µA 1) Average VCC supply current (RAS, CAS, address cycling, tRC = tRC min) -50 version -60 version ICC1 – – 1240 1120 mA mA 2),3),4) Standby VCC supply current (RAS = CAS = VIH) ICC2 – 48 mA Average VCC supply current during RAS only refresh cycles (per bank) (RAS cycling, CAS = VIH, tRC = tRC min) -50 version -60 version ICC3 – – 1240 1120 mA mA Semiconductor Group 5 2),4) HYM 368025S/GS-50/-60 8M × 36-Bit EDO-Module DC Characteristics1) (cont’d) Parameter Symbol Limit Values min. Average VCC supply current during fast page mode (RAS = VIL, CAS, address cycling, tPC = tPC min) -50 version -60 version ICC4 Standby VCC supply current (RAS = CAS = VCC – 0.2 V) ICC5 Average VCC supply current during CASbefore-RAS refresh mode (per bank) (RAS, CAS cycling, tRC = tRC min) -50 version -60 version ICC6 Unit Test Condition max. – – 840 680 mA mA – 24 mA – – 1240 1120 mA mA 2),3),4) 2),4) Capacitance TA = 0 to 70 °C, VCC = 5 V ± 10 %, f = 1 MHz Parameter Symbol Limit Values min. Unit max. Input capacitance (A0 to A10,WE) CI1 – 180 pF Input capacitance (RAS0 - RAS3) CI2 – 50 pF Input capacitance (CAS0 - CAS3) CI3 – 40 pF I/O capacitance (DQ0-DQ35) CIO – 25 pF Semiconductor Group 6 HYM 368025S/GS-50/-60 8M × 36-Bit EDO-Module AC Characteristics 5)6) TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 2 ns Parameter Limit Values Symbol -50 min. Unit Note -60 max. min. max. common parameters Random read or write cycle time tRC 84 – 104 – ns RAS precharge time tRP 30 – 40 – ns RAS pulse width tRAS 50 10k 60 10k ns CAS pulse width tCAS 8 10k 10 10k ns Row address setup time tASR 0 – 0 – ns Row address hold time tRAH 8 – 10 – ns Column address setup time tASC 0 – 0 – ns Column address hold time tCAH 8 – 10 – ns RAS to CAS delay time tRCD 12 37 14 45 ns RAS to column address delay time tRAD 10 25 12 30 ns RAS hold time tRSH 13 15 – ns CAS hold time tCSH 40 50 – ns CAS to RAS precharge time tCRP 5 – 5 – ns Transition time (rise and fall) tT 1 50 1 50 ns Refresh period tREF – 32 – 32 ms Access time from RAS tRAC – 50 – 60 ns 8, 9 Access time from CAS tCAC – 13 – 15 ns 8, 9 Access time from column address tAA – 25 – 30 ns 8,10 Column address to RAS lead time tRAL 25 – 30 – ns Read command setup time tRCS 0 – 0 – ns Read command hold time tRCH 0 – 0 – ns 11 Read command hold time referenced to RAS tRRH 0 – 0 – ns 11 CAS to output in low-Z tCLZ 0 – 0 – ns 8 Output buffer turn-off delay tOFF 0 13 0 15 ns 12 7 Read Cycle Semiconductor Group 7 HYM 368025S/GS-50/-60 8M × 36-Bit EDO-Module AC Characteristics (cont’d) 5)6) TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 2 ns Parameter Limit Values Symbol -50 min. Unit Note -60 max. min. max. Early Write Cycle Write command hold time tWCH 8 – 10 – ns Write command pulse width tWP 8 – 10 – ns Write command setup time tWCS 0 – 0 – ns Write command to RAS lead time tRWL 13 – 15 – ns Write command to CAS lead time tCWL 13 – 15 – ns Data setup time tDS 0 – 0 – ns 14 Data hold time tDH 8 – 10 – ns 14 Hyper page mode (EDO) cycle time tHPC 20 – 25 – ns CAS precharge time tCP 8 – 10 – ns Access time from CAS precharge tCPA – 27 – 32 ns Output data hold time tCOH 5 – 5 – ns RAS pulse width in hyper page mode tRAS 50 200k 60 200k ns CAS precharge to RAS Delay tRHCP 27 – 32 – ns CAS setup time tCSR 10 – 10 – ns CAS hold time tCHR 10 – 10 – ns RAS to CAS precharge time tRPC 5 – 5 – ns Write to RAS precharge time tWRP 10 – 10 – ns Write hold time referenced to RAS tWRH 10 – 10 – ns 13 Hyper Page Mode (EDO) Cycle CAS before RAS Refresh Cycle Semiconductor Group 8 7 HYM 368025S/GS-50/-60 8M × 36-Bit EDO-Module Notes: 1) All voltages are referenced to VSS. Vil may undershoot to -2.0 V for pulse width of less than or equal to 4 ns. Pulse width is measured at 50% points with amplitude measured peak to the DC reference. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. 4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during a hyper page mode (EDO) cycle. 5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 2 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined by the latter of t RAC, tCAC, tAA,tCPA . tCAC is measured from tristate. . 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 13) tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.) , the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle. 14) These parameters are referenced to the CAS leading edge. Semiconductor Group 9 HYM 368025S/GS-50/-60 8M × 36-Bit EDO-Module Package Outline Dimensions in mm GLS05858 Module Package, L-SIM-72-14 (Single in-Line Memory Module) Semiconductor Group 10