1M × 36-Bit Dynamic RAM Module (2M × 18-Bit Dynamic RAM Module) HYM 361120/40S/GS-60/-70 Advanced Information • 1 048 576 words by 36-bit organization (alternative 2 097 152 words by 18-bit) • 12 decoupling capacitors mounted on substrate • Fast access and cycle time 60 ns access time 110 ns cycle time (-60 version) 70 ns access time 130 ns cycle time (-70 version) • All inputs, outputs and clock fully TTL compatible • 72 pin Single in-Line Memory Module • Utilizes four 1M × 1-DRAMs and eight 1M × 4-DRAMs in 300 mil SOJ packages Fast page mode capability with 40 ns cycle time (-60 version) 45 ns cycle time (-70 version) • 1024 refresh cycles/16 ms • Tin-Lead contact pads (S - version) • Gold contact pads (GS - version) • HYM 321140S: single sided module with 31.75 mm (1250 mil) height • HYM 321120S: double sided module with 25.40 mm (1000 mil) height • • Single + 5 V (± 10 %) supply • Low power dissipation max. 6820 mW active (-60 version) max. 6160 mW active (-70 version) CMOS – 66 mW standby TTL – 132 mW standby • CAS-before-RAS refresh, RAS-only-refresh, Hidden refresh Ordering Information Type Ordering Code Package Descriptions HYM 361140S-60 Q67100-Q959 L-SIM-72-8 DRAM module (access time 60 ns) HYM 361140S-70 Q67100-Q958 L-SIM-72-8 DRAM module (access time 70 ns) HYM 361120S-60 Q67100-Q942 L-SIM-72-3 DRAM module (access time 60 ns) HYM 361120S-70 Q67100-Q741 L-SIM-72-3 DRAM module (access time 70 ns) HYM 361140GS-60 Q67100-Q1019 L-SIM-72-8 DRAM module (access time 60 ns) HYM 361140GS-70 Q67100-Q651 L-SIM-72-8 DRAM module (access time 70 ns) HYM 361120GS-60 Q67100-Q961 L-SIM-72-3 DRAM module (access time 60 ns) HYM 361120GS-70 Q67100-Q960 L-SIM-72-3 DRAM module (access time 70 ns) Semiconductor Group 591 06.94 HYM 361120/40S/GS-60/-70 1M × 36-Bit The HYM 361120/40S/GS-60/-70 is a 4 MByte DRAM module organized as 1 048 576 words by 36-bit in a 72-pin single-in-line package comprising four HYB 511000BJ 1M × 1 DRAMs and eight HYB 514400BJ 1M × 4 DRAMs in 300 mil wide SOJ-packages mounted together with twelve 0.2 µF ceramic decoupling capacitors on a PC board. The HYM 361120/40S/GS-60/-70 can also be used as a 2 097 152 words by 18-bits dynamic RAM module by means of connecting DQ0 and DQ18, DQ1 and DQ19, DQ2 and DQ20, …, DQ17 and DQ35, respectively. Each HYB 511000BJ and HYB 514400BJ is described in the data sheet and is fully electrically tested and processed according to Siemens standard quality procedure prior to module assembly. After assembly onto the board, a further set of electrical tests is performed. The speed of the module can be detected by the use of four presence detect pins. The common I/O feature on the HYM 361120/40S/GS-60/-70 dictates the use of early write cycles. Pin Definitions and Functions Pin No. Function A0-A9 Address Inputs DQ0-DQ35 Data Input/Output CAS0 - CAS3 Column Address Strobe RAS0, RAS2 Row Address Strobe WE Read/Write Input VCC Power (+ 5 V) VSS Ground PD Presence Detect Pin N.C. No Connection Presence Detect Pins -60 -70 PD0 VSS VSS PD1 VSS VSS PD2 N.C. VSS PD3 N.C. N.C. Semiconductor Group 592 HYM 361120/40S/GS-60/-70 1M × 36-Bit Pin Configuration (top view) Semiconductor Group 593 HYM 361120/40S/GS-60/-70 1M × 36-Bit Block Diagram Semiconductor Group 594 HYM 361120/40S/GS-60/-70 1M × 36-Bit Absolute Maximum Ratings Operating temperature range ......................................................................................... 0 to + 70 ˚C Storage temperature range...................................................................................... – 55 to + 125 ˚C Soldering temperature ............................................................................................................ 260 ˚C Soldering time ............................................................................................................................. 10 s Input/output voltage ........................................................................................................ – 1 to + 7 V Power supply voltage...................................................................................................... – 1 to + 7 V Power dissipation................................................................................................................... 8.68 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics 1) TA = 0 to 70 ˚C; VCC = 5 V ± 10 % Parameter Symbol Limit Values min. max. Unit Test Condition Input high voltage VIH 2.4 5.5 V – Input low voltage VIL – 1.0 0.8 V – Output high voltage (IOUT = – 5 mA) VOH 2.4 – V – Output low voltage (IOUT = 4.2 mA) VOL – 0.4 V – Input leakage current (0 V < VIN < 6.5 V, all other pins = 0 V) II(L) – 20 20 µA – Output leakage current (DO is disabled, 0 V < VOUT < 5.5 V) IO(L) – 10 10 µA – Average VCC supply current: ICC1 – – 1240 1120 mA mA 2), 3) – 24 mA – -60 version -70 version (RAS, CAS, address cycling, tRC = tRC min.) Standby VCC supply current (RAS = CAS = VIH) ICC2 Average VCC supply current during RAS ICC3 only refresh cycles: -60 version -70 version (RAS cycling, CAS = VIH , tRC = tRC min.) Semiconductor Group 595 2) – – 1240 1120 mA mA HYM 361120/40S/GS-60/-70 1M × 36-Bit DC Characteristics (cont’d) 1) Parameter Symbol Limit Values min. Average VCC supply current during fast ICC4 page mode: -60 version -70 version Unit max. Test Condition 2), 3) – – 840 720 mA mA – 12 mA (RAS = VIL, CAS, address cycling tPC = tPC min.) Standby VCC supply current (RAS = CAS = VCC – 0.2 V) ICC5 Average VCC supply current during ICC6 CAS-before-RAS refresh mode: -60 version -70 version – 1) – – 1240 1120 mA mA (RAS, CAS cycling, tRC = tRC min.) Capacitance TA = 0 to 70 ˚C; VCC = 5 V ± 10 %; f = 1 MHz Parameter Symbol Limit Values min. max. Unit Input capacitance (A0 to A9) CI1 – 80 pF Input capacitance (RAS0, RAS2) CI2 – 42 pF Input capacitance (CAS0-CAS3) CI3 – 35 pF Input capacitance (WE) CI4 – 80 pF I/O capacitance (DQ0-DQ7, DQ9-DQ16, DQ18-DQ25, DQ27-DQ34) CIO1 – 15 pF I/O capacitance (DQ8, DQ17, DQ26, DQ35) CIO2 – 20 pF Semiconductor Group 596 HYM 361120/40S/GS-60/-70 1M × 36-Bit AC Characteristics 4) 5) TA = 0 to 70 ˚C; VCC = 5 V ± 10 %; tT = 5 ns Parameter Symbol Limit Values HYM 361120/40S/GS-60 Unit HYM 361120/40S/GS-70 min. max. min. max. Random read or write cycle time tRC 110 – 130 – ns Fast page mode cycle time tPC 40 – 45 – ns Access time from RAS 6) 11) 12) tRAC – 60 – 70 ns Access time from CAS 6) 11) tCAC – 15 – 20 ns tAA – 30 – 35 ns tCPA – 35 – 40 ns Access time from column address 6) 12) Access time from CAS prech arge 6) CAS to output in low-Z 6) tCLZ 0 – 0 – ns Output buffer turn-off delay 7) tOFF 0 20 0 20 ns Transition time (rise and fall) 5) tT 3 50 3 50 ns RAS precharge time tRP 40 – 50 – ns RAS pulse width tRAS 60 10000 70 10000 ns RAS pulse width tRASP 60 200000 70 200000 ns CAS precharge to RAS delay tRHCP 35 – 40 – ns RAS hold time tRSH 15 – 20 – ns CAS hold time tCSH 60 – 70 – ns tCAS 15 10000 20 10000 ns tRCD 20 45 20 50 ns tRAD 15 30 15 35 ns CAS to RAS precharge time tCRP 5 – 5 – ns CAS precharge time (fast page mode) tCP 10 – 10 – ns Row address setup time tASR 0 – 0 – ns Row address hold time tRAH 10 – 10 – ns Column address setup time tASC 0 – 0 – ns Column address hold time tCAH 15 – 15 – ns (fast page mode) CAS pulse width RAS to CAS delay time RAS to column address delay time 11) 12) . Semiconductor Group 597 HYM 361120/40S/GS-60/-70 1M × 36-Bit AC Characteristics (cont’d) 4) 5) TA = 0 to 70 ˚C; VCC = 5 V ± 10 %; tT = 5 ns Parameter Symbol Limit Values HYM 361120/40S/GS-60 Unit HYM 361120/40S/GS-70 min. max. min. max. 30 – 35 – ns tRCS 0 – 0 – ns tRCH 0 – 0 – ns tRRH 0 – 0 – ns Write command hold time tWCH 10 – 15 – ns Write command pulse width tWP 10 – 15 – ns Write command to RAS lead time tRWL 15 – 20 – ns Write command to CAS lead time tCWL 15 – 20 – ns Column address to RAS lead time tRAL Read command setup time Read command hold time Read command hold time ref. to RAS 8) 8) Data setup time 9) tDS 0 – 0 – ns Data hold time 9) tDH 15 – 15 – ns tREF – 16 – 16 ms Write command setup time 10) tWCS 0 – 0 – ns CAS setup time 13) tCSR 5 – 5 – ns CAS hold time 13) tCHR 15 – 15 – ns Refresh period tRPC 0 – 0 – ns CAS precharge time 13) tCP 10 – 10 – ns Write to RAS precharge time 13) tWRP 10 – 10 – ns Write to time ref. to RAS 13) tWRH 10 – 10 – ns RAS to CAS precharge time . Semiconductor Group 598 HYM 361120/40S/GS-60/-70 1M × 36-Bit Notes 1) All voltages are referenced to VSS . 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles out of which at least one cycle has to be a refresh cycle before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 5) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL . 6) Measured with a load equivalant of 2 TTL loads and 100 pF. 7) tOFF (max.) defines the time at which the output achieves the open-circuit condition and is not referenced to output voltage levels. 8) Either tRCH or tRRH must be satisfied for a read cycle. 9) These parameters are referenced to the CAS leading edge. 10) tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristic only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance). 11) Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 12) Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 13) For CAS-before-RAS cycles only. Semiconductor Group 599