3.3V 2M × 64-Bit EDO-DRAM Module 3.3V 2M x 72-Bit EDO-DRAM Module HYM64V2005GU-50/-60 HYM72V2005GU-50/-60 168pin unbuffered DIMM Module with serial presence detect • 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual In-Line Memory Module for PC main memory applications • 1 bank 2M x 64, 2M x 72 organisation • Optimized for byte-write non-parity or ECC applications • Extended Data Out (EDO) • Performance: -50 -60 tRAC RAS Access Time 50 ns 60 ns tCAC CAS Access Time 13 ns 15 ns tAA Access Time from Address 25 ns 30 ns tRC Cycle Time 84 ns 104 ns tHPC EDO Mode Cycle Time 20 ns 25 ns • Single +3.3 V ± 0.3 V Power Supply • CAS-before-RAS refresh, RAS-only-refresh • Decoupling capacitors mounted on substrate • All inputs, outputs and clocks are fully LV-TTL compatible • Serial presence detects (optional) • Utilizes 2M × 8 -DRAMs in SOJ packages • 2048 refresh cycles / 32 ms with 11 / 10 addressing (Row / Column) • Gold contact pad • Card Size: 133,35mm x 25,40 mm x 5,30 mm • This DRAM product module family is intended to be fully pin and architecture compatible with the 168pin unbuffered SDRAM DIMM module family Semiconductor Group 1 2.97 HYM 64(72)V2005GU-50/-60 2M x 64/72 DRAM Module The HYM64(72)V2005GU-50/-60 are industry standard 168-pin 8-byte Dual In-Line Memory Modules (DIMMs) which are organized as 2M x 64 and 2M x 72 high speed memory arrays designed with EDO DRAMs for non-parity and ECC applications. The DIMMs use eight 2M x 8 EDO DRAMs for the 2M x 64 organisation and nine 2M x 8 DRAMs for the 2M x 72 organisation, both in SOJ packages. Decoupling capacitors are mounted on the PC board. The DIMMs use optional serial presence detects implemented via a serial E 2PROM using the two pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes of serial PD data are available to the customer. All 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133,35 mm long spacesaving footprint. Ordering Information Type Ordering Code Package Descriptions HYM 64V2005GU-50 Q67100-Q2180 L-DIM-168-11 2M x 64 DRAM module (access time 50 ns) HYM 64V2005GU-60 Q67100-Q2181 L-DIM-168-11 2M x 64 DRAM module (access time 60 ns) HYM 72V2005GU-50 Q67100-Q2182 L-DIM-168-11 2M x 72 DRAM module (access time 50 ns) HYM 72V2005GU-60 Q67100-Q2183 L-DIM-168-11 2M x 72 DRAM module (access time 60 ns) Pin Names A0-A10 A0-A9 DQ0 - DQ63 CB0-CB7 RAS0, RAS2 CAS0 - CAS7 WE0, WE2 OE0, OE2 Vcc Vss SCL SDA SA0-SA2 N.C. DU Semiconductor Group Row Address Input Column Address Input Data Input/Output Check Bit Data Input/Output ( x72 only) Row Address Strobe Column Address Strobe Read / Write Input Output Enable Power (+3.3 Volt) Ground Clock for Presence Detect Serial Data Out for Presence Detect Serial Presence Detect Addresses No Connection Don’t use 2 HYM 64(72)V2005GU-50/-60 2M x 64/72 DRAM Module Pin Configuration PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Symbol VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS NC NC VCC WE0 CAS0 CAS1 RAS0 OE0 VSS A0 A2 A4 A6 A8 A10 NC VCC VCC DU Semiconductor Group PIN # 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Symbol PIN # VSS OE2 RAS2 CAS2 CAS3 WE2 VCC NC NC CB3 CB3 VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC DU NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS NC NC NC SDA SCL VCC 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 3 Symbol VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 CB5 VSS NC NC VCC DU CAS4 CAS5 NC DU VSS A1 A3 A5 A7 A9 NC NC VCC DU DU PIN # 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Symbol VSS DU NC CAS6 CAS7 DU VCC NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC DU NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS NC NC SA0 SA1 SA2 VCC HYM 64(72)V2005GU-50/-60 2M x 64/72 DRAM Module RAS2 RAS0 WE0 WE2 OE2 OE0 CAS0 DQ0-DQ7 CAS4 DQ32-DQ39 I/O1-I/O8 I/O1-I/O8 D0 CAS1 DQ8-DQ15 D4 CAS5 DQ40-DQ47 I/O1-I/O8 I/O1-I/O8 D1 CAS6 CAS2 DQ16-DQ23 D5 DQ48-DQ55 I/O1-I/O8 I/O1-I/O8 D6 D2 CAS7 CAS3 DQ24-DQ31 DQ56-DQ63 I/O1-I/O8 I/O1-I/O8 D7 D3 A0-A10 E2PROM (256wordx8bit) D0-D7 VCC SA0 SA1 SA2 C0-C7 VSS 2M x 64 DIMM Module Block Diagram Semiconductor Group 4 SCL SDA HYM 64(72)V2005GU-50/-60 2M x 64/72 DRAM Module RAS2 RAS0 WE0 OE0 WE2 OE2 CAS0 CAS4 DQ0-DQ7 DQ32-DQ39 I/O1-I/O8 I/O1-I/O8 D0 CAS1 DQ8-DQ15 D4 CAS5 DQ40-DQ47 I/O1-I/O8 I/O1-I/O8 D1 D5 CAS6 CB0-CB7 I/O1-I/O8 DQ48-DQ55 I/O1-I/O8 D8 CAS2 DQ16-DQ23 D6 CAS7 I/O1-I/O8 DQ56-DQ63 I/O1-I/O8 D2 D7 CAS3 DQ24-DQ31 I/O1-I/O8 D3 A0-A10 E2PROM (256wordx8bit) D0-D8 VCC SA0 SA1 SA2 C0-C8 VSS 2M x 72 DIMM Module Block Diagram Semiconductor Group 5 SCL SDA HYM 64(72)V2005GU-50/-60 2M x 64/72 DRAM Module TRUTH TABLE FUNCTION RAS CAS WRITE OE ROW ADDR COL ADDR DQ0-DQ63 Standby H X X X X X High Impedance Read L L H L ROW COL Data Out Early-Write L L L X ROW COL Data In Late-Write L L H-L H ROW COL Data In Read-Modify-Write (RMW) L L H-L L-H ROW COL Data Out, Data In 1st Cycle L H-L H L ROW COL Data Out 2nd Cycle L H-L H L n/a COL Data Out 1st Cycle L H-L L X ROW COL Data In 2nd Cycle L H-L L X n/a COL Data In 1st Cycle L H-L H-L L-H ROW COL Data Out, Data In 2st Cycle L H-L H-L L-H n/a COL Data Out, Data In L H X X ROW n/a High Impedance H-L L H X X n/a High Impedance READ L-H-L L H L ROW COL Data Out WRITE L-H-L L L X ROW COL Data In H-L L H X X X High Impedance EDO Page Mode Read EDO Page Mode Write EDO Page Mode RMW RAS only refresh CAS-before-RAS refresh Hidden Refresh Self Refresh Semiconductor Group 6 HYM 64(72)V2005GU-50/-60 2M x 64/72 DRAM Module Absolute Maximum Ratings Operating temperature range ......................................................................................... 0 to + 70 °C Storage temperature range...................................................................................... – 55 to + 125 °C Input/output voltage .............................................................................. –0.5 to min (Vcc+0.5, 4.6) V Power supply voltage.................................................................................................... –0.5 to 4.6 V Power dissipation.................................................................................................................. 4.97 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 °C; VCC = 3.3 V ± 0.3 V Parameter Symbol x 64/ x72 min. Unit Notes max. Input high voltage VIH 2.0 Input low voltage VIL – 0.5 0.8 V 1) Output high voltage (LVTTL) Output „H“level voltage ( IOUT = – 2 mA) VOH 2.4 – V 1) Output low voltage (LVTTL) Output „L“ level voltage ( IOUT = + 2 mA) VOL – 0.4 V 1) Output high voltage (LVCMOS) Output „H“level voltage ( IOUT =– 100µA) VOH Vcc-0.2 – V 1) Output low voltage (LVCMOS) Output „L“ level voltage ( IOUT =+100 µA) VOL – 0.4 V 1) Input leakage current (0 V < VIN < Vcc, all other pins = 0 V) II(L) – 10 10 µA 1) Output leakage current (DO is disabled, 0 V < VOUT < Vcc) IO(L) – 10 +10 µA 1) Semiconductor Group 7 Vcc + 0.5 V 1) HYM 64(72)V2005GU-50/-60 2M x 64/72 DRAM Module DC Characteristics (cont’d) TA = 0 to 70 °C; VCC = 3.3 V ± 0.3 V Parameter Symbol Average VCC supply current: x 64 x 72 max. Unit Note s min. max. min. – – 960 880 – – 1080 990 mA mA 2) 3) – 16 – 18 mA – ICC1 -50 version -60 version 4) (RAS, CAS, address cycling, tRC = tRC min.) Standby VCC supply current ICC2 (RAS = CAS = VIH, one address change) Average VCC supply current during RAS ICC3 only refresh cycles: -50 version -60 version 2) 4) – – 960 880 – – 1080 990 mA mA – – 320 280 – – 360 315 mA mA 2) 3) ICC5 – 8 – 9 mA – ICC6 Average VCC supply current during CAS-before-RAS refresh mode: -50 version -60 version – – 960 880 – – 1080 990 mA mA 2) 4) (RAS cycling, CAS = VIH , t RC = tRC min.) Average VCC supply current during ICC4 hyper page mode (EDO): -50 version -60 version 4) (RAS = VIL, CAS, address cycling tPC = tPC min.) Standby VCC supply current (RAS = CAS = VCC – 0.2 V, one address change) (RAS, CAS cycling, tRC = tRC min.) Semiconductor Group 8 HYM 64(72)V2005GU-50/-60 2M x 64/72 DRAM Module AC Characteristics 5)6) TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, tT = 2 ns Parameter 16E Limit Values Symbol -50 Unit Note -60 min. max. min. max. common parameters Random read or write cycle time tRC 84 – 104 – ns RAS precharge time tRP 30 – 40 – ns RAS pulse width tRAS 50 10k 60 10k ns CAS pulse width tCAS 8 10k 10 10k ns Row address setup time tASR 0 – 0 – ns Row address hold time tRAH 8 – 10 – ns Column address setup time tASC 0 – 0 – ns Column address hold time tCAH 8 – 10 – ns RAS to CAS delay time tRCD 12 37 14 45 ns RAS to column address delay tRAD 10 25 12 30 ns RAS hold time tRSH 13 15 – ns CAS hold time tCSH 40 50 – ns CAS to RAS precharge time tCRP 5 – 5 – ns Transition time (rise and fall) tT 1 50 1 50 ns Refresh period tREF – 32 – 32 ms Access time from RAS tRAC – 50 – 60 ns 8, 9 Access time from CAS tCAC – 13 – 15 ns 8, 9 Access time from column address tAA – 25 – 30 ns 8,10 OE access time tOEA – 13 – 15 ns Column address to RAS lead time tRAL 25 – 30 – ns Read command setup time tRCS 0 – 0 – ns Read command hold time tRCH 0 – 0 – ns 11 Read command hold time referenced to tRRH RAS 0 – 0 – ns 11 CAS to output in low-Z tCLZ 0 – 0 – ns 8 Output buffer turn-off delay tOFF 0 13 0 15 ns 12 Output turn-off delay from OE tOEZ 0 13 0 15 ns 12 7 Read Cycle Semiconductor Group 9 HYM 64(72)V2005GU-50/-60 2M x 64/72 DRAM Module AC Characteristics (cont’d) 5)6) TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, tT = 2 ns Parameter 16E Limit Values Symbol -50 Unit Note -60 min. max. min. max. Data to CAS low delay tDZC 0 – 0 – ns 13 Data to OE low delay tDZO 0 – 0 – ns 13 CAS high to data delay tCDD 10 – 13 – ns 14 OE high to data delay tODD 10 – 13 – ns 14 Write command hold time tWCH 8 – 10 – ns Write command pulse width tWP 8 – 10 – ns Write command setup time tWCS 0 – 0 – ns Write command to RAS lead time tRWL 13 – 15 – ns Write command to CAS lead time tCWL 13 – 15 – ns Data setup time tDS 0 – 0 – ns 16 Data hold time tDH 8 – 10 – ns 16 Read-write cycle time tRWC 113 – 138 – ns RAS to WE delay time tRWD 64 – 77 – ns 15 CAS to WE delay time tCWD 27 – 32 – ns 15 Column address to WE delay time tAWD 39 – 47 – ns 15 OE command hold time tOEH 10 – 13 – ns Hyper page mode (EDO) cycle time tHPC 20 – 25 – ns CAS precharge time tCP 8 – 10 – ns Access time from CAS precharge tCPA – 27 – 32 ns Output data hold time tCOH 5 – 5 – ns RAS pulse width in EDO mode tRAS 50 200k 60 200k ns CAS precharge to RAS Delay tRHPC 27 – 32 – ns OE setup time prior to CAS tOES Write Cycle 15 Read-modify-Write Cycle Hyper Page Mode (EDO) Cycle Semiconductor Group 5 10 – 5 – ns 7 HYM 64(72)V2005GU-50/-60 2M x 64/72 DRAM Module AC Characteristics (cont’d) 5)6) TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, tT = 2 ns Parameter 16E Limit Values Symbol -50 min. Unit Note -60 max. min. max. Hyper Page Mode (EDO) Read-modify-Write Cycle Hyper page mode (EDO) read-write cycle time tPRWC 58 – 68 – ns CAS precharge to WE tCPWD 41 – 49 – ns CAS setup time tCSR 10 – 10 – ns CAS hold time tCHR 10 – 10 – ns RAS to CAS precharge time tRPC 5 – 5 – ns Write to RAS precharge time tWRP 10 – 10 – ns Write hold time referenced to RAS tWRH 10 – 10 – ns CAS-before-RAS Refresh Cycle Capacitance TA = 0 to 70 °C; VCC = 3.3 V ± 0.3 V; f = 1 MHz Parameter Symbol Limit Values min. max. Unit Input Capacitance (A0 to A9) CI1 – 55 pF Input Capacitance (RAS0, RAS2) CI2 – 50 pF Input Capacitance (CAS0-CAS7) CI3 – 10 pF Input Capacitance (WE0,WE2,OE0,OE2) CI4 – 50 pF I/O Capacitance (DQ0-DQ63,CB0-CB8) CIO1 – 11 pF Input Capacitance (SCL, SA0-2) Cs – 8 pF Input/Output Capacitance (SDA) Cs – 10 pF Semiconductor Group 11 HYM 64(72)V2005GU-50/-60 2M x 64/72 DRAM Module Notes: 1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. 4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during a hyper page mode (EDO) cycle 5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 2 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined by the latter of t RAC, tCAC, tAA,tCPA ,tOEA. t CAC is measured from tristate. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.), tOEZ (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 13) Either tDZC or tDZO must be satisfied. 14) Either tCDD or tODD must be satisfied. 15) tWCS , tRWD , tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.) , the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.) , tCWD > tCWD (min.) and tAWD > tAWD (min.) , the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate. 16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. Semiconductor Group 12 HYM 64(72)V2005GU-50/-60 2M x 64/72 DRAM Module Serial Presence Detects: A serial presence detect storage device -- EEPROM 24C02 -- is assembled on to the module. Information about the modul confuguration, speed, etc. is written into the EEPROM device during module production using a serial presence detect protocol ( I 2C synchronous 2-wire bus). Hex HYM Byte# Description SPD Entry Value 64 V2005 GU-50 0 Number of SPD bytes 128 80 1 Total bytes in Serial PD 256 08 2 Memory Type EDO 02 3 Number of Row Addresses 11 0B 4 Number of Column Addresses 10 0A 5 Number of DIMM Banks 1 01 6 Module Data Width x64 / x72 40 7 Module Data Width (cont’d) 0 00 8 Module Interface Levels LVTTL 01 9 RAS access time 50 / 60 ns 32 10 CAS access time 13 / 15 ns 0D 11 Dimm Config (Error Det/Corr.) none / ECC 00 12 Refresh Rate/Type normal 00 15.6µs 13 Primary DRAM data width x8 08 14 Error checking DRAM data width none / x 8 00 15-31 reserved for future offerings FF 32 Superset Memory Type NA FF 33-61 Superset information (may be used in NA FF future) 62 SPD Revision Designator Rev. 1.0 01 63 Checksum for bytes 0-62 0C 64-127 Manufacturer Information (optional) FF 128- Unused Storage Locations FF 255 Semiconductor Group 13 64 V2005 GU-60 80 08 02 0B 0A 01 40 00 01 3C 0F 00 00 72 V2005 GU-50 80 08 02 0B 0A 01 48 00 01 32 0D 02 00 72 V2005 GU-60 80 08 02 0B 0A 01 48 00 01 3C 0F 02 00 08 00 FF FF FF 08 08 FF FF FF 08 08 FF FF FF 01 06 FF FF 01 XX FF FF 01 18 FF FF HYM 64(72)V2005GU-50/-60 2M x 64/72 DRAM Module L-DIM-168-11 Module package (168 pin, dual read-out, single in-line memory module) 133,35 5,3 3,0 1 10 11 40 84 41 25,40 * 17,78 127,35 42,18 66,68 85 A B 94 95 124 C 125 168 * On x72 only (CB0-CB7) 6,35 6,35 2,0 Detail A 1,0 + - 0.5 2,54 min. 3,125 3,125 1,27 2,0 0,2+- 0,15 Detail C Detail B DM168-11.WMF preliminary drawing Semiconductor Group 14