Hex-Half-Bridge / Double Six-Driver TLE 6208-6 G Data Sheet 1 Overview 1.1 Features • • • • • • • • • • • • • • SPT 4 Six High-Side and six Low-Side-Drivers Free configurable as switch, halfbridge or H-bridge Optimized for DC motor management applications 0.6 A continuous (1 A peak) current per switch RDS ON; typ. 0.8 Ω, @ 25 °C per switch Outputs fully short circuit protected with diagnosis Overtemperature-Protection with hysteresis and diagnosis Temperature prewarning Standard SPI-Interface Very low current consumption (typ. 10 µA, @ 25 °C) in stand-by (Inhibit) mode Over- and Undervoltage-Lockout CMOS/TTL compatible inputs with hysteresis Internal clamp diodes Enhanced power P-DSO-Package P-DSO-28-6 Enhanced Power Type Ordering Code Package TLE 6208-6 G Q67007-A9462 P-DSO-28-6 Functional Description The TLE 6208-6 G is a fully protected Hex-Half-Bridge-Driver designed specifically for automotive and industrial motion control applications. The part is based on Infineons Smart Power Technology SPT® which allows bipolar and CMOS control circuitry in accordance with DMOS power devices existing on the same monolithic circuitry. The six low and high side drivers are freely configurable and can be controlled separately. Therefore all kind of loads can be combined. In motion control up to 5 actuators (DCMotors) can be connected to the 6 halfbridge-outputs (cascade configuration). Operation modes forward (cw), reverse (ccw), brake and high impedance are controlled from a standard SPI-Interface. The possibility to control the outputs via software from a central logic, allows limiting the power dissipation. So the standard P-DSO-28-6-package meets the application requirements and saves PCB-Board-space and cost. Furthermore the build-in features like Over- and Undervoltage-Lockout, OverTemperature-Protection and the very low quiescent current in stand-by mode opens a wide range of automotive- and industrial-applications. Data Sheet 1 2001-11-15 TLE 6208-6 G 1.2 Pin Configuration (top view) P-DSO-28-6 Figure 1 Data Sheet 2 2001-11-15 TLE 6208-6 G 1.3 Pin Definitions and Functions Pin No. Symbol Function 1 OUTL5 Low-Side-Output 5; Power-MOS open drain with internal reverse diode; no internal clamp diode or active zenering; short circuit protected and open load controlled. 2 OUTH5 High-Side-Output 5; Power-MOS open source with internal reverse diode; no internal clamp diode or active zenering; short circuit protected and open load controlled. 3 OUTH4 High-Side-Output 4; see pin2. 4 OUTL4 Low-Side-Output 4; see pin1. 5 VS Power supply; external connection to pin 10 necessary; needs a blocking capacitor as close as possible to GND Value: 22 µF electrolytic in parallel to 220 nF ceramic. 6, 7, 8, 9 GND Ground; Reference potential; internal connection to pin 20, 21, 22 and 23; cooling tab; to reduce thermal resistance; place cooling areas on PCB close to this pins. 10 VS Power Supply; see pin 5. 11 OUTL3 Low-Side-Output 3; see pin1. 12 OUTH3 High-Side-Output 3; see pin2. 13 OUTH2 High-Side-Output 2; see pin2. 14 OUTL2 Low-Side-Output 2; see pin1. 15 OUTH1 High-Side-Output 1; see pin2. 16 OUTL1 Low-Side-Output 1; see pin1. 17 INH Inhibit input; has an internal pull down; device is switched in standby condition by pulling the INH terminal low. 18 DO Serial-Data-Output; this 3-state output transfers diagnosis data to the control device; the output will remain 3-stated unless the device is selected by a low on Chip-Select-Not (CSN); see Table 2 for Diagnosis protocol. 19 VCC Logic supply voltage; needs a blocking capacitor as close as possible to GND; Value: 10 µF electrolytic in parallel to 220 nF ceramic. Data Sheet 3 2001-11-15 TLE 6208-6 G 1.3 Pin Definitions and Functions (cont’d) Pin No. Symbol Function 20, 21, 22, 23 GND Ground 24 CSN Chip-Select-Not input; CSN is an active low input; serial communication is enabled by pulling the CSN terminal low; CSN input should only be transitioned when CLK is low; CSN has an internal active pull up and requires CMOS logic level inputs. 25 CLK Serial clock input; clocks the shiftregister; CLK has an internal active pull down and requires CMOS logic level inputs. 26 DI Serial data input; receives serial data from the control device; serial data transmitted to DI is an 16bit control word with the Least Significant Bit (LSB) being transferred first: the input has an active pull down and requires CMOS logic level inputs; DI will accept data on the falling edge of CLK-signal; see Table 1 for input data protocol. 27 OUTL6 Low-Side-Output 6; see pin1. 28 OUTH6 High-Side-Output 6; see pin2. Data Sheet 4 2001-11-15 TLE 6208-6 G 1.4 Functional Block Diagram Figure 2 Block Diagram Data Sheet 5 2001-11-15 TLE 6208-6 G 1.5 Circuit Description Figure 2 shows a block schematic diagram of the module. There are 6 halfbridge drivers on the right-hand side. An HS driver and an LS driver are combined to form a halfbridge driver in each case. The drivers communicate via the internal data bus with the logic and the other control and monitoring functions: undervoltage (UV), overvoltage (OV), overtemperature (TSD), charge pump and fault detect. Two connection interfaces are provided for supply to the module: All power drivers are connected to the supply voltage VS. These are monitored by overvoltage and undervoltage comparators with hysteresis, so that the correct function can be checked in the application at any time. The logic is supplied by the VCC voltage, typ. with 5 V. The VCC voltage uses an internally generated Power-On Reset (POR) to initialize the module at power-on. The advantage of this system is that information stored in the logic remains intact in the event of shortterm failures in the supply voltage VS. The system can therefore continue to operate following VS undervoltage, without having to be reprogrammed. The “undervoltage” information is stored, and can be read out via the interface. The same logically applies for overvoltage. “Interference spikes” on VS are therefore effectively suppressed. The situation is different in the case of undervoltage on the VCC connection pin. If this occurs, then the internally stored data is deleted, and the output levels are switched to high-impedance status (tristate). The module is initialized by VCC following restart (Power-On Reset = POR). The 16-bit wide programming word or control word (see Table 1) is read in via the DI data input, and this is synchronized with the clock input CLK. The status word appears synchronously at the DO data output (see Table 2). The transmission cycle begins when the chip is selected with the CSN input (H to L). If the CSN input changes from L to H then the word which has been read in becomes the control word. The DO output switches to tristate status at this point, thereby releasing the DO bus circuit for other uses. The INH inhibit input can be used to cut off the complete module. This reduces the current consumption to just a few µA, and results in the loss of any data stored. The output levels are switched to tristate status. The module is reinitialized with the internally generated POR (Power-On Reset) at restart. This feature allows the use of this module in battery-operated applications (vehicle body control applications). Every driver block from DRV 1 to 6 contains a low-side driver and a high-side driver. The output connections have been selected so that each HS driver and LS driver pair can be combined to form a halfbridge by short-circuiting adjacent connections. The full flexibility of the configuration can be achieved by dissecting the halfbridges into “quarter-bridges”. Table 3 shows examples of possible applications. Data Sheet 6 2001-11-15 TLE 6208-6 G When commutating inductive loads, the dissipated power peak can be significantly reduced by activating the transistor located parallel to the internal freewheeling diode. A special, integrated “timer” for power ON/OFF times ensures there is no crossover current at the halfbridge. Figure 3 Configuration Examples for “Quarter Bridges” on the TLE 6208-6 G Data Sheet 7 2001-11-15 TLE 6208-6 G Table 1 Input Data Protocol Table 2 Diagnosis Data Protocol BIT BIT 15 OVLO on/off 15 Power supply fail 14 Underload SD on/off 14 Underload 13 Overcurrent SD on/off 13 Overload 12 HS-Switch 6 12 Status HS-Switch 6 11 LS-Switch 6 11 Status LS-Switch 6 10 HS-Switch 5 10 Status HS-Switch 5 9 LS-Switch 5 9 Status LS-Switch 5 8 HS-Switch 4 8 Status HS-Switch 4 7 LS-Switch 4 7 Status LS-Switch 4 6 HS-Switch 3 6 Status HS-Switch 3 5 LS-Switch 3 5 Status LS-Switch 3 4 HS-Switch 2 4 Status HS-Switch 2 3 LS-Switch 2 3 Status LS-Switch 2 2 HS-Switch 1 2 Status HS-Switch 1 1 LS-Switch 1 1 Status LS-Switch 1 0 Status Register Reset 0 Temp. Prewarning H = ON L = OFF Data Sheet H = ON L = OFF 8 2001-11-15 TLE 6208-6 G Table 3 Fault Result Table Fault Diag.-Bit Result Overcurrent (load) 13 Only the failed output is switched OFF. Function and protection can be deactivated by bit No. 13. Short circuit to GND (high-side-switch) 13 Only the failed output is switched OFF. Function and protection can be deactivated by bit No. 13. Short circuit to VS (low-side-switch) 13 Only the failed output is switched OFF. Function and protection can be deactivated by bit No. 13. Temperature warning 0 Reaction of control device needed. Temperature shut down (SD) – All outputs OFF. Openload 14 Only the failed output is switched OFF. Function can be deactivated by bit No. 14. Underload 14 Only the failed output is switched OFF. Function can be deactivated by bit No. 14. Undervoltage lockout 15 (UVLO) All outputs OFF. Overvoltage lockout (OVLO) All outputs OFF. Function can be deactivated by bit No. 15. 15 H = failure; L = no failure. Data Sheet 9 2001-11-15 TLE 6208-6 G 2 Electrical Characteristics 2.1 Absolute Maximum Ratings Parameter Symbol Limit Values Unit Remarks min. max. VS VS VCC VI – 0.3 40 V – –1 – V – 0.3 5.5 V – 0.3 5.5 V VDO – 0.3 VCC V t < 0.5 s; IS > – 2 A 0 V < VS < 40 V 0 V < VS < 40 V 0 V < VCC < 5.5 V 0 V < VS < 40 V 0 V < VCC < 5.5 V IOUT1-6 – – A internal limited – 1.5 1.5 A – 0.7 0.7 A Voltages Supply voltage Supply voltage Logic supply voltage Logic input voltages (DI, CLK, CSN, INH) Logic output voltage (DO) Currents Output current (cont.), if Bit13 (OCSD) is set. IOUT1-6 Output current (cont.), if Bit13 (OCSD) is deactivated. Output current (peak), if Bit13 (OCSD) is set. IOUT1-6 IOUT1-6 Output current (peak), if Bit13 (OCSD) is deactivated. tP < 50 ms; t = 1 s; – 0.25 0.25 A VDS = 12 V VDS = 20 V VDS = 40 V – – A internal limited –2 2 A – 0.9 0.9 A – 0.3 0.3 A VDS = 12 V VDS = 20 V VDS = 40 V – 40 150 °C – – 50 150 °C – Temperatures Junction temperature Storage temperature Tj Tstg Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Data Sheet 10 2001-11-15 TLE 6208-6 G 2.2 Operating Range Parameter Symbol Limit Values min. Unit Remarks max. Supply voltage VS VUV OFF 40 V After VS rising above VUV ON Supply voltage slew rate d V S / dt – 10 V/µs – Logic supply voltage VCC VS VS VI 4.75 5.50 V – – 0.3 Outputs in tristate – 0.3 VUV ON V VUV OFF V VCC V fCLK Tj – 2 MHz – – 40 150 °C – Rthj-pin RthjA – 25 K/W measured to pin 7 – 65 K/W – Supply voltage increasing Supply voltage decreasing Logic input voltage (DI, CLK, CSN, INH) SPI clock frequency Junction temperature – 0.3 Outputs in tristate – Thermal Resistances Junction pin Junction ambient Data Sheet 11 2001-11-15 TLE 6208-6 G 2.3 Electrical Characteristics 8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max. IS – 10 20 Quiescent current IS – – 40 µA INH = Low; VS = 13.2 V Supply current IS ICC ICC – 2.0 4.0 mA – – 2 10 µA INH = Low – 1.6 3.0 mA SPI not active – 6.5 7.0 V 5.5 6.0 6.6 V – 0.5 – V 34 37 40 V 28 32 36 V – 5.0 – V VS increasing VS decreasing VUV ON – VUV OFF VS increasing VS decreasing VOV OFF – VOV ON Current Consumption Quiescent current Logic-Supply current Logic-Supply current µA INH = Low; VS = 13.2 V; Tj = 25 °C Over- and Under-Voltage Lockout UV-Switch-ON voltage UV-Switch-OFF voltage UV-ON/OFF-Hysteresis OV-Switch-OFF voltage OV-Switch-ON voltage OV-ON/OFF-Hysteresis Data Sheet VUV ON VUV OFF VUV HY VOV OFF VOV ON VOV HY 12 2001-11-15 TLE 6208-6 G 2.3 Electrical Characteristics (cont’d) 8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max. – 0.9 1.3 Ω – 2.0 Ω 2.0 – Ω – 4.0 Ω 0.8 1.2 Ω – 2.0 Ω 2.0 – Ω – 4.0 Ω Outputs OUTH1-6 and OUTL1-6 Static Drain-Source-On Resistance Source (High-Side) IOUT = – 0.5 A Sink (Low-Side) IOUT = 0.5 A RDS ON H RDS ON L – 8 V < VS < 40 V Tj = 25 °C 8 V < VS < 40 V VS OFF < VS ≤ 8 V Tj = 25 °C VS OFF < VS ≤ 8 V 8 V < VS < 40 V Tj = 25 °C 8 V < VS < 40 V VS OFF < VS ≤ 8 V Tj = 25 °C VS OFF < VS ≤ 8 V Note: Values of RDS ON for VS OFF < VS ≤ 8 V are guaranteed by design. Leakage Current Source-Output-Stage 1 to 6 IQLH –1 – – µA Source-Output-Stage 1 to 6 –5 – – µA Sink-Output-Stage 1 to 6 IQLH IQLL – – 1 µA Sink-Output-Stage 1 to 6 IQLL – – 5 µA Data Sheet 13 VOUTH1-6 = 0 V Tj = 25 °C VOUTH1-6 = 0 V VOUTL1-6 = VS Tj = 25 °C VOUTL1-6 = VS 2001-11-15 TLE 6208-6 G 2.3 Electrical Characteristics (cont’d) 8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values min. typ. Unit Test Condition max. Overcurrent Source shutdown threshold Sink shutdown threshold Current limit Shutdown delay time ISDU ISDL IOCL tdSD – 2.0 – 1.5 – 1.0 A – 1.0 1.5 2.0 A – – 3.0 5.0 A sink and source 10 25 50 µs sink and source IOCD tdOC 15 30 50 mA – 200 350 600 µs – – – 100 µs – Open Circuit Detection current Delay time Delay Time from Stand-by to Data In Setup time tset Note: setup time is guarnteed by design Output Delay Times; VS = 13.2 V; RLoad = 25 Ω (device not in stand-by for t > 1 ms) Source (high-side) ON Source (high-side) OFF Sink (low-side) ON Sink (low-side) OFF Dead time H to L Dead time L to H Data Sheet td ON H td OFF H td ON L td OFF L tD HL tD LH – 7.5 12 µs – – 3 6 µs – – 6.5 12 µs – – 2 5 µs – 1.5 – – µs 2.5 – – µs td ON L – td OFF H td ON H – td OFF L 14 2001-11-15 TLE 6208-6 G 2.3 Electrical Characteristics (cont’d) 8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values min. typ. Unit Test Condition max. Output Switching Times; VS = 13.2 V; RLoad = 25 Ω (device not in stand-by for t > 1 ms) Source (high-side) rise-time Source (high-side) fall-time Sink (low-side) fall-time Sink (low-side) rise-time tON H tOFF H tON L tOFF L – 4 8 µs – – 2 3 µs – – 1 3 µs – – 1 2 µs – VFU VFL – 0.9 1.3 V – 0.9 1.3 V IF = 0.5 A IF = 0.5 A VIH VIL VIHY II CI – – 0.7 – 0.2 – – VCC VCC 50 200 500 mV – 10 25 50 µA – 10 15 pF VI = 0.2 × VCC 0 V < VCC < Clamp Diodes Forward Voltage Upper Lower Inhibit Input H-input voltage threshold L-input voltage threshold Hysteresis of input voltage Pull down current Input capacitance – 5.25 V Note: Capacitances are guaranteed by design Data Sheet 15 2001-11-15 TLE 6208-6 G 2.3 Electrical Characteristics (cont’d) 8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max. – – 100 µs – – – 0.7 – 0.2 – – VCC VCC 50 200 500 mV – – 50 – 25 – 10 µA 10 25 50 µA 10 25 50 µA – 10 15 pF VCSN = 0.7 × VCC VDI = 0.2 × VCC VCLK = 0.2 × VCC 0 V < VCC < SPI-Interface Delay Time from Stand-by to Data In Setup time tset Logic Inputs DI, CLK and CSN VIH VIL L-input voltage threshold Hysteresis of input voltage VIHY IICSN Pull up current at pin CSN Pull down current at pin DI IIDI Pull down current at pin CLK IICLK Input capacitance CI H-input voltage threshold at pin CSN, DI or CLK – 5.25 V Note: Capacitances are guaranteed by design Logic Output DO H-output voltage level VDOH VCC VCC – V IDOH = 1 mA IDOL = – 1.6 mA VCSN = VCC 0 V < VDO < VCC VCSN = VCC 0 V < VCC < – 1.0 – 0.7 – 0.2 0.4 V Tri-state leakage current VDOL IDOLK – 10 – 10 µA Tri-state input capacitance CDO – 10 15 pF L-output voltage level 5.25 V Note: Capacitances are guaranteed by design Data Sheet 16 2001-11-15 TLE 6208-6 G 2.3 Electrical Characteristics (cont’d) 8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max. tpCLK tCLKH tCLKL tbef tlead tlag tbeh tDISU tDIHO trIN 1000 – – ns – 500 – – ns – 500 – – ns – 500 – – ns – 500 – – ns – 500 – – ns – 500 – – ns – 250 – – ns – 250 – – ns – – – 200 ns – tfIN – – 200 ns – trDO tfDO tENDO tDISDO tVADO – 50 100 ns – 50 100 ns CL = 100 pF CL = 100 pF – – 250 ns low impedance – – 250 ns high impedance – 100 250 ns VDO < 0.2 VCC; VDO > 0.7 VCC; CL = 100 pF Data Input Timing Clock period Clock high time Clock low time Clock low before CSN low CSN setup time CLK setup time Clock low after CSN high DI setup time DI hold time Input signal rise time at pin DI, CLK and CSN Input signal fall time at pin DI, CLK and CSN Data Output Timing DO rise time DO fall time DO enable time DO disable time DO valid time Data Sheet 17 2001-11-15 TLE 6208-6 G 2.3 Electrical Characteristics (cont’d) 8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max. 120 145 170 °C – Thermal Prewarning and Shutdown Thermal prewarning junction TjPW temperature Temperature prewarning hysteresis ∆T – 30 – K – Thermal shutdown junction temperature TjSD 150 175 200 °C – Thermal switch-on junction temperature TjSO 120 – 170 °C – Temperature shutdown hysteresis ∆T – 30 – K – Ratio of SD to PW temperature TjSD / TjPW 1.05 1.20 – – – Note: Temperatures are guaranteed by design Data Sheet 18 2001-11-15 TLE 6208-6 G 3 Timing Diagrams CSN High to Low & rising edge of CLK: DO is enabled. Status information is transfered to Output Shift Register CSN time CSN Low to High: Data from Shift-Register is transfered to Output Power Switches CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 actual Data DI 0 1 2 3 4 5 _ 6 7 8 0 1 new Data 9 10 11 12 13 14 15 0 + 1 + DI: Data will be accepted on the falling edge of CLK-Signal previous Status DO 0 _ _ 1 _ 2 _ 3 4 _ _ 5 _ 6 _ 7 _ 8 _ 9 actual Status 10 _ _ 11 12 _ 13 _ 14 _ 15 _ 0 1 DO: State will change on the rising edge of CLK-Signal eg. HS1 old Data actual Data Figure 4 Standard Data Transfer Timing CSN High to Low & CLK stays Low: Status information of Data Bit 0 ( Temperature prewarning ) is transfered to DO CSN time CLK DI DI: Data is not accepted DO 0 _ DO: Status information of Data Bit 0 ( Temperature prewarning ) will stay as long as CSN is low Figure 5 Timing for Temperature Prewarning only Data Sheet 19 2001-11-15 TLE 6208-6 G Figure 6 SPI-Input Timing trIN tfIN 70 % CSN 50 % 20 % tdOFF Case 1 IOUT 90% ON State OFF State 50 % 10 % tdON tOFF tON 90 % Case 2 IOUT ON State OFF State 50 % 10 % Figure 7 Turn OFF/ON Time Data Sheet 20 2001-11-15 TLE 6208-6 G trIN tfIN 0.7 VCC CLK 50 % 0.2 VCC trDO 0.7 VCC DO ( low to high ) 0.2 VCC tVADO tfDO 0.7 VCC DO ( high to low ) 0.2 VCC Figure 8 DO Valid Data Delay Time and Valid Time tfIN trIN 0.7 VCC CSN 50 % 0.2 VCC tENDO tDISDO 10 kΩ Ω Pullup to VCC DO tENDO 50 % tDISDO 10 kΩ Ω Pulldown 50 % to GND DO Figure 9 DO Enable and Disable Time Data Sheet 21 2001-11-15 TLE 6208-6 G 4 Application Figure 10 Application Circuit Data Sheet 22 2001-11-15 TLE 6208-6 G 5 Package Outlines GPS05123 P-DSO-28-6 (Plastic Dual Small Outline Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet 23 Dimensions in mm 2001-11-15