STGIPL14K60 IGBT intelligent power module (IPM) 14 A, 600 V, DBC isolated SDIP-38L molded Features ■ 14 A, 600 V 3-phase IGBT inverter bridge including control ICs for gate driving and freewheeling diodes ■ 3.3 V, 5 V, 15 V CMOS/TTL inputs comparators with hysteresis and pull down/pull up resistors ■ Internal bootstrap diode ■ Interlocking function ■ 5 kΩ NTC for temperature control ■ VCE(sat) negative temperature coefficient ■ Short-circuit rugged IGBTs ■ Under-voltage lockout ■ DBC fully isolated package Description ■ Isolation rating of 2500 Vrms/min ■ Smart shut down function ■ Op-amps for advanced current sensing ■ Comparators for fault protection against over current and short-circuit The STGIPL14K60 intelligent power module provides a compact, high performance AC motor drive for a simple and rugged design. It mainly targets low power inverters for applications such as home appliances and air conditioners. It combines ST proprietary control ICs with the most advanced short circuit rugged IGBT system technology. Please refer to dedicated technical note TN0107 for mounting instructions. AM01193v1 Applications ■ 3-phase inverters for motor drives ■ Home appliances, such as washing machines, refrigerators, air conditioners Table 1. SDIP-38L Device summary Order code Marking Package Packaging STGIPL14K60 GIPL14K60 SDIP-38L Tube June 2010 Doc ID 15589 Rev 3 1/21 www.st.com 21 Contents STGIPL14K60 Contents 1 Internal block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . 3 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.1 NTC thermistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1.2 Dead time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/21 Doc ID 15589 Rev 3 STGIPL14K60 Internal block diagram and pin configuration 1 Internal block diagram and pin configuration Figure 1. Internal block diagram Doc ID 15589 Rev 3 3/21 Internal block diagram and pin configuration Table 2. 4/21 STGIPL14K60 Pin description Pin Symbol Description 1 OUTU High side reference output for U phase 2 Vboot U Bootstrap voltage for U phase 3 LINU Low side logic input for U phase 4 HINU High side logic input for U phase 5 OP-U Opamp inverting input for U phase 6 OPOUT U 7 OP+U Opamp non inverting input for U phase 8 CINU Comparator input for U phase 9 OUTV High side reference output for V phase 10 Vboot V Bootstrap voltage for V phase 11 LINV Low side logic input for V phase 12 HINV High side logic input for V phase 13 OP-V Opamp inverting input for V phase 14 OPOUT V 15 OP+V Opamp non inverting input for V phase 16 CINV Comparator input for V phase 17 OUTW High side reference output for W phase 18 Vboot W Bootstrap voltage for W phase 19 LINW Low side logic input for W phase 20 HINW High side logic input for W phase 21 OP-W Opamp inverting input for W phase 22 OPOUT W 23 OP+W Opamp non inverting input for W phase 24 CINW Comparator input for W phase 25 VCC 26 SD / OD 27 GND 28 T2 NTC thermistor terminal 2 29 T1 NTC thermistor terminal 1 30 NW Negative DC input for W phase 31 W W phase output 32 P Positive DC input 33 NV Negative DC input for V phase 34 V V phase output Opamp output for U phase Opamp output for V phase Opamp output for W phase Low voltage power supply Shut down logic input (active low) / open drain (comparator output) Ground Doc ID 15589 Rev 3 STGIPL14K60 Internal block diagram and pin configuration Table 2. Pin description (continued) Pin Symbol 35 P 36 NU Negative DC input for U phase 37 U U phase output 38 P Positive DC input Figure 2. Description Positive DC input Pin layout (bottom view) Marking area Doc ID 15589 Rev 3 5/21 Electrical ratings STGIPL14K60 2 Electrical ratings 2.1 Absolute maximum ratings Table 3. Inverter part Symbol Value Unit Supply voltage applied between P-NU, NV, NW 450 V Supply voltage (surge) applied between P-NU, NV, NW 500 V VCES Collector emitter voltage (VIN(1) = 0) 600 V ± IC(2) Each IGBT continuous collector current at TC = 25°C 14 A Each IGBT pulsed collector current 30 A PTOT Each IGBT total dissipation at TC = 25°C 35 W tscw Short circuit withstand time, VCE = 0.5 V(BR)CES Tj = 125 °C, VCC = Vboot= 15 V, VIN (1)= 0÷5 V 5 µs Value Unit Vboot - 21 to Vboot + 0.3 V VPN VPN(surge) ± ICP (3) Parameter 1. Applied between HINi, LINi and GND for i = U, V, W 2. Calculated according to the iterative formula: T j ( max ) – T C I C ( T C ) = --------------------------------------------------------------------------------------------------------R thj – c × V CE ( sat ) ( max ) ( T j ( max ), I C ( T C ) ) 3. Pulse width limited by max junction temperature Table 4. Control part Symbol 6/21 Parameter VOUT Output voltage applied between OUTU, OUTV, OUTW - GND (VCC = 15 V) VCC Low voltage power supply -0.3 to +21 V VCIN Comparator input voltage -0.3 to VCC +0.3 V Vboot Bootstrap voltage applied between Vboot i - OUTi for i = U, V, W -0,3 to 620 V VIN Logic input voltage applied between HIN, LIN and GND -0.3 to 15 V VSD/OD Open drain voltage -0.3 to 15 V dVout/dt Allowed output slew rate 50 V/ns Doc ID 15589 Rev 3 STGIPL14K60 Electrical ratings Table 5. Total system Symbol VISO Tj 2.2 Parameter Value Unit 2500 V -40 to 125 °C Value Unit Thermal resistance junction-case single IGBT 2.8 °C/W Thermal resistance junction-case single diode 5 °C/W Isolation withstand voltage applied between each pin and heatsink plate (AC voltage, t = 60sec.) Operating junction temperature Thermal data Table 6. Symbol Rth(j-c) Thermal data Parameter Doc ID 15589 Rev 3 7/21 Electrical characteristics 3 STGIPL14K60 Electrical characteristics (Tj = 25 °C unless otherwise specified) Table 7. Inverter part Value Symbol VCE(sat) ICES VF Parameter Test condition Unit Min. Typ. Max. VCC = VBoot = 15 V, VIN(1)= 0 ÷ 5 V, IC = 7 A - 2.1 2.5 VCC = VBoot = 15 V, VIN(1)= 0 ÷ 5 V, IC = 7 A, Tj= 125 °C - Collector-cut off current (VIN(1)=0 “logic state”) VCE = 600 V VCC = Vboot = 15 V - 100 µA Diode forward voltage VIN(1) = 0 “logic state”, IC = 7 A - 2.1 V Collector-emitter saturation voltage V 1.8 Inductive load switching time and energy ton tc(on) toff tc(off) trr Turn-on time Crossover time (on) Turn-off time Crossover time (off) Reverse recovery time VDD = 300 V, VCC = Vboot = 15 V, VIN(1)= 0 ÷ 5 V, IC = 7 A (see Figure 3) - 270 - 130 - 320 - 110 - 130 Eon Turn-on switching losses - 150 Eoff Turn-off switching losses - 90 ns µJ 1. Applied between HINi LINi and GND for i = U, V, W (LIN inputs are active-low). Note: 8/21 ton and toff include the propagation delay time of the internal drive. tC(ON) and tC(OFF) are the switching time of IGBT itself under the internally given gate driving condition. Doc ID 15589 Rev 3 STGIPL14K60 Electrical characteristics Figure 3. Switching time test circuit Figure 4. Switching time definition Doc ID 15589 Rev 3 9/21 Electrical characteristics 3.1 Control part Table 8. Low voltage power supply Symbol Min. Typ. Vcc UV hysteresis 1.2 1.5 V Vcc_thON Vcc UV turn ON threshold 11.5 12.0 V Vcc_thOFF Vcc UV turn OFF threshold 10 10.5 V Vcc_hys Parameter STGIPL14K60 Test conditions Max. Unit Iqccu Undervoltage quiescent supply current VCC = 10 V SD/OD = 5 V; LIN = 5 V; HIN = 0, CIN = 0 450 µA Iqcc Quiescent current Vcc = 15 V SD/OD = 5 V; LIN = 5 V HIN = 0, CIN = 0 3.5 mA Vref Internal comparator (CIN) reference voltage 0.58 mV Table 9. Bootstrapped voltage Max. Unit Symbol Typ. VBS UV hysteresis 1.2 1.5 V VBS_thON VBS UV turn ON threshold 10.6 11.5 V VBS_thOFF VBS UV turn OFF threshold 9.0 10.0 V IQBSU Undervoltage VBS quiescent current VBS = 10 V SD/OD = 5 V; LIN and HIN = 5 V; CIN = 0 70 110 µA IQBS VBS quiescent current VBS = 15 V SD/OD = 5 V; LIN and HIN = 5 V; CIN = 0 150 210 µA Bootstrap driver on resistance LVG ON 120 RDS(on) Table 10. Symbol Test conditions 0.54 Min. VBS_hys Parameter 0.5 Logic inputs Parameter Vil Low logic level voltage Vih High logic level voltage Test conditions Min. Typ. Max. Unit 0.8 V 2.2 IHINh HIN logic “1” input bias current HIN = 15 V IHINl HIN logic “0” input bias current HIN = 0 V ILINl LIN logic “0” input bias current LIN = 0 V ILINh LIN logic “1” input bias current LIN = 15 V ISDh SD logic “1” input bias current SD = 15 V 10/21 Ω Doc ID 15589 Rev 3 V 175 6 120 260 µA 1 µA 20 µA 1 µA 300 µA STGIPL14K60 Table 10. Electrical characteristics Logic inputs (continued) Symbol Parameter Test conditions ISDl SD logic “0” input bias current SD = 0 V Dt Dead time see Figure 8 Table 11. Typ. Max. Unit 3 µA 600 ns OPAMP characteristics (VCC = 15 V) Symbol Parameter Vio Input offset voltage Iio Input offset current Iib Min. Input bias current (1) Test condition Min. Typ. Max. Unit 6 mV 4 40 nA 100 200 nA Vic = 0 V, Vo = 7.5 V Vic = 0 V, Vo = 7.5 V Vicm Input common mode voltage range VOL Low level output voltage RL = 10 kΩ to VCC VOH High level output voltage RL = 10 kΩ to GND 14 14.7 V Source, Vid = +1; Vo = 0 V 16 30 mA Sink, Vid = -1; Vo = VCC 50 80 mA Slew rate Vi = 1 ÷ 4 V; CL = 100 pF; unity gain 2.5 3.8 V/µs GBWP Gain bandwidth product Vo = 7.5 V 8 12 MHz Avd Large signal voltage gain RL = 2 kΩ 70 85 dB SVR Supply voltage rejection ratio vs. VCC 60 75 dB CMRR Common mode rejection ratio 55 70 dB Min. Typ. Io SR Output short circuit current 0 V 75 150 mV 1. The direction of input current is out of the IC. Table 12. Sense comparator characteristics (VCC = 15 V) Symbol Parameter Test conditions Max. Unit Iio Input bias current VCP+ = 1 V - 3 µA Vol Open-drain low-level output voltage Iod = - 3 mA - 0.5 V Comparator delay SD/OD pulled to 5 V through 100 kΩ resistor - 90 130 ns Slew rate CL = 180 pF; Rpu = 5 kΩ - 60 td_comp SR Doc ID 15589 Rev 3 V/µsec 11/21 Electrical characteristics Table 13. STGIPL14K60 Truth table Logic input (VI) Output Condition SD/OD LIN HIN LVG HVG Shutdown enable half-bridge tri-state L X X L L Interlocking half-bridge tri-state H L H L L 0 ‘’logic state” half-bridge tri-state H H L L L 1 “logic state” low side direct driving H L L H L 1 “logic state” high side direct driving H H H L H Note: X: don’t care. Figure 5. Maximum IC(RMS) current vs. switching frequency (1) Figure 6. Maximum IC(RMS) current vs. fsine(1) !-V ,&506 >$@ !-V ,&506 >$@ 931 9PRGXODWLRQLQGH[ 3) 7- &7 & & 7& & I 6: N+] 7& & I 6: N+] I 6: N+] 931 90RGXODWLRQLQGH[ 3) 7- &I 6,1( +] I 6:>N+]@ 1. Simulated curves refer to typical IGBT parameters and maximum Rthj-c. 12/21 Doc ID 15589 Rev 3 I 6,1( >+]@ STGIPL14K60 3.1.1 Electrical characteristics NTC thermistor Table 14. NTC thermistor Symbol Parameter Test conditions Min. Typ. Max. Unit. R25 Resistance TC = 25°C 5 kΩ R125 Resistance TC = 125°C 300 Ω B B-constant TC = 25°C 3435 k T Operating temperature -40 125 °C Equation 1: resistance variation vs temperature R ( T ) = R 25 ⋅ e Figure 7. 1 -⎞ B ⎛ --1- – -----------⎝ T 298k⎠ NTC resistance vs temperature Doc ID 15589 Rev 3 13/21 Electrical characteristics 3.2 STGIPL14K60 Waveforms definitions Figure 8. Dead time and interlocking waveforms definitions RLO CK ING INTE RLO CK HIN INTE CONTROL SIGNAL EDGES OVERLAPPED: INTERLOCKING + DEAD TIME ING LIN LVG DTHL DTLH HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIME HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, BUT INSIDE THE DEAD TIME: DEAD TIME HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, OUTSIDE THE DEAD TIME: DIRECT DRIVING HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) (*) HIN and LIN can be connected together and driven by just one control signal 14/21 Doc ID 15589 Rev 3 gate driver outputs OFF (HALF-BRIDGE TRI-STATE) STGIPL14K60 4 Smart shutdown function Smart shutdown function The STGIPL14K60 integrates a comparator for fault sensing purposes. The comparator non-inverting input (CIN) can be connected to an external shunt resistor in order to implement a simple over-current protection function. When the comparator triggers, the device is set in shutdown state and both its outputs are set to low-level leading the halfbridge in tri-state. In the common overcurrent protection architectures the comparator output is usually connected to the shutdown input through a RC network, in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition. Our smart shutdown architecture allows to immediately turn-off the output gate driver in case of overcurrent, the fault signal has a preferential path which directly switches off the outputs. The time delay between the fault and the outputs turn-off is no more dependent on the RC values of the external network connected to the shutdown pin. At the same time the internal logic turns on the open-drain output and holds it on until the shutdown voltage goes below the logic input lower threshold. Finally the smart shutdown function provides the possibility to increase the real disable time without increasing the constant time of the external RC network. Figure 9. Smart shutdown timing waveforms comp Vref CP+ PROTECTION HIN/LIN HVG/LVG SD/OD upper threshold lower threshold 1 2 open drain gate (internal) real disable time Fast shut down: the driver outputs are set in SD state immediately after the comparator triggering even if the SD signal has not yet reach the lower input threshold TIME CONSTANTS 1 = (RON_OD // RSD) CSD 2 = RSD CSD SHUT DOWN CIRCUIT VBIAS RSD FROM/TO CONTROLLER SD/OD CSD Doc ID 15589 Rev 3 RON_OD SMART SD LOGIC 15/21 Applications information 5 STGIPL14K60 Applications information Figure 10. Typical application circuit 16/21 Doc ID 15589 Rev 3 STGIPL14K60 5.1 Applications information Recommendations ● To prevent the input signals oscillation, the wiring of each input should be as short as possible. ● By integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler is possible. ● Each capacitor should be located as nearby the pins of IPM as possible. ● Low inductance shunt resistors should be used for phase leg current sensing. ● Electrolytic bus capacitors should be mounted as close to the module bus terminals as possible. Additional high frequency ceramic capacitor mounted close to the module pins will further improve performance. ● The SD/OD signal should be pulled up to 5 V / 3.3 V with an external resistor (see Section 4: Smart shutdown function for detailed info). Table 15. Recommended operating conditions Value Symbol Parameter Conditions Unit Min. VPN Supply Voltage Applied between P-Nu,Nv,Nw VCC Control supply voltage Applied between VCC-GND VBS High side bias voltage tdead Blanking time to prevent Arm-short For each input signal fPWM PWM input signal -40°C < Tc < 100°C -40°C < Tj < 125°C 13.5 Applied between VBOOTi-OUTi for i=U,V,W Doc ID 15589 Rev 3 Typ. Max. 300 400 V 15 18 V 18 V 1 µs 20 kHz 17/21 Package mechanical data 6 STGIPL14K60 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Please refer to dedicated technical note TN0107 for mounting instructions. Table 16. SDIP-38L mechanical data mm Dimensions Min. 18/21 Typ. Max. A 49.1 50.1 A1 44.1 45.1 A2 1.37 1.47 A3 1.23 2.23 B 24 25 B1 27.1 27.6 28.1 B2 28.6 29.1 29.6 B3 11.25 12.45 B4 12.05 13.25 C 5 6 C1 6.40 7.40 C2 10.41 11.41 e 1.1 1.3 1.5 e1 3.2 3.4 3.6 e2 5.8 6.0 6.2 e3 4.6 4.8 5.0 e4 5.6 5.8 6.0 e5 6.3 6.5 6.7 e6 4.5 4.7 4.9 F 0.8 1.0 1.2 F1 0.35 0.5 0.65 R1 1.3 T1 0.45 Doc ID 15589 Rev 3 2.1 0.55 0.65 STGIPL14K60 Package mechanical data Figure 11. SDIP-38L drawing dimensions 8142868_F Doc ID 15589 Rev 3 19/21 Revision history 7 STGIPL14K60 Revision history s Table 17. Document revision history Date Revision 16-Apr-2009 1 Initial release 2 Inserted Figure 5, Figure 6 and Section 4: Smart shutdown function. Updated Section 3.1: Control part and package mechanical data, Section 6. Minor text changes to improve readability. 3 Document status promoted from preliminary data to datasheet. Updated Table 7: Inverter part, Figure 5: Maximum IC(RMS) current vs. switching frequency and Figure 6: Maximum IC(RMS) current vs. fsine(1). 29-Mar-2010 14-Jun-2010 20/21 Changes Doc ID 15589 Rev 3 STGIPL14K60 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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