INFINEON TLE6208-3G

Triple-Half-Bridge
1
Overview
1.1
Features
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TLE 6208-3 G
Three Half-Bridges
Optimized for DC motor management applications
Delivers up to 0.6 A continuous, 1.2 A peak current
RDS ON; typ. 0.8 Ω, @ 25 °C per switch
Output: short circuit protected and diagnosis
Overtemperature-Protection with hysteresis
and diagnosis
Standard SPI-Interface/Daisy chain capable
Very low current consumption in stand-by (Inhibit)
mode (typ. 10 µA for power and 2 µA for logic
supply, @ 25 °C)
Over- and Undervoltage-Lockout
CMOS/TTL compatible inputs with hysteresis
No crossover current
Internal clamp diodes
Enhanced power P-DSO-Package
Programming compatibility to the TLE 5208-6 G
P-DSO-14-9
Enhanced Power
Type
Ordering Code
Package
TLE 6208-3 G
Q67006-A9334
P-DSO-14-9
Functional Description
The TLE 6208-3 G is a fully protected Triple-Half-Bridge-Driver designed specifically for
automotive and industrial motion control applications. The part is based on the Siemens
power technology SPT® which allows bipolar and CMOS control circuitry in accordance
with DMOS power devices existing on the same monolithic circuitry.
In motion control up to 2 actuators (DC-Motors) can be connected to the 3 halfbridgeoutputs (cascade configuration). Operation modes forward (cw), reverse (ccw), brake
and high impedance are controlled from a standard SPI-Interface. The possibility to
control the outputs via software from a central logic, allows limiting the power dissipation.
So the standard P-DSO-14-package meets the application requirements and saves
PCB-Board-space and cost. Furthermore the build-in features like Over- and
Undervoltage-Lockout, Over-Temperature-Protection and the very low quiescent current
in stand-by mode opens a wide range of automotive- and industrial-applications.
Data Sheet
1
2001-05-10
TLE 6208-3 G
1.2
Pin Configuration (top view)
P-DSO-14-9
GND
1
14 GND
OUT 3
2
VS
3
CSN
4
DI
5
10 INH
CLK
6
9 DO
GND
7
8 GND
Leadframe
13 OUT 1
12 OUT 2
Chip
11 V CC
AEP02438
Figure 1
Data Sheet
2
2001-05-10
TLE 6208-3 G
1.3
Pin Definitions and Functions
Pin No.
Symbol
Function
1
GND
Ground; Reference potential; internal connection to pin 7, 8 and 14;
cooling tab; to reduce thermal resistance place cooling areas on PCB
close to these pins.
2
OUT3
Halfbridge-Output 3;
Internally contected to Highside-Switch 3 and Lowside-Switch 3. The
HS-Switch is a Power-MOS open drain with internal reverse diode;
The LS-Switch is a Power-MOS open source with internal reverse
diode; no internal clamp diode or active zenering;
short circuit protected and open load controlled.
3
VS
Power Supply;
needs a blocking capacitor as close as possible to GND Value: 22 µF
electrolytic in parallel to 220 nF ceramic.
5
DI
Serial Data Input; receives serial data from the control device; serial
data transmitted to DI is an 16bit control word with the Least
Significant Bit (LSB) being transferred first: the input has an active
pull down and requires CMOS logic level inputs;
DI will accept data on the falling edge of CLK-signal;
see Table Input Data Protocol.
4
CSN
Chip-Select-Not Input; CSN is an active low input; serial
communication is enabled by pulling the CSN terminal low; CSN
input should only be transitioned when CLK is low; CSN has an
internal active pull up and requires CMOS logic level inputs.
6
CLK
Serial Clock Input; clocks the shiftregister; CLK has an internal
active pull down and requires CMOS logic level inputs.
7, 8, 14
GND
Ground; see pin 1.
9
DO
Serial-Data-Output; this 3-state output transfers diagnosis data to
the control device; the output will remain 3-stated unless the device
is selected by a low on Chip-Select-Not (CSN);
see Table Diagnosis Data Protocol.
10
INH
Inhibit Input; has an internal pull down;
device is switched in standby condition by pulling the INH terminal
low.
11
VCC
Logic Supply Voltage;
needs a blocking capacitor as close as possible to GND;
Value: 10 µF electrolytic in parallel to 220 nF ceramic.
12
OUT2
Halfbridge-Output 2; see pin 2.
13
OUT1
Halfbridge-Output 1; see pin 2.
Data Sheet
3
2001-05-10
TLE 6208-3 G
1.4
Functional Block Diagram
VS
V CC
11
INH
CSN
DI
CLK
DO
10
DRV1 3
Bias
Charge
Pump
Inhibit
FaultDetect
SPI
16 Bit
Logic
and
Latch
13
4
5
6
9
DRV2
12
UV
OV
OUT 1
OUT 2
DRV3
>1
2
OUT 3
TSD
1,7,8,14
GND
Figure 2
Data Sheet
AEB02439
Block Diagram
4
2001-05-10
TLE 6208-3 G
1.5
Circuit Description
Figure 2 shows a block schematic diagram of the module. There are 3 halfbridge drivers
on the right-hand side. An HS driver and an LS driver are combined to form a halfbridge
driver in each case. The drivers communicate via the internal data bus with the logic and
the other control and monitoring functions: undervoltage (UV), overvoltage (OV),
overtemperature (TSD), charge pump and fault detect.
Two connection interfaces are provided for supply to the module: All power drivers are
connected to the supply voltage VS. These are monitored by overvoltage and
undervoltage comparators with hysteresis, so that the correct function can be checked
in the application at any time.
The logic is supplied by the VCC voltage, typ. with 5 V. The VCC voltage uses an internally
generated Power-On Reset (POR) to initialize the module at power-on. The advantage
of this system is that information stored in the logic remains intact in the event of shortterm failures in the supply voltage VS. The system can therefore continue to operate
following VS undervoltage, without having to be reprogrammed. The “undervoltage”
information is stored, and can be read out via the interface. The same logically applies
for overvoltage. “Interference spikes” on VS are therefore effectively suppressed.
The situation is different in the case of undervoltage on the VCC connection pin. If this
occurs, then the internally stored data is deleted, and the output levels are switched to
high-impedance status (tristate). The module is initialized by VCC following restart
(Power-On Reset = POR).
The 16-bit wide programming word or control word (see Table Input Data Protocol) is
read in via the DI data input, and this is synchronized with the clock input CLK. The status
word appears synchronously at the DO data output (see Table Diagnosis Data
Protocol). It is also possible to connect two TLE 6208-3 G in a daisy chain configuration.
The DO data output of one device is connected with the DI data input of the second
device. In this configuration these two devices are controlled with a single CSN chip
select and using a 32-bit wide control word.
The transmission cycle begins when the chip is selected with the CSN input (H to L). If
the CSN input changes from L to H then the word which has been read in becomes the
control word. The DO output switches to tristate status at this point, thereby releasing the
DO bus circuit for other uses.
The INH inhibit input can be used to cut off the complete module. This reduces the
current consumption to just a few µA, and results in the loss of any data stored. The
output levels are switched to tristate status. The module is reinitialized with the internally
generated POR (Power-On Reset) at restart.
This feature allows the use of this module in battery-operated applications (vehicle body
control applications).
Data Sheet
5
2001-05-10
TLE 6208-3 G
Every driver block from DRV 1 to 3 contains a low-side driver and a high-side driver. Both
drivers are connected internally to form a half-bridge at the output. This reduction of
output pins was necessary to meet the small P-DSO-14 package.
When commutating inductive loads, the dissipated power peak can be significantly
reduced by activating the transistor located parallel to the internal freewheeling diode. A
special, integrated “timer” for power ON/OFF times ensures that there is no crossover
current.
Input Data Protocol
Diagnosis Data Protocol
BIT
BIT
15
OVLO on/off
15
Power supply fail
14
not used
14
Underload
13
Overcurrent SD on/off
13
Overload
12
not used
12
not used
11
not used
11
not used
10
not used
10
not used
9
not used
9
not used
8
not used
8
not used
7
not used
7
not used
6
HS-Switch 3
6
Status HS-Switch 3
5
LS-Switch 3
5
Status LS-Switch 3
4
HS-Switch 2
4
Status HS-Switch 2
3
LS-Switch 2
3
Status LS-Switch 2
2
HS-Switch 1
2
Status HS-Switch 1
1
LS-Switch 1
1
Status LS-Switch 1
0
Status Register Reset
0
Temp. Prewarning
H = ON
L = OFF
Data Sheet
H = ON
L = OFF
6
2001-05-10
TLE 6208-3 G
Fault Result Table
Fault
Diag.-Bit
Result
Overcurrent (load)
13
Only the failed output is switched OFF. Function
can be deactivated by bit No. 13.
Short circuit to GND
(high-side-switch)
13
Only the failed output is switched OFF. Function
can be deactivated by bit No. 13.
Short circuit to VS
(low-side-switch)
13
Only the failed output is switched OFF. Function
can be deactivated by bit No. 13.
Temperature warning 0
Reaction of control device needed.
Temperature shut
down (SD)
–
All outputs OFF.
Temperature warning is set before.
Underload/Openload
14
Reaction of control device needed.
Undervoltage lockout 15
(UVLO)
All outputs OFF.
Overvoltage lockout
(OVLO)
All outputs OFF.
Function can be deactivated by bit No. 15.
15
H = failure;
L = no failure.
Data Sheet
7
2001-05-10
TLE 6208-3 G
2
Electrical Characteristics
2.1
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
Remarks
min.
max.
VS
VS
VCC
VI
– 0.3
40
V
–
–1
–
V
– 0.3
5.5
V
– 0.3
5.5
V
Logic output voltage
(DO)
VDO
– 0.3
5.5
V
Output voltage
(OUT 1-3)
VOUT
– 0.3
40
V
t < 0.5 s; IS > – 2 A
0 V < VS < 40 V
0 V < VS < 40 V
0 V < VCC < 5.5 V
0 V < VS < 40 V
0 V < VCC < 5.5 V
0 V < VS < 40 V
Output current (cont.)
IOUT1-3
IOUT1-3
–
–
A
internal limited
–
–
A
internal limited
Supply voltage
Supply voltage
Logic supply voltage
Logic input voltages
(DI, CLK, CSN, INH)
Output current (peak)
Note: Current limits are mentioned in the overcurrent section of electrical charateristics
Junction temperature
Storage temperature
ESD voltage, human body
model, according to:
• MIL STD 883D,
• ANSI EOS\ESD S5.1
• JEDEC JESD22-A114
Tj
Tstg
VESD-HBM
VESD-HBM-
– 40
150
°C
–
– 50
150
°C
–
–
–
4kV
all pins
–
–
8kV
only pins 2, 12 and
13 (outputs)
–
–
300V
all pins
OUT
ESD voltage, mashine model, VESD-MM
according to:
• ANSI EOS\ESD S5.2
• JEDEC JESD22-A115
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Data Sheet
8
2001-05-10
TLE 6208-3 G
2.2
Operating Range
Parameter
Symbol
Limit Values
min.
Unit
Remarks
max.
Supply voltage
VS
VUV OFF 40
V
After VS rising
above VUV ON
Supply voltage slew rate
dV S / dt
–
10
V/µs
–
Logic supply voltage
VCC
VS
VS
VI
4.75
5.50
V
–
– 0.3
Outputs in tristate
– 0.3
VUV ON V
VUV OFF V
VCC
V
fCLK
Tj
–
1
MHz
–
– 40
150
°C
–
Junction pin
Rthj-pin
–
30
K/W
measured to
pin 1, 7, 8, 14
Junction ambient
RthjA
–
65
K/W
–
Supply voltage increasing
Supply voltage decreasing
Logic input voltage (DI, CLK,
CSN, INH)
SPI clock frequency
Junction temperature
– 0.3
Outputs in tristate
–
Thermal Resistances
Note: In the operating range, the functions given in the circuit description are fulfilled.
Data Sheet
9
2001-05-10
TLE 6208-3 G
2.3
Electrical Characteristics
8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C;
unless otherwise specified
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit Test Condition
Current Consumption
Quiescent current
IS
–
8
20
µA
INH = Low;
VS = 13.2 V
Tj = 25 °C
Quiescent current
IS
–
–
30
µA
INH = Low;
VS = 13.2 V;
Logic-Supply current
ICC
ICC
IS
–
2
10
µA
INH = Low
–
1
2
mA
SPI not active
–
2
5
mA
–
–
6.5
7
V
5.6
6.1
6.6
V
–
0.4
–
V
34
37
40
V
30
33
36
V
–
4
–
V
VS increasing
VS decreasing
VUV ON – VUV OFF
VS increasing
VS decreasing
VOV OFF – VOV ON
Logic-Supply current
Supply current
Over- and Under-Voltage Lockout
UV-Switch-ON voltage
UV-Switch-OFF voltage
UV-ON/OFF-Hysteresis
OV-Switch-OFF voltage
OV-Switch-ON voltage
OV-ON/OFF-Hysteresis
Data Sheet
VUV ON
VUV OFF
VUV HY
VOV OFF
VOV ON
VOV HY
10
2001-05-10
TLE 6208-3 G
2.3
Electrical Characteristics (cont’d)
8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C;
unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
–
0.8
0.95
Ω
8 V < VS < 40 V
Tj = 25 °C
–
1.6
Ω
8 V < VS < 40 V
1
–
Ω
–
2
Ω
0.75
0.9
Ω
–
1.5
Ω
1
–
Ω
–
2
Ω
VS OFF < VS ≤ 8 V
Tj = 25 °C
VS OFF < VS ≤ 8 V
8 V < VS < 40 V
Tj = 25 °C
8 V < VS < 40 V
VS OFF < VS ≤ 8 V
Tj = 25 °C
VS OFF < VS ≤ 8 V
Outputs OUT1-3
Static Drain-Source-On Resistance
Source (High-Side)
IOUT = – 0.5 A
Sink (Low-Side)
RDS ON H
RDS ON L
–
IOUT = 0.5 A
Leakage Current
Source-Output-Stage 1 to 3
Sink-Output-Stage 1 to 3
IQLH
IQLL
–5
–1
–
µA
–
150
300
µA
VOUT1-3 = 0 V
VOUT1-3 = VS
ISDU
ISDL
IOCL
tdSD
–2
– 1.3 – 1
A
–
1
1.2
2
A
–
–
2.4
4
A
sink and source
10
28
40
µs
sink and source
Overcurrent
Source shutdown threshold
Sink shutdown threshold
Current limit
Shutdown delay time
Data Sheet
11
2001-05-10
TLE 6208-3 G
2.3
Electrical Characteristics (cont’d)
8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C;
unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
15
30
45
mA
–
200
370
600
µs
–
Open Circuit/Underload Detection
Detection current
Delay time
IOCD
tdOC
Output Delay Times; VS = 13.2 V; RLoad = 25 Ω (device not in stand-by for t > 1 ms)
Source ON
Source OFF
Sink ON
Sink OFF
Dead time
Dead time
td ON H
td OFF H
td ON L
td OFF L
tD HL
tD LH
–
8
20
µs
–
–
4
20
µs
–
–
7
20
µs
–
–
3
20
µs
–
1
3
–
µs
1
5
–
µs
td ON L – td OFF H
td ON H – td OFF L
Output Switching Times; VS = 13.2 V; RLoad = 25 Ω (device not in stand-by for t > 1 ms)
Source ON
Source OFF
Sink ON
Sink OFF
tON H
tOFF H
tON L
tOFF L
–
5
20
µs
–
–
2
5
µs
–
–
2.0
10
µs
–
–
1.5
5
µs
–
–
0.9
1.3
V
–
0.9
1.3
V
IF = 0.5 A
IF = 0.5 A
Clamp Diodes Forward Voltage
Upper
Lower
Data Sheet
VFU
VFL
12
2001-05-10
TLE 6208-3 G
2.3
Electrical Characteristics (cont’d)
8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C;
unless otherwise specified
Parameter
Symbol
Limit Values
min.
typ.
max.
–
0.52
0.7
0.2
0.48
50
Unit Test Condition
Inhibit Input
H-input voltage threshold
L-input voltage threshold
Hysteresis of input voltage
Pull down current
Input capacitance
VIH
VIL
VIHY
II
CI
–
–
VCC
VCC
200
500
mV
–
5
25
100
µA
–
10
15
pF
VI = 0.2 × VCC
0 V < VCC <
–
5.25 V
Note: Capacitances are guaranteed by design.
SPI-Interface
Delay Time from Stand-by to Data In/Power on Reset
Setup time
tset
–
–
100
µs
–
–
0.52
0.7
–
0.2
0.48
–
VCC
VCC
50
200
500
mV
–
– 50
– 25
– 10
µA
10
25
50
µA
10
25
50
µA
–
10
15
pF
VCSN = 0.7 × VCC
VDI = 0.2 × VCC
VCLK = 0.2 × VCC
0 V < VCC <
Logic Inputs DI, CLK and CSN
VIH
VIL
L-input voltage threshold
Hysteresis of input voltage
VIHY
IICSN
Pull up current at pin CSN
Pull down current at pin DI
IIDI
Pull down current at pin CLK IICLK
Input capacitance
CI
H-input voltage threshold
at pin CSN, DI or CLK
–
5.25 V
Note: Capacitances are guaranteed by design.
Data Sheet
13
2001-05-10
TLE 6208-3 G
2.3
Electrical Characteristics (cont’d)
8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C;
unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
VCC
VCC
–
V
IDOH = 1 mA
IDOL = – 1.6 mA
VCSN = VCC
0 V < VDO < VCC
VCSN = VCC
0 V < VCC <
Logic Output DO
H-output voltage level
VDOH
– 1.0 – 0.7
–
0.2
0.4
V
Tri-state leakage current
VDOL
IDOLK
– 10
0
10
µA
Tri-state input capacitance
CDO
–
10
15
pF
L-output voltage level
5.25 V
Note: Capacitances are guaranteed by design.
Data Input Timing
Clock period
Clock high time
Clock low time
Clock low before CSN low
CSN setup time
CLK setup time
Clock low after CSN high
DI setup time
DI hold time
Input signal rise time
at pin DI, CLK and CSN
Input signal fall time
at pin DI, CLK and CSN
Data Sheet
tpCLK
tCLKH
tCLKL
tbef
tlead
tlag
tbeh
tDISU
tDIHO
trIN
1000
–
–
ns
–
500
–
–
ns
–
500
–
–
ns
–
500
–
–
ns
–
500
–
–
ns
–
500
–
–
ns
–
500
–
–
ns
–
250
–
–
ns
–
250
–
–
ns
–
–
–
200
ns
–
tfIN
–
–
200
ns
–
14
2001-05-10
TLE 6208-3 G
2.3
Electrical Characteristics (cont’d)
8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C;
unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
–
50
100
ns
–
50
100
ns
CL = 100 pF
CL = 100 pF
–
–
250
ns
low impedance
–
–
250
ns
high impedance
–
100
250
ns
VDO < 0.2 VCC;
VDO > 0.7 VCC;
CL = 100 pF
120
145
170
°C
–
Data Output Timing
DO rise time
DO fall time
DO enable time
DO disable time
DO valid time
trDO
tfDO
tENDO
tDISDO
tVADO
Thermal Prewarning and Shutdown
Thermal prewarning junction TjPW
temperature
Temperature prewarning
hysteresis
∆T
–
30
–
K
–
Thermal shutdown junction
temperature
TjSD
150
175
200
°C
–
Thermal switch-on junction
temperature
TjSO
120
–
170
°C
–
Temperature shutdown
hysteresis
∆T
–
30
–
K
–
Ratio of SD to PW
temperature
TjSD/TjPW 1.05
1.20
–
–
–
Note: Temperatures are guaranteed by design.
The listed characteristics are ensured over the operating range of the integrated
circuit. Typical characteristics specify mean values expected over the production
spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and
the given supply voltage.
Data Sheet
15
2001-05-10
TLE 6208-3 G
3
Timing Diagrams
CSN High to Low & rising edge of CLK: DO is enabled. Status information is transferred to Output Shift Register
CSN
time
CSN Low to High: Data from Shift-Register is transferred to Output Power Switches
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
time
Actual Data
DI
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
New Data
0 1
+ +
time
DI: Data will be accepted on the falling edge of CLK-Signal
Previous Status
DO
0
-
1
-
2
-
3
-
4
-
5
-
6
-
7
-
8
-
9 10 11 12 13 14 15
- - - - - - -
Actual Status
0
1
time
DO: State will change on the rising edge of CLK-Signal
e.g.
HS1
Old Data
Actual Data
time
AET02177
Figure 3
Data Sheet
Data Transfer Timing
16
2001-05-10
TLE 6208-3 G
CSN High to Low & CLK Stays Low: Status information of Data Bit 0 (temperature prewarning) is transfered to DO
CSN
time
CLK
time
DI
time
DI: Data is not accepted
0-
DO
time
DO: Status information of Data Bit 0 (temperature prewarning) will stay as long as CSN is low
AET02620
Figure 4
Timing for Temperature Prewarning only
0.7 VCC
CSN
0.2 VCC
t CLKH
0.7 VCC
CLK
0.2 VCC
t lead
t bef
DI
t CLKL
t DISU
Don’t Care
t lag
t beh
t DIHO
Valid
Don’t
Care
0.7 VCC
Valid
Don’t Care
0.2 VCC
AET02178
Figure 5
Data Sheet
SPI-Input Timing
17
2001-05-10
TLE 6208-3 G
t rIN
t fIN
70%
CSN
50%
20%
t dOFF
70%
Case 1
Ι OUT
ON State
OFF State
50%
20%
t OFF
t dON
t ON
70%
Case 2
Ι OUT
OFF State
50%
ON State
20%
AET02179
Figure 6
Turn OFF/ON Time
t fIN <_ 10 ns
t rIN
0.7 VCC
CLK
50%
0.2 VCC
t rDO
0.7 VCC
DO
(low to high)
0.2 VCC
t VADO
t fDO
DO
0.7 VCC
(high to low)
0.2 VCC
AET02180
Figure 7
Data Sheet
DO Valid Data Delay Time and Valid Time
18
2001-05-10
TLE 6208-3 G
t rIN <_ 10 ns
t fIN
0.7 VCC
CSN
50%
0.2 VCC
t DISDO
t ENDO
10 k Ω
Pullup
to VCC
DO
t ENDO
50%
t DISDO
10 k Ω
Pulldown
to GND
DO
50%
AET02181
Figure 8
Data Sheet
DO Enable and Disable Time
19
2001-05-10
TLE 6208-3 G
Watchdog
Reset
TLE 4278G
Ι
V S = 12V
Q
CQ
22 µF
WD R
CD
47 nF
D01
1N4001
D
V CC
V CC
INH 10
DRV1 3
Bias
Charge
Pump
Inhibit
FaultDetect
CSN 4
DI 5
CLK 6
SPI
DO 9
CS
10 µF
VS
11
µP
D02
Z39
16 Bit
Logic
and
Latch
13 OUT 1
M
DRV2
12 OUT 2
M
UV
OV
DRV3
>1
2 OUT 3
TSD
1,7,8,14
GND
Figure 9
Data Sheet
GND
AEB02441
Application Circuit
20
2001-05-10
TLE 6208-3 G
4
Package Outlines
GPS09222
P-DSO-14-9
(Plastic Dual Small Outline Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Data Sheet
21
Dimensions in mm
2001-05-10