Product Overview

Product Overview
MC100LVEP210: Clock Driver, 1:5 Differential, Dual ECL / PECL / HSTL, 2.5 V
/ 3.3 V
For complete documentation, see the data sheet
Product Description
The MC100LVEP210 is a low skew 1-to-5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input
signals can be either differential or single ended if the VBB output is used. The signal is fanned out to 5 identical differential outputs.
HSTL inputs can be used when the EP210 is operating in PECL mode.
The LVEP210 specifically guarantees low output-to-output skew.
Optimal design, layout, and processing minimize skew within a device and from device to device. To ensure the tight skew
specification is realized, both sides of the differential output need to be terminated identically into 50 ohms even if only one output is
being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew.
The MC100LVEP210, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the
LVEP210 to be used for high performance clock distribution in +3.3 V or +2.5 V systems. Single-ended CLK input operation is limited
to a VCC ? 3.0 V in PECL mode, or VEE ? -3.0 V in ECL mode.
Designers can take advantage of the LVEP210's performance to distribute low skew clocks across the backplane or the board. In a
PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For more
information on using PECL, designers should refer to Application Note AN1406/D.
Features
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85 ps Typical Device-to-Device Skew
20 ps Typical Output-to-Output Skew
VBBOutput
Jitter Less than 1 ps RMS
350 ps Typical Propagation Delay
Maximum Frequency >3 Ghz
The 100 Series Contains Temperature Compensation
PECL and HSTL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V
Open Input Default State
For more features, see the data sheet
Part Electrical Specifications
Product
Compliance
Status
Type
Chann
els
Input / Input
Output Level
Ratio
Output VCC
Level
Typ
(V)
tJitterR
MS
Typ
(ps)
tskew(oo) Max
(ps)
tpd Typ
(ns)
tR & tF
Max
(ps)
fmaxClo fmaxDat Packa
ck Typ a Typ ge
(MHz) (Mbps) Type
MC100LVEP210FAG
Pb-free
Active
Buffer
2
1:5
ECL
0.207
25
0.35
250
3000
LQFP32
0.207
25
0.35
250
3000
LQFP32
0.207
25
0.35
250
3000
QFN32
Halide free
HST
L
3.3
2.5
LVD
S
ECL
CML
MC100LVEP210FARG
Pb-free
Active
Buffer
2
1:5
Halide free
CML
ECL
HST
L
3.3
2.5
LVD
S
ECL
MC100LVEP210MNR
G
Pb-free
Halide free
Active
Buffer
2
1:5
CML
HST
L
LVD
S
ECL
ECL
3.3
2.5
For more information please contact your local sales support at www.onsemi.com
Created on: 6/30/2016