Product Overview MC100LVE111: 3.3 V ECL 1:9 Differential Clock Driver For complete documentation, see the data sheet Product Description The MC100LVE111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The MC100LVE111's function and performance are similar to the popular MC100E111, with the added feature of low voltage operation. It accepts one signal input, which can be either differential or single-ended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. The LVE111 is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within a device, and empirical modeling is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable, guaranteed low skew device. To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into 50 W, even if only one side is being used. In most applications, all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20 ps) of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin. The MC100LVE111, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the LVE111 to be used for high performance clock distribution in +3.3 V systems. Designers can take advantage of the LVE111's performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For systems incorporating GTL, parallel termination offers the lowest power Features • • • • • • • • • • 200ps Part-to-Part Skew. 50ps Output-to-Output Skew ESD Protection: >2 KV HBM, >200 V MM The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -3.8 V Internal Input Pulldown Resistors Q Output will Default LOW with Inputs Open or at VEE Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D For more features, see the data sheet Part Electrical Specifications Product Compliance Status Type Chann els Input / Input Output Level Ratio Output VCC Level Typ (V) tJitterR MS Typ (ps) tskew(oo) Max (ps) tpd Typ (ns) tR & tF Max (ps) fmaxClo fmaxDat Packa ck Typ a Typ ge (MHz) (Mbps) Type MC100LVE111FNG Pb-free Active Buffer 1 1:9 ECL ECL 3.3 0.2 50 0.535 600 1500 PLCC28 Active Buffer 1 1:9 ECL ECL 3.3 0.2 50 0.535 600 1500 PLCC28 Halide free MC100LVE111FNR2G Pb-free Halide free For more information please contact your local sales support at www.onsemi.com Created on: 6/30/2016