MC100LVEP210
Low-Voltage 1:5 Dual Diff.
LVECL/LVPECL/LVEPECL/HSTL
Clock Driver
The MC100LVEP210 is a low skew 1–to–5 dual differential driver,
designed with clock distribution in mind. The LVECL/LVPECL input
signals can be either differential or single–ended if the VBB output is
used. The signal is fanned out to 5 identical differential outputs. HSTL
inputs can be used when the EP210 is operating in LVPECL mode.
The LVEP210 specifically guarantees low output–to–output skew.
Optimal design, layout, and processing minimize skew within a device
and from lot to lot.
To ensure the tight skew specification is realized, both sides of the
differential output need to be terminated identically into 50Ω even if
only one side is being used. When fewer than all ten pairs are used,
identically terminate all the output pairs on the same package side
whether used or unused. If no outputs on a single side are used, then
leave these outputs open (unterminated). This will maintain minimum
output skew. Failure to do this will result in a 10–20ps loss of skew
margin (propagation delay) in the output(s) in use.
The MC100LVEP210, as with most other LVECL devices, can be
operated from a positive VCC supply in LVPECL mode. This allows
the LVEP210 to be used for high performance clock distribution in
+3.3V or +2.5V systems. Single ended input operation is limited to a
VCC ≥ 3.0V in PECL mode, or VEE ≤ –3.0V in ECL mode.
Designers can take advantage of the LVEP210’s performance to
distribute low skew clocks across the backplane or the board. In a
LVPECL environment, series or Thevenin line terminations are
typically used as they require no additional power supplies. For more
information on using PECL, designers should refer to Application
Note AN1406/D.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
100ps Part–to–Part Skew
35ps Output–to–Output Skew
Differential Design
VBB Output
475ps Typical Propagation Delay
High Bandwidth to 1.5GHz Typical
LVPECL and HSTL mode: 2.375V to 3.8V VCC with VEE = 0V
LVECL mode: 0V VCC with VEE = –2.375V to –3.8V
Internal Input Resistors: Pulldown on D, D
Pullup and Pulldown on CLK
ESD Protection: >2KV HBM, >100V MM
Moisture Sensitivity Level 2
For Additional Information, See Application Note AND8003/D
Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
Transistor Count = 461 devices
Semiconductor Components Industries, LLC, 1999
March, 2000 – Rev. 2
1
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32–LEAD TQFP
FA SUFFIX
CASE 873A
MARKING DIAGRAM*
MC100
LVEP210
AWLYYWW
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
32
1
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
MC100LVEP210FA
Package
Shipping
TQFP
250 Units/Tray
MC100LVEP210FAR2 TQFP
2000 Tape & Reel
Publication Order Number:
MC100LVEP210/D
MC100LVEP210
Qa3 Qa3 Qa4 Qa4 Qb0 Qb0 Qb1 Qb1
24
23
22
21
20
19
18
17
VCC
25
16
VCC
Qa2
26
15
Qb2
Qa2
27
14
Qb2
Qa1
28
13
Qb3
Qa1
29
12
Qb3
MC100LVEP210
PIN DESCRIPTION
Qa0
30
11
Qb4
Qa0
31
10
Qb4
VCC
32
9
VCC
1
2
3
4
5
6
7
PIN
FUNCTION
CLKn/CLKn
LVECL/LVPECL/HSTL CLK Inputs
Qn0:4/Qn0:4
LVECL/LVPECL Outputs
VBB
Reference Voltage Output
VCC
Positive Supply
VEE
Negative, 0 Supply
8
VCC NC CLKa CLKa VBB CLKb CLKb VEE
Figure 1. 32–Lead TQFP Pinout (Top View)
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Qa0
Qb0
Qa0
Qb0
Qa1
CLKa
Qa1
CLKa
Qa2
Qb1
CLKb
Qb1
CLKb
Qb2
Qa2
Qb2
Qa3
Qb3
Qa3
Qb3
Qa4
Qb4
Qa4
Qb4
VBB
Figure 2. Logic Symbol
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VEE
Power Supply (VCC = 0V)
–6.0 to 0
VDC
VCC
Power Supply (VEE = 0V)
6.0 to 0
VDC
VI
Input Voltage (VCC = 0V, VI not more negative than VEE)
–6.0 to 0
VDC
VI
Input Voltage (VEE = 0V, VI not more positive than VCC)
6.0 to 0
VDC
Iout
Output Current
50
100
mA
IBB
VBB Sink/Source Current{
± 0.5
mA
TA
Operating Temperature Range
–40 to +85
°C
Tstg
Storage Temperature
–65 to +150
°C
θJA
Thermal Resistance (Junction–to–Ambient)
80
55
°C/W
θJC
Thermal Resistance (Junction–to–Case)
12 to 17
°C/W
Tsol
Solder Temperature (<2 to 3 Seconds: 245°C desired)
265
°C
Continuous
Surge
Still Air
500lfpm
* Maximum Ratings are those values beyond which damage to the device may occur.
{ Use for inputs of same package only.
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2
MC100LVEP210
DC CHARACTERISTICS, ECL/LVECL (VCC = 0V; VEE = –3.3(+0.925, –0.5)V) (Note 5.)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
(Note 1.)
60
70
90
60
70
90
60
70
90
mA
VOH
Output HIGH Voltage
(Note 2.)
–1145
–1020
–895
–1145
–1020
–895
–1145
–1020
–895
mV
VOL
Output LOW Voltage
(Note 2.)
–1995
–1820
–1650
–1995
–1820
–1650
–1995
–1820
–1650
mV
VIH
Input HIGH Voltage
Single Ended
–1165
–880
–1165
–880
–1165
–880
mV
VIL
Input LOW Voltage
Single Ended
–1810
–1625
–1810
–1625
–1810
–1625
mV
VBB
Output Voltage Reference (Note 3.)
–1525
–1325
–1525
–1325
–1525
–1325
mV
0.0
V
150
µA
VIHCMR Input HIGH Voltage Common Mode
Range (Note 4.)
IIH
Input HIGH Current
IIL
Input LOW Current
–1425
VEE+1.2
0.0
–1425
VEE+1.2
150
CLK
CLK
0.5
–150
0.0
–1425
VEE+1.2
150
0.5
–150
µA
0.5
–150
NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
1. VCC = 0V, VEE = VEEmin to VEEmax, all other pins floating.
2. All loading with 50 ohms to VCC–2.0 volts.
3. Single ended input operation is limited VEE ≤ –3.0V in ECL/LVECL mode.
4. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
5. Input and output parameters vary 1:1 with VCC.
DC CHARACTERISTICS, LVPECL (VCC = 3.3V ± 0.5V, VEE = 0V) (Note 10.)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
(Note 6.)
60
70
90
60
70
90
60
70
90
mA
VOH
Output HIGH Voltage
(Note 7.)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage
(Note 7.)
1305
1480
1650
1305
1480
1650
1305
1480
1650
mV
VIH
Input HIGH Voltage
Single Ended
2135
2420
2135
2420
2135
2420
mV
VIL
Input LOW Voltage
Single Ended
1490
1675
1490
1675
1490
1675
mV
VBB
Output Voltage Reference (Note 8.)
1775
1975
1775
1975
1775
1975
mV
3.3
1.2
3.3
1.2
3.3
V
150
µA
VIHCMR Input HIGH Voltage Common Mode
Range (Note 9.)
IIH
Input HIGH Current
IIL
Input LOW Current
1875
1.2
150
CLK
CLK
0.5
–150
1875
150
0.5
–150
0.5
–150
1875
µA
NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
6. VCC = 3.3V ± 0.5V, VEE = 0V, all other pins floating.
7. All loading with 50 ohms to VCC–2.0 volts.
8. Single ended input operation is limited VCC ≥ –3.0V in PECL mode.
9. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
10. Input and output parameters vary 1:1 with VCC.
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3
MC100LVEP210
DC CHARACTERISTICS, LVEPECL (VCC = 2.5V ± 0.125V, VEE = 0V) (Note 14.)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
(Note 11.)
60
70
90
60
70
90
60
70
90
mA
VOH
Output HIGH Voltage
(Note 12.)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VOL
Output LOW Voltage
(Note 12.)
505
680
850
505
680
850
505
680
850
mV
VIH
Input HIGH Voltage
Single Ended
1335
1620
1335
1620
1335
1620
mV
VIL
Input LOW Voltage
Single Ended
690
875
690
875
690
875
mV
1.2
2.5
1.2
2.5
1.2
2.5
V
150
µA
VIHCMR Input HIGH Voltage Common Mode
Range (Note 13.)
IIH
Input HIGH Current
IIL
Input LOW Current
150
CLK
CLK
0.5
–150
150
0.5
–150
µA
0.5
–150
NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
11. VCC = 2.5V, VEE = 0V, all other pins floating.
12. All loading with 50 ohms to VEE.
13. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
14. Input and output parameters vary 1:1 with VCC.
DC CHARACTERISTICS, HSTL (VCC = 2.5(–0.125, +1.3)V, VEE = 0V)
–40°C
Symbol
Characteristic
VIH
VIL
Input HIGH Voltage
VX
Input Crossover Voltage
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
1200
mV
Input LOW Voltage
680
ICC
Power Supply Current (Note 15.)
100
15. VCC = 2.375V to 3.8V, VEE = 0V, all other pins floating.
Unit
400
mV
900
mV
100
100
mA
AC CHARACTERISTICS (VCC = 0V; VEE = –2.5V to –3.8V) or (VCC = 2.5V to 3.8V; VEE = 0V)
–40°C
Min
fmaxLVPECL
Maximum Toggle Frequency
for LVECL and LVPECL
(Note 16.)
1.5
GHz
fmaxHSTL
Maximum Toggle Frequency
for HSTL (Note 16.)
250
MHz
tPLH,
tPHL
Propagation Delay
Differential
tSKEW
Within Device Skew
Duty Cycle Skew (Note 17.)
tJITTER
Cycle–to–Cycle Jitter
VPP
Input Voltage Swing (Diff.)
300
Max
400
Min
200
TBD
TBD
TBD
150
800
Typ
85°C
Characteristic
200
Typ
25°C
Symbol
Max
350
450
25
100
35
Min
300
150
800
500
Max
750
TBD
TBD
TBD
1200
Typ
150
800
ps
ps
TBD
1200
Unit
ps
1200
mV
tr
Output Rise/Fall Times
Q
100
170
270
100
180
290
100
280
350
ps
tf
(20% – 80%)
16. Fmax guaranteed for functionality only.
17. Skew is measured between outputs under identical transitions of similar paths through a device. Duty cycle skew is defined only for differential
operation when the delays are measured from the crosspoint of the inputs to the crosspoint of the outputs.
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4
MC100LVEP210
PACKAGE DIMENSIONS
A
–T–, –U–, –Z–
TQFP
FA SUFFIX
32–LEAD PLASTIC PACKAGE
CASE 873A–02
ISSUE A
4X
A1
32
0.20 (0.008) AB T–U Z
25
1
–U–
–T–
B
V
AE
P
B1
DETAIL Y
17
8
V1
AE
DETAIL Y
9
4X
–Z–
9
0.20 (0.008) AC T–U Z
S1
S
DETAIL AD
G
–AB–
0.10 (0.004) AC
AC T–U Z
–AC–
BASE
METAL
ÉÉ
ÉÉ
ÉÉ
ÉÉ
F
8X
M_
R
M
N
D
J
0.20 (0.008)
SEATING
PLANE
SECTION AE–AE
W
K
X
DETAIL AD
Q_
GAUGE PLANE
H
0.250 (0.010)
C E
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5
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE
DETERMINED AT DATUM PLANE –AB–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE PROTRUSION
IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL
BE 0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
MC100LVEP210
Notes
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6
MC100LVEP210
Notes
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7
MC100LVEP210
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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8
MC100LVEP210/D