5 PMU_3_3V VOUT VIN 4 CONN_1 1 2 3 4 5 6 D 3 2 1 CONN_2 PG EN PS GPIO I2C_SDA_MODx I2C_SCL_MODx 1x6 HMTSW-106-07-G-S-230-003 1 2 3 4 5 6 1x6 THVT HMTSW-106-07-G-S-230 D SUB-MODULE CONNECTORS PMU_3_3V R1 10K 1/10W VIN R2 TBD TBD VOUT U1 C IN EN C2 TBD xx C 8 5 1 2 4 PWRP 7 6 3 OUT FB DNC/DELAY NR/NC PG *LDO C4 TBD xx U2 I2C_SDA_MODx B1 I2C_SCL_MODx B2 B SDA SCL C1 TBD xx C5 TBD xx R3 TBD TBD C3 TBD xx R4 TBD TBD PMU_3_3V V+ GND A1 A2 B C6 10nF ADDR = 1110000x TMP103AYFF DGN Package LDO Sub-Module TBD: See BOM for component values. A *Compatible LDO Devices: TPS7A4901 TPS7A3001 TPS7A4001 TPS7A1601 TPS7A1633 TPS7A1650 5 LB1 A 1 SMP-LDO-DGN1-MVK Title Approval 4 3 Designer Antonio Fadhel Drawn By Antonio Fadhel Layout DAWN RITZ Size B Date 2 SMP-LDO-DGN1-MVK 6527636 EDGE No Friday, December 16, 2011 1 Rev B Page 1 of 1