QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 917 POE TO [email protected] ISOLATED LTC4267CDHC DESCRIPTION Demonstration circuit 917 is a PoE to [email protected] Isolated Converter featuring the LTC4267CDHC. The board provides a complete IEEE 802.3af power device (PD) interface and isolated 3.3V power supply solution for use in Power over Ethernet (PoE) applications in a very small printed circuit board footprint. The LTC4267 integrates the 25kΩ signature resistor, classification current source, thermal overload protection, signature disable and power good signal along with an undervoltage lockout optimized for use with the IEEE required diode bridge. The precision dual level input current limit allows the Table 1. LTC4267 to charge load capacitors and interface with legacy PoE systems. The LTC4267 combines the above features with a current mode switching controller designed for driving a 6V rated N-channel MOSFET. It features programmable slope compensation, soft-start, and constant frequency operation, minimizing electrical noise even with light loads. Design files for this circuit board are available. Call the LTC factory. Performance Summary (TA = 25°C) PARAMETER CONDITION VALUE Turn-on Voltage Input from PSE -37V Maximum Turn-off Voltage Input from PSE, PD switch turns off -31V Minimum operating voltage IOUT = 2.6A -33V Power Converter Input operating range VOUT=3.3V, IOUT = 0 to 2.6A -37V to -57V Maximum Input Current Input from PSE, PD high level current limit 375 mA, typical Maximum Output Current VOUT=3.3V 2.6A Output Voltage VIN=48VDC from PSE, IOUT=2.6A 3.3V, typical Line (0% to 100% full load) 2% Load (0% to 100% of rated full load) 2% Output Regulation QUICK START PROCEDURE Demonstration circuit 917 is easy to set up to evaluate the performance of the LTC4267. For proper equipment setup, refer to figure 1 and follow the procedure below: 1. With the power source to the PSE turned off, connect the input power supply to the board through the J1 filtered Ethernet connector. 2. In addition to a PSE, the DC917 board can be powered by an alternate input power supply 1 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 917 POE TO [email protected] ISOLATED through the VAUX+ (TP16) and VPORTN (TP15) terminals. Do not connect more than one power source. 3. Connect the SIGNATURE DISABLE signal to VPORTN. 4. Turn on the PSE or alternate input power supply and increase the voltage until the power converter turns on. Be careful not to exceed 57VDC. NOTE: Make sure that the input voltage does not exceed 57VDC. If a higher voltage is required, power components with higher voltage ratings should be used. 5. Verify proper classification and signature detection. 6. Check the output voltage. It should be 3.3V, typical. If there is no output, temporarily disconnect the load to make sure that the load is not too high. 7. Once the proper output voltage is established, adjust the load current within the appropriate range and observe the output regulation, ripple voltage, efficiency and other parameters. OPERATION Demonstration circuit 917 interfaces with a customer’s Power-Over-Ethernet test setup per Figure 1. The front end of the demo circuit implements the required Ethernet input interface transformer coupling and common-mode termination through the integrated connector J1. The demonstration circuit is set up to allow data to pass in and back out of the demo circuit while the DC917 performs IEEE 802.3af interface functions. The Power Sourcing Equipment (PSE) is connected to J1 and the PHY is optionally connected to J2. The PD is required to have 0.1uF of capacitance during detection; this is provided by C2. It is also required to have at least 5uF of capacitance after the in-rush circuit, provided by capacitors C1 and C9. This demo circuit allows detection and power classification of the PD per the IEEE 802.3af specification. During the detection process of a PD, the LTC4267 displays the proper 25kΩ signature resistor. Signature detection may be disabled, if so desired, by pulling the SIGNATURE DISABLE line (TP10) up to VPORTP. If signature classification is disabled, all interface functions of the LTC4267 are disabled. Signature detection, classification and the internal power MOSFET switch are all disabled. Note that the SIGNATURE DISABLE signal at TP10 is an open circuit. While it is true that this signal is internally pulled down within the LTC4267, the data sheet explicitly states that this signal must be tied to VPORTN or VPORTP. This signal is left open only for the convenience of the using when operating the demonstration circuit. The SIGNATURE DISABLE signal must be properly terminated in a production application. Classification is programmed by the selection of a single external resistor, R17, connected to the RCLASS pin. After detection and classification, the PD is powered up when the input voltage exceeds the LTC4267 turn-on under-voltage lock out (UVLO) through a dual-level current-limited power switch. While the voltage between POUT and VPORTN is above the Power Good trip point, the amperage through the power switch is held below the low- 2 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 917 POE TO [email protected] ISOLATED level current limit. When the voltage between POUT and VPORTN falls below the Power Good trip point, the Power Good signal goes active low and the amperage through the power switch is held below the high-level current limit. For the PD to remain powered on, it must present to the PSE both AC and DC components of the Maintain Power Signature (MPS). The PD must hold the DC MPS by drawing at least 10mA or the PSE may disconnect power. The DC917 demo board does not implement a minimum load. It is assumed that the user will provide a minimum load in order to satisfy this requirement. The synchronous Flyback converter operates at a typical switching frequency of 200kHz, controlled by the current mode controller portion of the LT4267. Galvanic isolation is achieved through transformer T1 and opto-isolator ISO2. The primary side power path is comprised of C1, L1, C9, ½ of T1, Q2, and R11. These components should be as close to each other as possible when laying out the printed circuit board. The secondary side power path is made up of the other ½ of T1, D5, C4 and C5. These parts should also be laid out as close to each other as possible, without overlapping any of the circuitry or traces of the primary side. IN ORDER TO ENSURE PROPER OPERATION, THE DESIGNER MUST ENSURE THAT THE PD INPUT CURRENT REQUIREMENT DOES NOT EXCEED THE LTC4267 CURRENT LIMIT OVER THE UNIT’S OPERATING VOLTAGE RANGE. 3 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 917 POE TO [email protected] ISOLATED Figure 1. Proper Measurement Equipment Setup 4 PHY TO RX- RX+ TX- TX+ VPORTN PWRGD TP14 TP9 TP10 SIGNATURE DISABLE RJ45 1 2 3 6 4 5 7 8 45.3 1% R17 4.7uF TP4 J2 C2 D3 3.3uH 1 R3 220K 1 NGATE MMSZ5237BS 8.2V 2 SMAJ58A 100nF D2 C8 4.7uF 3 8 7 6 5 4 3 2 1 2 1 2 TP3 TP2 TP1 J1 HFJ11-RP28E-L12 14 13 12 TO 11 10 PSE 9 37V to 8 57V 7 6 5 RX4 RX+ 3 2 TX1 TX+ TP16 NC VPORTN NC RCLASS PVCC NGATE PGND ITH/RUN SENSE PGND VFB NC POUT PWRGD SIGDISA VPORTP U1 LTC4267CDHC MMBTA42 Q1 R2 220K 9 10 11 12 13 14 15 16 BAS516 2 2 1 BAS516 D9 HSWAP C9 1uF -48V TP8 R8 6.8K 3 Q2 Si3440DV 1 D6 150 R6 R14 6.8K ISO2 NEC PS2911 R11 0.082 1% 1 2 5 6 4 VPORTN VAUX+ TP15 TP5 3 4 2 PA1721 1 T1 0.047uF 250VAC C15 2.2nF C10 1 1K 8 7 6 5 R12 V+ Q3 FMMT3904 4 3 V+ 1 2 3 2 L1 2 3 0.1uF C4 100uF R18 39K MMSZ5231BS 5.1V D13 C19 R1 R25 43 4.7K 1 2 1 SBM1040 D5 C13 6.8nF D10 ZR431L 1 4.7uF C3 D12 3 BAS516 2 1 2 + 60.4K R19 100K 1% R13 330uF 4V C5 2 1 C1 VOUT+ TP7 GRN D11 R26 150 1206 VOUT- [email protected] TP6 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 917 POE TO [email protected] ISOLATED 5