MC07XS3200, Dual High-side Switch (7.0 mOhm) - Data Sheet

NXP Semiconductors
Advance Information
Document Number: MC07XS3200
Rev. 4.0, 1/2016
Dual High-side Switch (7.0 mOhm)
07XS3200
The 07XS3200 is one in a family of SMARTMOS devices designed for lowvoltage automotive lighting applications. Two low RDS(on) MOSFETs (dual
7.0 mΩ) can control two separate 55 W/28 W bulbs, and/or Xenon modules,
and/or LEDs.
Programming, control and diagnostics are accomplished using a 16-bit SPI
interface. Its output with selectable slew rate improves electromagnetic
compatibility (EMC) behavior. Additionally, each output has its own parallel input
or SPI control for pulse-width modulation (PWM) control if desired. The
07XS3200 allows the user to program via the SPI, the fault current trip levels and
duration of acceptable lamp inrush. The device has Fail-safe mode to provide
fail-safe functionality of the outputs in case of MCU damaged.
The 07XS3200 is packaged in a Pb-free power-enhanced 32 pins SOIC
package with exposed pad.
Features
• Dual 7.0 mΩ max high-side switch (at 25 °C)
• Operating voltage range of 6.0 to 20 V with sleep current < 5.0 µA, extended
mode from 4.0 V to 28 V
• 8.0 MHz 16-bit 3.3 V and 5.0 V SPI control and status reporting with daisy
chain capability
• PWM module using external clock or calibratable internal oscillator with
programmable outputs delay management
• Smart overcurrent shutdown compliant to huge inrush current, severe shortcircuit, overtemperature protections with time limited auto-retry, and Fail-safe
mode, in case of MCU damage
• Output OFF or ON open load detection compliant to bulbs or LEDs and short
to battery detection. Analog current feedback with selectable ratio and board
temperature feedback.
VDD
VDD
VDD
EK SUFFIX PB-FREE
98ASA00368D
32-PIN EXPOSED PAD SOIC
Applications
• Low-voltage automotive lighting
• Halogen bulbs
• Incandescent bulbs
• HID Xenon ballasts
• Low-voltage industrial lighting
VPWR
07XS3200
VDD
I/O
MCU
HIGH-SIDE SWITCH
I/O
FSB
WAKE
SO
SI
SCLK
SCLK
CSB
CSB
SO
SI
I/O
I/O
RSTB
CLOCK
I/O
IN0
I/O
IN1
A/D
VPWR
GND
HS1
HS0
LOAD
LOAD
CSNS
FSI
GND
Figure 1. 07XS3200 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© NXP Semiconductors N.V. 2016. All rights reserved.
Table of Contents
1
2
3
4
5
6
Orderable Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Static Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Dynamic Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2.1Output Current Monitoring (CSNS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2.2Direct Inputs (IN0, IN1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2.3Fault Status (FSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2.4WAKE (WAKE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2.5PWM Clock (CLOCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2.6RESET (RSTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2.7Chip Select (CSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2.8Serial Clock (SCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2.9Serial Input (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2.10Digital Drain Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2.11Ground (GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2.12Positive Power Supply (VPWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2.13Serial Output (SO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2.14High-side Outputs (HS0, HS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2.15Fail-safe Input (FSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3 Functional Internal Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.2 High-side Switches: HS0–HS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Functional Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1 SPI Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2.1 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.2.2 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2.3 Fail-safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.2.4 Normal & Fail-safe Mode Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2.5 Fault Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2.6 Start-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.3 Protection and Diagnostic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3.1 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3.2 Auto-retry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.3.3 Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.3.4 Open Load Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.3.5 Active Clamp ON VPWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3.6 Reverse Battery on VPWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3.7 Ground Disconnect Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
07XS3200
2
Analog Integrated Circuit Device Data
NXP Semiconductors
7
8
9
6.3.8 Loss of Supply Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.9 EMC Performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 Logic Commands and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.1 Serial Input Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.2 Device Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.3 Serial Output Communication (Device Status Return Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.4 Serial Output Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 Soldering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
33
33
33
35
39
39
42
43
43
43
47
07XS3200
Analog Integrated Circuit Device Data
NXP Semiconductors
3
1
Orderable Parts
Table 1. Orderable Part Variations
Part Number
MC07XS3200EK
(1)
Temperature (TA)
Package
-40 °C to 125 °C
32 SOIC
Notes
1. To order parts in Tape & Reel, add the R2 suffix to the part number.
07XS3200
4
Analog Integrated Circuit Device Data
NXP Semiconductors
2
Internal Block Diagram
VDD
IUP
VPWR
VDD Failure
Detection
Internal
Regulator
POR
Over/Undervoltage
Protections
Charge
Pump
VPWR
Voltage Clamp
VREG
CSB
SCLK
Selectable Slew Rate
Gate Driver
IDWN
Selectable Overcurrent
Detection
SO
SI
RSTB
WAKE
FSB
IN0
HS0
Severe Short-circuit
Detection
Logic
Short to VPWR
Detection
Overtemperature
Detection
IN1
CLOCK
Open Load
Detections
HS0
RDWN IDWN
RDWN
HS1
Calibratable
Oscillator
PWM
Module
HS1
Overtemperature
Prewarning
VREG
Selectable Output
Current Recopy
Temperature
Feedback
FSI
Programmable
Watchdog
Analog MUX
VDD
GND
CSNS
Figure 2. 07XS3200 Simplified Internal Block Diagram
07XS3200
Analog Integrated Circuit Device Data
NXP Semiconductors
5
3
Pin Connections
3.1
Pinout Diagram
Transparent top View
1
2
RSTB
CSB
SCLK
SI
VDD
SO
GND
VPWR
NC
HS1
HS1
HS1
HS1
NC
NC
NC
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
WAKE
FSB
IN1
IN0
CLOCK
CSNS
FSI
GND
NC
HS0
HS0
HS0
HS0
NC
NC
NC
Figure 3. 07XS3200 Pin Connection
3.2
Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 21.
Table 2. 07XS3200 Pin Definitions
Pin
Number
Pin Name
Pin
Function
Formal Name
Definition
1
RSTB
Input
Reset (Active Low)
This input pin is used to initialize the device configuration and fault registers, as well as
place the device in a low current Sleep mode.
2
CSB
Input
Chip Select (Active
Low)
This input pin is connected to a chip select output of a master microcontroller (MCU).
3
SCLK
Input
Serial Clock
This input pin is connected to the MCU providing the required bit shift clock for SPI
communication.
4
SI
Input
Serial Input
This is a command data input pin connected to the SPI Serial Data Output of the MCU or
to the SO pin of the previous device of a daisy chain of devices.
5
VDD
Input
Digital Drain Voltage
(Power)
6
SO
Output
Serial Output
This output pin is connected to the SPI serial data input pin of the MCU or to the SI pin of
the next device of a daisy chain of devices.
7, 25
GND
Ground
Ground
Those pins are the ground for the logic and analog circuitry of the device. These pins must
be shorted to board level.
8
VPWR
Power
9, 14 to 19,
24
NC
—
This is an external voltage input pin used to supply power to the SPI circuit.
Pin 8 is a positive supply for quiet and accurate control. Pin 33 is a power supply for the
Positive Power Supply high current switch. These pins must be shorted at board level. Connecting a heatsink to
pin 33 guarantees optimal heat-evacuation properties.
No Connect
These pins are no connected pins. It is recommended to connect these pins to ground.
07XS3200
6
Analog Integrated Circuit Device Data
NXP Semiconductors
Table 2. 07XS3200 Pin Definitions (continued)
Pin
Number
Pin Name
Pin
Function
Formal Name
Definition
10, 11, 12,
13
HS1
Output
High-side Output
Protected 7.0 mΩ high-side power output pin to the load. Those pins must be shorted at
board level.
20, 21, 22,
23
HS0
Output
High-side Output
Protected 7.0 mΩ high-side power output pin to the load. Those pins must be shorted at
board level.
26
FSI
Input
Fail-safe Input
The value of the resistance connected between this pin and ground determines the state
of the outputs after a watchdog timeout occurs.
27
CSNS
Output
Output Current
Monitoring
This pin is used to output a current proportional to the designated HS0-1 output.
28
CLOCK
Input
Reference Clock
29
IN0
Input
Direct Input 0
This input pin is used to directly control the output HS0.
30
IN1
Input
Direct Input 1
This input pin is used to directly control the output HS1.
31
FSB
Output
Fault Status (Active
Low)
This is an open drain configured output requiring an external pull-up resistor to VDD for
fault reporting.
32
WAKE
Input
Wake
This pin is used to input a Logic [1] signal so as to enable the watchdog timer function.
This pin is used to apply a reference clock used to control the outputs in PWM mode
through embedded PWM module.
07XS3200
Analog Integrated Circuit Device Data
NXP Semiconductors
7
4
Electrical Characteristics
4.1
Maximum Ratings
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Ratings
Value
Unit
Notes
ELECTRICAL RATINGS
VPWR(SS)
VDD
VPWR Supply Voltage Range
• Load Dump at 25 °C (400 ms)
• Maximum Operating Voltage
• Reverse Battery
VDD Supply Voltage Range
Input / Output Voltage
41
28
-18
V
-0.3 to 5.5
V
-0.3 to VDD + 0.3
V
ICL(WAKE)
WAKE Input Clamp Current
2.5
mA
ICL(CSNS)
CSNS Input Clamp Current
2.5
mA
VHS[0:1]
HS [0:1] Voltage
• Positive
• Negative
41
-24
V
IHS[0:1]
Output Current per Channel
• Nominal Continuous Current
• Short-circuit Transient Current
• Reverse Continuous Current
26
116
-26
VPWR - VHS
ECL [0:1]
VESD1
VESD2
VESD3
VESD4
A
(5)
(2)
High-side Breakdown Voltage
47
V
HS[0,1] Output Clamp Energy using single pulse method
100
mJ
(3)
V
(4)
ESD Voltage
• Human Body Model (HBM) for HS[0:1], VPWR and GND
• Human Body Model (HBM) for other pins
• Charge Device Model (CDM)
Corner Pins (1, 27, 28, 57)
All Other Pins
± 8000
± 2000
± 750
± 500
THERMAL RATINGS
TA
TJ
TSTG
Operating Temperature
• Ambient
• Junction
- 40 to 125
- 40 to 150
°C
Storage Temperature
- 55 to 150
°C
Notes
2. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current
using board thermal resistance is required.
3. Active clamp energy using single-pulse method (L = 2.0 mH, RL = 0 Ω, VPWR = 14 V, TJ = 150 °C initial).
4.
ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (MM) (CZAP =
200 pF, RZAP = 0 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF).
5.
Input / Output pins are: IN[0:1], CLOCK, RSTB, FSI, CSNS, SI, SCLK, CSB, SO, FSB
07XS3200
8
Analog Integrated Circuit Device Data
NXP Semiconductors
Table 3. Maximum Ratings (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Ratings
Value
Unit
Notes
Thermal Resistance
• Junction to Case
• Junction to Ambient
4.0
35
°C/ W
(6)
Peak Pin Reflow Temperature During Solder Mounting
260
°C
(7)
THERMAL RESISTANCE
RθJC
RθJA
TSOLDER
Notes
6. Device mounted on a 2s2p test board per JEDEC JESD51-2. 20 °C/W of RθJA can be reached in a real application case (4 layers board).
7.
Pin soldering temperature limit is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.
07XS3200
Analog Integrated Circuit Device Data
NXP Semiconductors
9
4.2
Static Electrical Characteristics
Table 4. Static Electrical Characteristics
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
Battery Supply Voltage Range
• Fully Operational
• Extended mode
6.0
4.0
–
–
20
28
V
(8)
Battery Clamp Voltage
41
47
53
V
(9)
IPWR(ON)
VPWR Operating Supply Current
• Outputs commanded ON, HS[0 : 1] open, IN[0:1] > VIH
–
6.5
20
mA
IPWR(SBY)
VPWR Supply Current
• Outputs commanded OFF, OFF Open-load Detection Disabled,
HS[0 : 1] shorted to the ground with VDD = 5.5 V
WAKE > VIH or RSTB > VIH and IN[0:1] < VIL
–
6.5
7.5
mA
–
–
1.0
–
5.0
30
3.0
–
5.5
V
POWER INPUTS
VPWR
VPWR(CLAMP)
IPWR(SLEEP)
Sleep State Supply Current
VPWR = 12 V, RSTB = WAKE = CLOCK = IN[0:1] < VIL, HS[0 :1]
shorted to ground
• TA = 25 °C
• TA = 85 °C
μA
VDD(ON)
VDD Supply Voltage
IDD(ON)
VDD Supply Current at VDD = 5.5 V
• No SPI Communication
• 8.0 MHz SPI Communication
–
–
1.6
5.0
2.2
–
mA
IDD(SLEEP)
VDD Sleep State Current at VDD = 5.5 V
–
–
5.0
μA
VPWR(OV)
Overvoltage Shutdown Threshold
28
32
36
V
VPWR(OVHYS)
Overvoltage Shutdown Hysteresis
0.2
0.8
1.5
V
VPWR(UV)
Undervoltage Shutdown Threshold
3.3
3.9
4.3
V
VSUPPLY(POR)
VPWR and VDD Power on Reset Threshold
0.5
–
0.9
VPWR(UV)
VPWR(UV)_UP
Recovery Undervoltage Threshold
3.4
4.1
4.5
V
VDD Supply Failure Threshold (for VPWR > VPWR(UV))
2.2
2.5
2.8
V
VDD(FAIL)
(10)
(11)
Notes
8. In extended mode, the functionality is guaranteed but not the electrical parameters. From 4.0 V to 6.0 V voltage range, the device is only protected
with the thermal shutdown detection.
9. Measured with the outputs open.
10. Typical value guaranteed per design.
11. Output automatically recovers with time limited auto-retry to instructed state when VPWR voltage is restored to normal as long as the VPWR
degradation level did not go below the undervoltage power-ON reset threshold. This applies to all internal device logic that is supplied by VPWR
and assumes that the external VDD supply is within specification.
07XS3200
10
Analog Integrated Circuit Device Data
NXP Semiconductors
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
–
–
–
–
–
–
–
–
25.2
11.2
7.0
7.0
–
–
–
–
–
–
–
–
42.8
19.1
11.9
11.9
–
–
–
–
10.5
14
21
47
75
89.9
67
48
42
35.2
28.8
21
13.3
11.3
7.4
114.8
83.7
61.2
53.2
44.6
36.4
26.6
18.4
14.2
9.3
139.8
100.4
74.4
64.4
54
44
32.1
23.5
17.1
11.2
–
–
1/10700
1/63600
–
–
Unit
Notes
OUTPUTS HS0 TO HS1
RDS_01(on)
HS[0,1] Output Drain-to-Source ON Resistance (IHS = 5.0 A,
TA = 25 °C)
• VPWR = 4.5 V
• VPWR = 6.0 V
• VPWR = 10 V
• VPWR = 13 V
RDS_01(on)
HS[0,1] Output Drain-to-Source ON Resistance (IHS = 5.0 A,
TA = 150 °C)
• VPWR = 4.5 V
• VPWR = 6.0 V
• VPWR = 10 V
• VPWR = 13 V
RSD_01(on)
HS[0,1] Output Source-to-Drain ON Resistance (IHS = -5.0 A,
VPWR= -18 V)
• TA = 25 °C
• TA = 150 °C
RSHORT_01
OCHI1
OCHI2
OC1
OC2
OC3
OC4
OCLO4
OCLO3
OCLO2
OCLO1
CSR0
CSR1
HS[0,1] Maximum Severe Short-circuit Impedance Detection
HS[0,1] Output Overcurrent Detection Levels (6.0 V < VHS[0:1] < 20 V)
HS[0,1] Current Sense Ratio (6.0 V < VHS[0:1] < 20 V, CSNS < 5.0 V)
• CSNS_ratio bit = 0
• CSNS_ratio bit = 1
mΩ
mΩ
mΩ
(12)
mΩ
(13)
A
–
(14)
Notes
12. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR.
13.
14.
Short-circuit impedance calculated from HS[0:1] to GND pins. Value guaranteed per design.
Current sense ratio = ICSNS / IHS[0:1]
07XS3200
Analog Integrated Circuit Device Data
NXP Semiconductors
11
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
-13
-20
-25
-30
–
–
–
–
13
20
26
30
-18
-25
-30
-40
–
–
–
–
18
25
30
40
Unit
Notes
OUTPUTS HS0 TO HS1 (CONTINUED)
HS[0,1] Current Sense Ratio (CSR0) Accuracy
(6.0 V < VHS[0:1] < 20 V)
25 °C and 125 °C
• IHS[0:1] = 12.5 A
CSR0_ACC
• IHS[0:1] = 5.0 A
• IHS[0:1] = 3.0 A
• IHS[0:1] = 1.5 A
-40 °C
• IHS[0:1] = 12.5 A
• IHS[0:1] = 5.0 A
• IHS[0:1] = 3.0 A
• IHS[0:1] = 1.5 A
CSR0_ACC
(CAL)
Δ(CSR0)/Δ(T)
CSR1_ACC
CSR1_ACC
(CAL)
HS[0,1] Current Recopy Accuracy with one calibration point
(6.0 V < VHS[0:1] < 20 V)
• IHS[0:1] = 5.0 A
HS[0,1] CSR0 Current Recopy Temperature Drift
(6.0 V < VHS[0:1] < 20 V)
• IHS[0:1] = 5.0 A
-5.0
–
%
%
(15)
%/°C
(16)
5.0
–
–
0.04
HS[0,1] Current Sense Ratio (CSR1) Accuracy
(6.0 V < VHS[0:1] < 20 V)
25 °C and 125 °C
• IHS[0:1] = 12.5 A
• IHS[0:1] = 75 A
-17
-15
–
–
17
15
-40 °C
• IHS[0:1] = 12.5 A
• IHS[0:1] = 75 A
-25
-22
–
–
25
22
HS[0,1] Current Recopy Accuracy with one calibration point
(6.0 V < VHS[0:1] < 20 V)
• IHS[0:1] = 12.5 A
-5.0
–
5.0
VDD+0.25
–
VDD+1.0
%
%
VCL(CSNS)
Current Sense Clamp Voltage
• CSNS Open; IHS[0:1] = 5.0 A with CSR0 ratio
IOLD(OFF)
OFF Open Load Detection Source Current
30
–
100
μA
VOLD(THRES)
OFF Open Load Fault Detection Voltage Threshold
2.0
3.0
4.0
V
IOLD(ON)
ON Open Load Fault Detection Current Threshold
80
330
660
mA
IOLD(ON_LED)
ON Open Load Fault Detection Current Threshold with LED
• VHS[0:1] = VPWR - 0.75 V
2.5
5.0
10
mA
VOSD(THRES)
Output Short to VPWR Detection Voltage Threshold
• Output programmed OFF
VPWR-1.2
VPWR-0.8
VPWR-0.4
V
(15)
V
VCL
Output Negative Clamp Voltage
• 0.5 A < IHS[0:1] < 5.0 A, Output programmed OFF
- 22
–
-16
V
TSD
Output Overtemperature Shutdown for 4.5 V < VPWR < 28 V
155
175
195
°C
(17)
Notes
15. Based on statistical analysis. It is not production tested.
16. Based on statistical data: delta(CSR0)/delta(T)={(measured ICSNS at T1 - measured ICSNS at T2) / measured ICSNS at room} / {T1-T2}. No production
tested.
17. Output OFF open load detection current is the current required to flow through the load for the purpose of detecting the existence of an open-load
condition when the specific output is commanded OFF. Pull-up current is measured for VHS = VOLD(THRES)
07XS3200
12
Analog Integrated Circuit Device Data
NXP Semiconductors
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
CONTROL INTERFACE
VIH
Input Logic High Voltage
2.0
–
VDD+0.3
V
(18)
VIL
Input Logic Low Voltage
-0.3
–
0.8
V
(18)
Input Logic Pull-down Current (SCLK, SI)
5.0
–
20
μA
(21)
IUP
Input Logic Pull-up Current (CSB)
5.0
–
20
μA
(22)
CSO
SO, FSB Tri-state Capacitance
–
–
20
pF
(19)
125
250
500
kΩ
Input Capacitance
–
4.0
12
pF
(19)
VCL(WAKE)
Wake Input Clamp Voltage
• ICL(WAKE) < 2.5 mA
18
25
32
V
(20)
VF(WAKE)
Wake Input Forward Voltage
• ICL(WAKE) = -2.5 mA
- 2.0
–
- 0.3
V
VSOH
SO High-state Output Voltage
• IOH = 1.0 mA
VDD-0.4
–
–
V
VSOL
SO and FSB Low-state Output Voltage
• IOL = -1.0 mA
–
–
0.4
V
- 2.0
0.0
2.0
μA
–
10
0.0
Infinite
1.0
–
kΩ
IDWN
RDWN
CIN
ISO(LEAK)
RFS
Input Logic Pull-down Resistor (RSTB, WAKE, CLOCk and IN[0:1])
SO, CSNS and FSB Tri-state Leakage Current
• CSB = VIH and 0 V < VSO < VDD, or FSB = 5.5 V, or
CSNS = 0.0 V
FSI External Pull-down Resistance
• Watchdog Disabled
• Watchdog Enabled
(23)
Notes
18. Upper and lower logic threshold voltage range applies to SI, CSB, SCLK, FSB, IN[0:1], CLOCK and WAKE input signals. The WAKE and RSTB
signals may be supplied by a derived voltage referenced to VPWR.
19.
20.
21.
Input capacitance of SI, CSB, SCLK, RSTB, IN[0:1], CLOCK and WAKE. This parameter is guaranteed by process monitoring but is not production
tested.
The current must be limited by a series resistance when using voltages > 7.0 V.
Pull-down current is with VSI > 1.0 V and VSCLK > 1.0 V.
22.
Pull-up current is with VCSB < 2.0 V. CSB has an active internal pull-up to VDD.
23.
In Fail-safe HS[0:1] depends respectively on IN[0:1]. FSI has an active internal pull-up to VREG ~ 3.0 V.
07XS3200
Analog Integrated Circuit Device Data
NXP Semiconductors
13
4.3
Dynamic Electrical Characteristics
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
SRR_00
Output Rising Medium Slew Rate (medium speed slew rate / SR[1:0] = 00)
• VPWR = 14 V
0.15
0.3
0.6
V/μs
(24)
SRR_01
Output Rising Slow Slew Rate (low speed slew rate / SR[1:0] = 01)
• VPWR = 14 V
0.07
0.15
0.3
V/μs
(24)
SRR_10
Output Falling Fast Slew Rate (high speed slew rate / SR[1:0] = 10)
• VPWR = 14 V
0.3
0.6
1.2
V/μs
(24)
SRF_00
Output Falling Medium Slew Rate (medium speed slew rate / SR[1:0] = 00)
• VPWR = 14 V
0.15
0.3
0.6
V/μs
(24)
SRF_01
Output Falling Slow Slew Rate (low speed slew rate / SR[1:0] = 01)
• VPWR = 14 V
0.07
0.15
0.3
V/μs
(24)
SRF_10
Output Rising Fast Slew Rate (high speed slew rate / SR[1:0] = 10)
• VPWR = 14 V
0.3
0.6
1.2
V/μs
(24)
t DLY_12
HS[0:1] Outputs Turn-ON and OFF Delay Times
VPWR = 14 V for medium speed slew rate (SR[1:0] = 00)
• tDLY(ON)
• tDLY(OFF)
90
40
135
70
180
100
μs
(25) (26)
Driver Output Matching Slew Rate (SRR /SRF)
• VPWR = 14 V at 25 °C and for medium speed slew rate
(SR[1:0] = 00)
0.8
1.0
1.2
HS[0:1] Driver Output Matching Time (t DLY(ON) - t DLY(OFF))
• VPWR = 14 V, f PWM = 240 Hz, PWM duty cycle = 50%, at 25 °C for
medium speed slew rate (SR[1:0] = 00)
25
60
95
μs
tFAULT
Fault Detection Blanking Time
1.0
5.0
20
μs
(27)
tDETECT
Output Shutdown Delay Time
–
7.0
30
μs
(28)
t CNSVAL
CSNS Valid Time
–
70
100
μs
(29)
Watchdog Timeout
217
310
400
ms
(30)
ON Open Load Fault Cyclic Detection Time with LED
105
150
195
ms
POWER OUTPUT TIMING HS0 TO HS1
Δ SR
Δ t RF_01
t WDTO
TOLD(LED)
Notes
24. Rise and Fall Slew Rates measured across a 5.0 Ω resistive load at high-side output = 30% to 70% (see Figure 4, page 18).
25. Turn-ON delay time measured from rising edge of any signal (IN[0 : 1] and CSB) that would turn the output ON to VHS[0 : 1] = VPWR / 2 with
RL = 5.0 Ω resistive load.
26.
Turn-OFF delay time measured from falling edge of any signal (IN[0 : 1] and CSB) that would turn the output OFF to VHS[0 : 1] = VPWR / 2 with
RL = 5.0 Ω resistive load.
27.
28.
Time necessary to report the fault to FSB pin.
Time necessary to switch-off the output in case of OT or OC or SC or UV fault detection (from negative edge of FSB pin to HS voltage = 50% of VPWR
29.
Time necessary for CSNS to be within ±5% of the targeted value (from HS voltage = 50% of VPWR to ±5% of the targeted CSNS value).
30.
For FSI open, the Watchdog timeout delay measured from the rising edge of RSTB, to HS[0,1] output state depend on the corresponding input
command.
07XS3200
14
Analog Integrated Circuit Device Data
NXP Semiconductors
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
4.40
1.62
2.10
2.88
4.58
10.16
73.2
6.30
2.32
3.00
4.12
6.56
14.52
104.6
8.02
3.00
3.90
5.36
8.54
18.88
134.0
1.10
0.40
0.52
0.72
1.14
2.54
18.2
1.57
0.58
0.75
1.03
1.64
3.63
26.1
2.00
0.75
0.98
1.34
2.13
4.72
34.0
OC[1:0]=10 (medium)
2.20
0.81
1.05
1.44
2.29
5.08
36.6
3.15
1.16
1.50
2.06
3.28
7.26
52.3
4.01
1.50
1.95
2.68
4.27
9.44
68.0
OC[1:0]=11 (very slow)
8.8
3.2
4.2
5.7
9.1
20.3
146.4
12.6
4.6
6.0
8.2
13.1
29.0
209.2
16.4
21.4
7.8
10.7
17.0
37.7
272.0
Unit
Notes
POWER OUTPUT TIMING HS0 TO HS1 (continued)
tOC1_00
tOC2_00
tOC3_00
tOC4_00
tOC5_00
tOC6_00
tOC7_00
tOC1_01
tOC2_01
tOC3_01
tOC4_01
tOC5_01
tOC6_01
tOC7_01
tOC1_10
tOC2_10
tOC3_10
tOC4_10
tOC5_10
tOC6_10
tOC7_10
tOC1_11
tOC2_11
tOC3_11
tOC4_11
tOC5_11
tOC6_11
tOC7_11
HS[0,1] Output Overcurrent Time Step
OC[1:0] = 00 (slow by default)
OC[1:0]=01 (fast)
tBC1_00
tBC2_00
tBC3_00
tBC4_00
tBC5_00
tBC6_00
HS[0,1] Bulb Cooling Time Step
CB[1:0] = 00 or 11 (medium)
242
126
140
158
181
211
347
181
200
226
259
302
452
236
260
294
337
393
tBC1_01
tBC2_01
tBC3_01
tBC4_01
tBC5_01
tBC6_01
CB[1:0] = 01 (fast)
121
63
70
79
90
105
173
90
100
113
129
151
226
118
130
147
169
197
484
252
280
316
362
422
694
362
400
452
518
604
1904
472
520
588
674
786
ms
ms
CB[1:0] = 10 (slow)
tBC1_10
tBC2_10
tBC3_10
tBC4_10
tBC5_10
tBC6_10
07XS3200
Analog Integrated Circuit Device Data
NXP Semiconductors
15
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
Input PWM Clock Range on CLOCK
7.68
–
30.72
kHz
fCLOCK(LOW)
Input PWM Clock Low Frequency Detection Range on CLOCK
1.0
2.0
4.0
kHz
(32)
fCLOCK(HIGH)
Input PWM Clock High Frequency Detection Range on CLOCK
100
–
400
kHz
(32)
fPWM
Output PWM Frequency Range Using external clock on CLOCK
31.25
–
781
Hz
(31)
Output PWM Frequency Accuracy Using Calibrated Oscillator
-10
–
+10
%
(31)
Default Output PWM Frequency Using Internal Oscillator
84
120
156
Hz
t CSB(MIN)
CSB Calibration Low Minimum Time Detection Range
14
20
26
μs
t CSB(MAX)
CSB Calibration Low Maximum Tine Detection Range
140
200
260
μs
RPWM_1k
Output PWM Duty Cycle Range for fPWM = 1.0 kHz for high speed slew
rate
10
–
94
%
(32)
RPWM_400
Output PWM Duty Cycle Range for fPWM = 400 Hz
6.0
–
98
%
(32)
RPWM_200
Output PWM Duty Cycle Range for fPWM = 200 Hz
5.0
–
98
%
(32)
Direct Input Toggle Timeout
175
250
325
ms
105
150
195
ms
Thermal Prewarning Detection
110
125
140
°C
Analog Temperature Feedback at TA = 25 °C with RCSNS = 2.5 kΩ
1.15
1.20
1.25
V
Analog Temperature Feedback Derating with RCSNS = 2.5 kΩ
-3.5
-3.7
-3.9
mV/°C
PWM MODULE TIMING
fCLOCK
AFPWM(CAL)
fPWM(0)
INPUT TIMING
tIN
AUTO-RETRY TIMING
tAUTO
Auto-retry Period
TEMPERATURE ON THE GND FLAG
TOTWAR
TFEED
DTFEED
(33)
(34)
Notes
31. Clock Fail detector available for PWM_en bit is set to logic [1] and CLOCK_sel is set to logic [0].
32. The PWM ratio is measured at VHS = 50% of VPWR and for the default SR value. It is possible to put the device fully-on (PWM duty cycle 100%)
and fully-off (duty cycle 0%). For values outside this range, a calibration is needed between the PWM duty cycle programming and the PWM on the
output with RL = 5.0 Ω resistive load.
33.
34.
Typical value guaranteed per design.
Value guaranteed per statistical analysis.
07XS3200
16
Analog Integrated Circuit Device Data
NXP Semiconductors
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
SPI INTERFACE CHARACTERISTICS(35)
f SPI
Maximum Frequency of SPI Operation
–
–
8.0
MHz
t WRSTB
Required Low State Duration for RSTB
10
–
–
μs
(36)
t CSB
Rising Edge of CSB to Falling Edge of CSB (Required Setup Time)
–
–
1.0
μs
(37)
t ENBL
Rising Edge of RSTB to Falling Edge of CSB (Required Setup Time)
–
–
5.0
μs
(37)
t LEAD
Falling Edge of CSB to Rising Edge of SCLK (Required Setup Time)
–
–
500
ns
(37)
t WSCLKh
Required High State Duration of SCLK (Required Setup Time)
–
–
50
ns
(37)
t WSCLKl
Required Low State Duration of SCLK (Required Setup Time)
–
–
50
ns
(37)
Falling Edge of SCLK to Rising Edge of CSB (Required Setup Time)
–
–
60
ns
(37)
t SI (SU)
SI to Falling Edge of SCLK (Required Setup Time)
–
–
37
ns
(38)
t SI (HOLD)
Falling Edge of SCLK to SI (Required Setup Time)
–
–
49
ns
(38)
t RSO
SO Rise Time
• CL = 80 pF
–
–
13
ns
t FSO
SO Fall Time
• CL = 80 pF
–
–
13
ns
t RSI
SI, CSB, SCLK, Incoming Signal Rise Time
–
–
13
ns
(38)
t FSI
SI, CSB, SCLK, Incoming Signal Fall Time
–
–
13
ns
(38)
t SO(EN)
Time from Falling Edge of CSB to SO Low-impedance
–
–
60
ns
(39)
t SO(DIS)
Time from Rising Edge of CSB to SO High-impedance
–
–
60
ns
(40)
t LAG
Notes
35.
36.
37.
38.
39.
40.
Parameters guaranteed by design.
RSTB low duration measured with outputs enabled and going to OFF or disabled condition.
Maximum setup time required for the 07XS3200 is the minimum guaranteed time needed from the microcontroller.
Rise and Fall time of incoming SI, CSB, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at SO. 1.0 kΩ on pull-up on CSB.
Time required for output status data to be terminated at SO. 1.0 kΩ on pull-up on CSB.
07XS3200
Analog Integrated Circuit Device Data
NXP Semiconductors
17
4.4
Timing Diagrams
IN[0:1]
High logic level
Low logic level
Time
or
CSB
High logic level
Low logic level
Time
VHS[0:1]
VPWR
RPWM
50%VPWR
Time
t DLY(ON)
VHS[0:1]
70% VPWR
t DLY(OFF)
SR F
SR R
30% VPWR
Time
Figure 4. Output Slew Rate and Time Delays
IOCH1
IOCH2
Load
Current
IOC1
IOC2
IOC3
IOC4
IOCLO4
IOCLO3
IOCLO2
IOCLO1
Time
t OC3
t OC1
t OC2
t OC4
t OC5
t OC6
t OC7
Figure 5. Overcurrent Shutdown Protection
07XS3200
18
Analog Integrated Circuit Device Data
NXP Semiconductors
IOCH1
IOCH2
IOC1
IOC2
IOC3
IOC4
IOCLO4
IOCLO3
IOCLO2
IOCLO1
t BC3
tB C1
t BC2
t BC4
tB C5
Previous OFF duration
(tOFF)
tB C6
Figure 6. Bulb Cooling Management
VIH
VIH
RSTB
RSTB
10%
0.2
VDDVDD
tWRSTB
VIL
VIL
TwRSTB
tENBL
TCSB
t CSB
TENBL
VIH
VIH
90%
VDD
0.7VDD
CSB
CSB
0.7VDD
10%
VDD
t WSCLKH
TwSCLKh
tTlead
LEAD
VIL
VIL
t RSI
TrSI
t LAG
90%
VDD
0.7VDD
SCLK
SCLK
Tlag
VIH
VIH
10% VDD
0.2VDD
VIL
VIL
t SI(SU)
TSIsu
SI
SI
Don’t Care
90%
0.7 VDD
VDD
0.2VDD
10%
VDD
t WSCLKl
TwSCLKl
t SI(HOLD)
TSI(hold)
tTfSI
FSI
VIH
VIH
Valid
Don’t Care
Valid
Don’t Care
VIH
VIL
Figure 7. Input Timing Switching Characteristics
07XS3200
Analog Integrated Circuit Device Data
NXP Semiconductors
19
tFSI
tRSI
TrSI
TfSI
VOH
VOH
90%
VDD
3.5V
50%
SCLK
SCLK
1.0V VDD
10%
VOL
VOL
t SO(EN)
TdlyLH
SO
SO
90%
VDD
0.7 VDD
0.210%
VDDVDD
VOH
VOH
VOL
VOL
Low-to-High
Low
to High
TrSO
t RSO
VALID
tTVALID
SO
TfSO
t FSO
SO
VOH
VOH
VDD
VDD
High to Low 0.790%
High-to-Low
0.2VDD
10% VDD
TdlyHL
VOL
VOL
t SO(DIS)
Figure 8. SCLK Waveform and Valid SO Data Delay Time
07XS3200
20
Analog Integrated Circuit Device Data
NXP Semiconductors
5
Functional Description
5.1
Introduction
The 07XS3200 is one in a family of devices designed for low-voltage automotive lighting applications. Its two low RDS(on) MOSFETs (dual
7.0 mΩ) can control two separate 55 W/28 W bulbs and/or Xenon modules.
Programming, control and diagnostics are accomplished using a 16-bit SPI interface. Its output with selectable slew rate improves
electromagnetic compatibility (EMC) behavior. Additionally, each output has its own parallel input or SPI control for pulse-width modulation
(PWM) control if desired. The 07XS3200 allows the user to program via the SPI, the fault current trip levels and duration of acceptable
lamp inrush. The device has fail-safe mode to provide fail-safe functionality of the outputs in case of MCU damaged.
5.2
Functional Pin Description
5.2.1
Output Current Monitoring (CSNS)
The Current Sense pin provides a current proportional to the designated HS0 : HS1 output or a voltage proportional to the temperature on
the GND flag. That current is fed into a ground-referenced resistor (2.5 kΩ typical) and its voltage is monitored by an MCU's A/D. The
output type is selected via the SPI. This pin can be tri-stated through the SPI.
5.2.2
Direct Inputs (IN0, IN1)
Each IN input wakes the device. The IN0 : IN1 high-side input pins are also used to directly control HS0 : HS1 high-side output pins. If the
outputs are controlled by PWM module, the external PWM clock is applied to IN0 pin. These pins are to be driven with CMOS levels, and
they have a passive internal pull-down, RDWN.
5.2.3
Fault Status (FSB)
This pin is an open drain configured output requiring an external pull-up resistor to VDD for fault reporting. If a device fault condition is
detected, this pin is active LOW. Specific device diagnostics and faults are reported via the SPI SO pin.
5.2.4
WAKE (WAKE)
The WAKE input wakes the device. An internal clamp protects this pin from high damaging voltages with a series resistor (10 kΩ typ).
This input has a passive internal pull-down, RDWN.
5.2.5
PWM Clock (CLOCK)
The clock input wakes the device. The PWM frequency and timing are generated from clock input by the PWM module. The clock input
frequency is the selectable factor 27 = 128. This input has a passive internal pull-down, RDWN.
5.2.6
RESET (RSTB)
The RESET input wakes the device. This is used to initialize the device configuration and fault registers, as well as place the device in a
low-current Sleep mode. The pin also starts the watchdog timer when transitioning from logic [0] to logic [1]. This pin has a passive internal
pull-down, RDWN.
07XS3200
Analog Integrated Circuit Device Data
NXP Semiconductors
21
5.2.7
Chip Select (CSB)
The CSB pin enables communication with the master microcontroller (MCU). When this pin is in a logic [0] state, the device is capable of
transferring information to, and receiving information from, the MCU. The 07XS3200 latches in data from the Input Shift registers to the
addressed registers on the rising edge of CSB. The device transfers status information from the power output to the Shift register on the
falling edge of CSB. The SO output driver is enabled when CSB is logic [0]. CSB should transition from a logic [1] to a logic [0] state only
when SCLK is a logic [0]. CSB has an active internal pull-up from VDD, IUP.
5.2.8
Serial Clock (SCLK)
The SCLK pin clocks the internal shift registers of the 07XS3200 device. The serial input (SI) pin accepts data into the input shift register
on the falling edge of the SCLK signal while the serial output (SO) pin shifts data information out of the SO line driver on the rising edge
of the SCLK signal. It is important the SCLK pin be in a logic low state whenever CSB makes any transition. For this reason, it is
recommended the SCLK pin be in a logic [0] whenever the device is not accessed (CSB logic [1] state). SCLK has an active internal pulldown. When CSB is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high-impedance) (see Figure 10, page 24).
SCLK input has an active internal pull-down, IDWN.
5.2.9
Serial Input (SI)
This is a serial interface (SI) command data input pin. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of serial data is
required on the SI pin, starting with D15 (MSB) to D0 (LSB). The internal registers of the 07XS3200 are configured and controlled using
a 5-bit addressing scheme described in Table 10, page 34. Register addressing and configuration are described in Tables 11, page 34.
SI input has an active internal pull-down, IDWN.
5.2.10 Digital Drain Voltage (VDD)
This pin is an external voltage input pin used to supply power to the SPI circuit. In the event VDD is lost (VDD Failure), the device goes to
Fail-safe mode.
5.2.11 Ground (GND)
These pins are the ground for the device.
5.2.12 Positive Power Supply (VPWR)
This pin connects to the positive power supply and is the source of operational power for the device. The VPWR contact is the backside
surface mount tab of the package.
5.2.13 Serial Output (SO)
The SO data pin is a tri-stateable output from the shift register. The SO pin remains in a high impedance state until the CSB pin is put into
a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, the state of the key inputs, etc. The
SO pin changes state on the rising edge of SCLK and reads out on the falling edge of SCLK. SO reporting descriptions are provided in
Table 23, page 40.
5.2.14 High-side Outputs (HS0, HS1)
Protected 7.0 mΩ high-side power outputs to the load.
5.2.15 Fail-safe Input (FSI)
This pin incorporates an active internal pull-up current source from internal supply (VREG). This enables the watchdog timeout feature.
When the FSI pin is opened, the watchdog circuit is enabled. After a watchdog timeout occurs, the output states depends on IN[0:1].
When the FSI pin is connected to GND, the watchdog circuit is disabled. The output states depends on IN[0:1] in case of VDD Failure
condition, in case VDD failure detection is activated (VDD_FAIL_en bit sets to logic [1]).
07XS3200
22
Analog Integrated Circuit Device Data
NXP Semiconductors
5.3
Functional Internal Block Description
07XS3200 - Functional Block Diagram
Power Supply
MCU Interface & Output Control
SPI Interface
Parallel Control Inputs
MCU
Interface
Self-protected
High-side
Switches
HS0 - HS1
PWM Controller
Supply
MCU Interface & Output Control
Self-protected High-side Switches
Figure 9. Functional Block Diagram
5.3.1
Power Supply
The 07XS3200 is designed to operate from 4.0 V to 28 V on the VPWR pin. Characteristics are provided from 6.0 V to 20 V for the device.
The VPWR pin supplies power to internal regulator, analog, and logic circuit blocks. The VDD supply is used for Serial Peripheral Interface
(SPI) communication to configure and diagnose the device. This IC architecture provides a low quiescent current sleep mode. Applying
VPWR and VDD to the device places the device in the Normal mode. The device transits to Fail-safe mode in case of failures on the SPI
or/and on VDD voltage.
5.3.2
High-side Switches: HS0–HS1
These pins are the high-side outputs controlling automotive lamps located for the front of vehicle, such as 65 W/55 W bulbs and XenonHID modules. N-channel MOSFETs with 7.0 mΩ RDS(on) are self-protected and present extended diagnostics to detect bulb outage and
a short-circuit fault condition. The HS output is actively clamped during turn off of inductive loads and inductive battery line. When driving
DC motor or solenoid loads demand multiple switching, an external recirculation device must be used to maintain the device in its Safe
Operating Area.
5.3.3
MCU Interface and Output Control
In Normal mode, each bulb is controlled directly from the MCU through the SPI. A pulse width modulation control module allows
improvement of lamp lifetime with bulb power regulation (PWM frequency range from 100 Hz to 400 Hz) and addressing the dimming
application (day running light). An analog feedback output provides a current proportional to the load current or the temperature of the
board. The SPI is used to configure and to read the diagnostic status (faults) of high-side outputs. The reported fault conditions are: open
load, short-circuit to battery, short-circuit to ground (overcurrent and severe short-circuit), thermal shutdown, and under/overvoltage. The
vehicle is lighter thanks to accurate and configurable overcurrent detection circuitry and wire-harness optimization.
In Fail-safe mode, each lamp is controlled with dedicated parallel input pins. The device is configured in default mode.
07XS3200
Analog Integrated Circuit Device Data
NXP Semiconductors
23
6
Functional Device Operation
6.1
SPI Protocol Description
The SPI interface has a full duplex, three-wire synchronous data transfer with four I/O lines associated with it: Serial Input (SI), Serial
Output (SO), Serial Clock (SCLK), and Chip Select (CSB).
The SI / SO pins of the 07XS3200 follow a first-in first-out (D15 to D0) protocol, with both input and output words transferring the most
significant bit (MSB) first. All inputs are compatible with 5.0 V or 3.3 V CMOS logic levels.
CSB
CSB
CS
SCLK
SI
SO
D15
D14
D13
D12
D11
D10
D9
OD15 OD14 OD13 OD12 OD11 OD10 OD9
D8
OD8
D7
OD7
D6
D5
OD6
OD5
D4
OD4
D3
D2
OD3
OD2
D1
D0
OD1 OD0
Notes 1. RSTB is a logic [1] state during the above operation.
D15is: D0
to the
most
ordered entry of data into the device.
NOTES: 1. 2.RSTB
in arelate
logic H state
during
therecent
above operation.
OD15
: OD0
relate
thetofirst
16 bits
ofordered
ordered
fault
and status
data
out IC
of the device.
device.
2. 3.DO,
D1, D2,
... , and
D15to
relate
the most
recent
entry
of program
data into
the LUX
Figure 10. Single 16-Bit Word SPI Communication
6.2
Operational Modes
The 07XS3200 has four operating modes: Sleep, Normal, Fail-safe and Fault. Table 6 and Figure 12 summarize details contained in
succeeding paragraphs.
The Figure 11 describes an internal signal called IN_ON[x] depending on IN[x] input.
IN[x]
tIN
IN_ON[x]
Figure 11. IN_ON[x] internal signal
The 07XS3200 transits to operating modes according to the following signals:
• wake-up = RSTB or WAKE or IN_ON[0] or IN_ON[1] or CLOCK_ON,
• fail = (VDD Failure and VDD_FAIL_en) or (Watchdog timeout and FSI input not shorted to ground),
• fault = OC[0:1] or OT[0:1] or SC[0:1] or UV or (OV and OV_dis).
07XS3200
24
Analog Integrated Circuit Device Data
NXP Semiconductors
Table 6. 07XS3200 Operating Modes
Mode
Wake-up Fail Fault
Comments
Sleep
0
x
x
Device is in Sleep mode. All outputs are OFF.
Normal
1
0
0
Device is currently in Normal mode. Watchdog is active if enabled.
Fail-safe
1
1
0
Device is currently in Fail-safe mode due to watchdog timeout or VDD Failure conditions. The output states are defined
with the RFS resistor connected to FSI.
Fault
1
X
1
Device is currently in fault mode. The faulted output(s) is (are) OFF. The safe auto-retry circuitry is active to turn-on
again the output(s).
x = Don’t care.
(fail=0) and (wake-up=1) and (fault=0)
Sleep
(wake-up=0)
(wake-up=1) and
(fail=1)
and (fault=0)
(wake-up=1)
and (fault=1)
(wake-up=0)
(fail=1) and
(wake-up=1)
and (fault=1)
Fail-safe
Fault
(fail=1) and
(wake-up=1)
and (fault=0)
(wake-up=0)
(fail=0) and
(wake-up=1)
and (fault=1)
Normal
(fail=0) and
(wake-up=1)
and (fault=0)
(fail=0) and (wake-up=1) and (fault=0)
(fail=1) and (wake-up=1) and (fault=0)
Figure 12. Operating Modes
6.2.1
Sleep Mode
The 07XS3200 is in Sleep mode when:
• VPWR and VDD are within the normal voltage range,
• wake-up = 0,
• fail = X,
• fault = X.
This is the Default mode of the device after first applying battery voltage (VPWR) prior to any I/O transitions. This is also the state of the
device when the WAKE and RSTB, CLOCK_ON and IN_ON[0:1] are logic [0]. In the Sleep mode, the output and all unused internal
circuitry, such as the internal regulator, are off to minimize draw current. In addition, all SPI-configurable features of the device are as if
set to logic [0].
In the event of an external VPWR supply disconnect, an unexpected current consumption may sink on the VDD supply pin (In Sleep state).
This current leakage is about 70 mA instead of 5.0 µA and it may impact the device reliability. The device recovers its normal operational
mode once VPWR is reconnected.
To avoid this unexpected current leakage on the VDD supply pin, maintain the device in Normal mode with RSTB pin set to logic[1]. This
allows diagnosis of the battery disconnection event through UV fault reporting in SPI. Then, apply 0 V on the VDD supply pin to switch
the device to Sleep state.
07XS3200
Analog Integrated Circuit Device Data
NXP Semiconductors
25
6.2.2
Normal Mode
The 07XS3200 is in Normal mode when:
• VPWR and VDD are within the normal voltage range,
• wake-up = 1,
• fail = 0,
• fault = 0.
In this mode, the NM bit is set to lfault_contrologic [1] and the outputs HS[0:1] are under control, as defined by the hson signal:
hson[x] = (((IN[x] and DIR_dis[x]) or On bit[x]) and PWM_en) or (On bit [x] and Duty_cycle[x] and PWM_en).
In this mode and also in Fail-safe, the fault condition reset depends on fault_control signal, as defined below:
fault_control[x] = ((IN_ON[x] and DIR_dis[x]) and PWM_en) or (On bit [x]).
6.2.2.1
Programmable PWM Module
The outputs HS[0:1] are controlled by the programmable PWM module if PWM_en and On bits are set to logic [1].
The clock frequency from CLOCK input pin or from the internal clock is the factor 27 (128) of the output PWM frequency (CLOCK_sel bit).
The outputs HS[0:1] can be controlled in the range of 5.0% to 98% with a resolution of 7 bits of duty cycle (Table 7). The state of other IN
pin is ignored.
Table 7. Output PWM Resolution
On bit
Duty cycle
Output state
0
X
OFF
1
0000000
PWM (1/128 duty cycle)
1
0000001
PWM (2/128 duty cycle)
1
0000010
PWM (3/128 duty cycle)
1
n
PWM ((n+1)/128 duty cycle)
1
1111111
fully ON
The timing includes seven programmable PWM switching delay (number of PWM clock rising edges) to improve overall EMC behavior of
the light module (Table 8).
Table 8. Output PWM Switching Delay
Delay bits
Output delay
000
no delay
001
16 PWM clock periods
010
32 PWM clock periods
011
48 PWM clock periods
100
64 PWM clock periods
101
80 PWM clock periods
110
96 PWM clock periods
111
112 PWM clock periods
The clock frequency from CLOCK is permanently monitored in order to report a clock failure in case the frequency is out a specified
frequency range (from fCLOCK(LOW) to fCLOCK(HIGH)). In case of clock failure, no PWM feature is provided, the On bit defines the outputs
state and the CLOCK_fail bit reports [1].
07XS3200
26
Analog Integrated Circuit Device Data
NXP Semiconductors
6.2.2.2
Calibratable Internal Clock
The internal clock can vary as much as ±30 percent corresponding to typical fPWM(0) output switching period.
Using the existing SPI inputs and the precision timing reference already available to the MCU, the 07XS3200 allows clock period setting
within ±10 percent of accuracy. Calibrating the internal clock is initiated by defined word to CALR register. The calibration pulse is provided
by the MCU. The pulse is sent on the CSB pin after the SPI word is launched. At the moment, the CSB pin transitions from logic [1] to [0]
until from logic [0] to [1] determines the period of internal clock with a multiplicative factor of 128.
CS
SI
CALR
SI command
ignored
Internal
clock duration
In case a negative CSB pulse is outside a predefined time range (from t CSB(MIN) to t CSB(MAX)), the calibration event is ignored and the
internal clock is unaltered or reset to the default value (fPWM(0)), if this was not calibrated before.
The calibratable clock is used, instead of the clock from CLOCK input, when CLOCK_sel is set to [1].
6.2.3
Fail-safe Mode
The 07XS3200 is in Fail-safe mode when:
• VPWR is within the normal voltage range,
• wake-up = 1,
• fail = 1,
• fault = 0.
6.2.3.1
Watchdog
If the FSI input is not grounded, the watchdog timeout detection is active when either the WAKE or IN_ON[0:1] or RSTB input pin
transitions from logic [0] to logic [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting resistance limiting the
internal clamp current according to the specification.
The watchdog timeout is a multiple of an internal oscillator. As long as the WD bit (D15) of an incoming SPI message is toggled within the
minimum watchdog timeout period (WDTO), the device operates normally.
6.2.3.2
Fail-safe Conditions
If an internal watchdog timeout occurs before the WD bit for FSI open (Table 9) or in case of VDD failure condition (VDD< VDD(FAIL))) for
VDD_FAIL_en bit is set to logic [1], the device reverts to a Fail-safe mode until the WD bit is written to logic [1] (see Fail-safe to Normal
mode transition paragraph) and VDD is within the normal voltage range.
Table 9. SPI Watchdog Activation
Typical RFSI (Ω)
Watchdog
0 (shorted to ground)
Disabled
(open)
Enable
During the Fail-safe mode, the outputs depend on the corresponding input. The SPI register content is reset to their default value (except
POR bit) and fault protections are fully operational.
The Fail-safe mode can be detected by monitoring the NM bit is set to [0].
07XS3200
Analog Integrated Circuit Device Data
NXP Semiconductors
27
6.2.4
Normal & Fail-safe Mode Transitions
Transition Fail-safe to Normal mode
To leave the Fail-safe mode, VDD must be in nominal voltage and the microcontroller has to send a SPI command with WDIN bit set to
logic [1]; the other bits are not considered. The previous latched faults are reset by the transition into Normal mode (auto-retry included).
Moreover, the device can be brought out of the Fail-safe mode due to watchdog timeout issue by forcing the FSI pin to logic [0].
Transition Normal to Fail-safe mode
To leave the Normal mode, a fail-safe condition must occurred (fail=1). The previous latched faults are reset by the transition into Fail-safe
mode (auto-retry included).
6.2.5
Fault Mode
The 07XS3200 is in Fault mode when:
• VPWR and VDD are within the normal voltage range,
• wake-up = 1,
• fail = X,
• fault=1.
This device indicates the faults below as they occur by driving the FSB pin to logic [0] for RSTB input is pulled up:
• Overtemperature fault,
• Overcurrent fault,
• Severe short-circuit fault,
• Output(s) shorted to VPWR fault in OFF state,
• Open load fault in OFF state,
• Overvoltage fault (enabled by default),
• Undervoltage fault.
The FSB pin automatically returns to logic [1] when the fault condition is removed, except for overcurrent, severe short-circuit,
overtemperature and undervoltage which is reset by a new turn-on command (each fault_control signal to be toggled).
Fault information is retained in the SPI fault register and is available (and reset) via the SO pin during the first valid SPI communication.
The open load fault in ON state is only reported through SPI register without effect on the corresponding output state (HS[x]) and the FS
pin.
6.2.6
Start-up Sequence
The 07XS3200 enters in Normal mode after start-up if following sequence is provided:
• VPWR and VDD power supplies must be above their undervoltage thresholds
• generate wake-up event (wake-up=1) from 0 to 1 on RSTB. The device switches to normal mode with SPI register content is reset (as
defined in Table 11 and Table 23). All features of the 07XS3200 are available after 50 μs typical, and all SPI registers are set to default
values (set to logic [0]).
• toggle WD bit from 0 to 1
And, in case the PWM module is used (PWM_en bit is set to logic [1]) with an external reference clock:
• apply PWM clock on CLOCK input pin after maximum 200 μs (min. 50 μs)
If the correct start-up sequence is not provided, the PWM function is not guaranteed.
07XS3200
28
Analog Integrated Circuit Device Data
NXP Semiconductors
6.3
Protection and Diagnostic Features
6.3.1
Protections
6.3.1.1
Over-temperature Fault
The 07XS3200 incorporates over-temperature detection and shutdown circuitry for each output structure.
Two cases need to be considered when the output temperature is higher than TSD:
• If the output command is ON: the corresponding output is latched OFF. FSB is latched to logic [0]. To delatch the fault and be able to
turn ON again the outputs, the failure condition must disappear and the auto-retry circuitry must be active, or the corresponding output
must be commanded OFF and then ON (toggling fault_control signal of corresponding output) or the VSUPPLY(POR) condition, if VDD = 0.
• If the output command is OFF: FSB changes to logic [0] till the corresponding output temperature are below TSD.
For both cases, the fault register OT[0:1] bit into the status register is set to [1]. The fault bits are cleared in the status register after a SPI
read command.
6.3.1.2
Overcurrent Fault
The 07XS3200 incorporates output shutdown in order to protect each output structure against resistive short-circuit condition. This
protection is composed by four predefined current levels (time dependent) to fit Xenon-HID manners by default or 55 W bulb profiles,
selectable by Xenon bit (as illustrated Figure 14, page 37).
In the first turn-on, the lamp filament is cold and the current is huge. Fault_control signal transitions from logic [0] to [1] or an auto-retry
defines this event. In this case, the overcurrent protection is fitted to inrush current, as shown in Figure 5. This overcurrent protection is
programmable: OC[1:0] bits select overcurrent slope speed and OCHI1 current step can be removed in case the OCHI bit is set to [1].
Over-current thresholds
fault_control
hson
signal
hson
PWM
In Steady state, the wire harness is protected by OCLO2 current level by default. Three other DC overcurrent levels are available: OCLO1
or OCLO3 or OCLO4 based on the state of the OCLO[1,0] bits.
If the load current level ever reaches the overcurrent detection level, the corresponding output latches the output OFF and FSB is also
latched to logic [0]. To delatch the fault and be able to turn ON again the corresponding output, the failure condition must disappear and
the auto-retry circuitry must be active or the corresponding output must be commanded OFF and then ON (toggling fault_control signal
of corresponding output) or VSUPPLY(POR) condition if VDD = 0.
The SPI fault report (OC[0:1] bits) is removed after a read operation.
In Normal mode using internal PWM module, the 07XS3200 incorporates also a cooling bulb filament management if OC_mode and
Xenon are set to logic [1]. In this case, the first step of multi-step overcurrent protection depends on the previous OFF duration, as
illustrated in Figure 6. The following figure illustrates the current level used in function to the duration of previous OFF state (toff). The
slope of cooling bulb emulator is configurable with OCOFFCB[1:0] bits.
07XS3200
Analog Integrated Circuit Device Data
NXP Semiconductors
29
Depending on toff
depending to toff
Over-current thresholds
Cooling
toff
fault_control
hson
signal
hson
PWM
6.3.1.3
Severe Short-circuit Fault
The 07XS3200 provides output shutdown to protect each output in case of a severe short-circuit during of the output switching.
If the short-circuit impedance is below RSHORT, the device latches the output OFF, FSB changes to logic [0] and the fault register SC[0:1]
bit is set to [1]. To delatch the fault and be able to turn ON again the outputs, the failure condition must disappear and the corresponding
output must be commanded OFF and then ON (toggling fault_control signal of corresponding output) or VSUPPLY(POR) condition if VDD = 0.
The SPI fault report (SC[0:1] bits) is removed after a read operation.
6.3.1.4
Overvoltage Fault (Enabled by Default)
By default, the overvoltage protection is enabled. The 07XS3200 shuts down all outputs and FSB goes to logic [0] during an overvoltage
fault condition on the VPWR pin (VPWR > VPWR(OV)). The outputs remain in the OFF state until the overvoltage condition is removed (VPWR
< VPWR(OV) - VPWR(OVHYS)). When experiencing this fault, the OVF fault bit is set to logic [1] and cleared after either a valid SPI read.
The overvoltage protection can be disabled through the SPI (OV_dis bit is disabled set to logic [1]). The fault register reflects any
overvoltage condition (VPWR > VPWR(OV)). This overvoltage diagnosis, as a warning, is removed after a read operation, if the fault condition
disappears. The HS[0:1] outputs are not commanded in RDS(on) above the OV threshold.
6.3.1.5
Undervoltage Fault
The output(s) latch off at some battery voltage below VPWR(UV). As long as the VDD level stays within its operating limits, internal logic
reporting and configuration remain accessible. However, it is not possible to turn the output ON again as long as VPWR remains below
VPWR(UV). In the case where battery voltage drops below the undervoltage threshold (VPWR < VPWR(UV)), the outputs turn off, FSB goes
to logic [0], and the fault register UV bit is set to [1].
Two cases need to be considered when the battery level recovers (VPWR > VPWR(UV)_UP):
• If outputs command are low, FSB goes to logic [1] but the UV bit remains set to 1 until the next read operation (warning report).
• If the output command is ON, FSB remains at logic [0]. To delatch the fault and be able to turn ON again the outputs, the failure condition
must disappear and the auto-retry circuitry must be active or the corresponding output must be commanded OFF and then ON (toggling
fault_control signal of corresponding output) or VSUPPLY(POR) condition if VDD = 0.
In extended mode, the output is protected by overtemperature shutdown circuitry. All previous latched faults, occurred when VPWR was
within the normal voltage range, are guaranteed if VDD is within the operational voltage range or until VSUPPLY(POR) if VDD = 0. Any new
OT fault is detected (VDD failure included) and reported through SPI above VPWR(UV). The output state is not changed as long as the
VPWR voltage does not drop any lower than 3.5 V typical.
All latched faults (overtemperature, overcurrent, severe short-circuit, over and undervoltage) are reset if:
• VDD < VDD(FAIL) with VPWR in nominal voltage range
• VDD and VPWR supplies is below VSUPPLY(POR) voltage value
07XS3200
30
Analog Integrated Circuit Device Data
NXP Semiconductors
(fault_control=0)
(open loadOFF=1
or ShortVpwr=1
or OV=1)
(fault_control=1 and OV=0)
OFF
if hson=0
ON
(fault_control=0 or OV=1)
(fault_control=0)
(open loadOFF=1
or ShortVpwr=1
or OV=1)
(open loadON=1)
(SC=1)
if hson=1
(Retry=1)
Latched
OFF
(count=16)
(SC=1)
(open loadON=1)
(after Retry Period and OV=0)
Auto-retry
(OV=1)
OFF
Auto-retry
ON
if hson=1
(open loadOFF=1
or ShortVpwr=1
or OV=1)
(Retry=1)
=> count=count+1
(fault_control=0)
Figure 13. Auto-retry State Machine
6.3.2
Auto-retry
The auto-retry circuitry is used to reactivate the output(s) automatically in case of overcurrent or overtemperature or undervoltage failure
conditions to provide a high availability of the load. Auto-retry feature is available in Fault mode. It is activated in case of internal retry
signal is set to logic [1]:
retry[x] = OC[x] or OT[x] or UV
The feature retries to switch-on the output(s) after one auto-retry period (tAUTO) with a limitation in term of number of occurrence (16 for
each output). The counter of retry occurrences is reset in case of Fail-safe to Normal or Normal to Fail-safe mode transitions. At each
auto-retry, the overcurrent detection is set to default values in order to sustain the inrush current. The Figure 13 describes the auto-retry
state machine.
6.3.3
Diagnostic
Output Shorted to VPWR Fault
The 07XS3200 incorporates output shorted to VPWR detection circuitry in OFF state. Output shorted to VPWR fault is detected if output
voltage is higher than VOSD(THRES) and reported as a fault condition when the output is disabled (OFF). The output shorted to VPWR fault
is latched into the status register after the internal gate voltage is pulled low enough to turn OFF the output. The OS[0:1] and OL_OFF[0:1]
fault bits are set in the status register and FSB pin reports in real time the fault. If the output shorted to VPWR fault is removed, the status
register is cleared after reading the register. The open output shorted to VPWR protection can be disabled through SPI (OS_DIS[0:1] bit).
6.3.4
Open Load Faults
The 07XS3200 incorporates three dedicated open load detection circuitries on the output to detect in OFF and in ON state.
07XS3200
Analog Integrated Circuit Device Data
NXP Semiconductors
31
6.3.4.1
Open Load Detection in Off State
The OFF output open load fault is detected when the output voltage is higher than VOLD(THRES) pulled up with internal current source
(IOLD(OFF)) and reported as a fault condition when the output is disabled (OFF). The OFF Output open load fault is latched into the status
register or when the internal gate voltage is pulled low enough to turn OFF the output. The OL_OFF[0:1] fault bit is set in the status register.
If the open load fault is removed (FSB output pin goes to high), the status register is cleared after reading the register.
The OFF output open load protection can be disabled through SPI (OLOFF_DIS[0:1] bit).
6.3.4.2
Open Load Detection in On State
The ON output open load current thresholds can be chosen by the SPI to detect a standard bulbs or LEDs (OLLED[0:1] bit set to logic [1]).
In the case where load current drops below the defined current threshold OLON bit is set to logic [1], the output stays ON and FSB is not
disturbed.
6.3.4.3
Open Load Detection in On State For Led
Open load for LEDs only (OLLED[0:1] set to logic [1]) is detected periodically each t OLLED (fully-on, D[6:0]=7F). To detect OLLED in fullyon state, the output must be ON at least t OLLED. To delatch the diagnosis, the condition should be removed and the SPI read operation is
needed (OL_ON[0:1] bit). The ON output open load protection can be disabled through the SPI (OLON_DIS[0:1] bit).
6.3.4.4
Analog Current Recopy and Temperature Feedbacks
The CSNS pin is an analog output reporting a current proportional to the designed output current or a voltage proportional to the
temperature of the GND flag (pin #14). The routing is SPI programmable (TEMP_en, CSNS_en, CSNS_s[1,0] and CSNS_ratio_s bits).
If the current recopy is active, the CSNS output delivers current only during ON time of the output switch without overshoot. The maximum
current is 2.0 mA, typical. The typical value of external CSNS resistor connected to the ground is 2.5 kΩ. The current recopy is not active
in Fail-safe mode.
6.3.4.5
Temperature Prewarning Detection
In Normal mode, the 07XS3200 provides a temperature prewarning reported via the SPI, in case the temperature of the GND flag is higher
than TOTWAR. This diagnosis (OTW bit set to [1]) is latched in the SPI DIAGR0 register. To delatch, a read SPI command is needed.
6.3.5
Active Clamp ON VPWR
The device provides an active gate clamp circuit in order to limit the maximum transient VPWR voltage at VPWR(CLAMP). In case of an
overload on an output, the corresponding output is turned off, which leads to high voltage at VPWR with an inductive VPWR line. When the
VPWR voltage exceeds VPWR(CLAMP) threshold, the turn-off on the corresponding output is deactivated and all HS[0:1] outputs are switched
ON automatically to demagnetize the inductive battery line.
6.3.6
Reverse Battery on VPWR
The output survives the application of reverse voltage as low as -18 V. Under these conditions, the ON resistance of the output is two
times higher than a typical ohmic value in forward mode. No additional passive components are required except on the VDD current path.
6.3.7
Ground Disconnect Protection
In the event the 07XS3200 ground is disconnected from load ground, the device protects itself and safely turns OFF the output, regardless
of the state of the output at the time of disconnection (maximum VPWR = 16 V). A 10 kΩ resistor needs to be added between the MCU and
each digital input pin to ensure the device turns off, during a ground disconnect and to prevent this pin from exceeding maximum ratings.
07XS3200
32
Analog Integrated Circuit Device Data
NXP Semiconductors
6.3.8
6.3.8.1
Loss of Supply Lines
Loss of VDD
If the external VDD supply is disconnected (or not within specification: VDD < VDD(FAIL), with the VDD_FAIL_en bit set to logic [1]), all SPI
register content is reset.
The outputs can still be driven by the direct inputs IN[0 : 1] if VPWR is within specified voltage range. The 07XS3200 uses the battery input
to power the output MOSFET-related current sense circuitry and any other internal logic providing Fail-safe device operation with no VDD
supplied. In this state, the overtemperature, overcurrent, severe short-circuit, short to VPWR and OFF open load circuitry are fully
operational, with default values corresponding to all SPI bits are set to logic [0]. No current is conducted from VPWR to VDD.
6.3.8.2
Loss of VPWR
If the external VPWR supply is disconnected (or not within specification), the SPI configuration, reporting, and daisy chain features are
provided for RSTB to set to logic [1] under VDD in nominal conditions. This fault condition can be diagnosed with UV fault in SPI STATR_s
registers. The SPI pull-up and pull-down current sources are not operational. The previous device configuration is maintained. No current
is conducted from VDD to VPWR.
6.3.8.3
Loss of VPWR and VDD
If the external VPWR and VDD supplies are disconnected (or not within specification: (VDD and VPWR) < VSUPPLY(POR)), all SPI register
contents are reset, with default values corresponding to all SPI bits set to logic [0] and all latched faults reset.
6.3.9
EMC Performances
All following tests are performed on the Freescale evaluation board in accordance with the typical application schematic.
The device is protected in the event of positive and negative transients on the VPWR line (per ISO 7637-2).
The 07XS3200 successfully meets the Class 5 of the CISPR25 emission standard and 200 V/m or BCI 200 mA injection level for immunity
tests.
6.4
Logic Commands and Registers
6.4.1
Serial Input Communication
SPI communication is accomplished using 16-bit messages. A message is transmitted by the MCU starting with the MSB D15 and ending
with the LSB, D0 (Table 10). Each incoming command message on the SI pin can be interpreted using the following bit assignments: the
MSB, D15, is the watchdog bit (WDIN). In some cases, output selection is done with bit D13. The next four bits, D14 -D12: D10, are used
to select the command register. The remaining nine bits, D8 : D0, are used to configure and control the outputs and their protection
features.
Multiple messages can be transmitted in succession to accommodate those applications where daisy-chaining is desirable, or to confirm
transmitted data, as long as the messages are all multiples of 16 bits. Any attempt made to latch in a message that is not 16 bits will be
ignored. The 07XS3200 has defined registers, which are used to configure the device and to control the state of the outputs. Table 11
summarizes the SI registers.
07XS3200
Analog Integrated Circuit Device Data
NXP Semiconductors
33
Table 10. SI Message Bit Assignment
Bit Sig
SI Msg Bit
Message Bit Description
MSB
D15
Watchdog in: toggled to satisfy watchdog requirements.
D13
Register address bit used in some cases for output selection (Table 12).
D14, D12 : D10
Register address bits.
D9
LSB
Not used (set to logic [0]).
D8:D0
Used to configure the inputs, outputs, and the device protection features and SO status content.
Table 11. Serial Input Address and Configuration Bit Map
SI
Register D15 D1 D1 D1 D1 D1 D9
4
3
2 1 0
SI Data
D8
D7
D6
D5
D4
D3
D2
D1
D0
STATR_s
WDI
N
X
X
0
0
0
0
0
0
0
0
SOA4
SOA3
SOA2
SOA1
SOA0
PWMR_s
WDI
N
1
A
0
0
1
0
0 (41)
ON_s
PWM6_s
PWM5_s
PWM4_s
PWM3_s
PWM2_s
PWM1_s
PWM0_s
CONFR0 WDI
_s
N
1
A
0
1
0
0
0
0
0
DIR_dis_s
SR1_s
SR0_s
DELAY2_s
CONFR1 WDI
_s
N
1
A
0
1
1
0
0
0
OCR_s
WDI
N
1
A
1
0
0
0
Xenon
_s
BC1_s
GCR
WDI
N
0
0
1
0
1
0
VDD_F
CLOCK_se
PWM_en
TEMP_en CSNS_en
AIL_en
l
CALR
WDI
N
0
0
1
1
1
0
1
0
1
0
0
0
0
X
X
X
0
0
0
0
0
Register
state after
RST=0 or
VDD(FAIL)
or
VSUPPLY(
DELAY1_
DELAY0_s
s
Retry_
Retry_dis_
OLON_dis_ OLOFF_dis OLLED_e CSNS_rati
OS_dis_s
s
s
_s
n_s
o_s
unlimited_s
BC0_s
OC1_s
OCHI_s
OLCO1_s
OLCO0_s
OC_mode_
s
CSNS1
CSNS0
X
OV_dis
1
1
0
1
1
0
0
0
0
0
OC0_s
POR)
condition
x = Don’t care.
s = Output selection with the bit A as defined in Table 12.
Notes
41. The PWMR_s D8 bit must always be a logic low and never placed in a logic high.
07XS3200
34
Analog Integrated Circuit Device Data
NXP Semiconductors
6.4.2
Device Register Addressing
The following section describes the possible register addresses (D[14:10]) and their impact on device operation.
6.4.2.1
Address XX000 — Status Register (STATR_s)
The STATR register is used to read the device status and the various configuration register contents without disrupting the device
operation or the register contents. The register bits D[4:0] determine the content of the first sixteen bits of SO data. In addition to the device
status, this feature provides the ability to read the content of the PWMR_s, CONFR0_s, CONFR1_s, OCR_s, GCR and CALR registers
(Refer to Serial Output Communication (Device Status Return Data).
6.4.2.2
Address A1A0001— Output PWM Control Register (PWMR_s)
The PWMR_s register allows the MCU to control the state of corresponding output through the SPI. Each output “s” is independently
selected for configuration based on the state of the D13 bit (Table 12).
Table 12. Output Selection
A (D13)
HS Selection
0
HS0 (default)
1
HS1
Bit D7 sets the output state. A logic [1] enables the corresponding output switch and a logic [0] turns it OFF (if IN input is also pulled down).
Bits D6:D0 set the output PWM duty cycle to one of 128 levels for PWM_en is set to logic [1], as shown Table 7.
6.4.2.3
Address A1A0010— Output Configuration Register (CONFR0_S)
The CONFR0_s register allows the MCU to configure corresponding output switching through the SPI. Each output “s” is independently
selected for configuration based on the state of the D14 : D13 bits (Table 12).
For the selected output, a logic [0] on bit D5 (DIR_DIS_s) enables the output for direct control. A logic [1] on bit D5 disables the output
from direct control (in this case, the output is only controlled by the On bit).
D4:D3 bits (SR1_s and SR0_s) are used to select the high or medium or low speed slew rate for the selected output, the default value
[00] corresponds to the medium speed slew rate (Table 13).
Table 13. Slew Rate Speed Selection
SR1_s (D4)
SR0_s (D3)
Slew Rate Speed
0
0
medium (default)
0
1
low
1
0
high
1
1
Not used
Incoming message bits D2 : D0 reflect the desired output that will be delayed of predefined PWM clock rising edges number, as shown
Table 8, (only available for PWM_en bit is set to logic [1]).
6.4.2.4
Address A1A0011 — Output Configuration Register (CONFR1_s)
The CONFR1_s register allows the MCU to configure corresponding output fault management through the SPI. Each output “s” is
independently selected for configuration based on the state of the D14 : D13 bits (Table 12).
A logic [1] on bit D6 (RETRY_unlimited_s) disables the auto-retry counter for the selected output, the default value [0] corresponds to
enable auto-retry feature with time limitation.
A logic [1] on bit D5 (RETRY_dis_s) disables the auto-retry for the selected output, the default value [0] corresponds to enable this feature.
A logic [1] on bit D4 (OS_dis_s) disables the output hard shorted to VPWR protection for the selected output, the default value [0]
corresponds to enable this feature.
A logic [1] on bit D3 (OLON_dis_s) disables the ON output open load detection for the selected output, the default value [0] corresponds
to enable this feature (Table 14).
07XS3200
Analog Integrated Circuit Device Data
NXP Semiconductors
35
A logic [1] on bit D2 (OLOFF_dis_s) disables the OFF output open load detection for the selected output, the default value [0] corresponds
to enable this feature.
A logic [1] on bit D1 (OLLED_en_s) enables the ON output open load detection for LEDs for the selected output, the default value [0]
corresponds to ON output open load detection is set for bulbs (Table 14).
Table 14. ON Open Load Selection
OLON_dis_s (D3)
OLLED_en_s
(D1)
0
0
enable with bulb threshold (default)
0
1
enable with LED threshold
1
X
disable
ON open load detection
A logic [1] on bit D0 (CSNS_ratio_s) selects the high ratio on the CSNS pin for the corresponding output. The default value [0] is the low
ratio (Table 15).
Table 15. Current Sense Ratio Selection
6.4.2.5
CSNS_high_s (D0)
Current Sense Ratio
0
CRS0 (default)
1
CRS1
Address A1A0100 — Output Overcurrent Register (OCR)
The OCR_s register allows the MCU to configure corresponding output overcurrent protection through the SPI. Each output “s” is
independently selected for configuration based on the state of the D14 : D13 bits (Table 12).
A logic [1] on bit D8 (Xenon_s) disables the Xenon bulb overcurrent profile, as described Figure 14.
07XS3200
36
Analog Integrated Circuit Device Data
NXP Semiconductors
Xenon bit set to logic [0]:
IOCH1
IOCH2
IOC1
IOC2
IOCLO4
IOCLO3
IOCLO2
IOCLO1
t OC1
t OC3 t OC4 t OC5
t OC2
t OC6
Time
t OC7
Xenon bit set to logic [1]:
IOCH1
IOCH2
IOC1
IOC2
IOC3
IOC4
IOCL4
IOCL3
IOCL2
IOCL1
t OC1 t OC3 t OC4 t OC5
t OC2
t OC6
Time
t OC7
Figure 14. Overcurrent Profile Depending on Xenon bit
D[7:6] bits allow to MCU to programmable bulb cooling curve and D[5:4] bits inrush curve for selected output, as shown Table 16 and
Table 17.
Table 16. Cooling Curve Selection
BC1_s (D7)
BC0_s (D6)
Profile Curves Speed
0
0
medium (default)
0
1
slow
1
0
fast
1
1
medium
Table 17. Inrush Curve Selection
OC1_s (D5)
OC0_s (D4)
Profile Curves Speed
0
0
slow (default)
0
1
fast
1
0
medium
1
1
very slow
A logic [1] on bit D3 (OCHI_s bit) the OCHI1 level is replaced by OCHI2 during tOC1, as shown Figure 15.
07XS3200
Analog Integrated Circuit Device Data
NXP Semiconductors
37
IOCH1
IOCH2
IOC1
IOC2
IOC3
IOC4
IOCL4
IOCL3
IOCL2
IOCL1
t OC1 t OC3 t OC4 t OC5
t OC2
t OC6
t OC7
Time
Figure 15. Overcurrent Profile with OCHI bit set to ‘1’
The wire harness is protected by one of four possible current levels in steady state, as defined in Table 18.
Table 18. Output Steady State Selection
OCLO1 (D2) OCLO0 (D1)
Steady State Current
0
0
OCLO2 (default)
0
1
OCLO3
1
0
OCLO4
1
1
OCLO1
Bit D0 (OC_mode_sel) allows to select the overcurrent mode, as described Table 19.
Table 19. Overcurrent Mode Selection
OC_mode_s (D0)
Overcurrent Mode
0
only inrush current management (default)
1
inrush current and bulb cooling management
Address 00101 — GLObal configuration regIster (GCR)
The GCR register allows the MCU to configure the device through the SPI.
Bit D8 allows the MCU to enable or disable the VDD failure detector. A logic [1] on VDD_FAIL_en bit allows switch of the outputs HS[0:1]
with PWMR register device in Fail-safe mode in case of VDD < VDD(FAIL).
Bit D7 allows the MCU to enable or disable the PWM module. A logic [1] on PWM_en bit allows control of the outputs HS[0:1] with PWMR
register (the direct input states are ignored).
Bit D6 (CLOCK_sel) allows to select the clock used as reference by PWM module, as described in the following Table 20.
Table 20. PWM Module Selection
PWM_en (D7) CLOCK_sel (D6)
PWM module
0
X
PWM module disabled (default)
1
0
PWM module enabled with external clock from CLOCK
1
1
PWM module enabled with internal calibrated clock
Bits D5:D4 allow the MCU to select one of two analog feedback on CSNS output pin, as shown in Table 21.
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38
Analog Integrated Circuit Device Data
NXP Semiconductors
Table 21. CSNS Reporting Selection
TEMP_en (D5) CSNS_en (D4)
0
CSNS reporting
0
CSNS tri-stated (default)
X
1
current recopy of selected output (D3:2] bits)
1
0
temperature on GND flag
Table 22. Output Current Recopy Selection
CSNS1 (D3)
CSNS0 (D2)
CSNS reporting
1
0
HS0
1
1
HS1
The GCR register disables the overvoltage protection (D0). When this bit is [0], the overvoltage is enabled (default value).
6.4.2.6
Address 00111 — Calibration Register (CALR)
The CALR register allows the MCU to calibrate internal clock, as explained in Figure 13.
6.4.3
Serial Output Communication (Device Status Return Data)
When the CSB pin is pulled low, the output register is loaded. Meanwhile, the data is clocked out MSB- (OD15-) first as the new message
data is clocked into the SI pin. The first sixteen bits of data clocking out of the SO, and following a CSB transition, is dependent upon the
previously written SPI word.
Any bits clocked out of the Serial Output (SO) pin after the first 16 bits are representative of the initial message bits clocked into the SI pin
since the CSB pin first transitioned to a logic [0]. This feature is useful for daisy-chaining devices as well as message verification.
A valid message length is determined following a CSB transition of [0] to [1]. If there is a valid message length, the data is latched into the
appropriate registers. A valid message length is a multiple of 16 bits. At this time, the SO pin is tri-stated and the fault status register is
now able to accept new fault status information.
SO data represents information ranging from fault status to register contents, user selected by writing to the STATR bits OD4, OD3, OD2,
OD1, and OD0. The value of the previous bit SOA3 determines which output the SO information applies to for the registers which are
output specific; viz., Fault, PWMR, CONFR0, CONFR1, and OCR registers.
Note that the SO data continues to reflect the information for each output that was selected during the most recent STATR write until
changed with an updated STATR write.
The output status register correctly reflects the status of the STATR-selected register data at the time that the CSB is pulled to a logic [0]
during SPI communication, and/or for the period of time since the last valid SPI communication, with the following exception:
• The previous SPI communication was determined to be invalid. In this case, the status is reported as though the invalid SPI
communication never occurred
• The VPWR voltage is below 4.0 V, the status must be ignored by the MCU
6.4.4
Serial Output Bit Assignment
The 16 bits of serial output data depend on the previous serial input message, as explained in the following paragraph. Table 23,
summarizes SO returned data for bits OD15 : OD0.
• Bit OD15 is the MSB; it reflects the state of the watchdog bit from the previously clocked-in message
• Bits OD14:OD10 reflect the state of the bits SOA4 : SOA0 from the previously clocked in message
• Bit OD9 is set to logic [1] in Normal mode (NM)
• The contents of bits OD8 : OD0 depend on bits D4 : D0 from the most recent STATR command SOA4 : SOA0 as explained in the
paragraph following Table 23
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39
Table 23. Serial Output Bit Map Description
Previous STATR
SO Returned Data
S S S S S
O O O O O OD OD OD
A A A A A 15 14 13
4 3 2 1 0
OD OD OD O
OD8 OD7
12 11 10 D9
OD6
OD5
OD4
STATR
_s
1
A
0
0
0
WDI SOA SOA SOA SOA SOA
NM POR
N
4
3
2
1
0
PWMR
_s
1
A
0
0
1
WDI SOA SOA SOA SOA SOA
NM
N
4
3
2
1
0
0
CONFR
0_s
1
A
0
1
0
WDI SOA SOA SOA SOA SOA
NM
N
4
3
2
1
0
X
X
CONFR
1_s
1
A
0
1
1
WDI SOA SOA SOA SOA SOA
NM
N
4
3
2
1
0
X
X
OCR_s
1
A
1
0
0
OC0_
WDI SOA SOA SOA SOA SOA
Xeno BC1_
NM
BC0_s OC1_s
N
4
3
2
1
0
n_s
s
s
GCR
0
0
1
0
1
WDI SOA SOA SOA SOA SOA
NM _FAI M_e
N
4
3
2
1
0
UV
OV
OLON_ OLOFF
s
_s
ON_ PWM6 PWM5 PWM4
s
_s
_s
_s
VDD PW
L_en
n
X
DIR_di
SR1_s
s_s
OD3
OD2
OD1
OD0
OS_s
OT_s
SC_s
OC_s
PWM3_s
PWM2_s
PWM1_s PWM0_s
SR0_s
DELAY2_s
DELAY1_ DELAY0_
s
s
Retry_
Retry_ OS_di OLON_dis_ OLOFF_dis_ OLLED_e CSNS_ra
unlimit dis_s
s_s
s
s
n_s
tio_s
ed_s
CLOC TEMP CSNS
K_sel
_en
_en
OCLO0_ OC_mod
s
e_s
OCHI_s
OCLO1_s
CSNS1
CSNS0
X
OV_dis
DIAGR
0
0
0
1
1
1
WDI SOA SOA SOA SOA SOA
NM
N
4
3
2
1
0
X
X
X
X
X
X
CLOCK_fail
CAL_fail
OTW
DIAGR
1
0
1
1
1
1
WDI SOA SOA SOA SOA SOA
NM
N
4
3
2
1
0
X
X
X
X
IN1
IN0
X
X
WD_en
DIAGR
2
1
0
1
1
1
WDI SOA SOA SOA SOA SOA
NM
N
4
3
2
1
0
X
X
X
X
X
X
0
1
0
X
0
0
0
0
0
0
0
0
Regist
er
state
after
RST=0
or
N/ N/ N/ N/ N/
VDD(FA A A A A A
or
IL)
VSUPP
0
0
0
0
0
0
0
LY(POR
)
conditi
on
s = Output selection with the bit A as defined in Table 12
6.4.4.1
Previous Address SOA4 : SOA0 = 1A000 (STATR_s)
The returned data OD8 reports logic [1] in case of previous Power ON Reset condition (VSUPPLY(POR)). This bit is only reset by a read
operation.
Bits OD7: OD0 reflect the current state of the Fault register (FLTR) corresponding to the output previously selected with the bits SOA3 =
A (Table 23).
• OC_s: overcurrent fault detection for a selected output,
• SC_s: severe short-circuit fault detection for a selected output,
• OS_s: output shorted to VPWR fault detection for a selected output,
• OLOFF_s: open load in OFF state fault detection for a selected output,
• OLON_s: open load in ON state fault detection (depending on current level threshold: bulb or LED) for a selected output,
• OV: overvoltage fault detection,
• UV: undervoltage fault detection
• POR: power on reset detection.
The FSB pin reports all faults. For latched faults, this pin is reset by a new Switch OFF command (toggling fault_control signal).
07XS3200
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Analog Integrated Circuit Device Data
NXP Semiconductors
6.4.4.2
Previous Address SOA4 : SOA0 = 1A001 (Pwmr_s)
The returned data contains the programmed values in the PWMR register for the output selected with A.
6.4.4.3
Previous Address SOA4 : SOA0 = 1A010 (confr0_s)
The returned data contains the programmed values in the CONFR0 register for the output selected with A.
6.4.4.4
Previous Address SOA4 : SOA0 = 1A011 (confr1_s)
The returned data contains the programmed values in the CONFR1 register for the output selected with A.
6.4.4.5
Previous Address SOA4 : SOA0 = 1A100 (ocr_s)
The returned data contains the programmed values in the OCR register for the output selected with A.
6.4.4.6
Previous Address SOA4 : SOA0 = 00101 (gcr)
The returned data contains the programmed values in the GCR register.
6.4.4.7
Previous Address SOA4 : SOA0 = 00111 (diagr0)
The returned data OD2 reports logic [1] in case of PWM clock on CLOCK pin is out of specified frequency range.
The returned data OD1 reports logic [1] in case of calibration failure.
The returned data OD0 reports logic [1] in case of overtemperature prewarning (temperature of GND flag is above TOTWAR).
6.4.4.8
Previous Address SOA4 : SOA0 = 01111 (diagr1)
The returned data OD4: OD3 report in real time the state of the direct input IN[1:0].
The OD0 indicates if the watchdog is enabled (set to logic [1]) or not (set to logic [0]). OD4:OD1 report the output state in case of Fail-safe
state due to watchdog timeout as explained in the following Table 24.
Table 24. Watchdog activation report
6.4.4.9
WD_en (OD0)
SPI Watchdog
0
disabled
1
enabled
Previous Address SOA4 : SOA0 = 10111 (diagr2)
The returned data is the product ID. Bits OD2:OD0 are set to 010 for Protected Dual 7.0 mΩ high-side switches.
6.4.4.10
Default Device Configuration
The default device configuration is explained by the following:
• HS output is commanded by the corresponding IN input or On bit through the SPI. The medium slew-rate is used.
• HS output is fully protected by the Xenon overcurrent profile by default, the severe short-circuit protection, the undervoltage and the
overtemperature protection. The auto-retry feature is enabled.
• open load in ON and OFF state and HS shorted to VPWR detections are available
• No current recopy and no analog temperature feedback active
• Overvoltage protection is enabled
• SO reporting fault status must be ignored
• VDD failure detection is disabled
07XS3200
Analog Integrated Circuit Device Data
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41
7
Typical Applications
The following figure shows a typical automotive lighting application (only one vehicle corner) using an external PWM clock from the main
MCU. A redundancy circuitry has been implemented to substitute light control (from MCU to watchdog) in case of a Fail-safe condition.
It is recommended to locate a 22 nF decoupling capacitor to the module connector.
VPWR
VDD
Voltage regulator
100 nF
10 µF
100 nF
VDD
10 µF
VPWR
ignition
switch
VDD
10 k
VPWR
VDD
VPWR
VDD
10 k
100 nF
100 nF
100 nF
VDD
WAKE
I/O
FSB
CLOCK
IN0
IN1
10 k
I/O
MCU
SCLK
CSB
I/O
SO
SI
22 nF
LOAD 0
SPDL07 SOIC
10 k
10 k
10 k
10 k
A/D
HS0
SCLK
CSB
RSTB
SI
SO
CSNS
FSI
10 k
22 nF
HS1
22 nF
LOAD 1
GND
2.5 k
VPWR
Watchdog
direct light commands (pedal, comodo,...)
07XS3200
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Analog Integrated Circuit Device Data
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8
Packaging
8.1
Soldering Information
The 07XS3200 is packaged in a surface mount power package intended to be soldered directly on the printed circuit board.
The 07XS3200 was qualified in accordance with JEDEC standards J-STD-020C Pb-Free reflow profile. The maximum peak temperature
during the soldering process should not exceed 260 °C for 40 seconds maximum duration.
8.2
Package Dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.freescale.com and
perform a keyword search for the drawing’s document number.
Package
Suffix
32-Pin SOICW
EK
Package Outline Drawing Number
98ASA00368D
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Analog Integrated Circuit Device Data
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07XS3200
44
Analog Integrated Circuit Device Data
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Analog Integrated Circuit Device Data
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9
Revision History
Revision
Date
Description of Changes
1.0
2/2013
2.0
6/2013
3.0
•
Initial release
•
•
Assigned final limits for HS[0,1] Current Sense Ratio, ON OpenLoad Fault Detection Current Threshold, HS[0:1]
Outputs Turn-ON and OFF Delay Times, and HS[0:1] Driver Output Matching Time
This revision was cancelled and not released
•
•
•
Updated per GPCN 5352
Corrected pinout on Figure 3 and Table 2
Updated document format
•
•
•
Deleted the 28W mode references as per PB 17069
• Table 4 - relabeled parameter descriptions, conditions, and symbols
• Table 5 - relabeled parameter descriptions, conditions, and symbols
• Table 11 - changed the PWMR_s D8 bit
• Table 23 - changed the PWMR_s D8 bit
Added note (41) for Table 11
Corrected errors in the revision history table
1/2016
•
Corrected PB number
1/2016
•
Detailed a description for the 28W mode change
9/2014
1/2016
4.0
07XS3200
Analog Integrated Circuit Device Data
NXP Semiconductors
47
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© NXP Semiconductors N.V. 2016. All rights reserved.
Document Number: MC07XS3200
Rev. 4.0
1/2016