Freescale Semiconductor Advance Information Document Number: MC10XSC425 Rev. 2.0, 9/2013 Quad High Side Switch (Dual 10 mOhm, Dual 25 mOhm) 10XSC425 The 10XSC425 is one in a family of devices designed for low-voltage lighting or factory automation applications. Its four low RDS(ON) MOSFETs (dual 10 m/dual 25 m) can control four separate 55 W / 28 W bulbs, and/or Xenon modules, and/or LEDs, and/or DC low voltage motors. Programming, control and diagnostics are accomplished using a 16-bit SPI interface. Its output with selectable slew-rate improves electromagnetic compatibility (EMC) behavior. Additionally, each output has its own parallel input or SPI control for pulse-width modulation (PWM) control if desired. The 10XSC425 allows the user to program via the SPI the fault current trip levels and duration of acceptable inrush. The device has fail-safe mode to provide fail-safe functionality of the outputs in case of MCU damaged. This device is powered by SMARTMOS technology. HIGH SIDE SWITCH EK SUFFIX (PB-FREE) 98ASA00368D 32-PIN SOICW-EP Features • Four protected 10 m and 25 m high side switches (at 25 °C) • Operating voltage range of 6.0 to 20 V with sleep current < 5.0 A, extended mode from 4.0 to 28 V • 8.0 MHz 16-bit 3.3 V and 5.0 V SPI control and status reporting with daisy chain capability • PWM module using external clock or calibratable internal oscillator with programmable output delay management • Smart overcurrent shutdown, severe short-circuit, overtemperature protections with time limited autoretry, and failsafe mode, in case of MCU damage • Output OFF or ON open-load detection compliant to bulbs or leds and short to battery detection. • Analog current feedback with selectable ratio and board temperature feedback Applications • Low-voltage industrial lighting • Halogen lamps • Incandescent bulbs • Light-emitting diodes (LEDs) • HID Xenon ballasts • Low voltage factory automation . VDD VDD VPWR VDD VPWR 10XSC425 VDD I/O SCLK CSB SI I/O MCU SO I/O I/O I/O I/O A/D VPWR HS0 WAKE FSB SCLK CSB SO RSTB SI IN0 IN1 IN2 IN3 CSNS FSI GND LOAD HS1 LOAD HS2 LOAD HS3 LOAD GND Figure 1. 10XSC425 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2013. All rights reserved. 10XSC425 2 Analog Integrated Circuit Device Data Freescale Semiconductor Table of Contents 1 2 3 Orderable Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 Static Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 Dynamic Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.1Output Current Monitoring (CSNS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.2Direct Inputs (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.3Fault Status (FSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.4WAKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.5Reset (RSTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.6Chip Select (CSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.7Serial Clock (SCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.8Serial Input (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.9Digital Drain Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.10Ground (GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.11Positive Power Supply (VPWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.12Serial Output (SO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.13High Side Outputs (HS3, HS1, HS0, HS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.14Fail-safe Input (FSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3 Functional Internal Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.2 High Side Switches (HS0–HS3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.3 MCU Interface and Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 Functional Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1 SPI Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2.1Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2.2Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2.3Fail-safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2.4Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2.5Normal and Fail-safe Mode Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2.6Fault Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2.7Start-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.3 Protection and Diagnostic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.3.1Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.3.2Auto-retry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.3.3Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.3.4Analog Current Recopy and Temperature Feedbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.3.5Active Clamp ON VPWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 3 6.3.6Reverse Battery ON VPWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.7Ground Disconnect Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.8Loss of Supply Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.9EMC PERFORMANCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 LOGIC COMMANDS AND REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 Serial Input Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.2 Device Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.3 Serial Output Communication (Device Status Return Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.4 Serial Output Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Soldering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Marking Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Package Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 40 40 40 40 40 42 46 47 50 50 51 51 51 51 55 10XSC425 4 Analog Integrated Circuit Device Data Freescale Semiconductor 1 Orderable Parts This section describes the part numbers available to be purchased along with their differences. Table 1. Orderable Part Variations Part Number (1) Temperature (TA) Package Quad version MC10XSC425EK -40 to 125°C 32 pin SOIC exposed pad Notes 1. To Order parts in Tape & Real, add the R2 suffix to the part number. Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http:// www.freescale.com and perform a part number search for the following device numbers: 07XS and 17XS. 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 5 2 Internal Block Diagram VDD IUP VPWR VDD Failure Detection Internal Regulator POR Over/Undervoltage Protections VPWR Voltage Clamp Charge Pump VREG CSB SCLK Selectable Slew Rate Gate Driver IDWN Selectable Overcurrent Detection SO SI RSTB WAKE FSB IN0 HS0 Severe Short-circuit Detection Logic Short to VPWR Detection Overtemperature Detection IN1 IN2 Open-Load Detections IN3 HS0 RDWN IDWN RDWN HS1 Calibratable Oscillator HS1 PWM Module HS2 VREG HS2 HS3 FSI HS3 Programmable Watchdog Selectable Output Current Recopy Temperature Feedback Overtemperature Prewarning Analog MUX VDD GND CSNS Figure 2. 10XSC425 Simplified Internal Block Diagram 10XSC425 6 Analog Integrated Circuit Device Data Freescale Semiconductor 3 Pin Connections 3.1 Pinout Diagram Transparent Top View of Package WAKE 1 32 FSB RSTB 2 31 IN3 CSB 3 30 IN2 SCLK 4 29 IN1 SI 5 28 IN0 VDD 6 27 CSNS SO 7 26 FSI GND 8 25 GND VPWR 9 24 NC HS3 10 23 HS2 HS3 11 22 HS2 HS3 12 21 HS2 HS3 13 20 HS2 HS1 14 19 HS0 HS1 15 18 HS0 HS1 16 17 HS0 Figure 3. 10XSC425 Pin Connections 3.2 Pin Definitions Table 2. 10XSC425 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 28. Pin Number Pin Name Pin Function Formal Name 1 WAKE Input Wake This input pin controls the device mode. 2 RSTB Input Reset This input pin is used to initialize the device configuration and fault registers, as well as drive the device into a low-current Sleep mode. 3 CSB Input Chip Select (Active Low) This input pin is connected to a chip select output of a master microcontroller (MCU). 4 SCLK Input Serial Clock This input pin is connected to the MCU providing the required bit shift clock for SPI communication. 5 SI Input Serial Input This pin is a command data input pin connected to the SPI Serial Data Output of the MCU or to the SO pin of the previous device of a daisy-chain of devices. 6 VDD Power Digital Drain Voltage This pin is an external voltage input pin used to supply power interfaces to the SPI bus. 7 SO Output Serial Output This output pin is connected to the SPI Serial Data Input pin of the MCU or to the SI pin of the next device of a daisy-chain of devices. Definition 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 7 Table 2. 10XSC425 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 28. Pin Number Pin Name Pin Function Formal Name Definition 8, 25 GND Ground Ground These pins, internally shorted, are the ground for the logic and analog circuitry of the device. These ground pins must be also shorted in the board. 9, 33 VPWR Power Positive Power Supply This pin connects to the positive power supply and is the source of operational power for the device. Pins 9 and 33 must be externally connected. 10, 11, 12, 13 HS3 Output High Side Output Protected 25 m high side power output pins to the load. 14, 15, 16 HS1 Output High Side Output Protected 10 m high side power output pins to the load. 17, 18, 19 HS0 Output High Side Output Protected 10 m high side power output pins to the load. 20, 21, 22, 23 HS2 Output High Side Output Protected 25 m high side power output pins to the load. 24 NC N/A No Connect 26 FSI Input Fail-safe Input This input enables the watchdog timeout feature. 27 CSNS Output Output Current Monitoring This pin reports an analog value proportional to the designated HS[0:3] output current or the temperature of the GND flag (pin 14). It is used externally to generate a ground-referenced voltage for the microcontroller (MCU) . Current recopy and temperature feedback is SPI programmable. 28 29 30 31 IN0 IN1 IN2 IN3 Input Direct Inputs Each direct input controls the device mode. The IN[0 : 3] high side input pins are used to directly control HS0 : HS3 high side output pins. The PWM frequency can be generated from IN0 pin to PWM module in case of external clock is set. 32 FSB Output Fault Status (Active Low) This pin is an open drain configured output requiring an external pull-up resistor to VDD for fault reporting. This pin may not be connected. 10XSC425 8 Analog Integrated Circuit Device Data Freescale Semiconductor 4 Electrical Characteristics 4.1 Maximum Ratings Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Ratings Value Unit Notes ELECTRICAL RATINGS VPWR(SS) VPWR Supply Voltage Range • Load Dump at 25 °C (400 ms) • Maximum Operating Voltage • Reverse Battery V 41 28 -18 VDD VDD Supply Voltage Range -0.3 to 5.5 V VDIG Input / Output Voltage -0.3 to 5.5 V VSO SO and CSNS Output Voltage -0.3 to VDD + 0.3 V IDIG Digital Input/ Output Current in Clamp Mode 100 µA ICL(WAKE) WAKE Input Clamp Current 2.5 mA ICL(CSNS) CSNS Input Clamp Current 2.5 mA HS [0:3] Voltage • Positive • Negative 41 -24 High Side Breakdown Voltage 47 V IHS[0:3] Output Current 6.0 A (2) ECL [0:1] HS[0,1] Output Clamp Energy using single pulse method 60 mJ (3) ECL [2:3] HS[2,3] Output Clamp Energy using single pulse method 25 mJ (3) V (4) VHS[0:3] VPWR - VHS VESD1 VESD2 VESD3 VESD4 ESD Voltage (VPWR Pins 9 and 33 must be externally connected.) • Human Body Model (HBM) for HS[0:3], VPWR and GND • Human Body Model (HBM) for other pins • Charge Device Model (CDM) Corner Pins (1, 13, 19, 21) All Other Pins (2-12, 14-18, 20, 22-24) (5) V ± 8000 ± 2000 ± 750 ± 500 Notes 2. Continuous high side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current using package thermal resistance is required. 3. Active clamp energy using single-pulse method (L = 2.0 mH, RL = 0 , VPWR = 14 V, TJ = 150 C initial). 4. Pins 9 and 33 must be externally connected. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), the Machine Model (MM) (CZAP = 200 pF, RZAP = 0 ), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). 5. Input / Output pins are: IN[0:3], RSTB, FSI, SI, SCLK, CSB, and FSB 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 9 Table 3. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Ratings Value Unit Notes C (5) THERMAL RATINGS TA TJ TSTG Operating Temperature • Ambient • Junction - 40 to 125 - 40 to 150 Storage Temperature - 55 to 150 C THERMAL RESISTANCE RJC RJA TSOLDER Thermal Resistance • Junction to Case • Junction to Ambient <2.5 30 Peak Pin Reflow Temperature During Solder Mounting 260 C/ W (7) C (8) Notes 6. To achieve high reliability over 10 years of continuous operation, the device's continuous operating junction temperature should not exceed 125C. 7. Device mounted on a 2s2p test board per JEDEC JESD51-2. 15 °C/W of RθJA can be reached in a real application case (4 layers board). 8. Pin soldering temperature limit is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 10XSC425 10 Analog Integrated Circuit Device Data Freescale Semiconductor 4.2 Static Electrical Characteristics Table 4. Static Electrical Characteristics Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes V (9) V (10) POWER INPUTS Battery Supply Voltage Range • Fully Operational • Extended mode 6.0 4.0 – – 20 28 VPWR (CLAMP) Battery Clamp Voltage 41 47 53 IPWR(ON) VPWR Operating Supply Current • Outputs commanded ON, HS[0 : 3] open, IN[0:3] > VIH – 6.5 20 VPWR IPWR(SBY) IPWR(SLEEP) VPWR Supply Current • Outputs commanded OFF, OFF Open-load Detection Disabled, HS[0 : 3] shorted to the ground with VDD = 5.5 V WAKE > VIH or RSTB > VIH and IN[0:3] < VIL Sleep State Supply Current VPWR = 12 V, RSTB = WAKE = IN[0:3] < VIL, HS[0 : 3] shorted to ground • TA = 25 °C mA mA – 6.5 7.5 A • TA = 85 °C – – 1.0 – 5.0 30 VDD(ON) VDD Supply Voltage 3.0 – 5.5 IDD(ON) VDD Supply Current at VDD = 5.5 V • No SPI Communication • 8.0 MHz SPI Communication – – 1.6 5.0 2.2 – IDD(SLEEP) VDD Sleep State Current at VDD = 5.5 V – – 5.0 A VPWR(OV) Overvoltage Shutdown Threshold 28 32 36 V VPWR (OVHYS) Overvoltage Shutdown Hysteresis 0.2 0.8 1.5 V VPWR(UV) Undervoltage Shutdown Threshold 3.3 3.9 4.3 V VSUPPLY VPWR and VDD Power on Reset Threshold 0.5 – 0.9 VPWR Recovery Undervoltage Threshold 3.4 4.1 4.5 V VDD Supply Failure Threshold ( for VPWR > VPWR(UV) ) 2.2 2.5 2.8 V (11) mA (POR) VPWR(UV) V (12) (UV) _UP VDD(FAIL) Notes 9. In extended mode, the functionality is guaranteed but not the electrical parameters. From 4.0 to 6.0 V voltage range, the device is only protected with the thermal shutdown detection. 10. Measured with the outputs open. 11. Typical value guaranteed per design. 12. Output will automatically recover with time limited autoretry to instructed state when VPWR voltage is restored to normal as long as the VPWR degradation level did not go below the undervoltage power-ON reset threshold. This applies to all internal device logic that is supplied by VPWR and assumes that the external VDD supply is within specification. 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 11 Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max – – – – – – – – 36 16 10 10 – – – – – – – – 62 27 17 17 Unit Notes OUTPUTS HS0 TO HS3 RDS_01(ON) HS[0,1] Output Drain-to-Source ON Resistance (IHS = 5.0 A, TA = 25 C) • VPWR = 4.5 V • VPWR = 6.0 V • VPWR = 10 V • VPWR = 13 V RDS_01(ON) HS[0,1] Output Drain-to-Source ON Resistance (IHS = 5.0 A, TA = 150 C) • VPWR = 4.5 V • VPWR = 6.0 V • VPWR = 10 V • VPWR = 13 V RSD_01(ON) HS[0,1] Output Source-to-Drain ON Resistance (IHS = -5.0 A, VPWR= -18 V) • TA = 25 C • TA = 150 C RDS_23(ON) HS[2,3] Output Drain-to-Source ON Resistance (IHS = 5.0 A, TA = 25 C) • VPWR = 4.5 V • VPWR = 6.0 V • VPWR = 10 V • VPWR = 13 V RDS_23(ON) HS[2,3] Output Drain-to-Source ON Resistance (IHS = 5.0 A, TA = 150 C) • VPWR = 4.5 V • VPWR = 6.0 V • VPWR = 10 V • VPWR = 13 V RSD_23(ON) HS[2,3] Output Source-to-Drain ON Resistance (IHS = -5.0 A, VPWR= -18 V) • TA = 25 C • TA = 150 C m m m – – – – 15 20 – – – – – – – – 90 40 25 25 – – – – – – – – 153 68 42.5 42.5 (13) m m – – – – 37.5 50 m (13) RSHORT_01 HS[0,1] Maximum Severe Short-circuit Impedance Detection 28 67 100 m (14) RSHORT_23 HS[2,3] Maximum Severe Short-circuit Impedance Detection 70 160 200 m (14) HS[0-3] Output Leakage Current in Off-state • in sleep mode • in normal mode (OS_dis = 1 and OLOFF_dis = 1) – – – – 5.0 30 IOFF A Notes 13. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR. 14. Short-circuit impedance calculated from HS[0:3] to GND pins. Value guaranteed per design. 10XSC425 12 Analog Integrated Circuit Device Data Freescale Semiconductor Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max 77.6 46.4 43.6 40.2 31.6 26.2 19.2 12.1 10.3 6.2 101.6 62 55.6 48.8 40.4 33.2 24.3 15.3 13.1 8.3 125.6 77.6 67.6 57.4 49.2 40.2 29.4 18.4 15.9 10.3 38.8 23.2 21.8 18.6 15.8 13.1 4.6 4.6 4.6 2.9 50.8 31 27.8 23.8 20.2 16.6 6.3 6.3 6.3 4.1 62.8 38.8 33.8 29 24.6 20.1 8.0 8.0 8.0 5.3 Unit Notes OUTPUTS HS0 TO HS3 (CONTINUED) OCHI1_0 OCHI2_0 OC1_0 OC2_0 OC3_0 OC4_0 OCLO4_0 OCLO3_0 OCLO2_0 OCLO1_0 OCHI1_1 OCHI2_1 OC1_1 OC2_1 OC3_1 OC4_1 OCLO4_1 OCLO3_1 OCLO2_1 OCLO1_1 CSR0_0 CSR1_0 CSR0_1 CSR1_1 CSR0_0_ACC HS[0,1] Output Overcurrent Detection Levels (6.0 V < VHS[0:3] < 20 V) • 28W bit = 0 • 28W bit = 1 HS[0,1] Current Sense Ratio (6.0 V < HS[0:3] < 20 V, CSNS < 5.0 V) • 28W bit = 0 CSNS_ratio bit = 0 CSNS_ratio bit = 1 • 28W bit = 1 CSNS_ratio bit = 0 CSNS_ratio bit = 1 HS[0,1] Current Sense Ratio (CSR0) Accuracy (6.0 V < VHS[0:1] < 20 V) with 28W bit = 0 At 25 C and 125 C • IHS[0:1] = 12.5 A • IHS[0:1] = 5.0 A • IHS[0:1] = 3.0 A • IHS[0:1] = 1.5 A At -40 C • IHS[0:1] = 12.5 A • IHS[0:1] = 5.0 A • IHS[0:1] = 3.0 A • IHS[0:1] = 1.5 A A – – – 1/9900 1/58500 – – – – 1/4950 1/29250 – – (15) % -18 -21 -22 -25 – – – – 18 21 22 25 -23 -26 -30 -35 – – – – 23 26 30 35 Notes 15. Current sense ratio = ICSNS / IHS[0:3] 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 13 Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes % (16) %/C (17) OUTPUTS HS0 TO HS3 (CONTINUED) CSR0_0_ACC (CAL) (CSR0_0)/ (T) CSR0_1_ACC HS[0,1] Current Recopy Accuracy with one calibration point (6.0 V < VHS[0:1] < 20 V) with 28W bit = 0 • IHS[0:1] = 5.0 A HS[0,1] CSR0 Current Recopy Temperature Drift (6.0 V < VHS[0:1] < 20 V) with 28W bit = 0 • IHS[0:1] =5.0 A HS[0,1] Current Sense Ratio (CSR0) Accuracy (6.0 V < VHS[0:1 < 20 V) with 28W bit = 1 At 25 C and 125 C • IHS[0:1] = 3.0 A • IHS[0:1] = 1.5 A At -40 C • IHS[0:1] = 3.0 A • IHS[0:1] = 1.5 A CSR0_1_ACC (CAL) CSR1_0_ACC HS[0,1] Current Recopy Accuracy with one calibration point (6.0 V < VHS[0:1] < 20 V) with 28W bit = 1 • IHS[0:1] = 3.0 A HS[0,1] Current Sense Ratio (CSR1) Accuracy (6.0 V < VHS[0:1] < 20 V) with 28W bit = 0 At 25 C and 125 C • IHS[0:1] = 12.5 A • IHS[0:1] = 75A At -40 C • IHS[0:1] = 12.5 A • IHS[0:1] = 75 A CSR1_0_ACC (CAL) CSR1_1_ACC HS[0,1] Current Recopy Accuracy with one calibration point (6.0 V < VHS[0:1] < 20 V) with 28W bit = 0 • IHS[0:1] = 12.5 A HS[0,1] Current Sense Ratio (CSR1) Accuracy (6.0 V < VHS[0:1] < 20 V) with 28W bit = 1 At 25 C and 125 C • IHS[0:1] = 12.5 A • IHS[0:1] = 37.5 A at -40 C • IHS[0:1] = 12.5 A • IHS[0:1] = 37.5 A CSR1_1_ACC (CAL) HS[0,1] Current Recopy Accuracy with one calibration point (6.0 V < VHS[0:1] < 20 V) with 28W bit = 1 • IHS[0:1] = 12.5 A -5.0 – – – 5.0 0.04 % -22 -25 – – 22 25 -30 -35 – – 30 35 % -5.0 – (16) 5.0 % -20 -18 – – 20 18 -30 -25 – – 30 25 % -5.0 – (16) 5.0 % -22 -20 – – 22 20 -27 -25 – – 27 25 % -5.0 – (16) 5.0 Notes 16. Based on statistical analysis. It is not production tested. 17. Based on statistical data: delta (CSR0)/delta (T) = {(measured ICSNS at T1 - measured ICSNS at T2) / measured ICSNS at room} / {T1-T2}. Not production tested. 10XSC425 14 Analog Integrated Circuit Device Data Freescale Semiconductor Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit VDD+0.25 – VDD+1.0 OFF OpenLoad Detection Source Current 30 – 100 A OFF OpenLoad Fault Detection Voltage Threshold 2.0 3.0 4.0 V 2.5 5.0 10 mA 80 55 360 165 660 330 VPWR-1.2 VPWR-0.8 VPWR-0.4 Output Negative Clamp Voltage • 0.5 A < IHS[0:3] < 5.0 A, Output programmed OFF - 22 – -16 Output Overtemperature Shutdown for 4.5 V < VPWR < 28 V 155 175 195 38.8 23.2 21.8 17.3 14.7 12.2 9.2 5.8 4.6 2.9 50.8 31 27.3 22.9 19.2 15.8 11.9 7.6 6.3 4.1 62.8 38.8 32.8 28.4 23.7 19.4 14.5 9.3 8.0 5.3 – – 1/4670 1/27270 – – Notes OUTPUTS HS0 TO HS3 (CONTINUED) VCL(CSNS) IOLD(OFF) VOLD(THRES) Current Sense Clamp Voltage • CSNS Open; IHS[0:3] = 5.0 A with CSR0 ratio IOLD(ON_LED) ON OpenLoad Fault Detection Current Threshold with LED (VHS[0:3] = VPWR -0.75 V IOLD(ON) ON OpenLoad Fault Detection Current Threshold • HS[0,1] • HS[2,3] VOSD(THRES) Output Short to VPWR Detection Voltage Threshold • Output programmed OFF VCL TSD V mA V V HS[2,3] Output Overcurrent Detection Levels (6.0 V < VHS[0:3] < 20 V) OCHI1_1 OCHI2_1 OC1_1 OC2_1 OC3_1 OC4_1 OCLO4_1 OCLO3_1 OCLO2_1 OCLO1_1 CSR0_x CSR1_x HS[2,3] Current Sense Ratio (6.0 V < HS[2:3] < 20 V, CSNS < 5.0 V) CSNS_ratio bit = 0 CSNS_ratio bit = 1 (18) C A – (19) Notes 18. Output OFF OpenLoad Detection Current is the current required to flow through the load for the purpose of detecting the existence of an OpenLoad condition when the specific output is commanded OFF. Pull-up current is measured for VHS = VOLD(THRES) 19. Current sense ratio = ICSNS / IHS[0:3] 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 15 Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes OUTPUTS HS0 TO HS3 (CONTINUED) CSR0_x_ACC HS[2,3] Current Sense Ratio (CSR0) Accuracy (6.0 V < VHS[2:3] < 20 V) with 28W bit = x At 25 C and 125 C • IHS[2:3] = 6.25 A • IHS[2:3] = 2.5 A • IHS[2:3] = 1.5 A • IHS[2:3] = 0.75 A At -40 C • IHS[2:3] = 6.25 A • IHS[2:3] = 2.5 A • IHS[2:3] = 1.5 A • IHS[2:3] = 0.75 A CSR0_x_ACC (CAL) (CSR0_x)/ (T) CSR1_x_ACC HS[2,3] Current Recopy Accuracy with one calibration point (6.0 V < VHS[2:3] < 20 V) • IHS[2:3] = 2.5 A HS[2,3] CSR0 Current Recopy Temperature Drift (6.0 V < VHS[2:3] < 20 V) with 28W bit = 0 • IHS[2:3] = 2.5 A HS[2,3] Current Sense Ratio (CSR1) Accuracy (6.0 V < VHS[2:3] < 20 V) At 25 C and 125 C • IHS[2:3] = 6.25 A • IHS[2:3] = 18.75 A At -40 C • IHS[2:3] = 6.25 A • IHS[2:3] = 18.75 A CSR1_x_ACC (CAL) HS[2,3] Current Recopy Accuracy with one calibration point (6.0 V < VHS[2:3] < 20 V) • IHS[2:3] = 6.2 A % -18 -21 -22 -25 – – – – 18 21 22 25 -23 -26 -30 -35 – – – – 23 26 30 35 -5.0 – – – % (20) %/C (20) 5.0 0.04 % -22 -25 – – +22 +25 -25 -27 – – +25 +27 -5.0 – 5.0 % (20) CONTROL INTERFACE VIH Input Logic High-voltage 2.0 – VDD+0.3 V (21) VIL Input Logic Low-voltage -0.3 – 0.8 V (21) Input Logic Pull-down Current (SCLK, SI) 5.0 – 20 A (22) IUP Input Logic Pull-up Current (CSB) 5.0 – 20 A (23) CSO SO, FSB Tri-state Capacitance – – 20 pF (24) IDWN Notes 20. Based on statistical analysis. It is not production tested. 21. Upper and lower logic threshold voltage range applies to SI, CSB, SCLK, RSTB, IN[0:3], and WAKE input signals. The WAKE and RSTB signals may be supplied by a derived voltage referenced to VPWR. 22. Pull-down current is with VSI > 1.0 V and VSCLK > 1.0 V. 23. Pull-up current is with VCSB < 2.0 V. CSB has an active internal pull-up to VDD. 24. Input capacitance of SI, CSB, SCLK, RSTB, IN[0:3], and WAKE. This parameter is guaranteed by process monitoring but is not production tested. 10XSC425 16 Analog Integrated Circuit Device Data Freescale Semiconductor Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes 125 250 500 k – 4.0 12 pF (26) V (25) CONTROL INTERFACE (CONTINUED) RDWN CIN VCL(WAKE) VF(WAKE) Input Logic Pull-down Resistor (RSTB, WAKE and IN[0:3]) Input Capacitance Wake Input Clamp Voltage • ICL(WAKE) < 2.5 mA VSOL ISO(LEAK) RFS 25 32 - 2.0 – - 0.3 VDD-0.4 – – – – 0.4 - 2.0 0 2.0 Wake Input Forward Voltage • ICL(WAKE) = -2.5 mA VSOH 18 SO High State Output Voltage • IOH = 1.0 mA SO and FSB Low State Output Voltage • IOL = -1.0 mA SO, CSNS and FSB Tri-state Leakage Current • CSB = VIH and 0.0 V < VSO < VDD, or FSB = 5.5 V, or CSNS = 0.0 V FSI External Pull-down Resistance Watchdog Disabled Watchdog Enabled V V V A (27) k – 10 0 Infinite 1.0 – Notes 25. The current must be limited by a series resistance when using voltages > 7.0 V. 26. Input capacitance of SI, CSB, SCLK, RSTB, IN[0:3], and WAKE. This parameter is guaranteed by process monitoring but is not production tested. 27. In Fail-safe, HS[0:3] depends respectively on ON[0:3]. FSI has an active internal pull-up to VREG 3.0 V. 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 17 4.3 Dynamic Electrical Characteristics Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max 300 650 1200 300 720 1200 0.8 0.9 1.2 150 330 600 150 370 600 600 1250 2400 600 1450 2400 Unit Notes POWER OUTPUT TIMING HS0 TO HS3 SRR00 SRF00 DSR_00 SRR01 SRF01 SRR10 SRF10 Output Rising Medium Slew Rate (medium speed slew rate / SR[1:0] = 00) Output Falling Medium Slew Rate (medium speed slew rate / SR[1:0] = 00) Driver Output Matching Slew Rate (SRR /SRF) • PWR = 14 V at 25 °C and for medium speed slew rate (SR[1:0] = 00) V SRR01 SRF01 mV/s Output Falling Fast Slew Rate (medium speed slew rate / SR[1:0] = 10) t DLY_OFF DSR_00 mV/s Output Rising Fast Slew Rate (medium speed slew rate / SR[1:0] = 10) HS[0:1] Outputs Turn-OFF Delay Times • VPWR = 14 for medium speed slew rate (SR[1:0] = 00) V SRF00 mV/s Output Falling Low Slew Rate (medium speed slew rate / SR[1:0] = 01) HS[0:1] Outputs Turn-ON Delay Times • VPWR = 14 for medium speed slew rate (SR[1:0] = 00) V SRR00 mV/s Output Rising Low Slew Rate (medium speed slew rate / SR[1:0] = 01) t DLY_ON t RF mV/s HS[0:1] Driver Output Matching Time (tDLY(ON) - tDLY(OFF)) • VPWR = 14 V, fPWM = 240 Hz, PWM duty cycle = 50%, at 25 °C for medium speed slew rate (SR[1:0] = 00) mV/s 40 64 10 32 s (28),(29) s (28),(29) s (28),(29) 100 60 10 32 60 200 470 800 200 570 800 0.6 0.8 1.0 100 230 400 100 300 400 HS[2,3] Output Overcurrent Detection Levels (6.0 V < VHS[0:3] < 20 V) mV/s HS[2,3] Output Overcurrent Detection Levels (6.0 V < VHS[0:3] < 20 V) mV/s HS[2,3] Output Overcurrent Detection Levels (6.0 V < VHS[0:3] < 20 V) HS[2,3] Output Overcurrent Detection Levels (6.0 V < VHS[0:3] < 20 V) mV/s HS[2,3] Output Overcurrent Detection Levels (6.0 V < VHS[0:3] < 20 V) mV/s Notes 28. Turn ON delay time measured from rising edge of any signal (IN[0 : 3] and CSB) that would turn the output ON to VHS[0 : 3] = VPWR / 2 with RL = 5.0 resistive load. 29. Turn OFF delay time measured from falling edge of any signal (IN[0 : 3] and CSB) that would turn the output OFF to VHS[0 : 3] = VPWR / 2 with RL = 5.0 resistive load. 10XSC425 18 Analog Integrated Circuit Device Data Freescale Semiconductor Table 5. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max 400 900 1600 400 1140 1600 40 87 160 15 36 65 10 51 110 Unit Notes POWER OUTPUT TIMING HS0 TO HS3 (CONTINUED) SRR10 SRF10 t DLY_ON t DLY_OFF t RF HS[2,3] Output Overcurrent Detection Levels (6.0 V < VHS[0:3] < 20 V) mV/s HS[2,3] Output Overcurrent Detection Levels (6.0 V < VHS[0:3] < 20 V) mV/s HS[2,3] Output Overcurrent Detection Levels (6.0 V < VHS[0:3] < 20 V) s HS[2,3] Output Overcurrent Detection Levels (6.0 V < VHS[0:3] < 20 V) s HS[2,3] Output Overcurrent Detection Levels (6.0 V < VHS[0:3] < 20 V) s tFAULT Fault Detection Blanking Time 1.0 5.0 20 s (30) tDETECT Output Shutdown Delay Time – 7.0 30 s (31) t CNSVAL CSNS Valid Time – 70 100 s (32) Watchdog Timeout 217 310 400 ms (33) ON OpenLoad Fault Cyclic Detection Time with LED 105 150 195 ms t WDTO TOLD(LED) Notes 30. Time necessary to report the fault to FSB pin. 31. Time necessary to switch-off the output in case of OT, or OC, or SC, or UV fault detection (from negative edge of FSB pin to HS voltage = 50% of VPWR. 32. 33. Time necessary for CSNS to be within ±5.0% of the targeted value (from HS voltage = 50% of VPWR to ±5.0% of the targeted CSNS value). For FSI open, the Watchdog timeout delay measured from the rising edge of RST, to HS[0,2] output state depend on the corresponding input command. 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 19 Table 5. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max 4.40 1.62 2.10 2.88 4.58 10.16 73.2 6.30 2.32 3.00 4.12 6.56 14.52 104.6 8.02 3.00 3.90 5.36 8.54 18.88 134.0 Unit Notes POWER OUTPUT TIMING HS0 TO HS3 (CONTINUED) tOC1_00 tOC2_00 tOC3_00 tOC4_00 tOC5_00 tOC6_00 tOC7_00 HS[0,1] Output Overcurrent Time Step for 28W bit = 0 • OC[1:0] = 00 (slow by default) ms tOC1_01 tOC2_01 tOC3_01 tOC4_01 tOC5_01 tOC6_01 tOC7_01 • OC[1:0] = 01 (fast) 1.10 0.40 0.52 0.72 1.14 2.54 18.2 1.57 0.58 0.75 1.03 1.64 3.63 26.1 2.00 0.75 0.98 1.34 2.13 4.72 34.0 tOC1_10 tOC2_10 tOC3_10 tOC4_10 tOC5_10 tOC6_10 tOC7_10 • OC[1:0] = 10 (medium) 2.20 0.81 1.05 1.44 2.29 5.08 36.6 3.15 1.16 1.50 2.06 3.28 7.26 52.3 4.01 1.50 1.95 2.68 4.27 9.44 68.0 tOC1_11 tOC2_11 tOC3_11 tOC4_11 tOC5_11 tOC6_11 tOC7_11 • OC[1:0] = 11 (very slow) 8.8 3.2 4.2 5.7 9.1 20.3 146.4 12.6 4.6 6.0 8.2 13.1 29.0 209.2 16.4 21.4 7.8 10.7 17.0 37.7 272.0 10XSC425 20 Analog Integrated Circuit Device Data Freescale Semiconductor Table 5. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes POWER OUTPUT TIMING HS0 TO HS3 (CONTINUED) tOC1_00 tOC2_00 tOC3_00 tOC4_00 tOC5_00 tOC6_00 tOC7_00 HS[0,1] Output Overcurrent Time Step for 28W bit = 1 HS[2,3] Output Overcurrent Time Step • OC[1:0] = 00 (slow by default) ms 3.4 1.1 1.4 2.0 3.4 8.5 62.4 4.9 1.6 2.1 2.9 4.9 12.2 89.2 6.4 2.1 2.8 3.8 6.4 15.9 116.0 tOC1_01 tOC2_01 tOC3_01 tOC4_01 tOC5_01 tOC6_01 tOC7_01 • OC[1:0] = 01 (fast) 0.86 0.28 0.36 0.51 0.78 2.14 20.2 1.24 0.40 0.52 0.74 1.12 3.06 22.2 1.61 0.52 0.68 0.96 1.46 3.98 28.9 tOC1_10 tOC2_10 tOC3_10 tOC4_10 tOC5_10 tOC6_10 tOC7_10 • OC[1:0] = 10 (medium) 1.7 0.5 0.7 1.0 1.7 4.2 31.2 2.5 0.8 1.0 1.5 2.5 6.1 44.6 3.3 1.0 1.3 2.0 3.3 6.0 58.0 tOC1_11 tOC2_11 tOC3_11 tOC4_11 tOC5_11 tOC6_11 tOC7_11 • OC[1:0] = 11 (very slow) 6.8 2.2 2.9 4.0 6.8 17.0 124.8 9.8 3.2 4.2 5.8 9.8 24.4 178.4 12.8 16.7 5.5 7.6 12.8 31.8 232.0 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 21 Table 5. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max 242 126 140 158 181 211 347 181 200 226 259 302 452 236 260 294 337 393 121 63 70 79 90 105 173 90 100 113 129 151 226 118 130 147 169 197 484 252 280 316 362 422 694 362 400 452 518 604 1904 472 520 588 674 786 291 156 178 208 251 314 417 224 255 298 359 449 542 292 332 388 467 584 146 78 88 101 126 226 209 112 127 145 180 324 272 146 166 189 234 422 583 312 357 417 501 628 834 448 510 596 717 898 1085 582 665 775 933 1170 Unit Notes POWER OUTPUT TIMING HS0 TO HS3 (CONTINUED) tBC1_00 tBC2_00 tBC3_00 tBC4_00 tBC5_00 tBC6_00 tBC1_01 tBC2_01 tBC3_01 tBC4_01 tBC5_01 tBC6_01 HS[0,1] Bulb Cooling Time Step for 28W bit = 0 • CB[1:0] = 00 or 11 (medium) • CB[1:0] = 01 (fast) ms • CB[1:0] = 10 (slow) tBC1_10 tBC2_10 tBC3_10 tBC4_10 tBC5_10 tBC6_10 HS[0,1] for 28W bit = 1 or for HS2-HS3 • CB[1:0] = 00 or 11 (medium) tBC1_00 tBC2_00 tBC3_00 tBC4_00 tBC5_00 tBC6_00 • CB[1:0] = 01 (fast) tBC1_01 tBC2_01 tBC3_01 tBC4_01 tBC5_01 tBC6_01 • CB[1:0] = 10 (slow) tBC1_10 tBC2_10 tBC3_10 tBC4_10 tBC5_10 tBC6_10 10XSC425 22 Analog Integrated Circuit Device Data Freescale Semiconductor Table 5. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes Input PWM Clock Range on IN0 7.68 – 30.72 kHz fIN0(LOW) Input PWM Clock Low Frequency Detection Range on IN0 1.0 2.0 4.0 kHz (35) fIN0(HIGH) Input PWM Clock High Frequency Detection Range on IN0 100 – 400 kHz (35) fPWM Output PWM Frequency Range using External Clock on IN0 31.25 – 781 Hz -10 – +10 % Default Output PWM Frequency using Internal Oscillator 84 120 156 Hz t CSB(MIN) CSB Calibration Low Minimum Time Detection Range 14 20 26 s t CSB(MAX) CSB Calibration Low Maximum Tine Detection Range 140 200 260 s RPWM_1k Output PWM Duty Cycle Range for fPWM = 1.0 kHz for high speed slew rate 10 – 94 % (35) RPWM_400 Output PWM Duty Cycle Range for fPWM = 400 Hz 6.0 – 98 % (35) RPWM_200 Output PWM Duty Cycle Range for fPWM = 200 Hz 5.0 – 98 % (35) 175 250 325 ms 105 150 195 ms Thermal Prewarning Detection 110 125 140 °C Analog Temperature Feedback at TA = 25 °C with RCSNS = 2.5 k 1.15 1.20 1.25 V Analog Temperature Feedback Derating with RCSNS = 2.5 k -3.5 -3.7 -3.9 mV/°C PWM MODULE TIMING fIN0 AFPWM(CAL) Output PWM Frequency Accuracy using Calibrated Oscillator fPWM(0) INPUT TIMING tIN Direct Input Toggle Timeout AUTORETRY TIMING tAUTO Autoretry Period TEMPERATURE ON THE GND FLAG TOTWAR TFEED DTFEED (36) (37) Notes 34. Clock Fail detector available for PWM_en bit is set to logic [1] and CLOCK_sel is set to logic [0]. 35. The PWM ratio is measured at VHS = 50% of VPWR and for the default SR value. It is possible to put the device fully on (PWM duty cycle 100%) and fully off (duty cycle 0%). For values outside this range, a calibration is needed between the PWM duty cycle programming and the PWM on the output with RL = 5.0 resistive load. 36. 37. Typical value guaranteed per design. Value guaranteed per statistical analysis. 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 23 Table 5. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes SPI INTERFACE CHARACTERISTICS(38) f SPI Maximum Frequency of SPI Operation – – 8.0 MHz t WRSTB Required Low State Duration for RSTB 10 – – s (39) t CSB Rising Edge of CSB to Falling Edge of CSB (Required Setup Time) – – 1.0 s (40) t ENBL Rising Edge of RSTB to Falling Edge of CSB (Required Setup Time) – – 5.0 s (40) t LEAD Falling Edge of CSB to Rising Edge of SCLK (Required Setup Time) – – 500 ns (40) t WSCLKh Required High State Duration of SCLK (Required Setup Time) – – 50 ns (40) t WSCLKl Required Low State Duration of SCLK (Required Setup Time) – – 50 ns (40) Falling Edge of SCLK to Rising Edge of CSB (Required Setup Time) – – 60 ns (40) t SI (SU) SI to Falling Edge of SCLK (Required Setup Time) – – 37 ns (41) t SI (HOLD) Falling Edge of SCLK to SI (Required Setup Time) – – 49 ns (41) SO Rise Time • CL = 80 pF – – 13 SO Fall Time • CL = 80 pF – – 13 t RSI SI, CSB, SCLK, Incoming Signal Rise Time – – 13 ns (41) t FSI SI, CSB, SCLK, Incoming Signal Fall Time – – 13 ns (41) t SO(EN) Time from Falling Edge of CSB to SO Low-impedance – – 60 ns (42) t SO(DIS) Time from Rising Edge of CSB to SO High-impedance – – 60 ns (43) t LAG t RSO t FSO Notes 38. 39. 40. 41. 42. 43. ns ns Parameters guaranteed by design. RSTB low duration measured with outputs enabled and going to OFF or disabled condition. Maximum setup time required for the 10XSC425 is the minimum guaranteed time needed from the microcontroller. Rise and Fall time of incoming SI, CSB, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for output status data to be available for use at SO. 1.0 kon pull-up on CSB. Time required for output status data to be terminated at SO. 1.0 kon pull-up on CSB. 10XSC425 24 Analog Integrated Circuit Device Data Freescale Semiconductor 4.4 Timing Diagrams IN[0:3] High logic level Low logic level Time or CSB High logic level Low logic level Time VHS[0:3] VPWR RPWM 50%VPWR Time t DLY(ON) VHS[0:3] 70% VPWR t DLY(OFF) SR F SR R 30% VPWR Time Figure 4. Output Slew Rate and Time Delays IOCH1 IOCH2 Load Current IOC1 IOC2 IOC3 IOC4 IOCLO4 IOCLO3 IOCLO2 IOCLO1 Time t OC1 t OC2 t OC3 t OC4 t OC5 t OC6 t OC7 Figure 5. Overcurrent Shutdown Protection 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 25 IOCH1 IOCH2 IOC1 IOC2 IOC3 IOC4 IOCLO4 IOCLO3 IOCLO2 IOCLO1 t BC3 tB C1 t BC2 t BC4 tB C5 Previous OFF duration (toff) tB C6 Figure 6. Bulb Cooling Management VIH VIH RSTB RSTB 10% 0.2 VDDVDD tWRSTB TwRSTB tENBL VIL VIL tTCSB CSB TENBL VIH VIH 90% VDD 0.7VDD CSB CSB 10% VDD 0.7VDD t WSCLKH TwSCLKh tTlead LEAD VIL VIL t RSI TrSI t LAG Tlag 90% VDD 0.7VDD SCLK SCLK VIH VIH 10% VDD 0.2VDD t TSIsu SI(SU) VIL VIL t WSCLKl TwSCLKl t SI(HOLD) TSI(hold) SI SI Don’t Care 90% VDD 0.7 VDD 0.2VDD 10% VDD Valid tTfSI FSI Don’t Care Valid Don’t Care VIH VIH VIL VIH Figure 7. Input Timing Switching Characteristics 10XSC425 26 Analog Integrated Circuit Device Data Freescale Semiconductor tFSI tRSI TrSI TfSI VOH VOH 90% VDD 3.5V 50% SCLK SCLK 1.0V VDD 10% VOL VOL t SO(EN) TdlyLH SO SO 90% VDD 0.7 VDD 0.210% VDDVDD VOH VOH VOL VOL Low-to-High Low to High TrSO t RSO VALID tTVALID SO TfSO t FSO SO VOH VOH VDD VDD High to Low 0.790% High-to-Low 0.2VDD 10% VDD TdlyHL VOL VOL t SO(DIS) Figure 8. SCLK Waveform and Valid SO Data Delay Time 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 27 5 Functional Description 5.1 Introduction The 10XSC425 is one in a family of devices designed for low-voltage lighting applications. Its four low RDS(ON) MOSFETs (dual 10 m, dual 25 m) can control four separate 55 W / 28 W bulbs and/or Xenon modules. Programming, control, and diagnostics are accomplished using a 16-bit SPI interface. Its output with selectable slew rate improves electromagnetic compatibility (EMC) behavior. Additionally, each output has its own parallel input or SPI control for pulse-width modulation (PWM) control if desired. The 10XSC425 allows the user to program via the SPI the fault current trip levels and duration of acceptable lamp inrush. The device has Fail-safe mode to provide Fail-safe functionality of the outputs in case of MCU damaged. 5.2 Functional Pin Description 5.2.1 Output Current Monitoring (CSNS) The current sense pin provides a current proportional to the designated HS0 : HS3 output or a voltage proportional to the temperature on the GND flag. That current is fed into a ground-referenced resistor (3.3 k, typical) and its voltage is monitored by an MCU's A/D. The output type is selected via the SPI. This pin can be tri-stated through the SPI. 5.2.2 Direct Inputs (IN0, IN1, IN2, IN3) Each IN input wakes the device. The IN0 : IN3 high side input pins are also used to directly control HS0 : HS3 high side output pins. If the outputs are controlled by the PWM module, the external PWM clock is applied to the IN0 pin. These pins are to be driven with CMOS levels, and they have a passive internal pull-down, RDWN. 5.2.3 Fault Status (FSB) This pin is an open drain configured output requiring an external pull-up resistor to VDD for fault reporting. If a device fault condition is detected, this pin is active LOW. Specific device diagnostics and faults are reported via the SPI SO pin. 5.2.4 WAKE The wake input wakes the device. An internal clamp protects this pin from high damaging voltages with a series resistor (10 k typ). This input has a passive internal pull-down, RDWN. 5.2.5 Reset (RSTB) The reset input wakes the device. This is used to initialize the device configuration and fault registers, as well as drive the device into a low-current Sleep mode. The pin also starts the watchdog timer when transitioning from logic [0] to logic [1]. This pin has a passive internal pull-down, RDWN. 5.2.6 Chip Select (CSB) The CSB pin enables communication with the master microcontroller (MCU). When this pin is in a logic [0] state, the device is capable of transferring information to, and receiving information from, the MCU. The 10XSC425 latches in data from the Input Shift registers to the addressed registers on the rising edge of CSB. The device transfers status information from the power output to the Shift register on the falling edge of CSB. The SO output driver is enabled when CSB is a logic [0]. CSB should transition from a logic [1] to a logic [0] state only when SCLK is a logic [0]. CSB has an active internal pull-up from VDD, IUP. 10XSC425 28 Analog Integrated Circuit Device Data Freescale Semiconductor 5.2.7 Serial Clock (SCLK) The SCLK pin clocks the internal shift registers of the 10XSC425 device. The serial input (SI) pin accepts data into the input shift register on the falling edge of the SCLK signal, while the serial output (SO) pin shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important the SCLK pin be in a logic low state whenever CSB makes any transition. For this reason, it is recommended the SCLK pin be in a logic [0] whenever the device is not accessed (CSB logic [1] state). SCLK has an active internal pull-down. When CSB is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (highimpedance) (see Figure 10, page 31). SCLK input has an active internal pull-down, IDWN. 5.2.8 Serial Input (SI) This is a serial interface (SI) command data input pin. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of serial data is required on the SI pin, starting with D15 (MSB) to D0 (LSB). The internal registers of the 10XSC425 are configured and controlled using a 5-bit addressing scheme described in Table 10. Register addressing and configuration are described in Table 11. SI input has an active internal pull-down, IDWN. 5.2.9 Digital Drain Voltage (VDD) This pin is an external voltage input pin used to supply power to the SPI circuit. In the event VDD is lost (VDD Failure), the device goes to Fail-safe mode. 5.2.10 Ground (GND) These pins are the ground for the device. 5.2.11 Positive Power Supply (VPWR) This pin connects to the positive power supply and is the source of operational power for the device. The VPWR contact is the backside surface mount tab of the package. 5.2.12 Serial Output (SO) The SO data pin is a tri-stateable output from the shift register. The SO pin remains in a high-impedance state until the CSB pin is put into a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, the state of the key inputs, etc. The SO pin changes state on the rising edge of SCLK and reads out on the falling edge of SCLK. SO reporting descriptions are provided in Table 23. 5.2.13 High Side Outputs (HS3, HS1, HS0, HS2) Protected 10 m and 25 m high side power outputs to the load. 5.2.14 Fail-safe Input (FSI) This pin incorporates an active internal pull-up current source from internal supply (VREG). This enables the watchdog timeout feature. When the FSI pin is opened, the Watchdog circuit is enabled. After a Watchdog timeout occurs, the output states depends on IN[0:3]. When the FSI pin is connected to GND, the Watchdog circuit is disabled. The output states depends on IN[0:3] in case of a VDD Failure condition. In case a VDD failure detection is activated (VDD_FAIL_en bit sets to logic [1]). 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 29 5.3 Functional Internal Block Description 10XSC425 - Functional Block Diagram Power Supply MCU Interface & Output Control Self-Protected High Side Switches HS0-HS3 SPI Interface Parallel Control Inputs MCU Interface PWM Controller Supply MCU Interface & Output Control Self-Protected High Side Switches Figure 9. Functional Block Diagram 5.3.1 Power Supply The 10XSC425 is designed to operate from 4.0 to 28 V on the VPWR pin. Characteristics are provided from 6.0 to 20 V for the device. The VPWR pin supplies power to internal regulator, analog, and logic circuit blocks. The VDD supply is used for Serial Peripheral Interface (SPI) communication in order to configure and diagnose the device. This IC architecture provides a low quiescent current Sleep mode. Applying VPWR and VDD to the device will place the device in the Normal mode. The device will transit to Fail-safe mode during failures on the SPI or/and on VDD voltage. 5.3.2 High Side Switches (HS0–HS3) These pins are the high side outputs controlling lamps located for the front of vehicle, such as 65 W/55 W bulbs and Xenon-HID modules. Those N-channel MOSFETs with 10 m and 25 m RDS(ON) are self-protected and present extended diagnostics in order to detect bulb outage and short-circuit fault condition. The HS output is actively clamped during turn off of inductive loads and inductive battery line. When driving DC motor or Solenoid loads demanding multiple switching, an external recirculation device must be used to maintain the device in its Safe Operating Area. 5.3.3 MCU Interface and Output Control In Normal mode, each bulb is controlled directly from the MCU through the SPI. A pulse-width modulation control module allows improvement of lamp lifetime with bulb power regulation (PWM frequency range of 100 to 400 Hz) and addressing the dimming application (day running light). An analog feedback output provides a current proportional to the load current or the temperature of the board. The SPI is used to configure and to read the diagnostic status (faults) of high side outputs. The reported fault conditions are: OpenLoad, short-circuit to battery, short-circuit to ground (overcurrent and severe short-circuit), thermal shutdown, and under/overvoltage. Owing to accurate and configurable overcurrent detection circuitry and wire-harness optimization, the vehicle is lighter. In Fail-safe mode, each lamp is controlled with dedicated parallel input pins. The device is configured in Default mode. 10XSC425 30 Analog Integrated Circuit Device Data Freescale Semiconductor 6 Functional Device Operation 6.1 SPI Protocol Description The SPI interface has a full duplex, three-wire synchronous data transfer with four I/O lines associated with it: Serial Input (SI), Serial Output (SO), Serial Clock (SCLK), and Chip Select (CSB). The SI / SO pins of the 10XSC425 follow a first-in first-out (D15 to D0) protocol, with both input and output words transferring the most significant bit (MSB) first. All inputs are compatible with 5.0 or 3.3 V CMOS logic levels. CSB CSB CS SCLK SI SO D15 D14 D13 D12 D11 D10 D9 OD15 OD14 OD13 OD12 OD11 OD10 OD9 D8 OD8 D7 D6 OD7 D5 OD6 OD5 D4 OD4 D3 OD3 D2 OD2 D1 D0 OD1 OD0 Notes 1. RSTB is a logic [1] state during the above operation. D15:D0 to the most ordered entry of data into the device. NOTES: 1. 2.RSTB is in arelate logic H state during therecent above operation. OD15:OD0 relate thetofirst 16 bits ofordered ordered fault and status data out of the device. device. 2. 3.DO, D1, D2, ... , and D15to relate the most recent entry of program data into the LUX IC device. 3. OD0, OD1, OD2, ..., and OD15 relate to the first 16 bits of ordered fault and status data out of the LUX IC Figure 10. Single 16-Bit Word SPI Communication 6.2 Operational Modes The 10XSC425 has four operating modes: Sleep, Normal, Fail-Safe and Fault. Table 6 and Figure 12 summarize details contained in succeeding paragraphs. The Figure 11 describes an internal signal called IN_ON[x] depending on IN[x] input. IN[x] tIN IN_ON[x] Figure 11. IN_ON[x] Internal Signal The 10XSC425 transits to operating modes according to the following signals: • wake-up = RSTB or WAKE or IN_ON[0] or IN_ON[1] or IN_ON[2] or IN_ON[3], • fail = (VDD Failure and VDD_FAIL_en) or (Watchdog timeout and FSI input not shorted to ground), • fault = OC[0:3] or OT[0:3] or SC[0:3] or UV or (OV and OV_dis). 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 31 Table 6. 10XSC425 Operating Modes Mode Wake-up Fail Fault Comments Sleep 0 x x Device is in Sleep mode. All outputs are OFF. Normal 1 0 0 Device is currently in Normal mode. Watchdog is active if enabled. Fail-safe 1 1 0 Device is currently in Fail-safe mode due to Watchdog timeout or VDD Failure conditions. The output states are defined with the RFS resistor connected to FSI. Fault 1 X 1 Device is currently in fault mode. The faulted output(s) is (are) OFF. The safe autoretry circuitry is active to turn-on again the output(s). x = Don’t care. (wake-up = 1) and (fail = 1) and (fault = 0) (wake-up = 1) and (fault = 1) (wake-up = 0) (fail = 1) and (wake-up 0 = 1) and (fault = 1) Fail-safe (fail = 0) and (wake-up = 1) and (fault = 0) Sleep (wake-up = 0) Fault (fail = 1) and (wake-up = 1) and (fault = 0) (wake-up = 0) (fail = 0) and (wake-up = 1) and (fault = 1) Normal (fail = 0) and (wake-up = 1) and (fault = 0) (fail = 0) and (wake-up = 1) and (fault = 0) (fail = 1) and (wake-up = 1) and (fault = 0) Figure 12. Operating Modes 6.2.1 Sleep Mode The 10XSC425 is in Sleep mode when: • VPWR and VDD are within the normal voltage range, • wake-up = 0, • fail = X, • fault = X. This is the Default mode of the device after first applying battery voltage (VPWR) prior to any I/O transitions. This is also the state of the device when the WAKE and RSTB and IN_ON[0:3] are logic [0]. In the Sleep mode, the output and all unused internal circuitry, such as the internal regulator, are off to minimize draw current. In addition, all SPI-configurable features of the device are as if set to logic [0]. 10XSC425 32 Analog Integrated Circuit Device Data Freescale Semiconductor 6.2.2 Normal Mode The 10XSC425 is in Normal mode when: • VPWR and VDD are within the normal voltage range, • wake-up = 1, • fail = 0, • fault = 0. In this mode, the NM bit is set to lfault_contrologic [1] and the outputs HS[0:3] are under control, as defined by hson signal: hson[x] = ( ( (IN[x] and DIR_dis[x]) or On bit[x] ) and PWM_en ) or (On bit [x] and Duty_cycle[x] and PWM_en). In this mode and also in Fail-safe, the fault condition reset depends on fault_control signal, as defined by the following: fault_control[x] = ( (IN_ON[x] and DIR_dis[x]) and PWM_en ) or (On bit [x]). 6.2.2.1 Programmable PWM Module The outputs HS[0:3] are controlled by the programmable PWM module if PWM_en and the On bits are set to logic [1]. The clock frequency from IN0 input pin or from internal clock is the factor 27 (128) of the output PWM frequency (CLOCK_sel bit). The outputs HS[0:3] can be controlled in the range of 5.0 to 98% with a resolution of seven bits of duty cycle (Table 7). The state of other IN pin is ignored. Table 7. Output PWM Resolution On bit Duty cycle Output state 0 X OFF 1 0000000 PWM (1/128 duty cycle) 1 0000001 PWM (2/128 duty cycle) 1 0000010 PWM (3/128 duty cycle) 1 n PWM ((n+1)/128 duty cycle) 1 1111111 fully ON The timing includes seven programmable PWM switching delay (number of PWM clock rising edges) to improve overall EMC behavior of the light module (Table 8). Table 8. Output PWM Switching Delay Delay bits Output delay 000 no delay 001 16 PWM clock periods 010 32 PWM clock periods 011 48 PWM clock periods 100 64 PWM clock periods 101 80 PWM clock periods 110 96 PWM clock periods 111 112 PWM clock periods The clock frequency from IN0 is permanently monitored in order to report a clock failure in case the frequency is out of the specified frequency range (from fIN0(LOW) to fIN0(HIGH)). In case of a clock failure, no PWM feature is provided, the On bit defines the outputs state and the CLOCK_fail bit reports [1]. 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 33 6.2.2.2 Calibratable Internal Clock The internal clock can vary as much as 30%, corresponding to a typical fPWM(0) output switching period. Using the existing SPI inputs and the precision timing reference already available to the MCU, the 10XSC425 allows clock period setting within 10% accuracy. Calibrating the internal clock is initiated by defined word to CALR register. The calibration pulse is provided by the MCU. The pulse is sent on the CSB pin after the SPI word is launched. At the moment, the CSB pin transitions from a logic [1] to [0], until from a logic [0] to [1], determine the period of the internal clock with a multiplicative factor of 128. CSB SI CALR SI command ignored Internal clock duration In case a negative CSB pulse is outside a predefined time range (from t CSB(MIN) to t CSB(MAX)), the calibration event will be ignored and the internal clock will be unaltered, or reset to the default value (fPWM(0)), if this was not calibrated before. The calibratable clock is used instead of the clock from the IN0 input, when CLOCK_sel is set to [1]. 6.2.3 Fail-safe Mode The 10XSC425 is in Fail-safe mode when: • VPWR is within the normal voltage range, • wake-up = 1, • fail = 1, • fault = 0. 6.2.4 Watchdog If the FSI input is not grounded, the watchdog timeout detection is active when either the WAKE, or IN_ON[0:3], or RSTB input pin transitions from logic [0] to logic [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting resistance limiting the internal clamp current according to the specification. The Watchdog timeout is a multiple of an internal oscillator. As long as the WD bit (D15) of an incoming SPI message is toggled within the minimum watchdog timeout period (WDTO), the device will operate normally. 6.2.4.1 Fail-Safe Conditions If an internal watchdog timeout occurs before the WD bit for FSI open (Table 9) or in case of a VDD failure condition (VDD< VDD(FAIL)) for VDD_FAIL_en bit is set to logic [1], the device will revert to a Fail-safe mode until the WD bit is written to a logic [1] (see fail-safe to normal mode transition paragraph) and VDD is within the normal voltage range. Table 9. SPI Watchdog Activation Typical RFSI () Watchdog 0 (shorted to ground) Disabled (open) Enable During the Fail-safe mode, the outputs will depend on the corresponding input. The SPI register content is reset to their default value (except POR bit) and fault protections are fully operational. The Fail-safe mode can be detected by monitoring the NM bit is set to [0]. 10XSC425 34 Analog Integrated Circuit Device Data Freescale Semiconductor 6.2.5 6.2.5.1 Normal and Fail-safe Mode Transitions Transition Fail-safe to Normal Mode To leave the Fail-safe mode, VDD must be in nominal voltage and the microcontroller has to send a SPI command with the WDIN bit set to logic [1]; the other bits are not considered. The previous latched faults are reset by the transition into Normal mode (autoretry included). Moreover, the device can be brought out of the Fail-safe mode due to a watchdog timeout issue, by forcing the FSI pin to logic [0]. 6.2.5.2 Transition Normal to Fail-safe Mode To leave the Normal mode, a fail-safe condition must occurred (fail=1). The previous latched faults are reset by the transition into Fail-safe mode (autoretry included). 6.2.6 Fault Mode The 10XSC425 is in Fault mode when: • VPWR and VDD are within the normal voltage range, • wake-up = 1, • fail = X, • fault=1. This device indicates the faults below as they occur by driving the FSB pin to logic [0] for RSTB input is pulled up: • Overtemperature fault, • Overcurrent fault, • Severe short-circuit fault, • Output(s) shorted to VPWR fault in OFF state, • OpenLoad fault in OFF state, • Overvoltage fault (enabled by default), • Undervoltage fault. The FSB pin will automatically return to logic [1] when the fault condition is removed, except for overcurrent, severe short-circuit, overtemperature, and undervoltage which will be reset by a new turn-on command (each fault_control signal to be toggled). Fault information is retained in the SPI fault register and is available (and reset) via the SO pin during the first valid SPI communication. The OpenLoad fault in ON state is only reported through SPI register without effect on the corresponding output state (HS[x]) and the FSB pin. 6.2.7 Start-up Sequence The 10XSC425 enters in Normal mode after start-up if following sequence is provided: • VPWR and VDD power supplies must be above their undervoltage thresholds, • generate wake-up event (wake-up = 1) from 0 to 1 on RSTB. The device switches to Normal mode with the SPI register content reset (as defined in Table 11 and Table 23). All features of the 10XSC425 will be available after 50 s (typical), and all SPI registers are set to default values (set to logic [0]). • toggle WD bit from 0 to 1. And, in case of the PWM module is used (PWM_en bit is set to logic [1]) with an external reference clock: • apply the PWM clock on the IN0 input pin after a maximum of 200 s (min. 50 s). If the correct start-up sequence is not provided, the PWM function is not guaranteed. 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 35 6.3 Protection and Diagnostic Features 6.3.1 Protections 6.3.1.1 Overtemperature Fault The 10XSC425 incorporates overtemperature detection and shutdown circuitry for each output structure. Two cases need to be considered when the output temperature is higher than TSD: • If the output command is ON: the corresponding output is latched OFF. FSB will be also latched to logic [0]. To delatch the fault and be able to turn the outputs ON again, the failure condition must disappear and the autoretry circuitry must be active, or the corresponding output must be commanded OFF and then ON (toggling fault_control signal of corresponding output), or VSUPPLY(POR) condition, if VDD = 0. • If the output command is OFF: FSB will go to logic [0] till the corresponding output temperature will be below TSD. For both cases, the fault register OT[0:3] bit into the status register will be set to [1]. The fault bits will be cleared in the status register after a SPI read command. 6.3.1.2 Overcurrent Fault The 10XSC425 incorporates output shutdown, to protect each output structure against a resistive short-circuit condition. This protection is composed by eight predefined current levels (time dependent) to fit Xenon-HID manners by default or, 55 W or 28 W bulb profiles, selectable separately by Xenon bit and 28 W bits (as illustrated Figure 14). At the first turn-on, the lamp filament is cold and the current will be huge. The fault_control signal transition from logic [0] to [1], or an autoretry define this event. In this case, the overcurrent protection will be fitted to inrush current, as shown in Figure 5. This overcurrent protection is programmable: OC[1:0] bits select the overcurrent slope speed and the OCHI1 current step can be removed in case the OCHI bit is set to [1]. Over-current thresholds fault_control hson signal hson PWM In steady state, the wire harness will be protected by a OCLO2 current level by default. Three other DC overcurrent levels are available: OCLO1, or OCLO3, or OCLO4, based on the state of the OCLO[1,0] bits. If the load current level ever reaches the overcurrent detection level, the corresponding output will latch the output OFF and FSB will be also latched to logic [0]. To delatch the fault and be able to turn the corresponding output ON again, the failure condition must disappear and the autoretry circuitry must be active, or the corresponding output must be commanded OFF and then ON (toggling fault_control signal of corresponding output), or VSUPPLY(POR) condition, if VDD = 0. The SPI fault report (OC[0:3] bits) is removed after a read operation. In Normal mode using the internal PWM module, the 10XSC425 also incorporates a cooling bulb filament management, if OC_mode and Xenon are set to logic [1]. In this case, the first step of multi-step overcurrent protection will depend on the previous OFF duration, as illustrated in Figure 6. The following figure illustrates the current level that will be used in the function to the duration of the previous OFF state (tOFF). The slope of the cooling bulb emulator is configurable with OCOFFCB[1:0] bits. 10XSC425 36 Analog Integrated Circuit Device Data Freescale Semiconductor Depending dependingon to toff toff Over-current thresholds Cooling toff hson signal fault_control PWM hson 6.3.1.3 Severe Short-circuit Fault The 10XSC425 provides output shutdown to protect each output, in case of a severe short-circuit during the output switching. If the short-circuit impedance is below RSHORT, the device will latch the output OFF, FSB will go to a logic [0] and the fault register SC[0:3] bit will be set to [1]. To delatch the fault and be able to turn the outputs ON again, the failure condition must disappear, and the corresponding output must be commanded OFF and then ON (toggling fault_control signal of corresponding output), or VSUPPLY(POR) condition if VDD = 0. The SPI fault report (SC[0:3] bits) is removed after a read operation. 6.3.1.4 Overvoltage Fault (Enabled by default) By default, the overvoltage protection is enabled. The 10XSC425 shuts down all outputs and FSB will go to a logic [0] during an overvoltage fault condition on the VPWR pin (VPWR > VPWR(OV)). The outputs remain in the OFF state until the overvoltage condition is removed (VPWR < VPWR(OV) - VPWR(OVHYS)). When experiencing this fault, the OVF fault bit is set to logic [1] and cleared after either a valid SPI read. The overvoltage protection can be disabled through the SPI (OV_dis bit is disabled set to logic [1]). The fault register reflects any overvoltage condition (VPWR > VPWR(OV)). This overvoltage diagnosis, as a warning, is removed after a read operation, if the fault condition disappears. The HS[0:3] outputs are not commanded in RDS(ON) above the OV threshold. 6.3.1.5 Undervoltage Fault The output(s) will latch off at some battery voltage below VPWR(UV). As long as the VDD level stays within the normal specified range, the internal logic states within the device will remain (configuration and reporting). In the case where battery voltage drops below the undervoltage threshold (VPWR < VPWR(UV)), the outputs will turn off, FSB will go to logic [0], and the fault register UV bit will be set to [1]. Two cases need to be considered when the battery level recovers (VPWR > VPWR(UV)_UP): • If the output command is low, FSB will go to a logic [1], but the UV bit will remain set to 1 until the next read operation (warning report). • If the output command is ON, FSB will remain at logic [0]. To delatch the fault and be able to turn the outputs ON again, the failure condition must disappear and the autoretry circuitry must be active, or the corresponding output must be commanded OFF and then ON (toggling fault_control signal of corresponding output), or a VSUPPLY(POR) condition, if VDD = 0. In extended mode, the output is protected by overtemperature shutdown circuitry. All previous latched faults, occurred when VPWR is within the normal voltage range, are guaranteed if VDD is within the operational voltage range, or until VSUPPLY(POR), if VDD = 0. Any new OT fault is detected (VDD failure included) and reported through SPI above VPWR(UV). The output state is not changed, as long as the VPWR voltage does not drop any lower than 3.5 V (typical). All latched faults (overtemperature, overcurrent, severe short-circuit, over and undervoltage) are reset if: • VDD < VDD(FAIL) with VPWR in nominal voltage range, • VDD and VPWR supplies is below the VSUPPLY(POR) voltage value. 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 37 (fault_control=0) (OpenLoadOFF = 1 or ShortVpwr = 1 or OV = 1) (fault_control = 1 and OV = 0) OFF if hson = 0 (fault_control = 0 or OV = 1) (OpenLoadOFF = 1 or ShortVpwr = 1 or OV = 1) (OpenLoadON = 1) ON (SC = 1) if hson=1 (Retry = 1) (fault_control = 0) Latched OFF (count = 16) (SC = 1) (OpenloadON = 1) (after Retry Period and OV = 0) Autoretry (OV = 1) OFF Autoretry ON if hson=1 (OpenLoadOFF = 1 or ShortVpwr = 1 or OV = 1) (Retry = 1) => count = count+1 (fault_control=0) Figure 13. Auto-retry State Machine 6.3.2 Auto-retry The auto-retry circuitry is used to reactivate the output(s) automatically, in case of an overcurrent, overtemperature, or undervoltage failure conditions to provide a high availability of the load. Auto-retry feature is available in Fault mode. It is activated in case of an internal retry signal is set to a logic [1]: retry[x] = OC[x] or OT[x] or UV. The feature retries to switch-on the output(s) after one auto-retry period (tAUTO) with a limitation in term of the number of occurrences (16 for each output). The counter of retry occurrences is reset in case of Fail-safe to Normal or Normal to Fail-safe mode transitions. At each auto-retry, the overcurrent detection will be set to default values in order to sustain the inrush current. Figure 13 describes the auto-retry state machine. 6.3.3 6.3.3.1 Diagnostic Output Shorted to VPWR Fault The 10XSC425 incorporates output shorted to VPWR detection circuitry in the OFF state. An output shorted to VPWR fault is detected if the output voltage is higher than VOSD(THRES) and reported as a fault condition when the output is disabled (OFF). The output shorted to VPWR fault is latched into the status register after the internal gate voltage is pulled low enough to turn OFF the output. The OS[0:3] and OL_OFF[0:3] fault bits are set in the status register and the FSB pin reports the fault in real time. If the output shorted to VPWR fault is removed, the status register will be cleared after reading the register. The open output shorted to VPWR protection can be disabled through the SPI (OS_DIS[0:3] bit). 6.3.3.2 OpenLoad Faults The 10XSC425 incorporates three dedicated OpenLoad detection circuitries on the output to detect in OFF and in ON states. 10XSC425 38 Analog Integrated Circuit Device Data Freescale Semiconductor 6.3.3.3 OpenLoad Detection In Off State The OFF output OpenLoad fault is detected when the output voltage is higher than VOLD(THRES) pulled up with internal current source (IOLD(OFF)), and reported as a fault condition when the output is disabled (OFF). The OFF Output OpenLoad fault is latched into the status register, or when the internal gate voltage is pulled low enough to turn the output OFF. The OL_OFF[0:3] fault bit is set in the status register. If the OpenLoad fault is removed (FSB output pin goes to high), the status register will be cleared after reading the register. The OFF output OpenLoad protection can be disabled through the SPI (OLOFF_DIS[0:3] bit). 6.3.3.4 OpenLoad Detection In On State The ON output OpenLoad current thresholds can be chosen by the SPI to detect a standard bulb or LED (OLLED[0:3] bit set to logic [1]). In the case where the load current drops below the defined current threshold, the OLON bit is set to logic [1], the output stays ON, and FSB is not disturbed. 6.3.3.5 OpenLoad Detection In On State For Led OpenLoad for LEDs only (OLLED[0:3] set to logic [1]) is detected periodically at each t OLLED (fully-on, D[6:0]=7F). To detect OLLED in a fully on state, the output must be ON at least t OLLED. To delatch the diagnosis, the condition should be removed and a SPI read operation is needed (OL_ON[0:3] bit). The ON output OpenLoad protection can be disabled through the SPI (OLON_DIS[0:3] bit). 6.3.4 Analog Current Recopy and Temperature Feedbacks The CSNS pin is an analog output reporting a current proportional to the designed output current, or a voltage proportional to the temperature of the GND flag (pin #14). The routing is SPI programmable (TEMP_en, CSNS_en, CSNS_s[1,0] and CSNS_ratio_s bits). In case the current recopy is active, the CSNS output delivers current only during the ON time of the output switch without overshoot. The maximum current is 2.0 mA (typical). The typical value of the external CSNS resistor connected to ground is 2.5 k. The current recopy is not active in Fail-safe mode. 6.3.4.1 Temperature Prewarning Detection In Normal mode, the 10XSC425 provides a temperature prewarning reported via the SPI, in case the temperature of the GND flag is higher than TOTWAR. This diagnosis (OTW bit set to [1]) is latched in the SPI DIAGR0 register. To delatch, a SPI read command is needed. 6.3.5 Active Clamp ON VPWR The device provides an active gate clamp circuit, to limit the maximum transient VPWR voltage at VPWR(CLAMP). In case of an overload on an output the corresponding output is turned off, which leads to high voltage at VPWR with an inductive VPWR line. When VPWR voltage exceeds the VPWR(CLAMP) threshold, the turn-off on the corresponding output is deactivated and all HS[0:3] outputs are switched ON automatically, to demagnetize the inductive Battery line. For long battery line (> 10 meters, corresponding to 10 µH of parasitic inductance) between the battery and the device, the smart high side switch output may be damaged, in cases of short-circuit due to unexpected behavior of internal active gate clamp circuitry. It is essential not to exceed the maximum rating on the VPWR pin (41 V). 6.3.6 Reverse Battery ON VPWR The output survives the application of reverse voltage as low as -18 V. Under these conditions, the ON resistance of the output is two times higher than the typical ohmic value in forward mode. No additional passive components are required except on the VDD current path. 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 39 6.3.7 Ground Disconnect Protection In the event the 10XSC425 ground is disconnected from load ground, the device protects itself and safely turns OFF the output, regardless of the state of the output at the time of disconnection (maximum VPWR = 16 V). A 10 k resistor needs to be added between the MCU and each digital input pin, to ensure that the device turns off during ground disconnects and to prevent this pin from exceeding maximum ratings. 6.3.8 6.3.8.1 Loss of Supply Lines Loss of VDD If the external VDD supply is disconnected (or not within specification: VDD < VDD(FAIL) with the VDD_FAIL_en bit set to a logic [1]), all SPI register content is reset. The outputs can still be driven by the direct inputs IN[0 : 3] if VPWR is within specified voltage range. The 10XSC425 uses the battery input to power the output MOSFET-related current sense circuitry, and any other internal logic providing Fail-safe device operation with no VDD supplied. In this state, the overtemperature, overcurrent, severe short-circuit, short to VPWR and OFF OpenLoad circuitry, are fully operational with default values corresponding to all SPI bits. These are set to logic [0]. An unexpected Power-On Reset (VSUPPLY(POR)) may occur at 4.8 V of VPWR. The extended battery voltage range specified from 4.0 to 28 V is reduced from 5.0 to 28 V. If the battery voltage drops below 5.0 V, the outputs will be turned off by the POR instead of undervoltage (UV). In this case, the outputs will turn on again once the battery voltage recovers to a nominal voltage. The counter of auto-retry will be also reset. So, it is recommended to command “off” the outputs when the battery voltage is below 5.0 V. No current is conducted from VPWR to VDD. 6.3.8.2 Loss of VPWR If the external VPWR supply is disconnected (or not within specification), the SPI configuration, reporting, and daisy chain features are provided for RSTB to set to a logic [1] under VDD in nominal conditions. This fault condition can be diagnosed with a UV fault in SPI STATR_s registers. The SPI pull-up and pull-down current sources are not operational. The previous device configuration is maintained. No current is conducted from VDD to VPWR. 6.3.8.3 Loss of VPWR and VDD If the external VPWR and VDD supplies are disconnected (or not within specification: (VDD and VPWR) < VSUPPLY(POR)), all SPI register contents are reset with default values corresponding to all SPI bits set to logic [0] and all latched faults are reset. 6.3.9 EMC PERFORMANCES All following tests are performed on a Freescale evaluation board, in accordance with the typical application schematic. The device is protected, in case of positive and negative transients on the VPWR line (per ISO 7637-2). The 10XSC425 successfully meets the Class 5 of the CISPR25 emission standard and 200 V/m or BCI 200 mA injection level for immunity tests. 6.4 LOGIC COMMANDS AND REGISTERS 6.4.1 Serial Input Communication SPI communication is accomplished using 16-bit messages. A message is transmitted by the MCU starting with the MSB D15 and ending with the LSB, D0 (Table 10). Each incoming command message on the SI pin can be interpreted using the following bit assignments: the MSB, D15, is the watchdog bit (WDIN). In some cases, output selection is done with bits D14 : D13. The next three bits, D12: D10, are used to select the command register. The remaining nine bits, D8 : D0, are used to configure and control the outputs and their protection features. 10XSC425 40 Analog Integrated Circuit Device Data Freescale Semiconductor Multiple messages can be transmitted in succession to accommodate those applications where daisy chaining is desirable, or to confirm transmitted data, as long as the messages are all multiples of 16 bits. Any attempt made to latch in a message that is not 16 bits will be ignored. The 10XSC425 has defined registers, which are used to configure the device and to control the state of the outputs. Table 11 summarizes the SI registers. Table 10. SI Message Bit Assignment Bit Sig SI Msg Bit MSB D15 Message Bit Description Watchdog in: toggled to satisfy watchdog requirements. D14 : D13 Register address bits used in some cases for output selection (Table 11). D12 : D10 Register address bits. Not used (set to logic [0]). D9 LSB Used to configure the inputs, outputs, and the device protection features and SO status content. D8:D0 Table 11. Serial Input Address and Configuration Bit Map SI Data SI Register D15 D1 D1 D1 D1 D1 D9 4 3 2 1 0 STATR_s WDI X N D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 SOA4 SOA3 SOA2 SOA1 SOA0 ON_s PWM6_s PWM3_s PWM2_s PWM1_s PWM0_s 0 X 0 0 0 0 PWMR_s WDI A1 A0 N 0 0 1 0 28W_s CONFR0 WDI A1 A0 _s N 0 1 0 0 0 0 CONFR1 WDI A1 A0 _s N 0 1 1 0 0 0 WDI A1 A0 N 1 0 0 0 Xenon BC1_s _s GCR WDI 0 N 0 1 0 1 0 VDD_ PWM_e CLOCK_s TEMP_en CSNS_e FAIL_ n el n en CALR WDI 0 N 0 1 1 1 0 1 0 1 0 0 X X X 0 0 0 0 0 OCR_s Register state after RSTB = 0 or VDD(FAIL) or VSUPPLY( 0 0 PWM5_s PWM4_s DIR_dis_ s SR1_s SR0_s DELAY2_s DELAY1_ DELAY0_ s s Retry_dis OS_dis_s OLON_dis OLOFF_di OLLED_e CSNS_rati Retry_ _s _s s_s n_s o_s unlimited_ s BC0_s OC1_s OC0_s OCHI_s OLCO1_s OLCO0_ OC_mode s _s CSNS1 CSNS0 X OV_dis 1 1 0 1 1 0 0 0 0 0 POR) condition x = Don’t care. s = Output selection with the bits A1A0 as defined in Table 12. 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 41 6.4.2 Device Register Addressing The following section describes the possible register addresses (D[14:10]) and their impact on device operation. 6.4.2.1 Address XX000 — Status Register (STATR_s) The STATR register is used to read the device status and the various configuration register contents without disrupting the device operation or the register contents. The register bits D[4:0] determine the content of the first sixteen bits of SO data. In addition to the device status, this feature provides the ability to read the content of the PWMR_s, CONFR0_s, CONFR1_s, OCR_s, GCR and CALR registers (Refer to the section entitled Serial Output Communication (Device Status Return Data). 6.4.2.2 Address A1A0001— Output PWM Control Register (PWMR_s) The PWMR_s register allows the MCU to control the state of corresponding output through the SPI. Each output “s” is independently selected for configuration, based on the state of the D14 : D13 bits (Table 12). Table 12. Output Selection A1 (D14) A0 (D13) HS Selection 0 0 HS0 (default) 0 1 HS1 1 0 HS2 1 1 HS3 A logic [1] on bit D8 (28W_s) selects the 28 W overcurrent protection profile: the overcurrent thresholds are divided by 2 and, the inrush and cooling responses are dedicated to 28 W lamps for HS[0,1] outputs. This bit it not taken into account for HS[2,3] outputs. Bit D7 sets the output state. A logic [1] enables the corresponding output switch and a logic [0] turns it OFF (if IN input is also pulled down). Bits D6:D0 set the output PWM duty-cycle to one of 128 levels for PWM_en is set to logic [1], as shown Table 7. 6.4.2.3 Address A1A0010— Output Configuration Register (CONFR0_S) The CONFR0_s register allows the MCU to configure corresponding output switching through the SPI. Each output “s” is independently selected for configuration based on the state of the D14 : D13 bits (Table 12). For the selected output, a logic [0] on bit D5 (DIR_DIS_s) will enable the output for direct control. A logic [1] on bit D5 will disable the output from direct control (in this case, the output is only controlled by the On bit). D4:D3 bits (SR1_s and SR0_s) are used to select the high, medium, or low speed slew rate for the selected output, the default value [00] corresponds to the medium speed slew rate (Table 13). Table 13. Slew Rate Speed Selection SR1_s (D4) SR0_s (D3) Slew Rate Speed 0 0 medium (default) 0 1 low 1 0 high 1 1 Not used Incoming message bits D2 : D0 reflect the desired output that will be delayed of predefined PWM clock rising edges number, as shown Table 8 (only available for PWM_en bit is set to logic [1]). 10XSC425 42 Analog Integrated Circuit Device Data Freescale Semiconductor 6.4.2.4 Address A1A0011 — Output Configuration Register (CONFR1_s) The CONFR1_s register allows the MCU to configure corresponding output fault management through the SPI. Each output “s” is independently selected for configuration, based on the state of the D14 : D13 bits (Table 12). A logic [1] on bit D6 (RETRY_unlimited_s) disables the autoretry counter for the selected output, the default value [1] corresponds to enable auto-retry feature without time limitation. A logic [1] on bit D5 (RETRY_dis_s) disables the auto-retry for the selected output, the default value [0] corresponds to enable this feature. A logic [1] on bit D4 (OS_dis_s) disables the output hard shorted to VPWR protection for the selected output, the default value [0] corresponds to enable this feature. A logic [1] on bit D3 (OLON_dis_s) disables the ON output OpenLoad detection for the selected output, the default value [0] corresponds to enable this feature (Table 14). A logic [1] on bit D2 (OLOFF_dis_s) disables the OFF output OpenLoad detection for the selected output, the default value [0] corresponds to enable this feature. A logic [1] on bit D1 (OLLED_en_s) enables the ON output OpenLoad detection for LEDs for the selected output, the default value [0] corresponds to ON output OpenLoad detection is set for bulbs (Table 14). Table 14. ON OpenLoad Selection OLON_dis_s (D3) OLLED_en_s (D1) 0 0 enable with bulb threshold (default) 0 1 enable with LED threshold 1 X disable ON OpenLoad detection A logic [1] on bit D0 (CSNS_ratio_s) selects the high ratio on the CSNS pin for the corresponding output. The default value [0] is the low ratio (Table 15). Table 15. Current Sense Ratio Selection 6.4.2.4.1 CSNS_high_s (D0) Current Sense Ratio 0 CRS0 (default) 1 CRS1 Address A1A0100 — Output Overcurrent Register (OCR) The OCR_s register allows the MCU to configure corresponding output overcurrent protection through the SPI. Each output “s” is independently selected for configuration based on the state of the D14 : D13 bits (Table 12). A logic [1] on bit D8 (Xenon_s) disables enables the Xenon 55 W or 28 W bulb overcurrent profile, as described Figure 14. 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 43 Xenon bit set to logic [0]: IOCH1 IOCH2 IOC1 IOC2 IOCLO4 IOCLO3 IOCLO2 IOCLO1 t OC1 t OC3 t OC4 t OC5 t OC2 t OC6 Time t OC7 Xenon bit set to logic [1]: IOCH1 IOCH2 IOC1 IOC2 IOC3 IOC4 IOCL4 IOCL3 IOCL2 IOCL1 t OC1 t OC3 t OC4 t OC5 t OC2 t OC6 Time t OC7 Figure 14. Overcurrent Profile Depending on Xenon Bit D[7:6] bits allow to MCU to programmable the bulb cooling curve and D[5:4] bits inrush curve for the selected output, as shown Table 16 and Table 17. Table 16. Cooling Curve Selection BC1_s (D7) BC0_s (D6) Profile Curves Speed 0 0 medium (default) 0 1 slow 1 0 fast 1 1 medium Table 17. Inrush Curve Selection OC1_s (D5) OC0_s (D4) Profile Curves Speed 0 0 slow (default) 0 1 fast 1 0 medium 1 1 very slow A logic [1] on bit D3 (OCHI_s bit) the OCHI1 level is replaced by OCHI2 during tOC1, as shown Figure 15. 10XSC425 44 Analog Integrated Circuit Device Data Freescale Semiconductor IOCH1 IOCH2 IOC1 IOC2 IOC3 IOC4 IOCL4 IOCL3 IOCL2 IOCL1 t OC1 t OC3 t OC4 t OC5 t OC2 t OC6 t OC7 Time Figure 15. Overcurrent Profile with OCHI Bit Set to ‘1’ The wire harness is protected by one of four possible current levels in steady state, as defined in Table 18. Table 18. Output Steady State Selection OCLO1 (D2) OCLO0 (D1) Steady State Current 0 0 OCLO2 (default) 0 1 OCLO3 1 0 OCLO4 1 1 OCLO1 Bit D0 (OC_mode_sel) allows to select the overcurrent mode, as described Table 19. Table 19. Overcurrent Mode Selection OC_mode_s (D0) Overcurrent Mode 0 only inrush current management (default) 1 inrush current and bulb cooling management Address 00101 — GLObal configuration regIster (GCR) The GCR register allows the MCU to configure the device through the SPI. Bit D8 allows the MCU to enable or disable the VDD failure detector. A logic [1] on VDD_FAIL_en bit allows switch of the outputs HS[0:3] with PWMR register device in Fail-safe mode in case of VDD < VDD(FAIL). Bit D7 allows the MCU to enable or disable the PWM module. A logic [1] on PWM_en bit allows control of the outputs HS[0:3] with PWMR register (the direct input states are ignored). Bit D6 (CLOCK_sel) allows to select the clock used as reference by PWM module, as described in the following Table 20. Table 20. PWM Module Selection PWM_en (D7) CLOCK_sel (D6) PWM module 0 X PWM module disabled (default) 1 0 PWM module enabled with external clock from IN0 1 1 PWM module enabled with internal calibrated clock Bits D5:D4 allow the MCU to select one of two analog feedbacks on CSNS output pin, as shown in Table 21. 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 45 Table 21. CSNS Reporting Selection TEMP_en (D5) CSNS_en (D4) CSNS reporting 0 0 CSNS tri-stated (default) X 1 current recopy of selected output (D3:2] bits) 1 0 temperature on GND flag Table 22. Output Current Recopy Selection CSNS1 (D3) CSNS0 (D2) CSNS reporting 0 0 HS0 (default) 0 1 HS1 1 0 HS2 1 1 HS3 The GCR register disables the overvoltage protection (D0). When this bits is [0], the overvoltage is enabled (default value). 6.4.2.5 Address 00111 — Calibration Register (CALR) The CALR register allows the MCU to calibrate internal clock, as explained in Figure 13. 6.4.3 Serial Output Communication (Device Status Return Data) When the CSB pin is pulled low, the output register is loaded. Meanwhile, the data is clocked out MSB- (OD15-) first, as the new message data is clocked into the SI pin. The first sixteen bits of data clocking out of the SO, and following a CSB transition, is dependent upon the previously written SPI word. Any bits clocked out of the Serial Output (SO) pin after the first 16 bits will be representative of the initial message bits clocked into the SI pin since the CSB pin first transitioned to a logic [0]. This feature is useful for daisy chaining devices as well as message verification. A valid message length is determined following a CSB transition of [0] to [1]. If there is a valid message length, the data is latched into the appropriate registers. A valid message length is a multiple of 16 bits. At this time, the SO pin is tri-stated and the fault status register is now able to accept new fault status information. SO data will represent information ranging from fault status to register contents, user selected by writing to the STATR bits OD4, OD3, OD2, OD1, and OD0. The value of the previous bits SOA4 and SOA3 will determine which output the SO information applies to for the registers, which are output specific; viz., Fault, PWMR, CONFR0, CONFR1, and OCR registers. Note that the SO data will continue to reflect the information for each output (depending on the previous SOA4, SOA3 state) that was selected during the most recent STATR write until changed with an updated STATR write. The output status register correctly reflects the status of the STATR-selected register data at the time that the CSB is pulled to a logic [0] during SPI communication, and/or for the period of time since the last valid SPI communication, with the following exception: • The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid SPI communication never occurred. • The VPWR voltage is below 4.0 V, the status must be ignored by the MCU. 10XSC425 46 Analog Integrated Circuit Device Data Freescale Semiconductor 6.4.4 Serial Output Bit Assignment The 16 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 23, summarizes SO returned data for bits OD15 : OD0. • Bit OD15 is the MSB; it reflects the state of the Watchdog bit from the previously clocked-in message. • Bits OD14:OD10 reflect the state of the bits SOA4 : SOA0 from the previously clocked-in message. • Bit OD9 is set to logic [1] in Normal mode (NM). • The contents of bits OD8 : OD0 depend on bits D4 : D0 from the most recent STATR command SOA4 : SOA0 as explained in the paragraphs following Table 23. Table 23. Serial Output Bit Map Description Previous STATR S O A 4 S O A 2 S O A 1 S O OD OD OD OD OD OD O OD8 OD7 A 15 14 13 12 11 10 D9 0 STATR A1 A0 0 _s 0 0 WDI SO SOA SOA SO N A4 3 2 A1 SO A0 N M POR PWMR A1 A0 0 _s 0 1 WDI SO SOA SOA SO N A4 3 2 A1 SO A0 N M 28W ON_ PWM _s s 6_s CONF A1 A0 0 R0_s 1 0 WDI SO SOA SOA SO N A4 3 2 A1 SO A0 N M X X CONF A1 A0 0 R1_s 1 1 WDI SO SOA SOA SO N A4 3 2 A1 SO A0 N M X X OCR_s A1 A0 1 0 0 WDI SO SOA SOA SO N A4 3 2 A1 SO A0 N Xeno BC1 M n_s _s 0 1 WDI SO SOA SOA SO N A4 3 2 A1 SO A0 N _FAI M_e K_sel M L_e n GCR 0 S O A 3 SO Returned Data 0 1 UV OD6 OD5 OD4 OD3 OD2 OD1 OD0 OV OLON _s OLOF F_s OS_s OT_s SC_s OC_s PWM PWM 5_s 4_s PWM3_s PWM2_s DIR_d SR1_ is_s s SR0_s X PWM1_s PWM0_s DELAY2_s DELAY1 DELAY0 _s _s Retry_ Retry_ OS_di OLON_dis OLOFF_dis OLLED_ CSNS_r _s _s en_s atio_s unlimit dis_s s_s ed_s BC0_ OC1_ OC0_ s s s OCHI_s OCLO1_s OCLO0_ OC_mod s e_s VDD PW CLOC TEMP CSNS _en _en CSNS1 CSNS0 X OV_dis n DIAGR 0 0 0 1 1 1 WDI SO SOA SOA SO N A4 3 2 A1 SO A0 N M X X X X X X CLOCK_fail CAL_fail OTW DIAGR 1 0 1 1 1 1 WDI SO SOA SOA SO N A4 3 2 A1 SO A0 N M X X X X IN3 IN2 IN1 IN0 WD_en DIAGR 2 1 0 1 1 1 WDI SO SOA SOA SO N A4 3 2 A1 SO A0 N M X X X X X X 0 1 1 0 0 0 0 Regist er state after RST= 0 or N/ N/ N/ N/ N/ VDD(F A A A A A AIL) or VSUPP 0 0 0 0 0 0 0 X 0 0 0 0 LY(POR ) conditi on s = Output selection with the bits A1A0 as defined in Table 12 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 47 6.4.4.1 Previous Address SOA4 : SOA0 = A1A0000 (STATR_s) The returned data OD8 reports logic [1] in case of previous Power ON Reset condition (VSUPPLY(POR)). This bit is only reset by a read operation. Bits OD7: OD0 reflect the current state of the Fault register (FLTR) corresponding to the output previously selected with the bits SOA4:SOA3 = A1A0 (Table 23). • OC_s: overcurrent fault detection for a selected output, • SC_s: severe short-circuit fault detection for a selected output, • OS_s: output shorted to VPWR fault detection for a selected output, • OLOFF_s: OpenLoad in OFF state fault detection for a selected output, • OLON_s: OpenLoad in ON state fault detection (depending on current level threshold: bulb or LED) for a selected output, • OV: overvoltage fault detection, • UV: undervoltage fault detection • POR: power on reset detection. The FSB pin reports all faults. For latched faults, this pin is reset by a new Switch OFF command (toggling fault_control signal). 6.4.4.2 Previous Address SOA4 : SOA0 = A1A0001 (Pwmr_s) The returned data contains the programmed values in the PWMR register for the output selected with A1A0. 6.4.4.3 Previous Address SOA4 : SOA0 = A1A0010 (confr0_s) The returned data contains the programmed values in the CONFR0 register for the output selected with A1A0. 6.4.4.4 Previous Address SOA4 : SOA0 = A1A0011 (confr1_s) The returned data contains the programmed values in the CONFR1 register for the output selected with A1A0. 6.4.4.5 Previous Address SOA4 : SOA0 = A1A0100 (ocr_s) The returned data contains the programmed values in the OCR register for the output selected with A1A0. 6.4.4.6 Previous Address SOA4 : SOA0 = 00101 (gcr) The returned data contains the programmed values in the GCR register. 6.4.4.7 Previous Address SOA4 : SOA0 = 00111 (diagr0) The returned data OD2 reports logic [1] in case of PWM clock on IN0 pin is out of specified frequency range. The returned data OD1 reports logic [1] in case of calibration failure. The returned data OD0 reports logic [1] in case of overtemperature prewarning (temperature of GND flag is above TOTWAR). 6.4.4.8 Previous Address SOA4 : SOA0 = 01111 (diagr1) The returned data OD4: OD1 report in real time the state of the direct input IN[3:0]. The OD0 indicates if the watchdog is enabled (set to logic [1]) or not (set to logic [0]). OD4:OD1 report the output state in case of Fail-safe state due to watchdog time-out as explained in the following Table 24. Table 24. Watchdog Activation Report WD_en (OD0) SPI Watchdog 0 disabled 1 enabled 10XSC425 48 Analog Integrated Circuit Device Data Freescale Semiconductor 6.4.4.9 Previous Address SOA4 : SOA0 = 10111 (diagr2) The returned data is the product ID. Bits OD2:OD0 are set to 011 for Protected Dual 10 m and 25 m high side Switches. Default Device configuration The default device configuration is explained by the following: • HS output is commanded by corresponding IN input or On bit through the SPI. The medium slew rate is used, • HS output is fully protected by the Xenon overcurrent profile by default, the severe short-circuit protection, the undervoltage, and the overtemperature protection. The auto-retry feature is enabled, • OpenLoad in ON and OFF state and HS shorted to VPWR detections are available, • No current recopy and no analog temperature feedback active, • Overvoltage protection is enabled, • SO reporting fault status from HS0, • VDD failure detection is disabled. 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 49 7 Typical Applications 7.1 Introduction The following figure shows a typical lighting application (only one vehicle corner) using an external PWM clock from the main MCU. A redundancy circuitry has been implemented to substitute light control (from MCU to watchdog) in case of a Fail-safe condition. It is recommended to locate a 22 nF decoupling capacitor to the module connector. VPWR VDD Voltage regulator 100nF 10µF 100nF VDD 10µF VPWR ignition switch VDD 10k VPWR VDD VPWR VDD 10k 100nF 100nF 100nF VDD WAKE I/O FS IN0 IN1 IN2 IN3 10k I/O MCU SCLK CS I/O SO SI 10k 10k 10k 10k A/D HS0 10XSC425 SCLK CS RST SI SO CSNS FSI 10k 22nF 22nF LOAD 0 HS1 22nF LOAD 1 HS2 22nF LOAD 2 HS3 GND 22nF LOAD 3 3.3k VPWR Watchdog direct light commands (pedal, comodo,...) Figure 16. Typical Lighting (One Corner) 10XSC425 50 Analog Integrated Circuit Device Data Freescale Semiconductor 8 Packaging 8.1 Soldering Information The 10XSC425 was qualified in accordance with JEDEC standards J-STD-020C Pb-free reflow profile. The maximum peak temperature during the soldering process should not exceed 260 °C for 40 seconds maximum duration. 8.2 Marking Information The device is identified by the part number: 10XSC425. Device markings indicate build information containing the week and year of manufacture. The date is coded with the last four characters of the nine character build information code (e.g. “CTKAH0929”). The date is coded as four numerical digits where the first two digits indicate the year and the last two digits indicate the week. For instance, the date code “1329” indicates the 29th week of the year 2013. 8.3 Package Mechanical Dimensions Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.freescale.com and perform a keyword search for the drawing’s document number. Table 25. Package Outline Package Suffix 32-Pin SOIC-EP EK Package Outline Drawing Number 98ASA00368D 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 51 EK SUFFIX 32-PIN SOIC-EP 98ASA00368D ISSUE 0 10XSC425 52 Analog Integrated Circuit Device Data Freescale Semiconductor EK SUFFIX 32-PIN SOIC-EP 98ASA00368D ISSUE 0 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 53 EK SUFFIX 32-PIN SOIC-EP 98ASA00368D ISSUE 0 10XSC425 54 Analog Integrated Circuit Device Data Freescale Semiconductor 9 Revision History REVISION 1.0 2.0 DATE 8/2013 9/2013 DESCRIPTION OF CHANGES • Initial release based on the MC10XS3425 data sheet • Added the note “To achieve high reliability over 10 years of continuous operation, the device's continuous operating junction temperature should not exceed 125C.” to Operating Temperature 10XSC425 Analog Integrated Circuit Device Data Freescale Semiconductor 55 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. Home Page: freescale.com There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits on Web Support: freescale.com/support Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no the information in this document. warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net/v2/webservices/Freescale/Docs/TermsandConditions.htm Freescale and the Freescale logo, are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. Document Number: MC10XSC425 Rev. 2.0 9/2013