Freescale Semiconductor
Advance Information
Document Number: MC35XS3400
Rev. 10.0, 8/2013
Quad High Side Switch
(Quad 35 mOhm)
35XS3400
The 35XS3400 is one in a family of devices designed for low-voltage
automotive lighting applications. Its four low RDS(ON) MOSFETs (quad
35 mOhm) can control four separate 28 W bulbs, and/or LEDs.
HIGH SIDE SWITCH
Programming, control and diagnostics are accomplished using a
16-bit SPI interface. Its output with selectable slew rate improves
electromagnetic compatibility (EMC) behavior. Additionally, each
output has its own parallel input or SPI control for pulse-width
modulation (PWM) control. The 35XS3400 allows the user to program
via the SPI the fault current trip levels and duration of acceptable lamp
inrush. The device has Fail-safe mode to provide functionality of the
outputs in case of MCU damage. This device is powered by
SMARTMOS technology.
Features
• Four protected 35 m high side switches (at 25 °C)
• Operating voltage range of 6.0 V to 20 V with standby current <
5.0 A, extended mode from 4.0 V to 28 V
• 8.0 MHz 16-bit 3.3 V and 5.0 V SPI control and status reporting
with daisy chain capability
• PWM module using external clock or calibratable internal
oscillator with programmable outputs delay management
• Smart over-current shutdown, severe short-circuit, overtemperature protection with time limited autoretry, and Fail-safe
mode in case of MCU damage
• Output OFF or ON OpenLoad detection compliant to bulbs or
LEDs and short to battery detection
• Analog current feedback with selectable ratio and board
temperature feedback
VDD
VDD
VPWR
FK SUFFIX (PB-FREE)
98ARL10596D
24-PIN PQFN
ORDERING INFORMATION
Device
(for Tape and Reel
orders add an R2
suffix to the part)
Temperature
Range (TA)
Package
- 40 to 125°C
24 PQFN
MC35XS3400CHFK
MC35XS3400DHFK
VDD
VPWR
35XS3400
VDD
I/O
SCLK
CS
SI
I/O
MCU SO
I/O
I/O
I/O
I/O
A/D
VPWR
HS0
WAKE
FS
SCLK
CS
SO
RST
SI
IN0
IN1
IN2
IN3
CSNS
FSI
GND
LOAD
HS1
LOAD
HS2
LOAD
HS3
LOAD
GND
Figure 1. 35XS3400 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2008 - 2013. All rights reserved.
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Variations
Characteristic
Symbol
Min
Typ
Max
35XS3400CHFK
18
25
32
35XS3400DHFK
20
27
35
35XS3400CHFK
-
5.0
20
35XS3400DHFK
-
5.0
10
35XS3400CHFK
-
7.0
30
35XS3400DHFK
-
7.0
20
170
212
270
Wake Input Clamp Voltage, ICL(WAKE) < 2.5 mA
Fault Detection Blanking Time
V
tFAULT
Output Shutdown Delay Time
OpenLoad detection time in OFF state
VCL(WAKE)
s
s
tDETECT
(1)
Peak Package Reflow Temperature During Reflow(2), (3)
s
tOLOFF
35XS3400CHFK and 35XS3400DHFK
TPPRT
Unit
Note 3
°C
Notes
1. Guaranteed by design.
2. Pin soldering temperature limit is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits
may cause malfunction or permanent damage to the device.
3. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics.
35XS3400
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VDD
IUP
VPWR
VDD Failure
Detection
Internal
Regulator
POR
Over/Under-voltage
Protections
VPWR
Voltage Clamp
Charge
Pump
VREG
CS
SCLK
Selectable Slew Rate
Gate Driver
IDWN
Selectable Over-current
Detection
SO
SI
RST
WAKE
FS
IN0
HS0
Severe Short-circuit
Detection
Logic
Short to VPWR
Detection
Over-temperature
Detection
IN1
IN2
OpenLoad
Detections
IN3
HS0
RDWN IDWN
RDWN
HS1
Calibratable
Oscillator
HS1
PWM
Module
HS2
VREG
HS2
HS3
FSI
HS3
Programmable
Watchdog
Selectable Output
Current Recopy
Temperature
Feedback
Over-temperature
Prewarning
Analog MUX
VDD
GND
CSNS
Figure 2. 35XS3400 Simplified Internal Block Diagram
35XS3400
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
PIN CONNECTIONS
RST
WAKE
FS
IN3
IN2
NC
IN1
IN0
CSNS
9
8
7
6
5
4
3
2
1
SI
SO
16
GND
17
HS3
18
SCLK
13 12 11 10
VDD
CS
Transparent Top View of Package
14
GND
24
FSI
23
GND
22
HS2
15
VPWR
19
20
21
HS1
NC
HS0
Figure 3. 35XS3400 Pin Connections
Table 2. 35XS3400 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 19.
Pin
Number
Pin Name
Pin
Function
1
CSNS
2
3
5
6
Formal Name
Definition
Output
Output Current
Monitoring
This pin reports an analog value proportional to the designated HS[0:3] output
current or the temperature of the GND flag (pin 14). It is used externally to
generate a ground-referenced voltage for the microcontroller (MCU). Current
recopy and temperature feedback is SPI programmable.
IN0
IN1
IN2
IN3
Input
Direct Inputs
Each direct input controls the device mode. The IN[0 : 3] high side input pins
are used to directly control HS0 : HS3 high side output pins.
7
FS
Output
Fault Status
(Active Low)
8
WAKE
Input
Wake
This input pin controls the device mode.
9
RST
Input
Reset
This input pin is used to initialize the device configuration and fault registers,
as well as place the device in a low-current Sleep mode.
10
CS
Input
Chip Select
(Active Low)
This input pin is connected to a chip select output of a master microcontroller
(MCU).
11
SCLK
Input
Serial Clock
This input pin is connected to the MCU providing the required bit shift clock for
SPI communication.
12
SI
Input
Serial Input
This pin is a command data input pin connected to the SPI serial data output
of the MCU or to the SO pin of the previous device of a daisy-chain of devices.
The PWM frequency can be generated from IN0 pin to PWM module in case
the external clock is set.
This pin is an open drain configured output requiring an external pull-up
resistor to VDD for fault reporting.
35XS3400
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
Table 2. 35XS3400 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 19.
Pin
Number
Pin Name
Pin
Function
Formal Name
Definition
13
VDD
Power
Digital Drain Voltage
This pin is an external voltage input pin used to supply power interfaces to the
SPI bus.
14, 17, 23
GND
Ground
Ground
These pins, internally shorted, are the ground for the logic and analog circuitry
of the device. These ground pins must be also shorted in the board.
15
VPWR
Power
16
SO
Output
Serial Output
18
19
21
22
HS3
HS1
HS0
HS2
Output
High Side Outputs
4, 20
NC
N/A
No Connect
24
FSI
Input
Fail-safe Input
Positive Power Supply This pin connects to the positive power supply and is the source of operational
power for the device.
This output pin is connected to the SPI serial data input pin of the MCU or to
the SI pin of the next device of a daisy-chain of devices.
Protected 35 m high side power output pins to the load.
These pins may not be connected.
This input enables the watchdog timeout feature.
35XS3400
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
VPWR Supply Voltage Range
VPWR(SS)
Load Dump at 25 °C (400 ms)
Maximum Operating Voltage
Reverse Battery at 25 °C (2.0 min.)
VDD Supply Voltage Range
V
41
28
-18
VDD
-0.3 to 5.5
V
(7)
-0.3 to VDD + 0.3
V
WAKE Input Clamp Current
ICL(WAKE)
2.5
mA
CSNS Input Clamp Current
ICL(CSNS)
2.5
mA
Input / Output Voltage
HS [0:3] Voltage
VHS[0:3]
Positive
Negative
V
41
-16
Output Current(4)
IHS[0:3]
6
A
Output Clamp Energy using single-pulse method(5)
ECL [0:3]
35
mJ
ESD Voltage(6)
Human Body Model (HBM) for HS[0:3], VPWR and GND
Human Body Model (HBM) for other pins
Charge Device Model (CDM)
Corner Pins (1, 13, 19, 21)
All Other Pins (2-12, 14-18, 20, 22-24)
V
VESD1
± 8000
VESD2
± 2000
VESD3
VESD4
± 750
± 500
TA
TJ
- 40 to 125
- 40 to 150
TSTG
- 55 to 150
RJC
RJA
<1.0
30
TPPRT
Note 10
THERMAL RATINGS
C
Operating Temperature
Ambient
Junction
Storage Temperature
C
THERMAL RESISTANCE
Thermal Resistance(8)
Junction to Case
Junction to Ambient
Peak Package Reflow Temperature During Reflow(9), (10)
C/ W
°C
Notes
4. Continuous high side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output
current using package thermal resistance is required.
5. Active clamp energy using single-pulse method (L = 2.0 mH, RL = 0 , VPWR = 14 V, TJ = 150C initial).
6.
ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), the Machine Model (MM)
(CZAP = 200 pF, RZAP = 0 ), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF).
7.
8.
Input / Output pins are: IN[0:3], RST, FSI, CSNS, SI, SCLK, CS, SO, FS
Device mounted on a 2s2p test board per JEDEC JESD51-2. 15 °C/W of RθJA can be reached in a real application case (4 layers board).
9.
Pin soldering temperature limit is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics.
10.
35XS3400
6
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUTS
Battery Supply Voltage Range
VPWR
V
Fully Operational
6.0
–
20
Extended mode(11)
4.0
–
28
41
47
53
–
6.5
20
Battery Clamp Voltage
(12)
VPWR Operating Supply Current
VPWR(CLAMP)
IPWR(ON)
Outputs commanded ON, HS[0 : 3] open, IN[0:3] > VIH
VPWR Supply Current
V
mA
IPWR(SBY)
mA
Outputs commanded OFF, OFF OpenLoad Detection Disabled,
HS[0 : 3] shorted to the ground with VDD= 5.5 V
–
6.0
8.0
WAKE > VIH or RST > VIH and IN[0:3] < VIL
Sleep State Supply Current
A
IPWR(SLEEP)
VPWR = 12 V, RST = WAKE = IN[0:3] < VIL, HS[0 : 3] shorted to the
ground
TA = 25 °C
–
1.0
5.0
TA = 85 °C
–
–
30
3.0
–
5.5
No SPI Communication
–
1.6
2.2
8.0 MHz SPI Communication(13)
–
5.0
–
VDD Supply Voltage
VDD(ON)
VDD Supply Current at VDD = 5.5 V
IDD(ON)
V
mA
VDD Sleep State Current at VDD = 5.5 V
IDD(SLEEP)
–
–
5.0
A
Over-voltage Shutdown Threshold
VPWR(OV)
28
32
36
V
Over-voltage Shutdown Hysteresis
VPWR(OVHYS)
0.2
0.8
1.5
V
VPWR(UV)
3.3
3.9
4.3
V
VSUPPLY(POR)
0.5
–
0.9
VPWR(UV)
VDD(FAIL)
2.2
2.5
2.8
V
VPWR(UV)_UP
3.4
4.1
4.5
V
VPWR = 4.0 V
–
–
100
VPWR = 6.0 V
–
–
55
VPWR = 10 V
–
–
35
VPWR = 13 V
–
–
35
Under-voltage Shutdown Threshold(14)
VPWR and VDD Power on Reset Threshold
VDD Supply Failure Threshold ( for VPWR > VPWR(UV) )
Recovery Under-voltage Threshold
OUTPUTS HS0 TO HS3
Output Drain-to-Source ON Resistance (IHS = 2.0 A, TA = 25 C)
RDS(ON)_25
m
Notes
11. In extended mode, the functionality is guaranteed but not the electrical parameters. From 4.0 to 6.0 V voltage range, the device is only
protected with the thermal shutdown detection.
12. Measured with the outputs open.
13. Typical value guaranteed per design.
14. Output will automatically recover with time limited autoretry to instructed state when VPWR voltage is restored to normal as long as the
VPWR degradation level did not go below the under-voltage power-ON reset threshold. This applies to all internal device logic that is
supplied by VPWR and assumes that the external VDD supply is within specification.
35XS3400
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
VPWR = 4.5 V
–
–
170
VPWR = 6.0 V
–
–
94
VPWR = 10 V
–
–
66
VPWR = 13 V
–
–
66
–
–
52.5
–
–
70
70
160
200
Unit
OUTPUTS HS0 TO HS3 (Continued)
Output Drain-to-Source ON Resistance (IHS = 2.0 A, TA = 150 C)
Output Source-to-Drain ON Resistance (IHS = -2.0 A, VPWR = -18 V)(15)
TA = 25 C
RDS(ON)_150
RSD(ON)
TA = 150 C
Maximum Severe Short-circuit Impedance Detection(16)
m
RSHORT
m
Output Over-current Detection Levels (6.0 V < VHS[0:3] < 20 V)
CSR0 Current Recopy Accuracy with one calibration point (6.0 V <
VHS[0:3] < 20 V)(18)
A
OCHI1_0
39.5
47
54.5
OCHI2_0
25.2
30
34.8
OC1_0
22
26.2
30.4
OC2_0
18.9
22.5
26.1
OC3_0
15.7
18.7
21.7
OC4_0
12.6
15
17.4
OCLO4_0
9.4
11.2
13.0
OCLO3_0
6.3
7.5
8.7
OCLO2_0
5.0
6.0
7.0
OCLO1_0
3.2
4.0
4.8
CSR0_0_ACC(CAL)
Output Current
2.0 A
%
-5.0
–
5.0
Current Sense Ratio (6.0 V < HS[0:3] < 20 V, CSNS < 5.0 V)(17)
–
CSNS_ratio bit = 0
CSR0_0
–
1/4300
–
CSNS_ratio bit = 1
CSR1_0
–
1/25800
–
Current Sense Ratio (CSR0) Accuracy (6.0 V < VHS[0:3] < 20 V)
m
CSR0_0_ACC
%
Output Current
6.75 A
-12
–
12
2.5 A
-13
–
13
1.5 A
-16
–
16
-20
–
20
0.75 A
Notes
15. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR.
16.
17.
Short-circuit impedance calculated from HS[0:3] to GND pins. Value guaranteed per design.
Current sense ratio = ICSNS / IHS[0:3].
18.
Based on statistical analysis, it is not production tested.
35XS3400
8
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
OUTPUTS HS0 TO HS3 (continued)
CSR0 Current Recopy Temperature Drift (6.0 V < VHS[0:3] < 20 V)(19)
(CSR0_0)/(T)
%/C
Output Current
2.0 A
Current Sense Ratio (CSR1) Accuracy (6.0 V < VHS[0:3] < 20 V)
0.04
CSR1_0_ACC
%
Output Current
6.25 A
-17
–
+17
39.5 A
-12
–
+12
VDD+0.25
–
VDD+1.0
IOLD(OFF)
30
–
100
A
OFF OpenLoad Fault Detection Voltage Threshold
VOLD(THRES)
2.0
3.0
4.0
V
ON OpenLoad Fault Detection Current Threshold
IOLD(ON)
100
300
600
mA
2.5
5.0
10
VPWR-1.2
VPWR-0.8
VPWR-0.4
Current Sense Clamp Voltage
VCL(CSNS)
CSNS Open; IHS[0:3] = 2.0 A with CSR0 ratio
OFF OpenLoad Detection Source Current(20)
ON OpenLoad Fault Detection Current Threshold with LED
IOLD(ON_LED)
VHS[0:3] = VPWR - 0.75 V
Output Short to VPWR Detection Voltage Threshold
V
VCL
0.5 A < IHS[0:3] < 5.0 A, Output programmed OFF
Output Over-temperature Shutdown for 4.5 V < VPWR < 28 V
mA
VOSD(THRES)
Output programmed OFF
Output Negative Clamp Voltage
V
TSD
V
- 22
–
-16
155
175
195
C
Notes
19. Based on statistical data: delta(CSR0)/delta(T)={(measured ICSNS at T1 - measured ICSNS at T2) / measured ICSNS at room} / {T1-T2}. No
production tested.
20. Output OFF OpenLoad Detection Current is the current required to flow through the load for the purpose of detecting the existence of
an OpenLoad condition when the specific output is commanded OFF. Pull-up current is measured for VHS=VOLD(THRES)
35XS3400
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VIH
2.0
–
VDD+0.3
V
VIL
-0.3
–
0.8
V
IDWN
5.0
–
20
A
Input Logic Pull-up Current (CS)
IUP
5.0
–
20
A
Capacitance(22)
CSO
–
–
20
pF
RDWN
125
250
500
k
CIN
–
4.0
12
pF
35XS3400CHFK
18
25
32
35XS3400DHFK
20
27
35
CONTROL INTERFACE
Input Logic High Voltage(21)
Input Logic Low
Voltage(21)
(24)
Input Logic Pull-down Current (SCLK, SI)
(25)
SO, FS Tri-state
Input Logic Pull-down Resistor (RST, WAKE and IN[0:3])
Input Capacitance
(22)
Wake Input Clamp Voltage
(23)
, ICL(WAKE) < 2.5 mA
Wake Input Forward Voltage
VCL(WAKE)
VF(WAKE)
ICL(WAKE) = -2.5 mA
SO High State Output Voltage
–
- 0.3
VSOH
V
VDD-0.4
–
–
–
–
0.4
- 2.0
0
2.0
–
0
1.0
10
Infinite
–
VSOL
IOL = -1.0 mA
SO, CSNS and FS Tri-state Leakage Current
V
- 2.0
IOH = 1.0 mA
SO and FS Low-state Output Voltage
V
V
A
ISO(LEAK)
CS = VIH and 0 V < VSO < VDD, or FS = 5.5 V, or CSNS=0.0 V
FSI External Pull-down Resistance(26)
Watchdog Disabled
k
RFS
Watchdog Enabled
Notes
21. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:3] and WAKE input signals. The WAKE and RST
signals may be supplied by a derived voltage referenced to VPWR.
22.
23.
24.
Input capacitance of SI, CS, SCLK, RST, IN[0:3] and WAKE. This parameter is guaranteed by process monitoring but is not production
tested.
The current must be limited by a series resistance when using voltages > 7.0 V.
Pull-down current is with VSI > 1.0 V and VSCLK > 1.0 V.
25.
Pull-up current is with VCS < 2.0 V. CS has an active internal pull-up to VDD.
26.
In Fail-Safe HS[0:3] depends respectively on ON[0:3]. FSI has an active internal pull-up to VREG ~ 3.0 V.
35XS3400
10
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
0.2
0.4
0.8
Unit
POWER OUTPUT TIMING HS0 TO HS3
Output Rising Medium Slew Rate (medium speed slew rate / SR[1:0]=00)(27)
SRR_00
VPWR = 14 V
Output Rising Slow Slew Rate (low speed slew rate / SR[1:0]=01)(27)
SRR_01
VPWR = 14 V
Output Falling Fast Slew Rate (high speed slew rate /
SR[1:0]=10)(27)
VPWR = 14 V, f PWM = 240 Hz, PWM duty-cycle = 50%, @ 25 °C for medium
speed slew rate (SR[1:0]=00)
1.6
0.2
0.4
0.8
0.1
0.2
0.4
0.4
0.8
1.6
35
60
85
35
60
85
0.8
1.0
1.2
-25
0
25
V/s
V/s
V/s
V/s
s
s
SR
VPWR = 14 V @ 25 °C and for medium speed slew rate (SR[1:0]=00)
Driver Output Matching Time (t DLY(ON) - t DLY(OFF))
0.8
t DLY(OFF)
VPWR = 14 V for medium speed slew rate (SR[1:0]=00)
Driver Output Matching Slew Rate (SRR /SRF)
0.4
t DLY(ON)
VPWR = 14 V for medium speed slew rate (SR[1:0]=00)
Output Turn-OFF Delay Time(29)
0.4
SRF_10
VPWR = 14 V
Output Turn-ON Delay Time(28)
0.2
SRF_01
VPWR = 14 V
Output Rising Fast Slew Rate (high speed slew rate / SR[1:0]=10)(27)
0.1
SRF_00
VPWR = 14 V
Output Falling Slow Slew Rate (low speed slew rate / SR[1:0]=01)(27)
V/s
SRR_10
VPWR = 14 V
Output Falling Medium Slew Rate (medium speed slew rate / SR[1:0]=00)(27)
V/s
s
t RF
Notes
27. Rise and Fall Slew rates measured across a 5.0 resistive load at high side output = 30% to 70% (see Figure 4, page 16).
28. Turn-ON delay time measured from rising edge of any signal (IN[0 : 3] and CS) that would turn the output ON to VHS[0 : 3] = VPWR / 2 with
RL = 5.0 resistive load.
29.
Turn-OFF delay time measured from falling edge of any signal (IN[0 : 3] and CS) that would turn the output OFF to VHS[0 : 3] =VPWR / 2
with RL = 5.0 resistive load.
35XS3400
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
-
5.0
20
-
5.0
10
Unit
POWER OUTPUT TIMING HS0 TO HS3 (CONTINUED)
Fault Detection Blanking Time(30)
tFAULT
35XS3400CHFK
35XS3400DHFK
(31)
Output Shutdown Delay Time
s
s
tDETECT
35XS3400CHFK
-
7.0
30
35XS3400DHFK
-
7.0
20
t CNSVAL
–
70
100
s
t WDTO
217
310
400
ms
-
fIN0 / 128
-
ms
(32)
CS to CSNS Valid Time
Watchdog
Timeout(33)
ON OpenLoad Fault Cyclic Detection Time with LED
Notes
30. Time necessary to report the fault to FS pin.
31. Time necessary to switch-off the output in case of OT or OC or SC or UV fault detection (from negative edge of FS pin to HS voltage =
50% of VPWR
32.
33.
Time necessary for the CSNS to be with ±5% of the targeted value.
For FSI open, the watchdog timeout delay measured from the rising edge of RST, to HS[0,2] output state depend on the corresponding
input command.
35XS3400
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
tOC1_00
3.4
5.0
6.6
tOC2_00
1.0
1.72
2.0
tOC3_00
1.4
2.0
2.6
tOC4_00
2.0
3.0
4.0
tOC5_00
3.4
5.0
6.74
tOC6_00
8.4
12.2
16
tOC7_00
31.2
44.6
48
tOC1_01
1.72
2.48
3.22
tOC2_01
0.56
0.8
1.04
tOC3_01
0.72
1.04
1.36
tOC4_01
1.02
1.58
1.92
tOC5_01
1.56
2.24
2.92
tOC6_01
4.28
6.12
7.96
tOC7_01
15.4
22.2
29
tOC1_10
6.8
9.8
12.8
tOC2_10
2.2
3.2
4.2
tOC3_10
2.8
4.2
5.6
tOC4_10
4.0
5.8
7.6
tOC5_10
6.8
9.8
12.8
tOC6_10
17
24.4
31.8
tOC7_10
6.24
89.2
116
tOC1_11
13.7
19.6
25.5
tOC2_11
4.5
6.4
8.3
tOC3_11
5.9
8.4
10.9
tOC4_11
8.1
11.6
15.1
tOC5_11
13.7
19.6
25.5
tOC6_11
34.2
48.8
63.4
tOC7_11
124.9
178.4
231.9
Output Over-current Time Step
OC[1:0]=00 (slow by default)
OC[1:0]=01 (fast)
OC[1:0]=10 (medium)
OC[1:0]=11 (very slow)
Unit
ms
35XS3400
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
tBC1_00
582
834
1084
tBC2_00
312
448
584
tBC3_00
356
510
664
tBC4_00
416
596
776
tBC5_00
502
718
934
tBC6_00
628
898
1168
tBC1_01
296
418
544
tBC2_01
156
224
292
tBC3_01
176
254
332
tBC4_01
202
290
378
Bulb Cooling Time Step
Unit
ms
CB[1:0]=00 or 11 (medium)
CB[1:0]=01 (fast)
tBC5_01
256
360
468
tBC6_01
452
648
884
tBC1_10
1166
1668
2170
tBC2_10
624
894
1164
tBC3_10
714
1022
1310
tBC4_10
834
1192
1552
tBC5_10
1002
1434
1866
tBC6_10
1256
1796
2340
CB[1:0]=10 (slow)
PWM MODULE TIMING
Input PWM Clock Range on IN0
fIN0
7.68
–
30.72
kHz
Input PWM Clock Low Frequency Detection Range on
IN0(34)
fIN0(LOW)
1.0
2.0
4.0
kHz
Input PWM Clock High Frequency Detection Range on
IN0(34)
fIN0(HIGH)
100
200
400
kHz
fPWM
–
–
1.0
kHz
AFPWM(CAL)
-10
–
+10
%
fPWM(0)
84
120
156
Hz
CS Calibration Low Minimum Time Detection Range
t CSB(MIN)
14
20
26
s
CS Calibration Low Maximum Tine Detection Range
t CSB(MAX)
140
200
260
s
RPWM_400
10
–
98
%
RPWM_200
5.0
–
98
%
RPWM_1k
6.0
–
94
%
tIN
175
250
325
ms
tAUTO
105
150
195
ms
Output PWM Frequency Range
Output PWM Frequency Accuracy using Calibrated Oscillator
Default Output PWM Frequency using Internal Oscillator
Output PWM Duty-cycle Range for fPWM = 400
Hz(35)
Output PWM Duty-cycle Range for fPWM = 200 Hz
(35)
Output PWM Duty-cycle Range for fPWM = 1.0 kHz for high speed slew rate
(35)
INPUT TIMING
Direct Input Toggle Timeout
AUTO-RETRY TIMING
Auto-retry Period
Notes
34. Clock Fail detector available for PWM_en bit is set to logic [1] and CLOCK_sel is set to logic [0].
35. The PWM ratio is measured at VHS = 50% of VPWR and for the default SR value. It is possible to put the device fully-on (PWM duty-cycle
100%) and fully-off (duty-cycle 0%). For values outside this range, a calibration is needed between the PWM duty-cycle programming
and the PWM on the output with RL = 5.0 resistive load.
35XS3400
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
TOTWAR
110
125
140
°C
TFEED
1.15
1.20
1.25
V
DTFEED
-3.5
-3.7
-3.9
mV/°C
f SPI
–
–
8.0
MHz
t WRST
10
–
–
s
t CS
–
–
1.0
s
t ENBL
–
–
5.0
s
t LEAD
–
–
500
ns
t WSCLKh
–
–
50
ns
t WSCLKl
–
–
50
ns
TEMPERATURE ON THE GND FLAG
Thermal Prewarning Detection(36)
Analog Temperature Feedback at TA = 25 °C with RCSNS = 2.5 k
Analog Temperature Feedback Derating with RCSNS = 2.5 k
SPI INTERFACE
(37)
CHARACTERISTICS(36)
Maximum Frequency of SPI Operation
(38)
Required Low State Duration for RST
Rising Edge of CS to Falling Edge of CS (Required Setup
Time)(39)
(39)
Rising Edge of RST to Falling Edge of CS (Required Setup Time)
Falling Edge of CS to Rising Edge of SCLK (Required Setup
Required High State Duration of SCLK (Required Setup
Time)(39)
Time)(39)
Required Low State Duration of SCLK (Required Setup Time)
(39)
(39)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
t LAG
–
–
60
ns
SI to Falling Edge of SCLK (Required Setup
Time)(40)
t SI (SU)
–
–
37
ns
Falling Edge of SCLK to SI (Required Setup
Time)(40)
t SI (HOLD)
–
–
49
ns
–
–
13
–
–
13
t RSI
–
–
13
ns
SO Rise Time
t RSO
CL = 80 pF
SO Fall Time
t FSO
CL = 80 pF
SI, CS, SCLK, Incoming Signal Rise Time(40)
SI, CS, SCLK, Incoming Signal Fall
Time(40)
Time from Rising Edge of SCLK to SO High Logic
ns
t FSI
–
–
13
ns
(41)
t SO(EN)
–
–
60
ns
Level(42)
t SO(DIS)
–
–
60
ns
Time from Rising Edge of SCLK to SO Low Logic Level
Notes
36.
37.
38.
39.
40.
41.
42.
ns
Parameters guaranteed by design.
Value guaranteed per statistical analysis
RST low duration measured with outputs enabled and going to OFF or disabled condition.
Maximum setup time required for the 35XS3400 is the minimum guaranteed time needed from the microcontroller.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at SO. 1.0 kon pull-up on CS.
Time required for output status data to be terminated at SO. 1.0 kon pull-up on CS.
35XS3400
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
IN[0:3]
high logic level
low logic level
Time
or
CS
high logic level
low logic level
Time
VHS[0:3]
VPWR
RPWM
50%VPWR
Time
t DLY(ON)
VHS[0:3]
70% VPWR
t DLY(OFF)
SR F
SR R
30% VPWR
Time
Figure 4. Output Slew Rate and Time Delays
IOCH1
IOCH2
Load
Current
IOC1
IOC2
IOC3
IOC4
IOCLO4
IOCLO3
IOCLO2
IOCLO1
Time
t OC1
t OC2
t OC3
t OC4
t OC5
t OC6
t OC7
Figure 5. Over-current Shutdown Protection
35XS3400
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
IOCH1
IOCH2
IOC1
IOC2
IOC3
IOC4
IOCLO4
IOCLO3
IOCLO2
IOCLO1
t BC3
tB C1
t BC2
t BC4
tB C5
Previous OFF duration
(toff)
tB C6
Figure 6. Bulb Cooling Management
VIH
VIH
RSTB
RST
10%
0.2
VDDVDD
tWRST
TwRSTB
tENBL
VIL
VIL
tTCSB
CS
TENBL
VIH
VIH
90%
VDD
0.7VDD
CS
CSB
10%
VDD
0.7VDD
t WSCLKh
TwSCLKh
tTlead
LEAD
VIL
VIL
t RSI
TrSI
t LAG Tlag
90%
VDD
0.7VDD
SCLK
SCLK
VIH
VIH
10% VDD
0.2VDD
t TSIsu
SI(SU)
VIL
VIL
t WSCLKl
TwSCLKl
t SI(HOLD)
TSI(hold)
SI
SI
90%
VDD
0.7 VDD
0.2VDD
10%
VDD
Don’t Care
Valid
tTfSI
FSI
Don’t Care
Valid
Don’t Care
VIH
VIH
VIH
VIL
Figure 7. Input Timing Switching Characteristics
35XS3400
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
tFSI
tRSI
TrSI
TfSI
VOH
VOH
90%
VDD
3.5V
50%
SCLK
SCLK
1.0V VDD
10%
VOL
VOL
t SO(EN)
TdlyLH
SO
SO
90%
VDD
0.7 VDD
0.210%
VDDVDD
Low-to-High
Low
to High
TrSO
t RSO
VOH
VOH
VOL
VOL
VALID
tTVALID
SO
TfSO
t FSO
SO
VOH
VOH
VDD
VDD
High to Low 0.790%
High-to-Low
0.2VDD
10% VDD
TdlyHL
VOL
VOL
t SO(DIS)
Figure 8. SCLK Waveform and Valid SO Data Delay Time
35XS3400
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 35XS3400 is one in a family of devices designed for
low-voltage automotive lighting applications. Its four low
RDS(ON) MOSFETs (quad 35 m) can control four separate
28 W bulbs.
Programming, control and diagnostics are accomplished
using a 16-bit SPI interface. Its output with selectable slewrate improves electromagnetic compatibility (EMC) behavior.
Additionally, each output has its own parallel input or SPI
control for pulse-width modulation (PWM) control if desired.
The 35XS3400 allows the user to program via the SPI the
fault current trip levels and duration of acceptable lamp
inrush. The device has Fail-safe mode to provide functionality
of the outputs in case of MCU damage.
FUNCTIONAL PIN DESCRIPTION
OUTPUT CURRENT MONITORING (CSNS)
The Current Sense pin provides a current proportional to
the designated HS0 : HS3 output or a voltage proportional to
the temperature on the GND flag. That current is fed into a
ground-referenced resistor (4.7 k typical) and its voltage is
monitored by an MCU's A/D. The output type is selected via
the SPI. This pin can be tri-stated through the SPI.
DIRECT INPUTS (IN0, IN1, IN2, IN3)
Each IN input wakes the device. The IN0 : IN3 high side
input pins are also used to directly control HS0 : HS3 high side
output pins. If the outputs are controlled by the PWM module,
the external PWM clock is applied to IN0 pin. These pins are
to be driven with CMOS levels, and they have a passive
internal pull-down, RDWN.
FAULT STATUS (FS)
This pin is an open drain configured output requiring an
external pull-up resistor to VDD for fault reporting. If a device
fault condition is detected, this pin is active LOW. Specific
device diagnostics and faults are reported via the SPI SO pin.
WAKE
The wake input wakes the device. An internal clamp
protects this pin from high damaging voltages with a series
resistor (10 k typ). This input has a passive internal pulldown, RDWN.
RESET (RST)
The reset input wakes the device. This is used to initialize
the device configuration and fault registers, as well as place
the device in a low-current Sleep mode. The pin also starts
the watchdog timer when transitioning from logic [0] to
logic [1]. This pin has a passive internal pull-down, RDWN.
CHIP SELECT (CS)
The CS pin enables communication with the master
microcontroller (MCU). When this pin is in a logic [0] state,
the device is capable of transferring information to, and
receiving information from, the MCU. The 35XS3400 latches
in data from the input shift registers to the addressed
registers on the rising edge of CS. The device transfers status
information from the power output to the Shift register on the
falling edge of CS. The SO output driver is enabled when CS
is logic [0]. CS should transition from a logic [1] to a logic [0]
state only when SCLK is a logic [0]. CS has an active internal
pull-up from VDD, IUP.
SERIAL CLOCK (SCLK)
The SCLK pin clocks the internal shift registers of the
35XS3400 device. The serial input (SI) pin accepts data into
the input shift register on the falling edge of the SCLK signal
while the serial output (SO) pin shifts data information out of
the SO line driver on the rising edge of the SCLK signal. It is
important the SCLK pin be in a logic low state whenever CS
makes any transition. For this reason, it is recommended the
SCLK pin be in a logic [0] whenever the device is not
accessed (CS logic [1] state). SCLK has an active internal
pull-down. When CS is logic [1], signals at the SCLK and SI
pins are ignored and SO is tri-stated (high-impedance) (see
Figure 9, page 22). SCLK input has an active internal pulldown, IDWN.
SERIAL INPUT (SI)
This is a serial interface (SI) command data input pin.
Each SI bit is read on the falling edge of SCLK. A 16-bit
stream of serial data is required on the SI pin, starting with
D15 (MSB) to D0 (LSB). The internal registers of the
35XS3400 are configured and controlled using a 5-bit
addressing scheme described in Table 10, page 29. Register
addressing and configuration are described in Table 11,
page 29. SI input has an active internal pull-down, IDWN.
DIGITAL DRAIN VOLTAGE (VDD)
This pin is an external voltage input pin used to supply
power to the SPI circuit. In the event VDD is lost (VDD Failure),
the device goes to Fail-safe mode.
35XS3400
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
GROUND (GND)
SCLK. SO reporting descriptions are provided in Table 23,
page 33.
These pins are the ground for the device.
HIGH SIDE OUTPUTS (HS3, HS1, HS0, HS2)
POSITIVE POWER SUPPLY (VPWR)
This pin connects to the positive power supply and is the
source of operational power for the device. The VPWR
contact is the backside surface mount tab of the package.
SERIAL OUTPUT (SO)
The SO data pin is a tri-stateable output from the shift
register. The SO pin remains in a high-impedance state until
the CS pin is put into a logic [0] state. The SO data is capable
of reporting the status of the output, the device configuration,
the state of the key inputs, etc. The SO pin changes state on
the rising edge of SCLK and reads out on the falling edge of
Protected 35 m high side power outputs to the load.
FAIL-SAFE INPUT (FSI)
This pin incorporates an active internal pull-up current
source from internal supply (VREG). This enables the
watchdog timeout feature.
When the FSI pin is opened, the watchdog circuit is
enabled. After a watchdog timeout occurs, the output states
depends on IN[0:3].
When the FSI pin is connected to GND, the watchdog
circuit is disabled. The output states depends on IN[0:3] in
case of VDD failure condition, in case VDD failure detection is
activated (VDD_FAIL_en bit sets to logic [1]).
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
POWER SUPPLY
MCU INTERFACE and
OUTPUT CONTROL
SELFPROTECTED
HIGH SIDE
SWITCHES
HS0-HS3
SPI INTERFACE
PARALLEL CONTROL
INPUTS
MCU
INTERFACE
PWM CONTROLLER
POWER SUPPLY
The 35XS3400 is designed to operate from 4.0 to 28 V on
the VPWR pin. Characteristics are provided from 6.0 to 20 V
for the device. The VPWR pin supplies power to internal
regulator, analog, and logic circuit blocks. The VDD supply is
used for Serial Peripheral Interface (SPI) communication in
order to configure and diagnose the device. This IC
architecture provides a low quiescent current Sleep mode.
Applying VPWR and VDD to the device will place the device in
the Normal mode. The device will transit to Fail-safe mode in
case of failures on the SPI or/and on the VDD voltage.
HIGH SIDE SWITCHES: HS0 – HS3
These pins are the high side outputs controlling
automotive lamps located for the rear of vehicle, such as
28 W bulbs and LED modules. 55 W/65 W lamps can be
driven for two outputs shorted together. Those N-channel
MOSFETs with 35 m RDS(ON) are self-protected and
present extended diagnostics in order to detect bulb outage
and short-circuit fault condition. The HS output is actively
clamped during turn off of inductive loads and inductive
battery line.
When driving DC motor or solenoid loads demanding
multiple switching, an external recirculation device must be
used to maintain the device in its Safe Operating Area.
MCU INTERFACE AND OUTPUT CONTROL
In Normal mode, each bulb is controlled directly from the
MCU through SPI. A pulse width modulation control module
allows improvement of lamp lifetime with bulb power
35XS3400
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
regulation (PWM frequency range from 100 to 400 Hz) and
addressing the dimming application (day running light). An
analog feedback output provides a current proportional to the
load current or the temperature of the board. The SPI is used
to configure and to read the diagnostic status (faults) of high
side outputs. The reported fault conditions are: OpenLoad,
short-circuit to battery, short-circuit to ground (over-current
and severe short-circuit), thermal shutdown, and under/overvoltage. Thanks to accurate and configurable over-current
detection circuitry and wire-harness optimization, the vehicle
is lighter.
In Fail-safe mode, each lamp is controlled with dedicated
parallel input pins. The device is configured in default mode.
35XS3400
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
SPI PROTOCOL DESCRIPTION
The SI / SO pins of the 35XS3400 follow a first-in first-out
(D15 to D0) protocol, with both input and output words
transferring the most significant bit (MSB) first. All inputs are
compatible with 5.0 V or 3.3 V CMOS logic levels.
The SPI interface has a full duplex, three-wire
synchronous data transfer with four I/O lines associated with
it: Serial Input (SI), Serial Output (SO), Serial Clock (SCLK),
and Chip Select (CS).
CSB
CS
CS
SCLK
SI
SO
D15
D14
D13
D12
D11
D10
D9
OD15 OD14 OD13 OD12 OD11 OD10 OD9
D8
OD8
D7
D6
OD7
D5
OD6
OD5
D4
D3
OD4
D2
OD3
OD2
D1
D0
OD1 OD0
Notes 1. RST is a logic [1] state during the above operation.
D15is: D0
to the
most
ordered entry of data into the device.
NOTES: 1. 2.RSTB
in arelate
logic H state
during
therecent
above operation.
OD15
: OD0
relate
thetofirst
16 bits
ofordered
ordered
fault
and status
data
out IC
of the device.
device.
2. 3.DO,
D1, D2,
... , and
D15to
relate
the most
recent
entry
of program
data into
the LUX
Figure 9. Single 16-Bit Word SPI Communication
OPERATIONAL MODES
The 35XS3400 has four operating modes: Sleep, Normal,
Fail-safe and Fault. Table 6 and Figure 11 summarize details
contained in succeeding paragraphs.
The Figure 10 describes an internal signal called IN_ON[x]
depending on IN[x] input.
IN[x]
tIN
IN_ON[x]
• fault = OC[0:3] or OT[0:3] or SC[0:3] or UV
( UV ) or ( OV and OV_dis ).
Table 6. 35XS3400 Operating Modes
Mode
wake-up
fail
faul
t
Sleep
0
x
x
Device is in Sleep mode. All
outputs are OFF.
Normal
1
0
0
Device is currently in Normal
mode. Watchdog is active if
enabled.
Fail-safe
1
1
0
Device is currently in Fail-safe
mode due to watchdog
timeout or VDD Failure
conditions. The output states
depend on the corresponding
input in case FSI is open.
Fault
1
X
1
Device is currently in Fault
mode. The faulted output(s) is
(are) OFF. The safe autoretry
circuitry is active to turn-on
again the output(s).
Figure 10. IN_ON[x] internal signal
The 35XS3400 transits to operating modes according to
the following signals:
• wake-up = RST or WAKE or IN_ON[0] or IN_ON[1] or
IN_ON[2] or IN_ON[3],
• fail = (VDD Failure and VDD_FAIL_en) or ( Watchdog
time-out and FSI input not shorted to ground ),
Comments
x = Don’t care.
35XS3400
22
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
(fail=0) and (wake-up=1) and (fault=0)
Sleep
(wake-up=0)
(wake-up=1) and
(fail=1)
and (fault=0)
(wake-up=1)
and (fault=1)
(wake-up=0)
(fail=1) and
(wake-up=1)
and (fault=1)
Fail Safe
(wake-up=0)
(fail=0) and
(wake-up=1)
and (fault=1)
Fault
Normal
(fail=0) and
(wake-up=1)
and (fault=0)
(fail=1) and
(wake-up=1)
and (fault=0)
(fail=0) and (wake-up=1) and (fault=0)
(fail=1) and (wake-up=1) and (fault=0)
Figure 11. Operating Modes
SLEEP MODE
The 35XS3400 is in Sleep mode when:
• VPWR and VDD are within the normal voltage range,
• wake-up = 0,
• fail = X,
• fault = X.
This is the Default mode of the device after first applying
battery voltage (VPWR) prior to any I/O transitions. This is
also the state of the device when the WAKE and RST and
IN_ON[0:3] are logic [0]. In the Sleep mode, the output and
all unused internal circuitry, such as the internal regulator, are
off to minimize draw current. In addition, all SPI-configurable
features of the device are as if set to logic [0].
NORMAL MODE
The 35XS3400 is in Normal mode when:
• VPWR and VDD are within the normal voltage range,
• wake-up = 1,
• fail = 0,
• fault = 0.
In this mode, the NM bit is set to lfault_contrologic [1] and
the outputs HS[0:3] are under control, as defined by hson
signal:
hson[x] = ( ( (IN[x] and DIR_dis[x]) or On bit[x] ) and
PWM_en ) or (On bit [x] and Duty_cycle[x] and PWM_en).
In this mode and also in Fail-safe, the fault condition reset
depends on fault_control signal, as defined below:
fault_control[x] = ( (IN_ON[x] and DIR_dis[x]) and
PWM_en ) or (On bit [x]).
Programmable PWM module
The outputs HS[0:3] are controlled by the programmable
PWM module if PWM_en and On bits are set to logic [1].
The clock frequency from IN0 input pin or from internal
clock is the factor 27 (128) of the output PWM frequency
(CLOCK_sel bit). The outputs HS[0:3] can be controlled in
the range of 5% to 98% with a resolution of 7 bits of dutycycle (Table 7). The state of other IN pin is ignored.
Table 7. Output PWM Resolution
On bit
Duty-cycle
Output state
0
X
OFF
1
0000000
PWM (1/128 duty-cycle)
1
0000001
PWM (2/128 duty-cycle)
1
0000010
PWM (3/128 duty-cycle)
1
n
PWM ((n+1)/128 duty-cycle)
1
1111111
fully ON
The timing includes seven programmable PWM switching
delay (number of PWM clock rising edges) to improve overall
EMC behavior of the light module (Table 8).
35XS3400
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 8. Output PWM Switching Delay
Delay bits
Output delay
000
no delay
001
16 PWM clock periods
010
32 PWM clock periods
FAIL-SAFE MODE
The 35XS3400 is in Fail-safe mode when:
• VPWR is within the normal voltage range,
• wake-up = 1,
• fail = 1,
• fault = 0.
011
48 PWM clock periods
Watchdog
100
64 PWM clock periods
101
80 PWM clock periods
110
96 PWM clock periods
111
112 PWM clock periods
If the FSI input is not grounded, the watchdog timeout
detection is active when either the WAKE or IN_ON[0:3] or
RST input pin transitions from logic [0] to logic [1]. The WAKE
input is capable of being pulled up to VPWR with a series of
limiting resistance limiting the internal clamp current
according to the specification.
The watchdog timeout is a multiple of an internal oscillator.
As long as the WD bit (D15) of an incoming SPI message is
toggled within the minimum watchdog timeout period
(WDTO), the device will operate normally.
The clock frequency from IN0 is permanently monitored in
order to report a clock failure in case of the frequency is out
a specified frequency range (from fIN0(LOW) to fIN0(HIGH)). In
case of clock failure, no PWM feature is provided, the On bit
defines the outputs state and the CLOCK_fail bit reports [1].
Calibratable Internal Clock
The internal clock can vary as much as +/-30 percent
corresponding to typical fPWM(0) output switching period.
Using the existing SPI inputs and the precision timing
reference already available to the MCU, the 35XS3400
allows clock period setting within 10 percent of accuracy.
Calibrating the internal clock is initiated by defined word to
CALR register. The calibration pulse is provided by the MCU.
The pulse is sent on the CS pin after the SPI word is
launched. At the moment, the CS pin transitions from logic [1]
to [0] until from logic [0] to [1] determine the period of internal
clock with a multiplicative factor of 128.
Fail Safe Conditions
If an internal watchdog time-out occurs before the WD bit
for FSI open (Table 9) or in case of VDD failure condition
(VDD< VDD(FAIL))) for VDD_FAIL_en bit is set to logic [1], the
device will revert to a Fail-safe mode until the WD bit is written
to logic [1] (see fail-safe to normal mode transition paragraph)
and VDD is within the normal voltage range.
Table 9. SPI Watchdog Activation
Typical RFSI ()
Watchdog
0 (shorted to ground)
Disabled
(open)
Enable
During the Fail-safe mode, the outputs will depend on the
corresponding input. The SPI register content is reset to their
default value (except POR bit) and fault protections are fully
operational.
The Fail-safe mode can be detected by monitoring the NM
bit is set to [0].
CS
SI
CALR
SI command
ignored
NORMAL & FAIL SAFE MODE TRANSITIONS
Transition Fail-safe to Normal mode
Internal
clock duration
In case of negative CS pulse is outside a predefined time
range (from t CSB(MIN) to t CSB(MAX)), the calibration event will
be ignored and the internal clock will be unaltered or reset to
default value (fPWM(0)) if this was not calibrated before.
The calibratable clock is used, instead of the clock from
IN0 input, when CLOCK_sel is set to [1].
To leave the Fail-safe mode, VDD must be in nominal
voltage and the microcontroller has to send a SPI command
with WDIN bit set to logic [1]; the other bits are not
considered. The previous latched faults are reset by the
transition into Normal mode (auto-retry included).
Moreover, the device can be brought out of the Fail-safe
mode due to watchdog timeout issue by forcing the FSI pin to
logic [0].
Transition Normal to Fail-Safe Mode
To leave the Normal mode, a Fail-safe condition must
occurred (fail=1). The previous latched faults are reset by the
transition into Fail-safe mode (autoretry included).
35XS3400
24
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
FAULT MODE
The 35XS3400 is in Fault mode when:
• VPWR and VDD are within the normal voltage range,
• wake-up = 1,
• fail = X,
• fault=1.
This device indicates the faults below as they occur by
driving the FS pin to logic [0] for RST input is pulled up:
• Over-temperature fault,
• Over-current fault,
• Severe short-circuit fault,
• Output(s) shorted to VPWR fault in OFF state,
• OpenLoad fault in OFF state,
• Over-voltage fault (enabled by default),
• Under-voltage fault.
The FS pin will automatically return to logic [1] when the
fault condition is removed, except for over-current, severe
short-circuit, over-temperature and under-voltage which will
be reset by a new turn-on command (each fault_control
signal to be toggled).
Fault information is retained in the SPI fault register and is
available (and reset) via the SO pin during the first valid SPI
communication.
The OpenLoad fault in ON state is only reported through
SPI register without effect on the corresponding output state
(HS[x]) and the FS pin.
START-UP SEQUENCE
The 35XS3400 enters in Normal mode after start-up if
following sequence is provided:
• VPWR and VDD power supplies must be above their
under-voltage thresholds,
• generate wake-up event (wake-up=1) from 0 to 1 on
RSTB. The device switches to Normal mode with SPI
register content is reset (as defined in Table 11 and
Table 23). All features of 35XS3400 will be available
after 50s typical and all SPI registers are set to default
values (set to logic [0]). The UV fault is reported in the
SPI status registers.
And, in case of the PWM module is used (PWM_en bit is
set to logic [1]) with an external reference clock:
• apply PWM clock on IN0 input pin after maximum
200 s (min. 50 s).
If the correct start-up sequence is not provided, the PWM
function is not guaranteed.
PROTECTION AND DIAGNOSTIC FEATURES
PROTECTIONS
Over-temperature Fault
The 35XS3400 incorporates over-temperature detection
and shutdown circuitry for each output structure.
Two cases need to be considered when the output
temperature is higher than TSD:
• If the output command is ON: the corresponding output
is latched OFF. FS will be also latched to logic [0]. To
delatch the fault and be able to turn ON again the
outputs, the failure condition must disappear and the
autoretry circuitry must be active or the corresponding
output must be commanded OFF and then ON (toggling
fault_control signal of corresponding output) or
VSUPPLY(POR) condition if VDD = 0.
• If the output command is OFF: FS will go to logic [0] until
the corresponding output temperature will be below
TSD.
For both cases, the fault register OT[0:3] bit into the status
register will be set to [1]. The fault bits will be cleared in the
status register after a SPI read command.
Over-current Fault
The 35XS3400 incorporates output shutdown in order to
protect each output structure against resistive short-circuit
condition. This protection is composed by eight predefined
current levels (time dependent) to fit 28 W bulb profiles.
In the first turn-on, the lamp filament is cold and the current
will be huge. fault_control signal transition from logic [0] to [1]
or an auto-retry define this event. In this case, the overcurrent protection will be fitted to inrush current, as shown in
Figure 5. This over-current protection is programmable:
OC[1:0] bits select over-current slope speed and OCHI1
current step can be removed in case the OCHI bit is set to [1].
Over-current thresholds
fault_control
hson
signal
hson
PWM
In steady state, the wire harness will be protected by
OCLO2 current level by default. Three other DC over-current
levels are available: OCLO1 or OCLO3 or OCLO4 based on
the state of the OCLO[1,0] bits.
If the load current level ever reaches the over-current
detection level, the corresponding output will latch the output
OFF and FS will be also latched to logic [0]. To delatch the
fault and be able to turn ON again the corresponding output,
35XS3400
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
the failure condition must disappear and the auto-retry
circuitry must be active or the corresponding output must be
commanded OFF and then ON (toggling fault_control signal
of corresponding output) or VSUPPLY(POR) condition if
VDD = 0.
The SPI fault report (OC[0:3] bits) is removed after a read
operation.
In Normal mode using the internal PWM module, the
35XS3400 also incorporates a cooling bulb filament
management, if the OC_mode is set to logic [1]. In this case,
the 1st step of multi-step over-current protection will depend
to the previous OFF duration, as illustrated in Figure 6. The
following figure illustrates the current level will be used in
function to the duration of previous OFF state (toff). The slope
of cooling bulb emulator is configurable with OCOFFCB[1:0]
bits.
(VPWR > VPWR(OV)). The outputs remain in the OFF state until
the over-voltage condition is removed (VPWR < VPWR(OV) VPWR(OVHYS)). When experiencing this fault, the OVF fault bit
is set to logic [1] and cleared after either a valid SPI read.
The over-voltage protection can be disabled through SPI
(OV_dis bit is disabled set to logic [1]). The fault register
reflects any over-voltage condition (VPWR > VPWR(OV)). This
over-voltage diagnosis, as a warning, is removed after a read
operation, if the fault condition disappears. The HS[0:3]
outputs are not commanded in RDS(ON) above the OV
threshold.
In Fail-safe mode, the over-voltage activation depends on
the RST logic state; enable for RST = 1 and disable for
RST = 0. The device is still protected with over-temperature
protection in case the over-voltage feature is disabled.
Under-voltage Fault
Depending on toff
depending to toff
Over-current thresholds
Cooling
toff
fault_control
hson
signal
hson
PWM
Severe Short-circuit Fault
The 35XS3400 provides output shutdown in order to
protect each output in case of severe short-circuit during of
the output switching.
If the short-circuit impedance is below RSHORT, the device
will latch the output OFF, FS will go to logic [0] and the fault
register SC[0:3] bit will be set to [1]. To delatch the fault and
be able to turn ON again the outputs, the failure condition
must disappear and the corresponding output must be
commanded OFF, and then ON (toggling fault_control signal
of corresponding output) or VSUPPLY(POR) condition, if
VDD = 0.
The SPI fault report (SC[0:3] bits) is removed after a read
operation.
Over-voltage Fault (Enabled by default)
By default, the over-voltage protection is enabled. The
35XS3400 shuts down all outputs and FS will go to logic [0]
during an over-voltage fault condition on the VPWR pin
The output(s) will latch off at some battery voltage below
VPWR(UV). As long as the VDD level stays within the normal
specified range, the internal logic states within the device will
remain (configuration and reporting).
In the case where battery voltage drops below the undervoltage threshold (VPWR < VPWR(UV)), the outputs will turn off,
FS will go to logic [0], and the fault register UV bit will be set
to [1].
Two cases need to be considered when the battery level
recovers (VPWR > VPWR(UV)_UP):
• If the output command is OFF, FS will go to logic [1], but
the UV bit will remain set to 1 until the next read
operation (warning report).
• If the output command is ON, FS will remain at logic [0].
To delatch the fault and be able to turn ON again the
outputs, the failure condition must disappear and the
autoretry circuitry must be active or the corresponding
output must be commanded OFF and then ON (toggling
fault_control signal of corresponding output) or
VSUPPLY(POR) condition if VDD = 0.
In extended mode, the output is protected by overtemperature shutdown circuitry. All previous latched faults,
occurred when VPWR was within the normal voltage range,
are guaranteed if VDD is within the operational voltage range
or until VSUPPLY(POR) if VDD = 0. Any new OT fault is
detected (VDD failure included) and reported through SPI
above VPWR(UV). The output state is not changed as long as
the VPWR voltage does not drop any lower than 3.5 V typical.
All latched faults (over-temperature, over-current, severe
short-circuit, over and under-voltage) are reset if:
• VDD < VDD(FAIL) with VPWR in nominal voltage range,
• VDD and VPWR supplies is below VSUPPLY(POR) voltage
value.
35XS3400
26
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
(fault_control=0)
(Open-oadOFF=1
or ShortVpwr=1
or OV=1)
(fault_control=1 and OV=0)
OFF
if hson=0
(SC=1)
ON
(fault_control=0 or OV=1)
(OpenLoadOFF=1
or ShortVpwr=1
or OV=1)
(OpenLoadON=1)
if hson=1
OFF
(Retry=1)
(fault_control=0)
Latched
(count=16)
(SC=1)
(OpenLoadON=1)
(after Retry Period and OV=0)
Auto-retry
(OV=1)
OFF
Auto-retry
ON
if hson=1
(Retry=1)
=> count=count+1
(OpenLoadOFF=1
or ShortVpwr=1
or OV=1)
(fault_control=0)
Figure 12. Auto-retry State Machine
AUTO-RETRY
The auto-retry circuitry is used to reactivate the output(s)
automatically in case of over-current or over-temperature or
under-voltage failure conditions to provide a high availability
of the load.
Auto-retry feature is available in Fault mode. It is activated
in case of internal retry signal is set to logic [1]:
retry[x] = OC[x] or OT[x] or UV.
The feature retries to switch-on the output(s) after one
auto-retry period (tAUTO) with a limitation in term of number of
occurrence (16 for each output). The counter of retry
occurrences is reset in case of Fail-safe to Normal or Normal
to Fail-safe mode transitions. At each auto-retry, the overcurrent detection will be set to default values in order to
sustain the inrush current.
The Figure 12 describes the auto-retry state machine.
DIAGNOSTIC
Output Shorted to VPWR Fault
The 35XS3400 incorporates output shorted to VPWR
detection circuitry in OFF state. Output shorted to VPWR fault
is detected if output voltage is higher than VOSD(THRES) and
reported as a fault condition when the output is disabled
(OFF). The output shorted to VPWR fault is latched into the
status register after the internal gate voltage is pulled low
enough to turn OFF the output. The OS[0:3] and
OL_OFF[0:3] fault bits are set in the status register and FS
pin reports in real time the fault. If the output shorted to
VPWR fault is removed, the status register will be cleared
after reading the register.
The open output shorted to VPWR protection can be
disabled through SPI (OS_DIS[0:3] bit).
OpenLoad Faults
The 35XS3400 incorporates three dedicated OpenLoad
detection circuitries on the output to detect in OFF and in ON
state.
OpenLoad Detection In Off State
The OFF output OpenLoad fault is detected when the
output voltage is higher than VOLD(THRES) pulled up with
internal current source (IOLD(OFF)) and reported as a fault
condition when the output is disabled (OFF). The OFF Output
OpenLoad fault is latched into the status register or when the
internal gate voltage is pulled low enough to turn OFF the
output. The OL_OFF[0:3] fault bit is set in the status register.
If the OpenLoad fault is removed (FS output pin goes to high),
the status register will be cleared after reading the register.
The OFF output OpenLoad protection can be disabled
through SPI (OLOFF_DIS[0:3] bit).
OpenLoad Detection In On State
The ON output OpenLoad current thresholds can be
chosen by SPI to detect a standard bulbs or LEDs
(OLLED[0:3] bit set to logic [1]). In cases where the load
current drops below the defined current threshold, the OLON
35XS3400
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
bit will be set to a logic [1], the output will stay ON and FS will
not be disturbed.
forward mode. No additional passive components are
required except on VDD current path.
OpenLoad Detection In On State For Led
GROUND DISCONNECT PROTECTION
OpenLoad for LEDs only (OLLED[0:3] set to logic [1]) is
detected periodically each t OLLED (fully-on, D[6:0]=7F). To
detect OLLED in fully-on state, the output must be ON at least
t OLLED.
To delatch the diagnosis, the condition should be removed
and SPI read operation is needed (OL_ON[0:3] bit). The ON
output OpenLoad protection can be disabled through SPI
(OLON_DIS[0:3] bit).
In the event the 35XS3400 ground is disconnected from
load ground, the device protects itself and safely turns OFF
the output regardless of the state of the output at the time of
disconnection (maximum VPWR=16 V). A 10 k resistor
needs to be added between the MCU and each digital input
pin in order to ensure that the device turns off in case of
ground disconnect and to prevent this pin from exceeding
maximum ratings.
Analog Current Recopy and Temperature Feedbacks
LOSS OF SUPPLY LINES
The CSNS pin is an analog output reporting a current
proportional to the designed output current or a voltage
proportional to the temperature of the GND flag (pin #14).
The routing is SPI programmable (TEMP_en, CSNS_en,
CSNS_s[1,0] and CSNS_ratio_s bits).
In case the current recopy is active, the CSNS output
delivers current only during ON time of the output switch
without overshoot. The maximum current is 2.0 mA typical.
The typical value of external CSNS resistor connected to the
ground is 4.7 k.
The current recopy is not active in Fail-safe mode.
Temperature Prewarning Detection
In Normal mode, the 35XS3400 provides a temperature
prewarning reported via SPI in case of the temperature of the
GND flag is higher than TOTWAR. This diagnosis (OTW bit set
to [1]) is latched in the SPI DIAGR0 register. To delatch, a
read SPI command is needed.
ACTIVE CLAMP ON VPWR
The device provides an active gate clamp circuit in order
to limit the maximum transient VPWR voltage at
VPWR(CLAMP). In case of overload on an output, the
corresponding output is turned off, which leads to a highvoltage at VPWR with an inductive VPWR line. When VPWR
voltage exceeds VPWR(CLAMP) threshold, the turn-off on the
corresponding output is deactivated and all HS[0:3] outputs
are switched ON automatically to demagnetize the inductive
Battery line.
For a long battery line between the battery and the device
(> 20 meters), the smart high side switch output may exceed
the energy capability, in case of a short-circuit. It is
recommended to implement a voltage transient suppressor
to drain the battery line energy.
REVERSE BATTERY ON VPWR
The output survives the application of reverse voltage as
low as -18 V. Under these conditions, the ON resistance of
the output is 2 times higher than typical ohmic value in
Loss of VDD
If the external VDD supply is disconnected (or not within
specification: VDD<VDD(FAIL)) with VDD_FAIL_en bit is set to
logic [1]), all SPI register content is reset.
The outputs can still be driven by the direct inputs IN[0 : 3]
if VPWR is within specified voltage range. The 35XS3400
uses the battery input to power the output MOSFET-related
current sense circuitry and any other internal logic providing
Fail-safe device operation with no VDD supplied. In this state,
the over-temperature, over-current, severe short-circuit,
short to VPWR and OFF OpenLoad circuitry are fully
operational with default values corresponding to all SPI bits
are set to logic [0]. No current is conducted from VPWR to
VDD.
Loss of VPWR
If the external VPWR supply is disconnected (or not within
specification), the SPI configuration, reporting, and daisy
chain features are provided for RST is set to logic [1] under
VDD in nominal conditions. This fault condition can be
diagnosed with a UV fault in the SPI STATS_s registers. The
SPI pull-up and pull-down current sources are not
operational. The previous device configuration is maintained.
No current is conducted from VDD to VPWR.
Loss of VPWR and VDD
If the external VPWR and VDD supplies are disconnected
(or not within specification: (VDD and VPWR) <
VSUPPLY(POR)), all SPI register contents are reset with default
values corresponding to all SPI bits are set to logic [0] and all
latched faults are also reset.
EMC PERFORMANCES
All following tests are performed on Freescale evaluation
board in accordance with the typical application schematic.
The device is protected in case of positive and negative
transients on the VPWR line (per ISO 7637-2).
The 35XS3400 successfully meets the Class 5 of the
CISPR25 emission standard and 200 V/m or BCI 200 mA
injection level for immunity tests.
35XS3400
28
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
SERIAL INPUT COMMUNICATION
SPI communication is accomplished using 16-bit
messages. A message is transmitted by the MCU starting
with the MSB D15 and ending with the LSB, D0 (Table 10).
Each incoming command message on the SI pin can be
interpreted using the following bit assignments: the MSB,
D15, is the watchdog bit (WDIN). In some cases, output
selection is done with bits D14 : D13. The next three bits,
D12: D10, are used to select the command register. The
remaining nine bits, D8 : D0, are used to configure and control
the outputs and their protection features.
Multiple messages can be transmitted in succession to
accommodate those applications where daisy-chaining is
desirable, or to confirm transmitted data, as long as the
messages are all multiples of 16 bits. Any attempt made to
latch in a message that is not 16 bits will be ignored.
The 35XS3400 has defined registers, which are used to
configure the device and to control the state of the outputs.
Table 11 summarizes the SI registers.
Table 10. SI Message Bit Assignment
Bit Sig
SI Msg Bit
MSB
Message Bit Description
D15
Watchdog in: toggled to satisfy watchdog requirements.
D14 : D13
Register address bits used in some cases for output selection (Table 12).
D12 : D10
Register address bits.
D9
LSB
Not used (set to logic [0]).
D8:D0
Used to configure the inputs, outputs, and the device protection features and SO status content.
Table 11. Serial Input Address and Configuration Bit Map
SI
Register D15 D1 D1 D1 D1 D1 D9
4 3 2 1 0
SI Data
D8
D7
D6
D5
D4
D3
D2
D1
D0
STATR_s
WDI
N
X
X
0
0
0
0
0
0
0
0
SOA4
SOA3
SOA2
SOA1
SOA0
PWMR_s
WDI
N
A1
A0
0
0
1
0
0
ON_s
PWM6_s
PWM5_s
PWM4_s
PWM3_s
PWM2_s
PWM1_s
PWM0_s
CONFR0_s WDI
N
A1
A0
0
1
0
0
0
0
0
DIR_dis_s
SR1_s
SR0_s
DELAY2_s
DELAY1_s
DELAY0_s
CONFR1_s WDI
N
A1
A0
0
1
1
0
0
0
0
BC1_s
OCR_s
WDI
N
A1
A0
1
0
0
0
GCR
WDI
N
0
0
1
0
1
0
CALR
WDI
N
0
0
1
1
1
0
1
0
Register
state after
RST=0 or
VDD(FAIL)
or
VSUPPLY(P
0
0
0
X
X
X
0
0
0
Retry_
Retry_dis_
s
unlimited_s
BC0_s
OS_dis_s
OLON_dis_ OLOFF_dis_ OLLED_en CSNS_ratio
s
s
_s
_s
OC1_s
OC0_s
OCHI_s
OCLO1_s
TEMP_en
CSNS_en
CSNS1
CSNS0
X
OV_dis
0
0
1
1
0
1
1
0
0
0
0
0
0
0
VDD_F PWM_en CLOCK_sel
AIL_en
OCLCO0_ OC_mode_
s
s
OR)
condition
x = Don’t care.
s = Output selection with the bits A1A0 as defined in Table 12.
35XS3400
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
DEVICE REGISTER ADDRESSING
The following section describes the possible register
addresses (D[14:10]) and their impact on device operation.
Table 13. Slew Rate Speed Selection
SR1_s (D4)
SR0_s (D3)
Slew Rate Speed
0
0
medium (default)
0
1
low
1
0
high
1
1
Not used
ADDRESS XX000 — STATUS REGISTER
(STATR_S)
The STATR register is used to read the device status and
the various configuration register contents without disrupting
the device operation or the register contents. The register bits
D[4:0] determine the content of the first sixteen bits of SO
data. In addition to the device status, this feature provides the
ability to read the content of the PWMR_s, CONFR0_s,
CONFR1_s, OCR_s, GCR and CALR registers (Refer to the
section entitled Serial Output Communication (Device Status
Return Data) on page 32.
ADDRESS A1A0001— OUTPUT PWM CONTROL
REGISTER (PWMR_S)
The PWMR_s register allows the MCU to control the state
of corresponding output through the SPI. Each output “s” is
independently selected for configuration based on the state
of the D14 : D13 bits (Table 12).
Table 12. Output Selection
A1 (D14)
A0 (D13)
HS Selection
0
0
HS0 (default)
0
1
HS1
1
0
HS2
1
1
HS3
Bit D7 sets the output state. A logic [1] enables the
corresponding output switch and a logic [0] turns it OFF (if IN
input is also pulled down). Bits D6:D0 set the output PWM
duty-cycle to one of 128 levels for PWM_en is set to logic [1],
as shown Table 7.
ADDRESS A1A0010— OUTPUT CONFIGURATION
REGISTER (CONFR0_S)
The CONFR0_s register allows the MCU to configure
corresponding output switching through the SPI. Each output
“s” is independently selected for configuration based on the
state of the D14 : D13 bits (Table 12).
For the selected output, a logic [0] on bit D5 (DIR_DIS_s)
will enable the output for direct control. A logic [1] on bit D5
will disable the output from direct control (in this case, the
output is only controlled by On bit).
D4:D3 bits (SR1_s and SR0_s) are used to select the high
or medium or low speed slew rate for the selected output, the
default value [00] corresponds to the medium speed slew rate
(Table 13).
Incoming message bits D2 : D0 reflect the desired output
that will be delayed of predefined PWM clock rising edges
number, as shown Table 8 (only available for PWM_en bit is
set to logic [1]).
ADDRESS A1A0011 — OUTPUT CONFIGURATION
REGISTER (CONFR1_S)
The CONFR1_s register allows the MCU to configure
corresponding output fault management through the SPI.
Each output “s” is independently selected for configuration
based on the state of the D14 : D13 bits (Table 12).
A logic [1] on bit D6 (RETRY_unlimited_s) disables the
autoretry counter for the selected output, the default value [0]
corresponds to enable auto-retry feature with time limitation.
A logic [1] on bit D5 (RETRY_dis_s) disables the autoretry for the selected output, the default value [0] corresponds
to enable this feature.
A logic [1] on bit D4 (OS_dis_s) disables the output hard
shorted to VPWR protection for the selected output, the
default value [0] corresponds to enable this feature.
A logic [1] on bit D3 (OLON_dis_s) disables the ON output
OpenLoad detection for the selected output, the default value
[0] corresponds to enable this feature (Table 14).
A logic [1] on bit D2 (OLOFF_dis_s) disables the OFF
output OpenLoad detection for the selected output, the
default value [0] corresponds to enable this feature.
A logic [1] on bit D1 (OLLED_en_s) enables the ON output
OpenLoad detection for LEDs for the selected output, the
default value [0] corresponds to ON output OpenLoad
detection is set for bulbs (Table 14).
Table 14. ON OpenLoad Selection
OLON_dis_s (D3)
OLLED_en_s
(D1)
0
0
enable with bulb threshold
(default)
0
1
enable with LED threshold
1
X
disable
ON OpenLoad detection
A logic [1] on bit D0 (CSNS_ratio_s) selects the high ratio
on the CSNS pin for the corresponding output. The default
value [0] is the low ratio (Table 15).
Table 15. Current Sense Ratio Selection
CSNS_high_s (D0)
Current Sense Ratio
35XS3400
30
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 15. Current Sense Ratio Selection
Table 18. Output Steady State Selection
0
CRS0 (default)
0
1
OCLO3
1
CRS1
1
0
OCLO4
1
1
OCLO1
ADDRESS A1A0100 — OUTPUT OVER-CURRENT
REGISTER (OCR)
The OCR_s register allows the MCU to configure
corresponding output over-current protection through the
SPI. Each output “s” is independently selected for
configuration based on the state of the D14 : D13 bits
(Table 12).
D[7:6] bits allow to MCU to programmable bulb cooling
curve and D[5:4] bits inrush curve for selected output, as
shown Table 16 and Table 17.
Table 16. Cooling and Inrush Curve Selection
BC1_s (D7)
BC0_s (D6)
Profile Curves Speed
0
0
medium (default)
0
1
slow
1
0
fast
1
1
medium
Table 17. Inrush Curve Selection
OC1_s (D5)
OC0_s (D4)
Profile Curves Speed
0
0
slow (default)
0
1
fast
1
0
medium
1
1
very slow
Bit D0 (OC_mode_sel) allows to select the over-current
mode, as described Table 19.
Table 19. Over-current Mode Selection
OC_mode_s (D0)
Over-current Mode
0
only inrush current management (default)
1
inrush current and bulb cooling management
ADDRESS 00101 — GLOBAL CONFIGURATION
REGISTER (GCR)
The GCR register allows the MCU to configure the device
through the SPI.
Bit D8 allows the MCU to enable or disable the VDD failure
detector. A logic [1] on VDD_FAIL_en bit allows transitioning
to Fail-safe mode for VDD < VDD(FAIL).
Bit D7 allows the MCU to enable or disable the PWM
module. A logic [1] on PWM_en bit allows control of the
outputs HS[0:3] with PWMR register (the direct input states
are ignored).
Bit D6 (CLOCK_sel) allows to select the clock used as
reference by PWM module, as described in the following
Table 20.
Table 20. PWM Module Selection
PWM_en (D7) CLOCK_sel (D6)
A logic [1] on bit D3 (OCHI_s bit) the OCHI1 level is
replaced by OCHI2 during tOC1, as shown Figure 13.
PWM module
0
X
PWM module disabled
(default)
1
0
PWM module enabled with
external clock from IN0
1
1
PWM module enabled with
IOCH1
internal calibrated clock
IOCH2
Bits D5:D4 allow the MCU to select one of two analog
feedback on CSNS output pin, as shown in Table 21.
IOC1
IOC2
IOC3
IOC4
Table 21. CSNS Reporting Selection
IOCLO4
IOCLO3
IOCLO2
IOCLO1
TEMP_en CSNS_en
(D5)
(D4)
t OC1 t OC3 t
t
OC4 OC5
t OC2
t OC7
t OC6
Time
Figure 13. Over-current profile with OCHI bit set to ‘1’
The wire harness is protected by one of four possible
current levels in steady state, as defined in Table 18.
Table 18. Output Steady State Selection
OCLO1 (D2) OCLO0 (D1)
0
0
CSNS reporting
0
0
CSNS tri-stated (default)
X
1
current recopy of selected output (D3:2]
bits)
1
0
temperature on GND flag
Table 22. Output Current Recopy Selection
CSNS1 (D3)
CSNS0 (D2)
CSNS reporting
Steady State Current
0
0
HS0 (default)
OCLO2 (default)
0
1
HS1
35XS3400
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 22. Output Current Recopy Selection
1
0
HS2
1
1
HS3
The GCR register disables the over-voltage protection
(D0). When this bits is [0], the over-voltage is enabled (default
value).
ADDRESS 00111 — CALIBRATION REGISTER
(CALR)
The CALR register allows the MCU to calibrate internal
clock, as explained in Figure 12.
SERIAL OUTPUT COMMUNICATION (DEVICE
STATUS RETURN DATA)
When the CS pin is pulled low, the output register is
loaded. Meanwhile, the data is clocked out MSB- (OD15-)
first as the new message data is clocked into the SI pin. The
first sixteen bits of data clocking out of the SO, and following
a CS transition, is dependent upon the previously written SPI
word.
Any bits clocked out of the Serial Output (SO) pin after the
first 16 bits will be representative of the initial message bits
clocked into the SI pin since the CS pin first transitioned to a
logic [0]. This feature is useful for daisy-chaining devices as
well as message verification.
A valid message length is determined following a CS
transition of [0] to [1]. If there is a valid message length, the
data is latched into the appropriate registers. A valid
message length is a multiple of 16 bits. At this time, the SO
pin is tri-stated and the fault status register is now able to
accept new fault status information.
SO data will represent information ranging from fault
status to register contents, user selected by writing to the
STATR bits OD4, OD3, OD2, OD1, and OD0. The value of
the previous bits SOA4 and SOA3 will determine which
output the SO information applies to for the registers which
are output specific; viz., Fault, PWMR, CONFR0, CONFR1,
and OCR registers.
Note that the SO data will continue to reflect the
information for each output (depending on the previous
SOA4, SOA3 state) that was selected during the most recent
STATR write until changed with an updated STATR write.
The output status register correctly reflects the status of
the STATR-selected register data at the time that the CS is
pulled to a logic [0] during SPI communication, and/or for the
period of time since the last valid SPI communication, with
the following exception:
• The previous SPI communication was determined to be
invalid. In this case, the status will be reported as
though the invalid SPI communication never occurred.
• The VPWR voltage is below 4.0 V, the status must be
ignored by the MCU.
SERIAL OUTPUT BIT ASSIGNMENT
The 16 bits of serial output data depend on the previous
serial input message, as explained in the following
paragraphs. Table 23, summarizes SO returned data for bits
OD15 : OD0.
• Bit OD15 is the MSB; it reflects the state of the
Watchdog bit from the previously clocked-in message.
• Bits OD14:OD10 reflect the state of the bits
SOA4 : SOA0 from the previously clocked in message.
• Bit OD9 is set to logic [1] in Normal mode (NM).
• The contents of bits OD8 : OD0 depend on bits D4 : D0
from the most recent STATR command SOA4 : SOA0
as explained in the paragraphs following Table 23.
35XS3400
32
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 23. Serial Output Bit Map Description
Previous
STATR
SO Returned Data
S S S S S
OD OD OD OD OD OD OD
O O O O O
OD8 OD7
15 14 13 12 11 10 9
A4 A3 A2 A1 A0
OD6
OD5
OD4
OD2
OD1
OD0
OS_s
OT_s
SC_s
OC_s
PWM3_s
PWM2_s
PWM1_s
PWM0_s
SR0_s
DELAY2_s
STATR
A1 A0 0
_s
0
0
WDI SOA SOA SOA SOA SOA
NM POR
N
4
3
2
1
0
PWMR_
A1 A0 0
s
0
1
WDI SOA SOA SOA SOA SOA
NM
N
4
3
2
1
0
0
CONFR
A1 A0 0
0_s
1
0
WDI SOA SOA SOA SOA SOA
NM
N
4
3
2
1
0
X
X
CONFR
A1 A0 0
1_s
1
1
WDI SOA SOA SOA SOA SOA
NM
N
4
3
2
1
0
X
X
OCR_s A1 A0 1
0
0
WDI SOA SOA SOA SOA SOA
NM
N
4
3
2
1
0
X
BC1_ BC0_s OC1_s OC0_s
s
OCHI_s
OCLO1_s
CSNS1
CSNS0
X
CLOCK_fail
IN2
IN1
UV
OV
OLON_ OLOFF
s
_s
OD3
ON_s PWM6_ PWM5_ PWM4_
s
s
s
X
DIR_dis SR1_s
_s
Retry_ Retry_d OS_dis OLON_dis_s OLOFF_dis_s OLLED_en CSNS_rati
_s
_s
o_s
unlimite is_s
d_s
0
0
1
0
1
VDD_ PWM CLOCK TEMP_ CSNS_
WDI SOA SOA SOA SOA SOA
NM FAIL_ _en
_sel
en
en
N
4
3
2
1
0
en
DIAGR0 0
0
1
1
1
WDI SOA SOA SOA SOA SOA
NM
N
4
3
2
1
0
X
X
X
X
X
DIAGR1 0
1
1
1
1
WDI SOA SOA SOA SOA SOA
NM
N
4
3
2
1
0
X
X
X
X
IN3
DIAGR2 1
0
1
1
1
WDI SOA SOA SOA SOA SOA
NM
N
4
3
2
1
0
X
X
X
X
X
x
X
0
0
0
0
0
GCR
Registe N/ N/ N/ N/ N/
r state A A A A A
after
RST=0
or
VDD(FAI
L) or
VSUPPL
0
0
0
0
0
0
0
DELAY1_s DELAY0_s
OCLO0_s OC_mode
_s
X
OV_dis
CAL_fail
OTW
IN0
WD_en
1
X
X
0
0
0
Y(POR)
conditi
on
s = Output selection with the bits A1A0 as defined in Table 12
PREVIOUS ADDRESS SOA4 : SOA0 = A1A0000
(STATR_S)
The returned data OD8 reports logic [1] in case of previous
Power ON Reset condition (VSUPPLY(POR)). This bit is only
reset by a read operation.
Bits OD7: OD0 reflect the current state of the Fault register
(FLTR) corresponding to the output previously selected with
the bits SOA4:SOA3 = A1A0 (Table 23).
• OC_s: over-current fault detection for a selected output,
• SC_s: severe short-circuit fault detection for a selected
output,
• OS_s: output shorted to VPWR fault detection for a
selected output,
• OLOFF_s: OpenLoad in OFF state fault detection for a
selected output,
• OLON_s: OpenLoad in ON state fault detection
(depending on current level threshold: bulb or LED) for a
selected output,
• OV: over-voltage fault detection,
• UV: under-voltage fault detection
• POR: power on reset detection.
The FS pin reports all faults. For latched faults, this pin is
reset by a new Switch OFF command (toggling fault_control
signal).
PREVIOUS ADDRESS SOA4 : SOA0 = A1A0001
(PWMR_S)
The returned data contains the programmed values in the
PWMR register for the output selected with A1A0.
35XS3400
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
PREVIOUS ADDRESS SOA4 : SOA0 = A1A0010
(CONFR0_S)
The returned data contains the programmed values in the
CONFR0 register for the output selected with A1A0.
PREVIOUS ADDRESS SOA4 : SOA0 = A1A0011
(CONFR1_S)
The returned data contains the programmed values in the
CONFR1 register for the output selected with A1A0.
The OD0 indicates if the watchdog is enabled (set to logic
[1]) or not (set to logic [0]). OD4:OD1 report the output state
in case of Fail-safe state due to watchdog time-out as
explained in the following Table 24.
Table 24. Watchdog Activation Report
WD_en (OD0)
0
disabled
1
enabled
PREVIOUS ADDRESS SOA4 : SOA0 = A1A0100
(OCR_S)
PREVIOUS ADDRESS SOA4 : SOA0 = 10111
(DIAGR2)
The returned data contains the programmed values in the
OCR register for the output selected with A1A0.
The returned data is the product ID. Bits OD2:OD0 are set
to 1XX for Protected Quad 35 m High Side Switches.
PREVIOUS ADDRESS SOA4 : SOA0 = 00101 (GCR)
DEFAULT DEVICE CONFIGURATION
The returned data contains the programmed values in the
GCR register.
The default device configuration is explained below:
• HS output is commanded by corresponding IN input or On
bit through SPI. The medium slew rate is used,
• HS output is fully protected by the severe short-circuit
protection, the under-voltage, and the over-temperature
protection. The auto-retry feature is enabled,
• OpenLoad in ON and OFF state and HS shorted to VPWR
detections are available,
• No current recopy and no analog temperature feedback
active,
• Over-voltage protection is enabled,
• SO reporting fault status from HS0,
• VDD failure detection is disabled.
PREVIOUS ADDRESS SOA4 : SOA0 = 00111
(DIAGR0)
The returned data OD2 reports logic [1] in case of PWM
clock on IN0 pin is out of specified frequency range.
The returned data OD1 reports logic [1] in case of
calibration failure.
The returned data OD0 reports logic [1] in case of overtemperature prewarning (temperature of GND flag is above
TOTWAR).
PREVIOUS ADDRESS SOA4 : SOA0 = 01111
(DIAGR1)
The returned data OD4: OD1 report in real time the state
of the direct input IN[3:0].
35XS3400
34
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
The following figure shows a typical automotive lighting
application (only one vehicle corner) using an external PWM
clock from the main MCU. A redundancy circuitry has been
VPWR
implemented to substitute light control (from MCU to
watchdog) in case of a Fail Safe condition.
It is recommended to locate a 22 nF decoupling capacitor
to the module connector.
VDD
Voltage regulator
100nF
10µF
100nF
VDD
10µF
ignition
switch
VDD
10k
VPWR
VDD
VPWR
VPWR
VDD
10k
100nF
100nF
100nF
VDD
WAKE
I/O
FS
IN0
IN1
IN2
IN3
MCU
SCLK
CS
I/O
SO
SI
10k
10k
10k
10k
A/D
HS0
35XS3400
SCLK
CS
RST
SI
SO
CSNS
FSI
10k
22nF
22nF
LOAD 0
HS1
22nF
LOAD 1
HS2
22nF
LOAD 2
HS3
GND
22nF
LOAD 3
4.7k
10k
VPWR
10k
10k
10k
Watchdog
direct light commands (pedal, comodo,...)
35XS3400
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
PACKAGING
SOLDERING INFORMATION
PACKAGING
SOLDERING INFORMATION
The 35XS3400 is packaged in a surface mount power
package intended to be soldered directly on the printed circuit
board.
The AN2467 Power Quad Flat No-Lead (PQFN) Package
provides guidelines for Printed Circuit Board design and
assembly.
35XS3400
36
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the 98ARL10596D listed below.
Dimensions shown are provided for reference ONLY.
FK SUFFIX
24-PIN PQFN
NONLEADED PACKAGE
98ARL10596D
ISSUE D
35XS3400
Analog Integrated Circuit Device Data
Freescale Semiconductor
37
PACKAGING
PACKAGE DIMENSIONS
FK SUFFIX
24-PIN PQFN
NONLEADED PACKAGE
98ARL10596D
ISSUE D
35XS3400
38
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
FK SUFFIX
24-PIN PQFN
NONLEADED PACKAGE
98ARL10596D
ISSUE D
35XS3400
Analog Integrated Circuit Device Data
Freescale Semiconductor
39
PACKAGING
PACKAGE DIMENSIONS
FK SUFFIX
24-PIN PQFN
NONLEADED PACKAGE
98ARL10596D
ISSUE D
35XS3400
40
Analog Integrated Circuit Device Data
Freescale Semiconductor
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
ADDITIONAL DOCUMENTATION
35XS3400
THERMAL ADDENDUM (REV 2.0)
Introduction
This thermal addendum is provided as a supplement to the 35XS3400
technical data sheet. The addendum provides thermal performance
information that may be critical in the design and development of system
applications. All electrical, application and packaging information is
provided in the data sheet.
24-PIN
PQFN
Package and Thermal Considerations
This 35XS3400 is a dual die package. There are two heat sources in the
package independently heating with P1 and P2. This results in two junction
temperatures, TJ1 and TJ2, and a thermal resistance matrix with RJAmn.
For m, n = 1, RJA11 is the thermal resistance from Junction 1 to the
reference temperature while only heat source 1 is heating with P1.
For m = 1, n = 2, RJA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P2. This applies
to RJ21 and RJ22, respectively.
TJ1
TJ2
=
RJA11 RJA12
RJA21 RJA22
.
P1
P2
FK SUFFIX (PB-FREE)
98ARL10596D
24-PIN PQFN (12 x 12)
Note For package dimensions, refer to
98ARL10596D.
The stated values are solely for a thermal performance comparison of
one package to another in a standardized environment. This methodology is not meant to and will not predict the performance
of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to
the standards listed below.
Standards
Table 25. Thermal Performance Comparison
Thermal
Resistance
1 = Power Chip, 2 = Logic Chip [C/W]
m = 1,
n=1
m = 1, n = 2
m = 2, n = 1
m = 2,
n=2
RJAmn (1)(2)
27.35
18.40
35.25
RJBmn (2)(3)
14.53
6.64
23.69
RJAmn (1)(4)
47.63
37.21
53.61
RJCmn (5)
1.48
0.00
0.95
Notes:
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
0.2 mm
0.2 mm
0.5 mm dia.
Figure 14. Detail of Copper Traces Under Device with
Thermal Vias
35XS3400
Analog Integrated Circuit Device Data
Freescale Semiconductor
41
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
76.2mm
114.3mm
114.3mm
76.2mm
WAKE
FS
IN3
IN2
NC
IN1
IN0
CSNS
9
8
7
6
5
4
3
2
1
SO
16
GND
17
HS3
18
SCLK
Transparent Top View
SI
13 12 11 10
VDD
RST
Figure 16. 2s2p JEDEC Thermal Test Board
(Red - Top Layer, Yellow - Two Buried Layers)
CS
Figure 15. 1s JEDEC Thermal Test Board Layout
14
GND
24
FSI
23
GND
22
HS2
15
VPWR
MC35XS3400 Pin Connections
24 Pin PQFN (12 x 12)
0.9mm Pitch
12.0mm x 12.0mm Body
19
20
21
HS1
NC
HS0
Figure 17. Pin Connections
35XS3400
42
Analog Integrated Circuit Device Data
Freescale Semiconductor
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
Device on Thermal Test Board
Material:
Single layer printed circuit board
FR4, 1.6 mm thickness
Cu traces, 0.07 mm thickness
Cu buried traces thickness
0.035 mm
Outline:
76.2 mm x 114.3 mm board area,
including edge connector for thermal
testing, 74 mm x 74 mm buried
layers area
Area A:
Cu heat-spreading areas on board
surface
Ambient Conditions:
Natural convection, still air
Table 26. Thermal Resistance Performance
Thermal
Resistance
RJAmn
Area A
(mm2)
1 = Power Chip, 2 = Logic Chip (C/W)
m = 1,
n=1
m = 1, n = 2
m = 2, n = 1
m = 2,
n=2
0
47.63
37.21
53.61
150
42.82
33.14
51.06
300
41.23
31.84
50.36
450
40.07
30.90
49.26
600
39.24
30.14
48.57
RJAis the thermal resistance between die junction and
ambient air.
This device is a dual die package. Index m indicates the
die that is heated. Index n refers to the number of the die
where the junction temperature is sensed.
Thermal resistance [K/W]
65.00
60.00
55.00
50.00
45.00
40.00
35.00
30.00
25.00
0
100
200
300
400
500
600
Heat spreading area [sqmm]
RJA11
RJA12=RJA21
RJA22
Figure 18. Steady State Thermal Resistance in Dependence on Heat Spreading Area;
1s JEDEC Thermal Test Board with Spreading Areas
35XS3400
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
Thermal Resistance [K/W]
100
10
1
0.1
0.000001
0.0001
0.01
1
100
10000
Time[s]
RJA11
RJA12
RJA22
Figure 19. Transient Thermal 1W Step Response; Device on
1s JEDEC Standard Thermal Test Board with Heat Spreading Areas 600 Sq. mm
Thermal resistance [K/W]
100
10
1
0.1
0.000001
0.0001
0.01
1
100
10000
Time [s]
RJA11
RJA12
RJA22
Figure 20. Transient Thermal 1W Step Response;
Device on 2s2p JEDEC Standard Thermal Test Board
35XS3400
44
Analog Integrated Circuit Device Data
Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION DATE
DESCRIPTION OF CHANGES
4.0
9/2008
•
Initial release
5.0
10/2008
•
•
Changed Maximum rating for Output Source-to-Drain ON Resistance in Static Electrical Characteristics
Table on page 7.
Added explanation for recovering to Sleep Mode on page 22.
6.0
7/2009
•
Added MC35XS3400DPNA part number. The “D” version has different soldering limits.
7.0
10/2009
•
•
Corrected minor formatting
Separated definitions for the 35XS3400C and 35XS3400D in the Static and Dynamic Tables
8.0
1/2011
•
Table 23, Serial Output Bit Map Description: (DIAGR2 register): OD1=X (instead of 0) and OD0=X
(instead of 0)
Previous Address SOA4 : SOA0 = 10111 (diagr2) on page 34: bits OD2:OD0 are set to 1XX (instead of
100) for protected.
•
9.0
05/2012
•
•
•
10
8/2013
•
Updated part number MC35XS3400DPNA to MC35XS3400DHFK and MC35XS3400CPNA to
MC35XS3400CHFK.
Updated the pin soldering temperature limit from 10 seconds to 40 seconds (Note (2) and (9) ).
Updated Freescale form and style.
Corrected Address A1A0011 — output CONFIGURATION REGISTER (CONFR1_s). Changed from “the
default value [0] corresponds to enable auto-retry feature without time limitation” to “the default value [0]
corresponds to enable auto-retry feature with time limitation”.
35XS3400
Analog Integrated Circuit Device Data
Freescale Semiconductor
45
How to Reach Us:
Information in this document is provided solely to enable system and software implementers to use Freescale products.
Home Page:
freescale.com
There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based
Web Support:
freescale.com/support
Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no
on the information in this document.
warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by
customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others.
Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address:
freescale.com/SalesTermsandConditions.
Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm.
Off.SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of
their respective owners.
© 2013 Freescale Semiconductor, Inc.
Document Number: MC35XS3400
Rev. 10.0
8/2013