MC10XS3535, Smart Front Corner Light Switch (Triple 10mOhm and Dual 35mOhm) - Data Sheet

Freescale Semiconductor
Technical Data
Document Number: MC10XS3535
Rev. 10.0, 8/2013
Smart Front Corner Light Switch
(Triple 10 mOhm and Dual
35 mOhm)
10XS3535
The 10XS3535 is designed for low voltage automotive and industrial
lighting applications. Its five low RDS(ON) MOSFETs (three 10 m, two
35 m) can control the high sides of five separate resistive loads
(bulbs, Xenon-HID modules and LEDs). This device is powered by
SMARTMOS technology.
Programming, control and diagnostics are accomplished using a
16-bit SPI interface (3.3 V or 5.0 V). Each output has its own pulsewidth modulation (PWM) control via the SPI. The 10XS3535 has highly
sophisticated failure mode handling to provide high availability of the
outputs. Its multiphase control and output edge shaping improves
electromagnetic compatibility (EMC) behavior.
The 10XS3535 is packaged in a power-enhanced 12 x 12 mm
nonleaded PQFN package with exposed tabs.
HIGH SIDE SWITCH
Bottom View
FK SUFFIX (Pb FREE)
98ART10511D
24-PIN PQFN
Features
• Triple 10 m and dual 35 m high side switches
• 16-bit SPI communication interface with daisy chain capability
• Current sense output with SPI-programmable multiplex switch
and board temperature feedback
• Digital diagnosis feature
• PWM module with multiphase feature including prescaler
• LEDs control including accurate current sensing and low dutycycle capability
• Fully protected switches
• Over-current shutdown detection
• Power net and reverse polarity protection
• Low-power mode
• Fail mode functions including autorestart feature
• External smart power switch control including current recopy
12V
5.0V
ORDERING INFORMATION
Device
(For Tape and Reel,
add R2 Suffix)
MCU
-40 to 125 °C
24 PQFN
* Recommended for all new designs
VBAT
CP
LIMP
OUT1
FLASHER
OUT2
IGN
RST
OUT3
CLOCK
OUT4
CS
FOG
OUT5
S0
FETIN
SI
SCLK
FETOUT
CSNS GND
Smart
Switch
Figure 1. 10XS3535 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2010-2013. All rights reserved.
Package
* MC10XS3535JHFK
10XS3535
Watchdog
Temperature
Range (TA)
MC10XS3535HFK
MC10XS3535DHFK
12V
VCC
FK SUFFIX (Pb FREE)
98ASA00426D
24-PIN PQFN
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. MC10XS3535 Device Variations
Part Number
MC10XS3535HFK
MC10XS3535DHFK
MC10XS3535JHFK
Package
24 PQFN
98ART10511D
24 PQFN
98ASA00426D
Temp.
Comment
Initial release
-40 to 125 °C
D version is more robust against VBAT interrupt
D version with enhancement MSL3 performance
MC10XS3535
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VCC
VBAT
Vcc failure
detection
RUP
Internal
Regulator
CP
Charge
Pump
OV/UV/POR
detections
CS
SO
SI
SCLK
Gate Drive
drain/gate clamp
Logic
LED Control
RDWN
OUT1
Over-current
Detection
CLOCK
LIMP
FOG
Open Load
Detection
FLASHER
IGN
RST
Over-temperature
Detection
OUT1
OUT2
OUT2
RDWN
OUT3
OUT3
Over-temperature
Prewarning
OUT4
OUT4
OUT5
OUT5
Selectable Output Current
Recopy (Analog MUX)
CSNS
Temperature
Feedback
FETIN
Current Recopy
Synchronization
VCC
Driver for External
MOSFET
FETOUT
GND
Figure 2. 10XS3535 Simplified Internal Block Diagram
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
SCLK
CS
FOG
LIMP
CLOCK
FLASHER
RST
IGN
FETIN
8
7
6
5
4
3
2
1
CP
16
GND
17
OUT5
18
VCC
9
SO
13 12 11 10
FETOUT
SI
PIN CONNECTIONS
14
GND
24
CSNS
23
GND
22
OUT1
15
VBAT
19
20
21
OUT4
OUT3
OUT2
Figure 3. 10XS3535 Pin Connections (Transparent Top View Of Package)
Table 2. 10XS3535 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on Page 20.
Pin
Number
Pin Name
Pin Function
Formal Name
1
FETIN
Input
External FET Input
2
IGN
Input
Ignition Input
(Active High)
This input wakes the device. It also controls the Outputs 1 and 2 in case of Fail
mode activation. This pin has a passive internal pull-down.
3
RST
Input
Reset
This input wakes the device. It is also used to initialize the device configuration
and fault registers through SPI. This digital pin has a passive internal pull-down.
4
FLASHER
Input
Flasher Input
(Active High)
5
CLOCK
Input/Output
Clock Input
6
LIMP
Input
Limp Home Input
(Active High)
The Fail mode can be activated by this digital input. This pin has a passive
internal pull-down.
7
FOG
Input
FOG Input (Active
high)
This input wakes the device. This pin has a passive internal pull-down.
8
CS
Input
Chip Select
(Active Low)
When this digital signal is high, SPI signals are ignored. Asserting this pin low
starts a SPI transaction. The transaction is signaled as completed when this
signal returns high. This pin has a passive internal pull-up resistance.
9
SCLK
Input
SPI Clock Input
This digital input pin is connected to the master microcontroller providing the
required bit shift clock for SPI communication. This pin has a passive internal
pull-down resistance.
Definition
This pin is the current sense recopy of the external SMART MOSFET.
This input wakes the device. This pin has a passive internal pull-down.
This pin state depends on RST logic level.
As long as RST input pin is set to logic [0], this pin is pulled up in order to report
wake event. Otherwise, the PWM frequency and timing are generated from this
digital clock input by the PWM module.
This pin has a passive internal pull-down.
MC10XS3535
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
Table 2. 10XS3535 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on Page 20.
Pin
Number
Pin Name
Pin Function
Formal Name
10
SI
Input
Master-Out SlaveIn
11
VCC
Power
Logic Supply
12
SO
Output
Master-In SlaveOut
13
FETOUT
Output
External FET Gate
Definition
This data input is sampled on the positive edge of the SCLK. This pin has a
passive internal pull-down resistance.
SPI Logic power supply.
SPI data is sent to the MCU by this pin. This data output changes on the
negative edge of SCLK and when CS is high, this pin is high-impedance.
This pin controls an external SMART MOSFET by logic level. This output is also
called OUT6.
If OUT6 is not used in the application, this output pin is set to logic high when
the current sense output becomes valid when CSNS sync SPI bit is set to logic
[1].
14,17,23
GND
Ground
Ground
15
VBAT
Power
Battery Input
Power supply pin.
16
CP
Output
Charge Pump
This pin is the connection for an external tank capacitor (for internal use only).
22
18
OUT1
OUT5
Output
Output 1
Output 5
Protected 35 m high side power output to the load.
21
20
19
OUT2
OUT3
OUT4
Output
Output 2
Output 3
Output 4
Protected 10 mhigh side power output to the load.
24
CSNS
Output
Current Sense
Output
This pin is the ground for the logic and analog circuitry of the device.(1)
This pin is used to output a current proportional to OUT1:OUT5, FET in current,
and it is used externally to generate a ground-referenced voltage for the
microcontroller to monitor output current. Moreover, this pin can report a voltage
proportional to the temperature on the GND flag.
OUT1:OUT5, FET in current sensing and Temperature feedback choice is SPI
programmable.
Notes
1. The pins 14, 17 and 23 must be shorted on the board.
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
Over-voltage Test Range (all OUT[1:5] ON with nominal DC current)
VBAT
V
Maximum Operating Voltage
28
Load Dump (400 ms) @ 25 °C
40
Reverse Polarity Voltage Range (all OUT[1:5] ON with nominal DC current)
VBAT
2.0 Min @ 25 °C
V
- 18
VCC Supply Voltage
VCC
OUT[1:5] Voltage
VOUT
-0.3 to 5.5
V
Positive
40
Negative (ground disconnected)
-16
Digital Current in Clamping Mode (SI, SCLK, CS, RST, IGN, FLASHER, LIMP
and FOG)
FETIN Input Current
IIN
IFETIN
V
±1.0
mA
+10
mA
-1.0
SO, FETOUT, CLOCK and CSNS Outputs Voltage
VSO
- 0.3 to VCC + 0.3
E1,5
30
E2,3,4
100
Outputs clamp energy using single pulse method (L = 2 mH; R = 0 ;
VBAT = 14 V @150°C initial)
OUT[1,5]
OUT[2:4]
ESD Voltage(2)
V
mJ
VESD
V
Human Body Model (HBM)
±2000
Human Body Model (HBM) OUT [1:5], VPWR, and GND
±8000
Charge Device Model (CDM)
Corner Pins (1, 13, 19, 21)
All Other Pins (2-12, 14-18, 20, 22-24)
750
500
Notes
2. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ) and the Charge Device
Model.
MC10XS3535
6
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
TA
- 40 to 125
TJ
- 40 to 150
TPPRT
Note 4
°C
TSTG
- 55 to 150
C
RJC
1.0
K/W
THERMAL RATINGS
Operating Temperature
°C
Ambient
Junction
Peak Package Reflow Temperature During Reflow
Storage Temperature
(3), (4)
THERMAL RESISTANCE
Thermal Resistance, Junction to Case(5)
Notes
3. Pin soldering temperature limit is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
4. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
5. Typical value guaranteed per design.
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions 3.0 V  VCC  5.5 V, 7.0 V  VBAT  2 0V, - 40 C  TA  125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
7.0
6.0
–
–
20.0
28.0
Unit
POWER INPUTS (VBAT, VCC)
Battery Supply Voltage Range
VBAT
Full Performance & Short Circuit
Extended Voltage Range(6)
V
Battery Supply Under-voltage (UV flag is set ON)
VBATUV
5.0
5.5
6.0
V
Battery Supply Over-voltage (OV flag is set ON)
VBATOV
27.5
30
32.5
V
VBATCLAMP
40
–
48
V
Battery Voltage
Clamp(9)
Battery Supply Power on Reset(10)
If VBAT < 5.5 V, VBAT = VCC
If VBAT < 5.5 V, VCC = 0
V
VBATPOR1
VBATPOR2
2.0
2.0
–
–
3.0
4.0
IBATSLEEP1
IBATSLEEP2
IBAT
–
–
–
0.5
0.5
10.0
5.0
5.0
20.0
A
A
mA
VCC
3.0
–
5.5
V
VCCUV
2.2
2.5
2.8
V
–
0.2
5.0
–
–
–
–
2.6
5.0
VBAT Supply Current @ 25 °C and VBAT = 12 V and VCC = 5 V
Sleep State Current, Outputs Opened
Sleep State Current, Outputs Grounded
Normal Mode, IGN = 5 V, RST = 5 V, Outputs Open
Digital Supply Voltage Range, Full Performance
Digital Supply Undervoltage (VCC Failure)
Sleep Current Consumption on VCC @ 25 °C and VBAT = 12 V
Supply Current Consumption on VCC and VBAT = 12 V
A
ICCSLEEP
Output OFF
ICC
No SPI
3.0 MHz SPI Communication
mA
LOGIC INPUT/OUTPUT (IGN, CS, CSNS, SI, SCLK, CLOCK, SO, FLASHER, RST, LIMP, FOG)
Input High Logic Level(7)
VIH
2.0
–
–
V
Input Low Logic Level(7)
VIL
–
–
0.8
V
VIGNTH
1.0
–
2.2
V
7.5
–
13
- 2.0
–
-0.3
RUP
100
200
400
k
RDWN
100
200
500
k
0.8
0.95
–
VCC
Voltage Threshold for wake-up (IGN, FLASHER, FOG and RST)
Input Clamp Voltage (IGN, FLASHER, LIMP, FOG, CS, SCLK, SI, RST)
VCL_POS
I = 1.0 mA
Input Forward Voltage (IGN, FLASHER, LIMP, FOG, CS, SCLK, SI, RST)
VCL_NEG
I = -1.0 mA
Input Passive Pull-up Resistance on CS input(8)
Input Passive Pull-down Resistance on SI, SCLK, FLASHER, IGN, FOG,
CLOCK, LIMP and RST pins(8)
SO High-state Output Voltage
VSOL
IOL = -1.6 mA
CLOCK Output Voltage reporting wake-up event (ICLOCK = 1.0 mA)
Notes
6.
7.
8.
9.
10.
V
VSOH
IOH = 1.0 mA
SO Low-state Output Voltage
V
VCLOCKH
V
–
0.2
0.4
0.8
0.95
–
Vcc
In extended mode, the functionality is guaranteed but not the electrical parameters.
Valid for RST, SI, SCLK, CS, CLOCK, IGN, FLASHER, FOG, and LIMP pins.
Valid for the following input voltage range: -0.3 V to VCC + 0.3 V.
Outputs shorted to ground, IOUT = + 500 mA and IOUT =OCHI (guaranteed by design).
Please refer to Loss of Supply Lines section for more details.
MC10XS3535
8
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.0 V  VCC  5.5 V, 7.0 V  VBAT  2 0V, - 40 C  TA  125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
- 5.0
0
1.0
VCC = 5.0 V, CSNS = 5.5 V
- 10
0
1.0
VCC = 5.0 V, CSNS = 3.0 V
- 1.0
0
1.0
5.0
6.0
7.0
Sleep mode, Outputs Grounded
–
0
2.0
Normal mode, Outputs Grounded
–
20
25
- 22.0
–
-16.0
LOGIC INPUT/OUTPUT (IGN, CS, CSNS) (CONTINUED)
CSNS Tri-state Leakage Current
Current Sense Output Clamp Voltage
A
ICSNSLEAK
VCC = 5.5 V, CSNS = 4.5 V
VCSNS
CSNS open and IOUT[1:5] = IFSR
V
OUTPUTS (OUT 1-5)
Output Leakage Current in OFF state
Output Negative Clamp Voltage
VOUT
IOUT = - 500 mA, Outputs OFF
Current Sense Output Precision(11)
A
IOUTLEAK
V
ICS / ICS
%
Full-Scale Range (FSR) for LED Control bit = 0
0.75 FSR
-14
–
14
0.50 FSR
-15
–
15
0.25 FSR
-17
–
17
0.10 FSR
-22
–
22
0.187 FSR = 0.75 FSRLED
-13
–
13
0.125 FSR = 0.50 FSRLED
-13
–
13
0.062 FSR = 0.25 FSRLED
-20
–
20
0.025 FSR = 0.10 FSRLED
-30
–
30
Full-Scale Range for LED Control bit = 1 (OUT1 and OUT5 only)
Notes
11. 10 V < VBAT < 16 V. ICS / ICS = (measured ICS - targeted ICS)/ targeted ICS with targeted ICS = 5 mA
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.0 V  VCC  5.5 V, 7.0 V  VBAT  2 0V, - 40 C  TA  125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Min
Typ
Max
Unit
Current Sense Output Precision with one calibration point (50% FSR,
VBAT = 13.5 at 25 °C(13)
-6.0
–
6.0
%
Current Sense Output Precision with one calibration point (50% FSRLED,
VBAT = 13.5 V at 25 °C(13)
-6.0
–
6.0
%
–
±280
± 400
ppm/°C
250
–
–
65
–
–
Temperature Drift of Current Sense Output(12)
Symbol
ICS /T
VBAT = 13.5 V, IOUT1,5 = 2.8 A, IOUT2-4 = 5.5 A, reference taken at
TA=25 °C
Minimum Output Current Reported in CSNS for OUT[2-4](15)
I10MIN(CSNS)
10 V VBAT 16 V
Minimum Output Current Reported in CSNS for OUT[1,5](15)
mA
I35MIN(CSNS)
10 V VBAT 16 V
mA
Minimum Output Current Reported in CSNS for OUT[2-4] in LED Mode(15) I10MIN(CSNS)LED
10 V VBAT 16 V
140
–
–
Minimum Output Current Reported in CSNS for OUT[1,5] in LED Mode(15) I35MIN(CSNS)LED
10 V VBAT 16 V
40
–
–
Over-temperature Shutdown
Thermal Prewarning(14)
Output Voltage Threshold
mA
mA
TOTS
155
175
195
°C
TOTSWARN
110
125
140
°C
VOUT_TH
0.475
0.5
0.525
VBAT
Notes
12. Based on statistical data. Not production tested. ICS /T=[(measured ICS at T1 - measured ICS at T2) / measured ICS at room] / (T1 -T2).
13.
14.
15.
Based on statistical analysis covering 99.74% of parts, except 10% of FSR. Please refer to Current Sense section for more details.
Parameter guaranteed by design; however, it is not production tested.
Output current value computed after leakage current removal (open load condition)
MC10XS3535
10
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.0 V  VCC  5.5 V, 7.0 V  VBAT  2 0V, - 40 C  TA  125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
VBAT = 13.5 V
–
–
35
VBAT = 7.0 V
–
–
55
Unit
PARKING LIGHT OUT1
Output Drain-to-Source ON Resistance (IOUT = 2.8 A, TA = 25 °C)
Output Drain-to-Source ON Resistance (IOUT = 2.8 A, VBAT = 13.5 V,
RDS(ON)25
RDS(ON)150
(14)
TA = 150 °C)
Output Drain-to-Source ON Resistance (IOUT = 1.5 A, TA = 25 °C) for LED
Control = 1
m
m
–
–
59.5
–
–
70
–
–
110
–
–
119
–
–
70
RDS(ON)25_LED
VBAT = 13.5 V
m
VBAT = 7.0 V
Output Drain-to-Source ON Resistance (IOUT = 1.5 A, VBAT = 13.5 V,
TA = 150 °C) for LED Control =
RDS(ON)150_LED
1(14)
Reverse Output ON Resistance (IOUT = -2.8 A, TA = 25 C)(16)
RSD(ON)
VBAT = -12 V
High Over-current Shutdown Threshold 1
m
IOCHI1
m
28.0
35.0
43.5
VBAT = 16 V, TA = -40 °C
30.2
36.0
41.8
VBAT = 16 V, TA = 25 °C
29.4
35.0
40.6
VBAT = 16 V, TA = 125 °C
28.3
33.8
39.3
A
Notes
16. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VBAT.
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.0 V  VCC  5.5 V, 7.0 V  VBAT  2 0V, - 40 C  TA  125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
High Over-current Shutdown Threshold 2
IOCHI2
12.3
15.4
18.5
A
Low Over-current Shutdown Threshold
IOCLO
5.7
7.2
8.9
A
IOL
0.05
0.2
0.5
PARKING LIGHT OUT1 (CONTINUED)
Open Load-current Threshold in ON State(17)
Open Load-current Threshold in ON State with LED(18)
IOLLED
VOUT = VBAT - 0.8 V
A
mA
4.0
10.0
20.0
–
5.7
–
ICS FSR_LED
–
1.6
–
A
RSC1(OUT1)
350
–
–
m
VBAT = 13.5 V
–
–
10
VBAT = 7.0 V
–
–
15
Current Sense Full-Scale Range
(19)
Current Sense Full-Scale Range
(19)
ICS FSR
depending on LED Control = 1
Severe short-circuit impedance range(20)
A
LOW BEAM OUT2
Output Drain-to-Source ON Resistance (IOUT = 5.5 A, TA = 25 °C)
RDS(ON)
Output Drain-to-Source ON Resistance (IOUT = 5.5 A, VBAT = 13.5 V,
m
RDS(ON)
(20)
m
–
–
17.0
–
–
20
63.2
79.0
94.8
67.2
80.0
92.8
VBAT = 16 V, TA = 25 C
66.3
79.0
91.7
VBAT = 16 V, TA = 125 C
62.5
74.5
86.5
26.2
32.8
39.4
TA = 150 °C)
Reverse Source-to-Drain ON Resistance (IOUT = -5.5 A, TA = 25 C)
(21)
RSD(ON)
VBAT = -12 V
High Over-current Shutdown Threshold 1
IOCHI1
VBAT = 16 V, TA = -40 C
High Over-current Shutdown Threshold 2
IOCHI2
Low Over-current Shutdown Threshold
IOCLO
m
17.6
22.0
26.4
Optional H7 Bulb
12.1
15.2
18.3
0.1
0.4
1.0
4.0
10.0
20.0
–
21.9
–
–
12.5
–
100
–
–
Open Load Current Threshold in ON State with LED
IOL
(23)
IOLLED
VOL = VBAT - 0.8 V
Current Sense Full-scale Range(24)
Optional H7 Bulb
Severe short-circuit impedance
range(20)
RSC1(OUT2)
A
mA
ICS FSR
Optional Xenon Bulb
A
A
Optional Xenon Bulb
Open Load Current Threshold in ON State(22)
A
A
m
Notes
17. OLLED1, bit D0 in SI data is set to [0].
18. OLLED1, bit D0 in SI data is set to [1].
19. For typical value of ICS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is no more guaranteed.
20.
21.
Parameter guaranteed by design; however, it is not production tested.
Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VBAT.
22.
23.
24.
OLLED2, bit D1 in SI data is set to [0].
OLLED2, bit D1 in SI data is set to [1].
For typical value of ICS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is no more guaranteed
MC10XS3535
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.0 V  VCC  5.5 V, 7.0 V  VBAT  2 0V, - 40 C  TA  125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
VBAT = 13.5 V
–
–
10
VBAT = 7.0 V
–
–
15
Unit
HIGH BEAM OUT3
Output Drain-to-Source ON Resistance (IOUT = 5.5 A, TA = 25 °C)
Output Drain-to-Source ON Resistance (IOUT = 5.5 A, VBAT = 13.5 V
RDS(ON)25
m
RDS(ON)150
m
–
TA = 150 °C)(25)
Reverse Source-to-Drain ON Resistance (IOUT = -5.5 A, TA = 25 C)(26)
–
17.0
RSD(ON)25
VBAT = -12 V
m
–
–
20
65.6
82.0
98.4
VBAT = 16 V, TA = -40 C
70.1
83.5
96.9
VBAT = 16 V, TA = 25 C
68.8
82.0
95.2
VBAT = 16 V, TA = 125 C
65.5
78.0
90.5
IOCHI2
27.5
34.4
41.3
A
IOCLO
12.5
15.7
18.9
A
IOL
0.1
0.4
1.0
A
4.0
10.0
20.0
ICS FSR
–
12.7
–
A
RSC1(OUT3)
100
–
–
m
High Over-current Shutdown Threshold 1
IOCHI1
High Over-current Shutdown Threshold 2
Low Over-current Shutdown Threshold
Open Load Current Threshold in ON State
(27)
Open Load Current Threshold in ON State with LED(28)
IOLLED
VOL = VBAT - 0.8 V
Current Sense Full-scale Range(29)
Severe short-circuit impedance
range(25)
A
mA
Notes
25. Parameter guaranteed by design; however, it is not production tested.
26. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VBAT.
27.
28.
29.
OLLED3, bit D2 in SI data is set to [0].
OLLED3, bit D2 in SI data is set to [1].
For typical value of ICS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is no more guaranteed.
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.0 V  VCC  5.5 V, 7.0 V  VBAT  2 0V, - 40 C  TA  125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
VBAT = 13.5V
–
–
10
VBAT = 7.0V
–
–
15
Unit
FOG LIGHT OUT4
Output Drain-to-Source ON Resistance (IOUT = 5.5 A, TA = 25 °C)
RDS(ON)25
Output Drain-to-Source ON Resistance (IOUT = 5.5 A, VBAT = 13.5 V,
RDS(ON)150
(30)
TA = 150 °C)
Reverse Source-to-Drain ON Resistance (IOUT = -5.5 A, TA = 25 C)
(31)
m
–
–
17.0
–
–
20
RSD(ON)25
VBAT = -12 V
High Over-current Shutdown Threshold 1
m
IOCHI1
m
63.2
79.0
94.8
VBAT = 16 V, TA = -40 C
67.2
80.0
92.8
VBAT = 16 V, TA = 25 C
66.3
79.0
91.7
VBAT = 16 V, TA = 125 C
62.5
74.5
86.5
IOCHI2
26.2
32.8
39.4
A
IOCLO
12.1
15.2
18.3
A
IOL
0.1
0.4
1.0
A
4.0
10.0
20.0
ICS FSR
–
12.5
–
A
RSC1(OUT4)
100
–
–
m
VBAT = 13.5 V
–
–
35
VBAT = 7.0 V
–
–
55
High Over-current Shutdown Threshold 2
Low Over-current Shutdown Threshold
Open Load Current Threshold in ON State
(32)
Open Load Current Threshold in ON State with LED(33)
IOLLED
VOL = VBAT - 0.8 V
Current Sense Full-scale Range(34)
Severe short-circuit impedance range(30)
A
mA
FLASHER OUT5
Output Drain-to-Source ON Resistance (IOUT = 2.8 A, TA = 25 °C)
Output Drain-to-Source ON Resistance (IOUT = 2.8 A, VBAT = 13.5 V,
RDS(ON)25
RDS(ON)150
TA = 150 °C)(35)
Output Drain-to-Source ON Resistance (IOUT = 1.5 A, TA = 25 °C) for LED
Control = 1
m
m
–
–
59.5
–
–
70
–
–
110
–
–
119
RDS(ON)25_LED
VBAT = 13.5 V
m
VBAT = 7.0 V
Output Drain-to-Source ON Resistance (IOUT = 1.5 A, VBAT = 13.5 V,
TA = 150 °C) for LED Control =
Reverse Source-to-Drain ON Resistance (IOUT = -2.8 A, TJ = 25 C)(36)
VBAT = -12 V
RDS(ON)150_LED
1(35)
m
RSD(ON)25
m
–
–
70
Notes
30. Parameter guaranteed by design; however, it is not production tested.
31. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VBAT.
32.
33.
34.
OLLED4, bit D3 in SI data is set to [0].
OLLED4, bit D3 in SI data is set to [1].
For typical value of ICS FSR, ICSNS = 5.0mA. If the range is exceeded, no current clamp and the precision is no more guaranteed.
MC10XS3535
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.0 V  VCC  5.5 V, 7.0 V  VBAT  2 0V, - 40 C  TA  125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
IOCHI1
A
FLASHER OUT5 (CONTINUED)
High Over-current Shutdown Threshold 1
28.0
35.0
43.5
VBAT = 16 V, TA = -40 C
30.2
36.0
41.8
VBAT = 16 V, TA = 25 C
29.4
35.0
40.6
VBAT = 16 V, TA = 125 C
28.3
33.8
39.3
High Over-current Shutdown Threshold 2
IOCHI2
12.3
15.4
18.5
A
Low Over-current Shutdown Threshold
IOCLO
5.7
7.2
8.9
A
IOL
0.05
0.2
0.5
A
4.0
10.0
20.0
–
5.7
–
ICS FSR_LED
–
1.6
–
A
RSC1(OUT5)
350
–
–
m
FETOUT Output High Level @ I = 1.0 mA
VH MAX
0.8
–
–
VCC
FETOUT Output Low Level @ I = -1.0 mA
VH MIN
–
0.2
0.4
V
FETIN Input Full Scale Range Current
IFET IN
–
5.0
–
mA
FETIN Input Clamp Voltage
VCLIN
5.3
–
13
Open Load Current Threshold in ON State(38)
Open Load Current Threshold in ON State with LED
IOLLED
(38)
VOL = VBAT - 0.8 V
ICS FSR
Current Sense Full-Scale Range(39)
Current Sense Full-Scale
Range(19)
depending on LED Control = 1
Severe short-circuit impedance range
(35)
mA
A
SPARE FETOUT / FETIN
IFET IN = 5mA, CSNS open
Drop Voltage between FETIN and CSNS for MUX[2:0]=110
V
VDRIN
IFET IN = 5 mA, 5.5 V > CSNS > 0.0 V
V
0.0
FETIN Leakage Current when external current switch sense is enabled
–
0.4
A
IFETINLEAK
4.5 V > VFET IN > 0 V, 5.5 V > VCC > 4.5 V, CSNS open
- 1.0
–
5.0
3.0 V > VFET IN > 0 V, 4.5 V > VCC > 0, CSNS open
- 1.0
–
1.0
TEMPERATURE OF GND FLAG
TFEED_RANGE
Analog Temperature Feedback Range
Analog Temperature Feedback at TA = 25 °C with 5.0 k > RCSNS > 500 
(35)
Analog Temperature Feedback Derating with 5.0 k > RCSNS > 500 
Analog Temperature Feedback Precision(35)
Analog Temperature Feedback Precision with calibration point at 25 °C
(35)
-40
150
°C
VT_FEED
920
1025
1140
mV
VDT_FEED
10.9
11.3
11.7
mV/°C
VDT_ACC
-15
–
15
°C
VDT_ACC_CAL
-5.0
–
5.0
°C
Notes
35. Parameter guaranteed by design; however, it is not production tested.
36. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VBAT.
37.
38.
39.
OLLED5, bit D4 in SI data is set to [0].
OLLED5, bit D4 in SI data is set to [1].
For typical value of ICS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is no more guaranteed.
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.0V  VCC  5.5V, 7.0V  VBAT  20V, - 40C  TA  125C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
SR bit = 0
–
90
150
SR bit = 1
–
45
75
Unit
POWER OUTPUTS TIMING (OUT1 TO OUT5)
Current Sense Valid Time on resistive load only(40)
s
t CSNS(VAL)
s
t CSNS(SYNC)
Current Sense Synchronization Time on FETOUT
SR bit = 0
–
130
185
SR bit = 1
–
70
110
–
10
30
Current Sense Settling Time on resistive load only
(40)
Driver Output Positive Slew Rate (30% to 70% @ VBAT = 14 V)
t CSNS(SET)
SRR
s
V/s
SR bit = 0
IOUT = 2.8 A for OUT1 and OUT5
0.10
0.25
0.56
IOUT = 5.5 A for OUT2, OUT3, and OUT4
0.14
0.30
0.56
0.20
0.40
0.80
0.30
0.55
1.05
SR bit = 1
IOUT =0.7 A for OUT1 and OUT5
IOUT = 1.4 A for OUT2, OUT3, and OUT4
Driver Output Negative Slew Rate (70% to 30% @ VBAT = 14 V)
SRF
V/s
SR bit = 0
IOUT = 2.8 A for OUT1 and OUT5
0.10
0.25
0.56
IOUT = 5.5 A for OUT2, OUT3, and OUT4
0.14
0.30
0.56
0.20
0.40
0.80
0.30
0.55
1.05
SR bit = 0: IOUT = 2.8 A for OUT1 and OUT5 and IOUT = 5.5 A for OUT2/3/4
0.8
1.0
1.2
SR bit = 1: IOUT = 0.7 A for OUT1 and OUT5 and IOUT = 1.4 A for OUT2/3/4
0.8
1.0
1.2
SR bit = 1
IOUT = 0.7 A for OUT1 and OUT5
IOUT = 1.4 A for OUT2, OUT3, and OUT4
Driver Output Matching Slew Rate (SRR /SRF) (70% to 30% @ VBAT = 14 V
@ 25 °C)
Driver Output Turn-ON Delay (SPI ON Command [No PWM, CS Positive Edge]
to Output = 50% VBAT @ VBAT = 14 V) (see Figure 6)
SR
s
t DLYON
SR bit = 0: IOUT = 2.8 A for OUT1 and OUT5 and IOUT = 5.5 A for OUT2/3/4
50
–
120
SR bit = 1: IOUT = 0.7 A for OUT1 and OUT5 and IOUT = 1.4 A for OUT2/3/4
25
–
65
Driver Output Turn-OFF Delay (SPI OFF command [CS Positive Edge] to
Output = 50% VBAT @ VBAT = 14 V) (see Figure 6)
s
t DLYOFF
SR bit = 0: IOUT = 2.8 A for OUT1 and OUT5 and IOUT = 5.5 A for OUT2/3/4
50
–
120
SR bit = 1: IOUT = 0.7 A for OUT1 and OUT5 and IOUT = 1.4 A for OUT2/3/4
25
–
65
Notes
40. Not production tested.
MC10XS3535
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.0V  VCC  5.5V, 7.0V  VBAT  20V, - 40C  TA  125C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUTS TIMING (OUT1 TO OUT5) (CONTINUED)
Driver Output Matching Time (t DLY(ON) - t DLY(OFF)) @ Output = 50% VBAT with
VBAT = 14 V, f PWM = 240 Hz, PWM = 50%, @ 25 °C
s
t RF
SR bit = 0: IOUT = 2.8 A for OUT1 and OUT5 and IOUT = 5.5 A for OUT2/3/4
SR bit = 1: IOUT = 0.7 A for OUT1 and OUT5 and IOUT = 1.4 A for OUT2/3/4
- 40
–
20
- 23
–
7.0
PWM MODULE
Nominal PWM Frequency Range(41)
f PWM
30.0
–
400
Hz
Clock Input Frequency Range
f CLK
7.68
–
51.2
kHz
PWM_MAX
4.0
–
96
%
PWM_LIN
5.5
–
96
%
200 Hz Output PWM frequency
5.5
–
96
400 Hz Output PWM frequency
11
–
90
Output PWM Duty Cycle maximum range for 11 V < VBAT < 18 V(41), (42)
Output PWM Duty Cycle linear range for 11 V < VBAT < 18 V(43)
Output PWM Duty Cycle range for full diagnostic for 11 V < VBAT < 18 V(44)
%
PWM_DIAG
Notes
41. Not production tested.
42. The PWM ratio is measured at VOUT = 50% of VBAT in nominal range of PWM frequency. It is possible to put the device fully on (PWM
duty cycle = 100%) and fully off (PWM duty cycle = 0%). Between 4%-96%, OCHI1,2, OCLO and open load are available in ON state.
See Figure 6, Output Slew Rate and Time Delays.
43. Linear range is defined by output duty cycle to SPI duty cycle configuration +/-1 LSB. For values outside linear duty cycle range, a
calibration curve is available.
44. Full diagnostic corresponds to the availability of the following features: output current sensing, output status and open load detection. Not
production tested.
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.0V  VCC  5.5V, 7.0V  VBAT  20V, - 40C  TA  125C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
t WDTO
50
75
100
ms
t SD
–
7.0
30
s
t UV
0.8
1.25
2.0
s
WATCHDOG TIMING
Watchdog Timeout (SPI Failure)
I/O PLAUSIBILITY CHECK TIMING
Fault Shutdown Delay Time (from Overtemperature or OCHI1 or OCHI2 or
OCLO or UV Fault Detection to Output = 50% VBAT without round shaping
feature for turn off)
Under-voltage Deglitch Time(45)
ms
High Over-current Threshold Time 1
t1
for OUT1 and OUT5
for OUT2, OUT3, and OUT4
7.0
10
13.5
14
20
26
ms
High Over-current Threshold Time 2
t2
52.5
75
97.5
105
150
195
52.5
75
97.5
105
150
195
3.5
5.0
6.5
7.0
10.0
13.0
t LIMP
7.0
10.0
13.0
ms
t OLLED
105
150
195
ms
t FLASHER
1.4
2.3
3.0
s
t FOG
1.4
2.3
3.0
s
Ignition Toggle Timeout
t IGNITION
1.4
2.3
3.0
s
Clock Input Low Frequency Detection Range
f LCLK DET
1.0
2.0
4.0
kHz
Clock Input High Frequency Detection Range
f HCLK DET
100
200
400
kHz
for OUT1 and OUT5
for OUT2, OUT3, and OUT4
ms
Autorestart Period
tAUTORST
for OUT1 and OUT5
for OUT2, OUT3, and OUT4
ms
Autorestart Over-current Shutdown Delay Time
t OCHI_AUTO
for OUT1 and OUT5
for OUT2, OUT3, and OUT4
Limp Home Input pin Deglicher Time
Cyclic Open Load Detection Timing with
LED(46)
Flasher Toggle Timeout
Fog Toggle Timeout
Notes
45. This time is measured from the VBAT(UV) level to the fault reporting. Parameter guaranteed in testmode.
46.
IOLLEDn bit (where “n” corresponds to respective outputs 1 through 5) in SI data is set to logic [1]. Refer to Table 8, Serial Input Address
and Configuration Bit Map, page 29.
MC10XS3535
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.0V  VCC  5.5V, 7.0V  VBAT  20V, - 40C  TA  125C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
f SPI
–
–
3.0
MHz
t CS
–
–
1.0
us
t LEAD
–
–
500
ns
t WSCLKH
–
–
167
ns
t WSCLKL
–
–
167
ns
t LAG
–
50
167
ns
t SI(SU
–
25
83
ns
t SI HOLD
–
25
83
ns
–
25
50
SPI INTERFACE CHARACTERISTICS
Maximum Frequency of SPI Operation
Rising Edge of CS to Falling Edge of CS (Required Setup
Time)(47)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
Required High State Duration of SCLK (Required Setup Time)
Required Low State Duration of SCLK (Required Setup
(47)
Time)(47)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
SI to Falling Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to SI (Required Setup
(47)
(48)
Time)(48)
SO Rise Time
(47)
t RSO
CL = 80 pF
SO Fall Time
t FSO
CL = 80 pF
SI, CS, SCLK, Incoming Signal Rise
ns
Time(48)
SI, CS, SCLK, Incoming Signal Fall Time
(48)
ns
–
25
50
t RSI
–
–
50
ns
t FSI
–
–
50
ns
Time from Falling Edge of SCLK to SO
Low-impedance(49)
t SO(EN)
–
–
145
ns
Time from Rising Edge of SCLK to SO
High-impedance(50)
t SO(DIS)
–
65
145
ns
Notes
47.
48.
49.
50.
Maximum setup time required for the 10XS3535 is the minimum guaranteed time needed from the microcontroller.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at SO. 1.0 kon pull-up on CS.
Time required for output status data to be terminated at SO. 1.0 kon pull-up on CS.
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
VIL
VIL
TwRSTB
t
tTCSB
CS
ENBL
TENBL
VIH
V
90%
VCC
0.7VDD
CS
CSB
IH
10%
VCC
0.7VDD
t WSCLKH
TwSCLKh
tTlead
LEAD
VIL
V
IL
t RSI
TrSI
t LAG Tlag
90%
VCC
0.7VDD
SCLK
SCLK
VIH
VIH
10% VCC
0.2VDD
VIL
V
t TSIsu
SI(SU)
IL
t WSCLKL
TwSCLKl
tTfSI
FSI
t SI(HOLD)
TSI(hold)
SI
SI
VIH
V
90%
VCC
0.7 VDD
0.2VDD
10% VCC
Don’t Care
Don’t Care
Valid
Valid
Don’t Care
IH
VIL
VIL
Figure 4. Input Timing Switching Characteristics
t FSI
t RSI
TrSI
TfSI
VOH
VOH
2.0 V
3.5V
50%
SCLK
SCLK
1.0VV
0.8
VOL
VOL
t SO(EN)
TdlyLH
SO
SO
VOH
VOH
90%
VCC
0.7 VDD
0.210%
VDDVCC
Low-to-High
Low
to High
VOL
VOL
TrSO
t RSO
VALID
tTVALID
SO
TfSO
t FSO
SO
VOH
VOH
VCC
VDD
High to Low 0.790%
High-to-Low
0.2VDD
10% VCC
TdlyHL
VOL
VOL
tSO(DIS)
Figure 5. SCLK Waveform and Valid SO Data Delay Time
MC10XS3535
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
CS
High logic level
Low logic level
Time
VOUT[1:5]
VPWR
RPWM
50%VPWR
Time
t DLY(ON)
VOUT[1:5]
70% VPWR
t DLY(OFF)
SR F
SR R
30% VPWR
Time
Figure 6. Output Slew Rate and Time Delays
CS
High logic level
Low logic level
Time
IOUT[1:5]
IMAX
Time
t DLY(ON)
ICSNS
t CSNS(SET)
t DLY(OFF)
t CSNS(VAL)
Time
VFETOUT
t CSNS(SYNC)
High logic level
with CSNS sync bit = 1
Low logic level
Time
Figure 7. Current Sensing Time Delays
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 10XS3535 is designed for low-voltage automotive and
industrial lighting applications. Its five low RDS(ON) MOSFETs
(three 10 mandtwo 35 m) can control the high sides of
five separate resistive loads (bulbs). Programming, control,
and diagnostics are accomplished using a 16-bit SPI
interface.
FUNCTIONAL PIN DESCRIPTION
SUPPLY VOLTAGE (VBAT)
The VBAT pin of the 10XS3535 is the power supply of the
device. In addition to its supply function, this tab contributes
to the thermal behavior of the device by conducting the heat
from the switching MOSFETs to the printed circuit board.
Ch.1
Ch.2
Ch.3
Ch.4
SUPPLY VOLTAGE (VCC)
This is an external voltage input pin used to supply the
digital portion of the circuit and the gate driver of the external
SMART MOSFET.
Total
0°
90°
180°
270°
0°
0°
90°
180°
270°
0°
GROUND (GND)
This pin is the ground of the device.
CLOCK INPUT / WAKE-UP OUTPUT (CLOCK)
When the part is in Normal Mode (RST=1), the PWM
frequency and timing are generated from the rising edge of
clock input by the PWM module. The clock input frequency is
the selectable factor 27 = 128 or 28 = 256 of the PWM
frequency per output, depending PR bit value.
The OUT1:6 can be controlled in the range of 4% to 96%
with a resolution of 7 bits of duty cycle (bits D[6:0]).
The following table describes the PWM resolution.
On/Off
(Bit D7)
Duty cycle (7 bits
resolution)
Output state
0
X
OFF
1
0000000
PWM (1/128 duty cycle)
1
0000001
PWM (2/128 duty cycle)
1
0000010
PWM (3/128 duty cycle)
1
1111111
fully ON
The timing includes four programmable PWM switching
phases (0°, 90°, 180°, and 270°) to improve overall EMC
behavior of the light module.
The amplitude of the input current is divided by four while
the frequency is 4 times the original one. The two following
pictures illustrate this behavior.
Ch.1
Ch.2
Ch.3
Ch.4
Total
The synchronization of the switching phases between
different IC is provided by an SPI command in combination
with the CS input. The bit in the SPI is called PWM sync
(initialization register).
In Normal mode, no PWM feature (100% duty cycle) is
provided in the following instances:
•with the following SPI configuration: D7:D0=FF.
•In case of clock input signal failure (out of f PWM), the
outputs state depends of D7 bit value (D7=1=ON) in
Normal mode.
In Fail mode, the ouputs state depend on IGN, FLASHER,
and FOG pins.
If RST=0, this pin reports the wake-up event for wake=1
when VBAT and VCC are in operational voltage range.
LIMP HOME INPUT (LIMP)
The Fail mode of the component can be activated by this
digital input port. The signal is “high active”, meaning the Fail
mode can be activated by a logic high signal at the input.
MC10XS3535
22
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
IGNITION INPUT (IGN)
FET OUT OUTPUT (FETOUT)
The ignition input wakes the device. It also controls the Fail
mode activation. The signal is “high active”, meaning the
component is active in case of a logic high at the input.
This output pin is used to control an external MOSFET
(OUT6).
FLASHER INPUT (FLASHER)
The high level of the FETOUT Output is VCC, if VBAT and
VCC are available, in case FETOUT is a controlled ON.
The flasher input wakes the device. It also controls the Fail
Mode activation. The signal is “high active”, meaning the
component is active in case of a logic high at the input.
FETOUT is not protected if there is a short-circuit or undervoltage on VBAT.
In case of a reverse battery, OUT6 is OFF.
FOG INPUT (FOG)
FET IN INPUT (FETIN)
The fog input wakes the device. It also controls the Fail
Mode activation. The signal is “high active”, meaning the
component is active in case of a logic high at the input.
This input pin gives the current recopy of the external
MOSFET. It can be routed on CSNS output by a SPI
command.
RESET INPUT (RST)
SPI PROTOCOL DESCRIPTION
This input wakes the device when the RST pin is at
logic [1]. It is also used to initialize the device configuration
and the SPI faults registers when the signal is low. All SI/SO
registers described Table 8 and Table 11 are reset. The fault
management is not affected by RST.
The SPI interface has a full-duplex, three-wire,
synchronous data transfer with four I/O lines associated with
it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO),
and Chip Select (CS).
The SI/SO pins of the 10XS3535 device follow a first-in,
first-out (D15 to D0) protocol, with both input and output
words transferring the most significant bit (MSB) first. All
inputs are compatible with 3.3 V and 5.0 V CMOS logic
levels, supplied by VCC.
The SPI lines perform the following functions:
CURRENT SENSE OUTPUT (CSNS)
The current sense output pin is an analog current output or
a voltage proportional to the temperature on the GND flag.
The routing to the external resistor is SPI programmable.
This current sense monitoring may be synchronized in
case of the OUT6 is not used. So, the current sense
monitoring can be synchronized with a rising edge on the
FETOUT pin (tCSNS(SYNC)) if CSNS sync SPI bit is set to logic
[1]. Connection of the FETOUT-pin to a MCU input pin allows
the MCU to sample the CSNS-pin during a valid time-slot.
Since this falling edge is generated at the end of this timeslot, upon a switch-off command, this feature may be used to
implement maximum current control.
CHARGE PUMP (CP)
An external capacitor is connected between this pin and
the VBAT pin. It is used as a tank for the internal charge
pump. Its value is 100 nF ± 20%, 25 V maximum.
SERIAL CLOCK (SCLK)
The SCLK pin clocks the internal shift registers of the
10XS3535 device. The SI pin accepts data into the input shift
register on the falling edge of the SCLK signal, while the SO
pin shifts data information out of the SO line driver on the
rising edge of the SCLK signal. It is important that the SCLK
pin be in a logic low state whenever CS makes any transition.
For this reason, it is recommended the SCLK pin be in a logic
[0] whenever the device is not accessed (CS logic [1] state).
SCLK has a passive pull-down, RDWN. When CS is logic [1],
signals at the SCLK and SI pins are ignored and SO is tristated (high-impedance) (see Figure 8).
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
CSB
CS
CS
SCLK
SI
SO
D15
D14
D13
D12
D11
D10
D9
OD15 OD14 OD13 OD12 OD11 OD10 OD9
NOTES: 1.
2.
3.
D8
OD8
D7
OD7
D6
OD6
D5
OD5
D4
D3
OD4
OD3
D2
OD2
D1
D0
OD1 OD0
Notes
RSTB
is in a logic H state during the above operation.
1....D15
most
recent
ordered
entry ofdata
data
the IC
device.
device.
DO, D1, D2,
, and: D0
D15 relate
relate toto
thethe
most
recent
ordered
entry of program
intointo
the LUX
OD15
: OD0
relate
thefirst
first
of ordered
and
data
out
device.
OD0, OD1,2.
OD2,
..., and
OD15
relate to
to the
16 16
bitsbits
of ordered
fault andfault
status
datastatus
out of the
LUX
IC of the device.
Figure 8. Single 16-Bit Word SPI Communication
SERIAL INPUT (SI)
CHIP SELECT (CS)
The SI pin is a serial interface command data input pin.
Each SI bit is read on the falling edge of SCLK. A 16-bit
stream of serial data is required on the SI pin, starting with
D15 to D0. SI has a passive pull-down, RDOWN.
The CS pin enables communication with the master
device. When this pin is in a logic [0] state, the device is
capable of transferring information to, and receiving
information from, the master device. The 10XS3535 device
latches in data from the Input Shift registers to the addressed
registers on the rising edge of CS. The device transfers
status information from the power output to the Shift register
on the falling edge of CS. The SO output driver is enabled
when CS is logic [0]. CS should transition from a logic [1] to a
logic [0] state only when SCLK is a logic [0]. CS has a
passive pull-up, RUP.
SERIAL OUTPUT (SO)
The SO data pin is a tri-stateable output from the shift
register. The SO pin remains in a high-impedance state until
the CS pin is put into a logic [0] state. The SO data is capable
of reporting the status of the output, the device configuration,
and the state of the key inputs. The SO pin changes state on
the rising edge of SCLK and reads out on the falling edge of
SCLK.
MC10XS3535
24
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SLEEP MODE
The Sleep mode is the default mode of the 10XS3535.
This is the state of the device after first applying battery
voltage (VBAT) and prior to any I/O transitions. This is also the
state of the device when IGN, FOG, FLASHER, and RST are
logic [0] (wake=0). In the Sleep mode, the outputs and all
internal circuitry are OFF to minimize current draw. In
addition, all SPI-configurable features of the device are reset.
The 10XS3535 will transit to two modes (Normal and Fail)
depending on wake and fail signals (see Fig13).
The transition to the other modes is according following
signals:
• Wake = IGN or IGN_ON or FLASHER or
FLASHER_ON or RST or FOG or FOG_ON
• Fail = VCC fail or SPI fail or External limp
D7 bit
D0-D6 bits
Output
Over-current
FAIL MODE
The 10XS3535 is in Fail mode when:
• Wake = 1
• Fail = 1
In Fail mode:
NORMAL MODE
The 10XS3535 is in Normal mode when:
• Wake = 1
• Fail = 0
In Normal operating mode the power outputs are under full
control of the SPI as follows:
• The outputs 1 to 6, including multiphase timing and
selectable slew-rate, are controlled by the
programmable PWM module.
• The outputs 1 to 5 are switched OFF in case of an
under-voltage on VBAT.
• The outputs 1 to 5 are protected by the selectable overcurrent double window and over-temperature shutdown
circuit.
• The digital diagnosis feature transfers status of the
smart outputs via SPI.
• The analog current sense output (current recopy
feature) can be routed by SPI.
• The outputs 1 and 5 can be configured to control LED
loads: RDS(ON) is increased by a factor of 2 and the
current recopy ratio is scaled by a factor of 4.
• The SPI reports NM=1 in this mode.
The figure below describes the PWM, outputs and overcurrent behavior in Normal mode.
• The outputs are under control of external pins (see
Table 6)
• The outputs are fully protected in case of an overload,
over-temperature and under-voltage (on VBAT or on
VCC).
• The SPI reports continuously the content of address 11,
disregard to previous requested output data word.
• Analog current sense is not available.
• Output 2 is configured in Xenon mode.
• In case of an overload (OCHI2 or OCLO) conditions or
under-voltage on VBAT, the outputs are under control
of autorestart feature.
• In case of serious overload condition (OCHI1 or OT) the
corresponding output is latched OFF until a new wakeup event (wake=0 then 1).
IGN_ON
1.4 sec min
IGN (external)
OUT[1,2]
Over-current
Table 6. Limp Home Output State
Output 1
Parking Light
Output 2
Low Beam
Output 3
High Beam
Output 4
Fog Light
Output 5
Flasher
External Switch
Spare
IGN Pin
IGN Pin
OFF
FOG Pin
FLASHER Pin
OFF
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
AUTORESTART STRATEGY
The autorestart circuitry is used to supervise the outputs
and reactivate high side switches in cases of overload or
under-voltage failure conditions, to provide a high availability
of the outputs.
Autorestart feature is available in Fail mode when no
supervising intelligence of the microcontroller is available.
Autorestart is activated in case of overload condition (OCHI2
or OCLO) or under-voltage condition on VBAT (see
Figure 12).
The autorestart switches ON the outputs. During ON state
of the switch OCHI1 window is enabled for tochi_Auto, then
after the output is protected by OCLO.
Output current
OCHI1
In case of under-voltage in Fail mode, the outputs 1 to 5
will be latched off. The corresponding output is switched on
only after its autorestart period (tAUTORST-T1 or tAUTORST-T2).
The Autorestart is not limited in time.
TRANSITION FAIL TO NORMAL MODE
To leave the Fail mode, the fail condition must be removed
(fail=0). The microcontroller has to toggle the SPI D10 bit (0
to 1) to reset the watchdog bit; the other bits are not
considered. The previous latched faults are reset by the
transition into Normal mode.
TRANSITION NORMAL TO FAIL MODE
To leave the Normal mode, a fail condition must occur
(fail=1). The previous latched faults are reset by the transition
into Fail mode.
If the SI is shorted to VCC, the device transmits to Fail
Safe mode until the WD bit toggles through the SPI (from [0]
to [1]).
All settings are according to predefined values (all bits set
to logic [0]).
OCLO or UV fault
START-UP SEQUENCE
The 10XS3535 enters in Normal mode after start-up if
following sequence is provided:
OCLO
•VBAT and VCC power supplies must be above their
under-voltage thresholds (Sleep mode).
tochi_auto
Auto period
time
Figure 9. Over-current window in case of Autorestart
In case of OCHI1 or OT, the switch is latched OFF until
wake-up (wake=0 then 1).
In case of OCLO or under-voltage, the output switch OFF
and after auto restart period (150 ms for 10 mohm or 75 ms
for 35 mOhm) turn ON again.
•generate wake up event (wake=1) from 0 to 1 on RST.
The device switches to Normal mode.
•apply PWM clock after maximum 200 s (min. 50 s).
•send SPI command to the Device status register to clear
the clock fail flag to enable the PWM module to start.
Figure 10 describes the wake-up block diagram.
MC10XS3535
26
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
POWER OFF MODE
The 10XS3535 is in Power OFF mode when the battery
voltage is below VBATPOR[1,2] thresholds. For more details,
please refer to Loss of VBAT paragraph.
Sleep
(wake=0)
(fail=0) and (wake=1)
(wake=1) and (fail=1) *
(wake=0)
VBAT > VBATPOR[1,2]
VBAT < VBATPOR[1,2]
VBAT < VBATPOR[1,2]
Power OFF
VBAT < VBATPOR[1,2]
Normal
Fail
(fail=0) and (wake=1)
(fail=1) and (wake=1)
Notes:
* only available in case of Vcc fail condition
wake = (RST = 1) OR (IGN_ON = 1) OR (Flasher_ON = 1) OR (FOG_ON = 1)
fail = (VCC_fail = 1) OR (SPI_fail = 1) OR (ext_limp = 1)
Figure 10. Operating Modes State Machine
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
VBAT
wake
Wake-up bar
VBAT
IGN
Deglitcher
VCC
IGN_ON
Internal
regulator
Dig2.5V
FLASHER
FOG
Flasher_ON
Deglitcher
Oscillator
Fog_ON
Fault
management
Deglitcher
PWM freq
detector
SPI registers
VCC fail
SPI fail
External
Limp
RST
PWM module
OR
Fail
reset
VCC
OR
CLOCK
UVF
1.4 sec min
external
external_ON
external: IGN, FLASHER, FOG
external_ON: IGN_ON, FLASHER_ON, FOG_ON
Figure 11. Wake-up block diagram
MC10XS3535
28
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
SERIAL INPUT COMMUNICATION

Table 7. SI Message Bit Assignment
SPI communication compliant to 3.3 V and 5.0 V is
accomplished using 16-bit messages. A message is
transmitted by the master starting with the MSB, D15, and
ending with the LSB, D0. Each incoming command message
on the SI pin can be interpreted using the bit assignment
described in Table 7. The 5 bits D15 : D11, called register
address bits, are used to select the command register. Bit
D10 is the watchdog bit. The remaining 10 bits, D9 : D0, are
used to configure and control the output and its protection
features. Multiple messages can be transmitted in
succession to accommodate those applications where daisy
chaining is desirable or to confirm transmitted data as long as
the messages are all multiples of 16 bits. Any attempt made
to latch in a message that is not 16 bits will be ignored.
Bit Sig
SI Msg Bit
MSB
D15 : D11
Message Bit Description
Register address bits.
D10
LSB
Watchdog in: toggled to satisfy watchdog
requirements.
D9 : D0
Used to configure inputs, outputs, device
protection features, and SO status content.
DEVICE REGISTER ADDRESSING
The register addresses (D15 : D11) and the impact of the
serial input registers on device operation are described in this
section. Table 8 summarizes the SI registers.
All SPI registers are reset (all bit equal 0) in case of RST
equal 0 or fail mode (Fail=1).
Table 8. Serial Input Address and Configuration Bit Map
SI Address
SI Register
SI Data
D1 D1 D1 D1 D1
D10
5
4
3
2
1
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MUX2
MUX1
MUX0
SOA1
SOA0
Initialization
0
0
0
0
0
WD
0
0
FOGen
PWM
sync
Xenon
Config OL
0
0
0
0
1
WD
LEDControl5
0
0
0
LEDControl1
Config
Prescaler
0
0
0
1
0
WD
0
PR1
PR2
PR3
0
0
0
PR4
PR5
PR6
Config SR
0
0
0
1
0
WD
1
SR1
SR2
SR3
0
0
0
SR4
SR5
0
Config CSNS 0
0
0
1
1
WD
0
0
0
0
CSNS
sync
OLLED5 OLLED4 OLLED3 OLLED2 OLLED1
NO_OCHI5 NO_OCHI4 NO_OCHI3 NO_OCHI2 NO_OCHI1
Control
OUT1
0
1
0
0
1
WD Phase2
Phase1
ONoff
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
Control
OUT2
0
1
0
1
0
WD Phase2
Phase1
ONoff
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
Control
OUT3
0
1
0
1
1
WD Phase2
Phase1
ONoff
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
Control
OUT4
0
1
1
0
0
WD Phase2
Phase1
ONoff
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
Control
OUT5
0
1
1
0
1
WD Phase2
Phase1
ONoff
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
Control
External
Switch
0
1
1
1
0
WD Phase2
Phase1
ONoff
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
RESET
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
Note: testmode address used only by FSL is D[15:11]=01111 with RST pin voltage higher than 8V typ.
X = Don’t care and 0 = need to rewrite logic “0”
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
ADDRESS 00000 — INITIALIZATION
The Initialization register is used to read the various
statuses, choose one of the six outputs current recopy, load
the H7 bulbs profile for OUT2 only, enable the FOG pin and
synchronize the switching phases between different devices.
The register bits D1 and D0 determine the content of the 16
bits of the next SO data. (Refer to the section entitled Serial
Output Communication (Device Status Return Data)
beginning on page 31.) Table 9 describes the register of
initialization.
The watchdog timeout is specified by t WDTO parameter. As
long as the WD bit (D10) of an incoming SPI message is
toggled within the minimum watchdog timeout period
(WDTO), the device will operate normally. If an internal
watchdog timeout occurs before the WD bit is toggled, the
device will revert to Fail mode. All registers are cleared. To
exit the Fail mode, send valid SPI communication with
WD bit = 1.
Table 9. Initialization Register
SI Address
SI Data
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
WD
0
0
FOGen
PWM
sync
Xenon
MUX2
MUX1
MUX0
SOA1
SOA0
D6 (PWM sync) = 0, No synchronization
D4, D3, D2 (MUX2, MUX1, MUX0) = 000, No current sense
D6 (PWM sync) = 1, Synchronization on CSB positive edge
D4, D3, D2 (MUX2, MUX1, MUX0) = 001, OUT1 current sense
D5 (Xenon) = 0, Xenon
D4, D3, D2 (MUX2, MUX1, MUX0) = 010, OUT2 current sense
D5 (Xenon) = 1, H7 Bulb
D4, D3, D2 (MUX2, MUX1, MUX0) = 011, OUT3 current sense
D7 (FOGen) = 0, FOG pin does not control the output 4
D4, D3, D2 (MUX2, MUX1, MUX0) = 100, OUT4 current sense
D7 (FOGen) = 1, FOG input controls the output 4
D4, D3, D2 (MUX2, MUX1, MUX0) = 101, OUT5 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 110, External Switch current
sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 111, Temperature analog
feedback
ADDRESS 00001 — CONFIGURATION OL
The Configuration OL register is used to enable the open
load detection for LEDs in Normal Mode (OLLEDn in Table 8,
page 29) and to active the LED Control.
When bit D0 is set to logic [1], the open load detection
circuit for LED is activated for output 1. When bit D0 is set to
logic [0], open load detection circuit for standard bulbs is
activated for output 1.
When bit D5 is set to logic [1], the LED Control is activated
for output 1.
ADDRESS 00010 — CONFIGURATION PRESCALER
AND SR
Two configuration registers are available at this address.
The Configuration Prescaler when D9 bit is set to logic [0] and
Configuration SR when D9 bit is set to logic [1].
The Configuration Prescaler register is used to enable the
PWM clock prescaler per output. When the corresponding
PR bit is set to logic [1], the clock prescaler (reference clock
divided by 2) is activated for the dedicated output.
The SR Prescaler register is used to increase the output
slew-rate by a factor of 2. When the corresponding SR bit is
set to logic [1], the output switching time is divided by 2 for the
dedicated output.
MC10XS3535
30
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
ADDRESS 00011 — CONFIGURATION CSNS
The Configuration Current Sense register is used to
disable the high over-current shutdown phase (OCHI1 and
OCHI2 dynamic levels) in order to activate immediately the
current sense analog feedback.
When bit D9 is set to logic [1], the current sense
synchronization signal is reported on FETOUT output pin.
When the corresponding NO_OCHI bit is set to logic [1],
the output is only protected with OCLO level. And the current
sense is immediately available if it is selected through SPI, as
described in Figures 13. The NO_OCHI bit per output is
automatically reset at each corresponding ONoff bit transition
from logic [1] to [0] and in case of over-temperature or overcurrent fault. All NO_OCHI bits are also reset in case of
under-voltage fault detection.
ADDRESS 01001 — CONTROL OUT1
Bits D9 and D8 control the switching phases as shown in
Table 10.
Table 10. Switching Phases
D9 : D8
PWM Phase
00
0°
01
90°
10
180°
11
270°
Bit D7 at logic [1] turns ON OUT1. OUT1 is turned OFF
with bit D7 at logic [0]. This register allows the master to
control the duty cycle and the switching phases of OUT1. The
duty cycle resolution is given by bits D6 : D0.
D7 = 0, D6 : D0 = XX output OFF.
D7 = 1, D6 : D0 = 00 output ON during 1/128.
D7 = 1, D6 : D0 = 1A output ON during 27/128 on PWM
period.
D7 = 1, D6 : D0 = 7F output continuous ON (no PWM).
ADDRESS 01010 — CONTROL OUT2
Same description as OUT1.
ADDRESS 01011 — CONTROL OUT3
Same description as OUT1.
ADDRESS 01100 — CONTROL OUT4
Same description as OUT1.
ADDRESS 01101 — CONTROL OUT5
ADDRESS 01110 — CONTROL EXTERNAL SWITCH
Same description as OUT1.
ADDRESS 01111 — TEST MODE
This register is reserved for test and is not available with
SPI during normal operation.
SERIAL OUTPUT COMMUNICATION (DEVICE
STATUS RETURN
DATA)
When the CS pin is pulled low, the output register is
loaded. Meanwhile, the data is clocked out MSB first as the
new message data is clocked into the SI pin. The first 16 bits
of data clocking out of the SO, and following a CS transition,
is dependant upon the previously written SPI word (SOA1
and SOA0 defined in the last SPI initialization word).
Any bits clocked out of the SO pin after the first 16 will be
representative of the initial message bits clocked into the SI
pin since the CS pin first transitioned to a logic [0]. This
feature is useful for daisy chaining devices.
A valid message length is determined following a CS
transition of logic [0] to logic [1]. If the message length is
valid, the data is latched into the appropriate registers. A valid
message length is a multiple of 16 bits. At this time, the SO
pin is tri-stated and the fault status register is now able to
accept new fault status information.
The output status register correctly reflects the status of
the Initialization-selected register data at the time that the CS
is pulled to a logic [0] during SPI communication and / or for
the period of time since the last valid SPI communication,
with the following exceptions:
•The previous SPI communication was determined to be
invalid. In this case, the status will be reported as
though the invalid SPI communication never occurred.
•Battery transients below 6.0 V, resulting in an undervoltage shutdown of the outputs, may result in incorrect
data loaded into the SPI register, except the UVF fault
reporting (OD13).
SERIAL OUTPUT BIT ASSIGNMENT
The contents of bits OD15 : OD0 depend on bits D1: D0
from the most recent initialization command SOA[1:0] (refer
to Table 8, page 29), as explained in the paragraphs that
follow.
The register bits are reset by a read operation and also if
the fault is removed.
Table 11 summarizes the SO register content. Bit OD10
reflects Normal mode (NM).
Same description as OUT1.
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 11. Serial Output Bit Map Description
Previous
Status / SI Data
Mode SO SO
SO Data
OD15 OD14 OD13 OD12 OD11 OD10 OD9
OD8
OD7
OD6
OD4
OD3
OD2
OD1
OD0
OL5
OVL5
OL4
OVL4 OL3 OVL3
OL2
OVL2
OL1
OVL1
NM
OC5
OTS5
OC4 OTS4 OC3 OTS3
OC2
OTS2
OC1 OTS1
OTS
NM
0
OV
OTW
OTS
NM
0
0
X
X
X
OUT5
OUT4
OUT3
OUT2
OUT1
0
0
1
0
0
0
0
0
0
0
0
0
0
A1
A0
Fault
Status
0
0
0
0
UVF
OTW
OTS
NM
Overload
Status
0
1
0
1
UVF
OTW
OTS
Device
Status
1
0
1
0
UVF
OTW
Output
Status
1
1
1
1
UVF
Reset
X
X
0
0
0
OD5
FOG_ IGN_ FLAS
ON
ON HER_
ON
RC
FOG FLASHER IGN CLOCK
pin
fail
pin
pin
X = Don’t care
PREVIOUS ADDRESS SOA[1:0] = 00
If the previous two LSBs are 00, bits OD15 : OD0 reflect the
fault status (Table 12).
Table 12. Fault Status
OD15
OD14
OD13
OD12
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
0
0
UVF
OTW
OTS
NM
OL5
OVL5
OL4
OVL4
OL3
OVL3
OL2
OVL2
OL1
OVL1
OD13 (UVF) = Under-voltage Flag on VBAT
OD9, OD7, OD5, OD3, OD1 (OL5, OL4, OL3, OL2, OL1) = Open Load
Flag at Outputs 5 through 1, respectively.
OD8, OD6, OD4, OD2, OD0 (OVL5, OVL4, OVL3, OVL2,
OVL1) = Overload Flag for Outputs 5 through 1, respectively.This
corresponds to OCHI or OCLO faults.
OD12 (OTW) = Over-temperature Prewarning Flag
OD11 (OTS) = Over-temperature Flag for all outputs
OD10 (NM) = Normal mode
Note
A logic [1] at bits OD9:OD0 indicates a fault. If there is no fault, bits OD9:OD0 are logic [0].
OVL=OCHI1+OCHI2+OCLO
PREVIOUS ADDRESS SOA[1:0] = 01
If the previous two LSBs are 01, bits OD15 :O D0 reflect
reflect the temperature status (Table 13).
Table 13. Overload Status
OD15
OD14
OD13
OD12
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
0
1
UVF
OTW
OTS
NM
OC5
OTS5
OC4
OTS4
OC3
OTS3
OC2
OTS2
OC1
OTS1
OD13 (UVF) = Under-voltage Flag on Vbat
OD12 (OTW) = Over-temperature Prewarning Flag
OD11 (OTS) = Over-temperature Flag for all outputs
OD10 (NM) = Normal mode
OD9, OD7, OD5, OD3, OD1 (OC5, OC4, OC3, OC2, OC1) = High
Over-current Shutdown Flag for Outputs 5 through 1, respectively
OD8, OD6, OD4, OD2, OD0 (OTS5, OTS4, OTS3, OTS2,
OTS1) = Over-temperature Flag for Outputs 5 through 1, respectively
Note
A logic [1] at bits OD9:OD0 indicates a fault. If there is no fault, bits OD9:OD0 are logic [0].
OC=OCHI1+OCHI2
MC10XS3535
32
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
PREVIOUS ADDRESS SOA[1:0] = 10
If the previous two LSBs are 10, bits OD15 : OD0 reflect the
status of the 10XS3535 (Table 14).
Table 14. Device Status
OD15
OD14
OD13
OD12
OD11
OD10
OD9
OD8
1
0
UVF
OTW
OTS
NM
0
OV
OD7
OD6
OD5
FOG_ IGN_ON FLASH
ON
ER_ON
OD4
RC
OD3
OD2
OD1
OD0
FOG pin FLASHER IGN pin CLOCK
pin
fail
OD13 (UVF) = Under-voltage Flag on Vbat
OD5 = Indicates the state of internal FLASHER_ON signal
OD12 (OTW) = Over-temperature Prewarning Flag
OD11 (OTS) = Over-temperature Flag for all outputs
OD4 (RC) = Logic [0] indicates a Front Penta Device. Logic [1] indicates
a Rear Penta Device
OD10 (NM) = Normal mode
OD3 (FOG pin) = indicates the FOG pin state in real time
OD8 (Overvoltage) = Over-voltage Flag on Vbat in real time
OD2 (FLASHER pin) = Indicates the FLASHER pin state in real time
OD7 = Indicates the state of internal FOG_ON signal, as
OD1 (IGN pin) = Indicates the IGN pin state in real time
described in Figures 11
OD0 (CLOCK fail) = Logic [1], which indicates a clock failure. The
content of this bit is reset by read operation.
OD6 = Indicates the state of internal IGN_ON signal
PREVIOUS ADDRESS SOA[1:0] = 11
If the previous two LSBs are 11, bits OD15 : OD0 reflect the
status of the 10XS3535 (Table 15).
Table 15. Output Status
OD15
OD14
OD13
OD12
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
1
1
UVF
OTW
OTS
NM
0
0
X
X
X
OUT5
OUT4
OUT3
OUT2
OUT1
OD13 (UVF) = Under-voltage Flag on Vbat
OD12 (OTW) = Over-temperature Prewarning Flag
OD11 (OTS) = Over-temperature Flag for all outputs
OD10 (NM) = Normal mode
OD4 (OUT5) = Logic [0] indicates the OUT5 voltage is lower than
VOUT_TH. Logic [1] indicates the OUT5 voltage is higher than
VOUT_TH
OD3 (OUT4) = Logic [0] indicates the OUT4 voltage is lower than
VOUT_TH. Logic [1] indicates the OUT4 voltage is higher than VOUT_TH
OD2 (OUT3) = Logic [0] indicates the OUT3 voltage is lower than
VOUT_TH. Logic [1] indicates the OUT3 voltage is higher than VOUT_TH
OD1 (OUT2) = Logic [0] indicates the OUT2 voltage is lower than
VOUT_TH. Logic [1] indicates the OUT2 voltage is higher than VOUT_TH
OD0 (OUT1) = Logic [0] indicates the OUT5 voltage is lower than
VOUT_TH. Logic [1] indicates the OUT1 voltage is higher than VOUT_TH
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
PROTECTION AND DIAGNOSIS FEATURES
OUTPUT PROTECTION FEATURES
The 10XS3535 provides the following protection features:
•Protection against transients on VBAT supply line (per
ISO 7637)
•Active clamp, including protection against negative
transients on output line
•Over-temperature
•Severe and resistive Over-current
•Open Load during ON state
These protections are provided for each output (OUT1:5).
Over-temperature detection
The 10XS3535 provides over-temperature shutdown for
each output (OUT1:OUT5 ). It can occur when the output pin
is in the ON or OFF state. An over-temperature fault condition
results in turning OFF the corresponding output. The fault is
latched and reported via SPI. To delatch the fault and be able
to turn ON again the outputs, the failure condition must be
removed (T< 175 °C typically) and:
•if the device was in Normal mode, the output
corresponding register (bit D7) must be rewritten. 
Application of complete OCHI window (OCHI1+OCHI2
during t2) depends on toggling or not toggling the D7 bit.
•if the device was in Fail mode, the corresponding output
is locked until restart of the device: wake up from Sleep
mode or VBATPOR1.
The corresponding SPI fault report (OTS bit) is removed
after a read operation.
OCHI (IOCHI1 and then IOCHI2) is only activated after
toggling D7 bit in Normal Mode. During the switch-on, a
severe short-circuit condition provided on the module
connector is reported as an OCHI fault. In Fail Mode, the
control of OCHI window is provided by the toggles: IGN_ON,
Flasher_ON, and FOG_ON. The current thresholds (IOCHI1,
IOCHI2 and IOCLO) and the time (t1 and t2) are fixed numbers
for each driver. After t2, OCLO current threshold is set to
protect in steady state. t1 and t2 times are compared to “on”
state duration (tON) of the output. In case of the output is
controlled in PWM mode during the inrush period, the tON
corresponds to the sum of each “on” state duration in order to
expand dynamically the transient overcurrent profile.
OUT2 is default loaded with the Xenon profile. The use of
H7 bulbs at this output requires SPI programming (Xenon
bit).
In case of overload (OCHI1 or OCHI2 or OCLO detection),
the corresponding output is disabled immediately. The fault is
latched and the status is reported via SPI. To delatch the
fault, the failure condition must be removed and:
For OCHI1:
•if the device was in Normal Mode: the output
corresponding register (bit D7) must be rewritten D7=1.
Application of complete OCHI window depends on
toggling or not toggling D7 bit.
•if the device was in Fail Mode, the failure is locked until
restart of the device: wake up from Sleep Mode or
VBATPOR1.
For OCHI2 and OCLO:
Over-current detections
The 10XS3535 provides intelligent over-current shutdown
(see Figure 12) in order to protect the internal power
transistors and the harness in the event of overload (fuse
characteristic).
Output current
OCHI1
•if the device was in Normal Mode: the output
corresponding register (bit D7) must be rewritten D7=1.
Application of complete OCHI window depends on
toggling or not toggling D7 bit.
•if the device was in Fail Mode, Autorestart is activated.
The device Autorestart feature provides a fixed duty
cycle and fixed period with OCHI1 window.
Autorestart feature resets OCHI2 or OCLO fault after
corresponding Autorestart period.
The SPI fault reports are removed together after a read
operation:
OCHI2
- OC bit=(OCHI1) or (OCHI2) fault
OCLO
- OVL bit=(OCHI1) or (OCHI2) or (OCLO) fault
Overvoltage detection and active clamp
t1
t2
time
Figure 12. Double Over-current Window in Normal Mode
The 10XS3535 provides an active gate clamp circuit in
order to limit the maximum drain to source voltage.
In case of overload on an output the corresponding switch
(OUT[1 to 5]) is turned off which leads to high voltage at
MC10XS3535
34
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
VBAT with an inductive VBAT line. The maximum VBAT
voltage is limited at VBATCLAMP by active clamp circuitry
through the load. In case of open load condition, the positive
transient pulses (ISO 7637 pulse 2 and inductive battery line)
shall be handled by the application.
Figures 13 and 14 describe the faults management in
Normal mode and Fail mode.
Note: t1 and t2 please refer to Figure 12.
(OCHI2 = 1) or (OT = 1) or (UV = 1) or (D7 = 0)
t1<tON<t2 and (NO_OCHI=0)
without fault
(OCHI1 = 1) or (OT = 1) or (UV = 1) or (D7 = 0)
D7 = 0 then 1 without fault
and (NO_OCHI = 0)
tON = t1 without fault
OFF
OCHI2
(rewrite D7 = 1) and
(tON<t1) without fault and
(NO_OCHI = 0)
OCHI1
tON = t2 without fault
(NO_OCHI = 1) without fault
(NO_OCHI = 1) without fault
OCLO
tON<t1 and (NO_OCHI = 0) without fault
tON>t1 without fault and (rewrite D7 = 1) and (NO_OCHI = 0)
(tON>t2) and (rewrite D7 = 1) without fault
D7=0 then 1 without fault and (NO_OCHI=1)
(OCLO=1) or (OT=1) or (UV=1) or (D7=0)
Figure 13. Faults Management in Normal Mode (for OUT[1:5] only)
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
(OT = 1) or
(OCHI1 = 1)
(external_ON = 0)
OFF-latched
State
(OT = 1
(external_ON = 0)
(OT=1)
(external_ON = 1)
OFF
out: OFF
auto restart = 0
(t>tOCHI2) and (auto restart = 0)
(t>tOCHI1) and (auto restart = 0)
OCHI2
out: external
OCHI1
out: external
OCLO
out: external
(t>tOCHI1_AUTO) and (auto restart = 1)
(UV = 1
(UV = 1)
and
(external_on = 1)
(t>tautorestart)
(UV* = 0)
and
(UV = 1) or (OCHI2 = 1)
(OCLO = 1) or
(UV = 1)
(external_ON = 0)
OFF Autorestart
out: OFF
autorestart=1
(external_ON = 0)
1.4 sec min
external
external_ON
external: IGN, FLASHER, FOG
external_ON: IGN_ON, Flasher_ON, FOG_ON
Note: * See Autorestart strategy chapter.
Figure 14. Faults Management in Fail Mode (for OUT[1:5] only)
DIAGNOSTIC
Open Load
The 10XS3535 provides open load detection for each
output (OUT1:OUT5 ) when the output pin is in the ON state.
Open load detection levels can be chosen by SPI to detect a
standard bulb, a Xenon bulb for OUT2 only, or LEDs (OLLED
bit). Open load for LEDs only is detected during each regular
switch-off state or periodically each t OLLED (fully-on,
D[6:0] = 7F). To detect OLLED in fully on state, the output
must be on at least t OLLED. When an open load has been
detected, the output stays ON.
To delatch the diagnosis, the condition should be removed
and the SPI read operation is needed (OL bit). In case of a
Power on Reset on VBAT, the fault will be reset.
Current Sense
The 10XS3535 diagnosis for load current (OUT1:6) is
done using the current sense (CSNS) pin connected to an
external resistor. The CSNS resistance value is defined in
function to VCC voltage value. It is recommended to use
resistor 500  < RCSNS < 5.0 k. Typical value is 1.0 k for
5.0 V application. The routing of the current sense sources is
SPI programmable (MUX[2,0] bits).
MC10XS3535
36
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
The current recopy feature for OUT1:5 is disabled during
a high over-current shutdown phase (t2) and is only enabled
during low over-current shutdown thresholds. The current
recopy output delivers current only during ON time of the
output switch without overshoot (aperiodic settling).
available in CSNS output pin for MUX[2,0] bits set to “111”,
as described in Figure 16.
min
max
The current recopy is not active in Fail mode.
2
CSNS feedback (V)
With a calibration strategy, the output current sensing
precision can be improved significantly. One calibration point
at 25 °C for 50% of FSR allows removing part to part
contribution. So, the calibrated part precision goes down to 
+/-6.0% over [20% - 75%] output current FSR, over voltage
range (10 V to 16 V) and temperature range (-40 to 125 °C).
typ
2.5
1.5
1
0.5
With dedicated calibration points, the current recopy
allows diagnosing lamp damage in paralleling operations, like
as flasher topology. The Figure 15 summaries test results
covering 99.74% of parts (device ageing not included) for
Standard lamps and LEDs.
0
-40
-20
0
20
40
60
80
100
Board tem perature (°C)
120
140
160
180
Figure 16. Analog temperature precision
The board temperature feedback is not active in Fail
mode.
With a calibration strategy, the temperature monitoring
precision can be improved. So, one calibration point at 25 °C
allows removing part to part contribution, as presented in
Figure 17.
typ
2.5
min
max
CSNS feedback (V)
2
Orange = LED mode
Blue = lamp mode (default mode)
Figure 15. Current sense precision with calibration
strategy for OUT1/5
Board Temperature Feedback
The 10XS3535 provides a voltage proportional to the
temperature on the GND flag. This analog feedback is
1.5
1
0.5
0
-40
-20
0
20
40
60
80
100
Board tem perature (°C)
120
140
160
180
Figure 17. Analog temperature precision with
calibration strategy
Output Status
The 10XS3535 provides the state of OUT1:OUT5 outputs
in real time through SPI. The OUT bit is set to logic [1] when
the corresponding output voltage is closed to half of battery.
This bit allows synchronizing current sense and diagnosing
short-circuit between OUT and VBAT terminals.
TEMPERATURE PREWARNING
The 10XS3535 provides a temperature prewarning
reported via the SPI (OTW bit) in Normal mode. The
information is latched. To delatch, a read SPI command is
needed. In case of a Power on Reset, the fault will be reset.
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
37
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
EXTERNAL PIN STATUS
The 10XS3535 provides the status of the FLASHER, FOG,
and IGN pins via the SPI in real time and in Normal mode.
FAILURE HANDLING STRATEGY
A highly sophisticated failure handling strategy enables
light functionality even in case of failures inside the
component or the light module. Components are protected
against:
• Reverse Polarity
• Loss of Supply Lines
• Fatal Mistreatment of Logic I/O Pins
• all latched faults are maintained under VCC in nominal
conditions. In case VBAT is disconnected, OUT[1:5]
outputs are OFF. OUT6 output state depends on the
previous SPI configuration. The SPI configuration,
reporting (if VBAT was previously in the nominal voltage
range for at least 35 sec), and daisy-chain features are
provided for RST is set to logic [1]. The SPI pull-up and
pull-down current resistors are available. This fault
condition can be diagnosed with UVF fault in OD13
reporting bit. The previous device configuration is
maintained. No current is conducted from VCC to VBAT.
LOSS OF VCC (DIGITAL LOGIC SUPPLY LINE)
In case of a permanently reverse polarity operation, the
output transistors are turned ON (Rsd) to prevent thermal
overloads and no protections are available.
During loss of VCC (VCC < VCCUV ) and with wake=1, the
10XS3535 is switched automatically into Fail mode (no
deglich time). The external SMART MOSFET is OFF. All SPI
registers are reset and must be reprogrammed when VCC
goes above VCCUV. The device will transit in OFF mode if
VBAT < VBATPOR2.
An external diode on VCC is necessary in order to not to
destroy the 10XS3535 in cases of reverse polarity.
LOSS OF VCC AND VBAT
REVERSE POLARITY PROTECTION ON VBAT
In case of negative transients on the VBAT line (per
ISO 7637), the VCC line is still operating, while the VBAT line
is negative. Without loads on OUT1:5 terminal, an external
clamp between VBAT and GND is mandatory to avoid
exceeding maximum rating. The maximum external clamp
voltage shall be between the reverse battery condition and 
-20 V.
Therefore, the device is protected against latch-up with or
without load on OUT outputs.
If the external VBAT and VCC supplies are disconnected (or
not within specification: (VCC and VBAT) < VBATPOR1), all SPI
register contents are reset with default values corresponding
to all SPI bits are set to logic [0] and all latched faults are also
reset.
LOSS OF GROUND (GND)
The 10XS3535 is protected against the loss of any supply
line. The detection of the supply line failure is provided inside
the device itself.
During loss of ground, the 10XS3535 cannot operate the
loads (the outputs (1:5) are switched OFF), but is not
destroyed by the operating condition. Current limit resistors in
the digital input lines protect the digital supply against
excessive current (1kohm typical). The state of the external
smart power switch controlled by FETOUT is not guaranteed,
and the state of external smart MOS is defined with an
external termination resistor.
LOSS OF VBAT
FATAL MISTREATMENT OF LOGIC I / O PINS
During an under-voltage of VBAT (VBATPOR1 <
VBAT < VBATUV), the outputs [1-5] are switched off
immediately. No current path from VBAT to VCC. The
external MOSFET (OUT6) can be controlled in Normal Mode
by the SPI if VCC remains and is above VCCUV. The fault is
reported to the UVF bit (OD13). To delatch the fault, the
under-voltage condition should be removed and:
• To turn-on the output, the corresponding D7 bit must be
rewritten to logic [1] in Normal mode. Application of the
OCHI window depends on toggling or not toggling the
D7 bit.
• If the device was in Fail mode, the fault will be delatched
by the Autorestart feature periodically.
The digital I / Os are protected against fatal mistreatment
by signal plausibility check according to Table 16.
LOSS OF SUPPLY LINES
In case of VBAT < VBATPOR1 (Power OFF mode), the
behavior depends on VCC:
• all latched faults are reset if VCC < VCCUV,
Table 16. Logic I / O Plausibility Check
Input / Output
Signal Check Strategy
LIMP
Debounce for 10ms
(PWM) CLOCK
Frequency range
(bandpass filter)
SPI (MOSI, SCLK, CS)
WD, D10 bit internal toggle
In case the LIMP input is set to logic [1] for a delay longer
than 10ms typical, the 10XS3535 is switched into Fail mode.
In case of a (PWM) Clock failure, no PWM feature is provided
and the bit D7 defines the outputs state. In case of SPI failure,
the 10XS3535 is switched into Fail mode (see Figure 18)
MC10XS3535
38
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
WD Bit D10
1
0
0
timeout
D10 is toggled after
the window watchdog
75ms window watchdog
75ms window watchdog
Fail Mode activation
Figure 18. Watchdog window
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
39
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
Figure 19 below shows full vehicle light functionality, including fog lights, battery redundancy concept, light substitution mode,
and Fail mode.
t
ig
h t
L o Be
w am
Fl Be
as am
P a her
rk
in
g
Li
gh
e
gh
Sp
ar
Li
Li
t
H
gh
g
Fl
ng
Fo
e
ar
t
Sp
gh
Li
g
Fo e a m
B
h
ig eam
B r
e
w
L o as h
i
rk
H
Pa
MOSI, MISO, SCLK
CP
100nF
10XS3535
VBAT
CornerLight
Switch
(Front Left)
VCC
CP
CS
CLOCK
CS
CLOCK
RST
RST
IGN
IGN
FOG
CSNS
gh
ce riv
t
n e
St se Lig
op L
ht
i
g
Fl L i g h t
as h t
h
Ta er
il
Li
gh
t
Li
g
Fo
ea
r
VCC
FLASHER
t
gh
t
Li
gh
og
Li
t
e
rF
r iv i g h
ea
R
rD eL t
h
ea s
R c en Lig
Li op er
h
St
as
F l ht
ig
lL
rD
R
VBAT
i
Ta
Li
ea
100nF
CornerLight
Switch
(Front Right)
LIMP
LIMP
FLASHER
FOG
CSNS
R
10XS3535
100nF
100nF
CP
35XS3500
VBAT
CornerLight
Switch
(Rear Left)
VCC
CS
CS
CLOCK
CLOCK
RST
IGN
CP
35XS3500
RST
IGN
LIMP
FLASHER
LIMP
FLASHER
STOP
STOP
CSNS
CSNS
Microcontroller
Watchdog
VCC
(5.0V)
WD
(5.0V)
VBAT
Ignition
VBAT
CornerLight
Switch
(Rear Right)
VCC
Stop Light
Flasher
VBAT
Figure 19. Typical Application
EMC & EMI PERFORMANCES
The 10XS3535 is compliant to CISPR25 Class5 with 22nF
decoupling capacitor on OUT[1:5]
MC10XS3535
40
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS
PACKAGING
PACKAGING DIMENSIONS
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to
www.freescale.com and perform a keyword search for the drawing’s document number.
Package
24-Pin PQFN
Suffix
Package Outline Drawing Number
HFK and DHFK
98ART10511D
JHFK
98ASA00426D
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
41
PACKAGING
PACKAGING DIMENSIONS
FK SUFFIX
24-PIN PQFN
98ART10511D
ISSUE 0
MC10XS3535
42
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS
FK SUFFIX
24-PIN PQFN
98ART10511D
ISSUE 0
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
PACKAGING
PACKAGING DIMENSIONS
FK SUFFIX
24-PIN PQFN
98ART10511D
ISSUE 0
MC10XS3535
44
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS
FK SUFFIX
24-PIN PQFN
98ART10511D
ISSUE 0
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
45
PACKAGING
PACKAGING DIMENSIONS
FK SUFFIX
24-PIN PQFN
98ASA00426D
ISSUE 0
MC10XS3535
46
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS
FK SUFFIX
24-PIN PQFN
98ASA00426D
ISSUE 0
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
47
PACKAGING
PACKAGING DIMENSIONS
FK SUFFIX
24-PIN PQFN
98ASA00426D
ISSUE 0
MC10XS3535
48
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS
FK SUFFIX
24-PIN PQFN
98ASA00426D
ISSUE 0
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
49
PACKAGING
PACKAGING DIMENSIONS
FK SUFFIX
24-PIN PQFN
98ASA00426D
ISSUE 0
MC10XS3535
50
Analog Integrated Circuit Device Data
Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
Revision
Date
Description of Changes
5/2010
•
Initial Release
2.0
7/2010
•
•
Changed PN to MC10XS3535PNA
Changed classification to Advance Information
3.0
9/2010
•
•
•
•
•
Added Minimum Output Current Reported in CSNS for OUT[2-4](15) to Table 3.
Added Minimum Output Current Reported in CSNS for OUT[1,5](15) to Table 3.
Added Minimum Output Current Reported in CSNS for OUT[2-4] in LED Mode(15) to Table 3.
Added Minimum Output Current Reported in CSNS for OUT[1,5] in LED Mode(15) to Table 3.
Added Note: Output current value computed after leakage current removal (open load condition)to
Table 3.
4.0
5/2011
•
Added Under-voltage Deglitch Time parameter.
5.0
4/2012
•
•
Added Orderable Part Number PC10XS3535HFK
Corrected errors in Table 11 and Table 14
6.0
6/2012
•
Removed MC10XS3535PNA from the ordering information and changed PC10XS3535HFK to
MC10XS3535HFK.
Added (4)
Updated Under-voltage Deglitch Time t UV parameter in Table 5, Dynamic Electrical Characteristics
on page 15
Updated Freescale form and style
1.0
•
•
•
7.0
12/2012
•
Added “if VBAT was previously in the nominal voltage range for at least 35 sec” to Loss of VBAT
Section.
Added MC10XS3535DHFK to the ordering information.
•
8.0
3/2013
•
•
Added MC10XS3535JHFK to ordering information.
Added 98ASA00426D package information.
9.0
4/2013
•
•
Clarified MC10XS3535JHFK in Table 1 and in Packaging Dimensions
Revised back page. Updated document properties. Added SMARTMOS sentence to first
paragraph.
10
8/2013
•
•
Changed CSNS conditions for CSNS Tri-state Leakage Current
Changed upper and lower limits for Driver Output Matching Time (t DLY(ON) - t DLY(OFF)) @
Output = 50% VBAT with VBAT = 14 V, f PWM = 240 Hz, PWM = 50%, @ 25 °C
Corrected conditions for FETIN Leakage Current when external current switch sense is enabled
•
MC10XS3535
Analog Integrated Circuit Device Data
Freescale Semiconductor
51
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© 2013 Freescale Semiconductor, Inc.
Document Number: MC10XS3535
Rev. 10.0
8/2013