FREESCALE PC33480PNA

Freescale Semiconductor
Technical Data
Document order number: MC33480
Rev 2.0, 1/2006
Smart Front Corner Light
Switch (Triple 10 mΩ and Dual
35 mΩ)
33480
The 33480 is designed for low-voltage automotive and industrial
lighting applications. Its five low RDS(ON) MOSFETs (three 10 mΩ,
two 35 mΩ) can control the high sides of five separate resistive loads
(bulbs).
Programming, control, and diagnostics are accomplished using a
16-bit SPI interface. Each output has its own PWM control via SPI.
The 33480 has highly sophisticated failure mode handling to provide
high availability of the outputs. Its multiphase control and output edge
shaping improves electromagnetic compatibility (EMC) behavior.
The 33480 is packaged in a power-enhanced 12 x 12 nonleaded
Power QFN package with exposed tabs.
HIGH-SIDE SWITCH
Bottom View
Features
•
•
•
•
•
•
•
•
•
•
•
PNASUFFIX
98ARL10596D
24-TERMINAL PQFN
Triple 10 mΩ and Dual 35 mΩ High-Side Switches
16-bit SPI Communication Interface with Daisy Chain Capability
Current Sense Output with SPI-Programmable Multiplex Switch
Digital Diagnosis Feature
PWM Module with Multiphase Feature
Fully Protected Switches
Overcurrent Shutdown detection
Power Net and Reverse Polarity Protection
Low-Power Mode
Fail Mode Functions including Autorestart feature
External smart power switch control including current recopy
12 V
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
PC33480PNA/R2
-40°C to 125°C
24 PQFN
5.0 V
12 V
33480
VCC
Watchdog
VBAT
CP
LIMP
OUT1
FLASHER
IGN
OUT2
RSTB
MCU
CLOCK
OUT3
CS
OUT4
SO
OUT5
SI
SCLK
FETIN
CSNS
FETOUT
GND
Smart
Switch
Figure 1. 33480 Simplified Application DiagraM
* This document contains information on a product under development.
Freescale reserves the right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VCC
VBAT
Vcc failure
detection
Internal
Regulator
CP
OV/UV/POR
detections
Charge Pump
IUP
CS
SO
SPI
3.0 MHz
SI
PWM
Module
SCLK
Gate Drive
drain/gate clamp
IDWN
OUT1
Logic
Overcurrent
Detection
(fault management)
CLOCK
LIMP
FLASHER
IGN
RSTB
Open Load
Detection
Overtemperature
Detection
OUT1
IDWN
RDWN
OUT2
OUT3
Overtemperature
Prewarning
OUT4
OUT5
OUT2
OUT3
OUT4
OUT5
Selectable Output Current
Recopy (Analog MUX)
CSNS
Vcc
FETIN
Driver for External
MOSFET
FETOUT
GND
Figure 2. 33480 Simplified Internal Block Diagram
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2
Analog Integrated Circuit Device Data
Freescale Semiconductor
TERMINAL CONNECTIONS
SCLK
CS
NC
LIMP
CLOCK
FLASHER
RSTB
IGN
FETIN
8
7
6
5
4
3
2
1
CP
16
GND
17
OUT5
18
VCC
9
SO
13 12 11 10
FETOUT
SI
TERMINAL CONNECTIONS
14
GND
24
CSNS
23
GND
22
OUT1
15
VBAT
19
20
21
OUT4
OUT3
OUT2
Figure 3. 33480 Terminal Connections (Transparent Top View Of Package)
Table 1. 33480 Terminal Definitions
A functional description of each terminal can be found in the Functional Terminal Description section beginning on Page 17.
Terminal
Number
Terminal
Name
Terminal
Function
Formal Name
1
FETIN
Input
External FET Input
2
IGN
Input
Ignition Input
(Active High)
This input wakes the device. It also controls the Outputs 1 and 2 in case of Fail
mode activation. This terminal has a passive internal pulldown.
3
RSTB
Input
Reset
This input wakes the device. It is also used to initialize the device configuration
and fault registers through SPI. This digital terminal has a passive internal
pulldown.
4
FLASHER
Input
Flasher Input
(Active High)
This input wakes the device. The Fail mode can be activated by this digital input.
This terminal has a passive internal pulldown.
5
CLOCK
Input
Clock Input
The PWM frequency and timing are generated from this digital clock input by
the PWM module. This terminal has an active internal pulldown current source.
6
LIMP
Input
Limp Home Input
(Active High)
The Fail mode can be activated by this digital input. This terminal has an active
internal pulldown current source.
7
NC
NC
No Connect
No internal connection to this terminal.
8
CS
Input
Chip Select
(Active Low)
When this digital signal is high, SPI signals are ignored. Asserting this terminal
low starts an SPI transaction. The transaction is signaled as completed when
this signal returns high. This terminal has an active internal pullup current
source.
9
SCLK
Input
SPI Clock Input
This digital input terminal is connected to the master microcontroller providing
the required bit shift clock for SPI communication. This terminal has an active
internal pulldown current source.
Definition
This terminal is the current sense recopy of the external SMART MOSFET.
33480
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
TERMINAL CONNECTIONS
Table 1. 33480 Terminal Definitions (continued)
A functional description of each terminal can be found in the Functional Terminal Description section beginning on Page 17.
Terminal
Number
Terminal
Name
Terminal
Function
Formal Name
Definition
10
SI
Input
Master-Out SlaveIn
This data input is sampled on the positive edge of the SCLK. This terminal has
an active internal pulldown current source.
11
VCC
Power
Logic Supply
12
SO
Output
Master-In SlaveOut
SPI data is sent to the MCU by this terminal. This data output changes on the
negative edge of SCLK and when CS is high, this terminal is high impedance.
13
FETOUT
Output
External FET Gate
This terminal controls an external SMART MOSFET by logic level. This output
is also called OUT6.
14,17,23
GND
Ground
Ground
15
VBAT
Power
Battery Input
Power supply terminal.
16
CP
Output
Charge Pump
This terminal is the connection for an external tank capacitor (for internal use
only).
18
OUT1
OUT5
Output
Output 1
Output 5
Protected 35 mΩ high-side power output to the load.
OUT2
OUT3
OUT4
Output
Output 2
Output 3
Output 4
Protected 10 mΩ high-side power output to the load.
CSNS
Output
Current Sense
Output
22
19
20
21
24
SPI Logic power supply.
This terminal is the ground for the logic and analog circuitry of the device(1).
This terminal is used to output a current proportional to OUT1:OUT5, FET in
current, and it is used externally to generate a ground-referenced voltage for the
microcontroller to monitor output current. OUT1:OUT5 and FET in choice is SPI
programmable.
Notes
1. The pins 14, 17 and 23 must be shorted on the board.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
MAXIMUM RATINGS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
Overvoltage Test Range (all OUT[1:5] ON with nominal DC current)
VBAT
V
2.0 Hours @ 25°C
20
1.0 Min @ 25°C
27
Load Dump (400 ms) @ 25°C
40
Reverse Polarity Voltage Range (all OUT[1:5] ON with nominal DC current)
VBAT
2.0 Min @ 25°C
V
- 15
VCC Supply Voltage
VCC
OUT[1:5] Voltage
VOUT
-0.3 to 5.5
V
Positive
40
Negative (ground disconnected)
-16
Digital Input Current in Clamping Mode (SI, SCLK, CS, IGN, FLASHER, LIMP)
SO and FETOUT Outputs Voltage
FET in Input Current
IIN
5.0
mA
VSO
- 0.3 to VCC + 0.3
V
IFET in
10
mA
E1,5
85
E2,3,4
300
Outputs clamp energy using single pulse method (L=2mH; R=0; Vbat=14V
@150°C initial)
OUT[1,5]
OUT[2:4]
ESD Voltage (2)
V
mJ
VESD
V
Human Body Model (HBM)
±2kV
Human Body Model (HBM) OUT [1:5]
±8kV
Charge Device Model (CDM)
TBD
THERMAL RATINGS
Operating Temperature
°C
Ambient
TA
- 40 to 125
Junction
TJ
- 40 to 150
TSOLDER
260
°C
TSTG
- 55 to 150
°C
RθJC
1.0
°K/W
Peak Terminal Re-flow Temperature During Solder Mounting
Storage Temperature
(3)
THERMAL RESISTANCE
Thermal Resistance, Junction to Case (4)
Notes
2. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω) and the Charge Device
Model.
3. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits
may cause malfunction or permanent damage to the device. If the qualification fails, TSOLDER will be changed for 240°C.
4.
Typical value guaranteed per design.
33480
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VBAT ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Full Performance & Short Circuit
7.0
–
18.0
Extended Voltage Range (5)
6.0
–
20.0
VBATUV
5.0
5.3
6.0
V
VBATCLAMP
41.0
47.0
53.0
V
VBATPOR
–
4.2
5.0
V
IBATSLEEP
–
0.5
5.0
µA
IBAT
–
10.0
20.0
mA
VCC
4.5
–
5.5
V
VCCUV
2.5
3.0
3.5
POWER INPUTS (VBAT, VCC)
Battery Supply Voltage Range
Battery Supply Undervoltage (UV flag is set ON)
Battery Voltage Clamp (OV flaf is set ON)
Battery Supply Power on Reset (If Vbat < 5.5V, Vbat = Vcc)
VBAT
V
VBAT Supply Current @ 25°C and VBAT = 12 V and VCC = 5 V
Sleep State Current
Normal Mode, IGN=5V, RSTB=5V, Outputs Open
Digital Supply Voltage Range, Full Performance
Digital Supply Undervoltage (VCC Failure)
Standby Current Consumption on VCC @ 25°C and VBAT = 12 V
IQCC
Output OFF
Supply Current Consumption on VCC and VBAT = 12 V
V
µA
–
TBD
5.0
ICC
mA
No SPI
–
–
1.0
3.0 MHz SPI Communication
–
–
5.0
LOGIC INPUT/OUTPUT (IGN, CS, CSNS, SI, SCLK, CLOCK, SO, FLASHER, RSTB, LIMP)
Input High Logic Level (6)
VIH
0.7
–
–
Vcc
Input Low Logic Level (6)
VIL
–
–
0.3
Vcc
Ignition Threshold Level (IGN)
VIGNth
2.0
–
4.0
V
Input Clamp Voltage (IGN)
VIGNcl
7.0
–
14.0
- 2.0
–
-0.3
IDWN
5.0
–
20.0
µA
IUP
5.0
–
20.0
µA
Input Passive Pulldown Resistance (7)
RDWN
100
200
400
kΩ
SO High-State Output Voltage
VSOH
0.8
TBD
–
Vcc
IIGN < 2.5 mA
Input Forward Voltage (IGN)
VIGNfr
IIGN = -2.5 mA
Input Active Pulldown Current for LIMP, SI, SCLK and CLOCK inputs
Input Active Pullup Current (CS)
IOH = 1.0 mA
SO Low-State Output Voltage
V
V
VSOL
IOL = -1.6 mA
V
–
0.2
0.4
Notes
5. In extended mode, the functionality is guaranteed but not the electrical parameters.
6. Valid for RSTB, SI, SCLK, CLOCK, FLASHER and LIMP terminals.
7. Valid for FLASHER, IGN and RSTB terminals.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VBAT ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
- 1.0
0.0
1.0
5.0
6.0
7.0
- 20.0
–
-16.0
41.0
47.0
53.0
Unit
LOGIC INPUT/OUTPUT (IGN, CS, CSNS) (CONTINUED)
SO Tri-State Leakage Current
Current Sense Output Clamp Voltage
µA
ISOLEAK
CS > 0.7 VCC
VCSNS
V
ICSNS<10mA
OUTPUTS (OUT 1-5)
Output Negative Clamp Voltage
VOUT
IOUT = - 500 mA, Outputs OFF
Drain to Source Clamp Voltage
V
VDSCLAMP
IOUT = + 500 mA, Outputs shorted to ground
V
IOUT =OCHI, this parameter is guaranteed by design
Current Sense Output Precision (8)
ICS / ICS
%
Full-Scale Range (FSR)
0.75 FSR
–
TBD
TBD
0.50 FSR
–
TBD
TBD
0.25 FSR
–
TBD
TBD
0.10 FSR
–
TBD
TBD
∆ ICS /∆T
–
TBD
± 400
ppm/°C
TOTS
160
175
190
°C
TOTSWARN
110
125
140
°C
VBAT = 13.5 V
–
–
35
VBAT = 7.0 V
–
–
55
–
–
59.5
–
–
70
Temperature Drift of Current Sense Output (9)
VBAT=13.5V, IOUT1,5=2.8 A, IOUT2-4=5.5 A, reference taken at
TA=25°C
Over Temperature Shutdown
Thermal PreWarning
PARKING LIGHT OUT1
Output Drain-to-Source ON Resistance (IOUT = 2.8 A, TA = 25°C)
Output Drain-to-Source ON Resistance (IOUT = 2.8 A, VBAT = 13.5 V,
RDS(ON)
RDS(ON)
TA = 150°C) (10)
Reverse Output ON Resistance (IOUT = -2.8 A, TA = 25°C) (11)
mΩ
RSD(ON)
VBAT = -12 V
High Over Current Shutdown Threshold 1(10)
mΩ
IOCHI1
mΩ
27.7
34.6
38.9
VBAT = 16 V, TA = -40°C
TBD
TBD
TBD
VBAT = 16 V, TA = 25°C
TBD
34.6
TBD
VBAT = 16 V, TA = 125°C
TBD
TBD
TBD
A
Notes
8. TA = 25°C. δICS / ICS= (measured ICS - targeted ICS)/ targeted ICS with targeted ICS=5mA
9. Based on statistical data. Not production tested. ∆ ICS /∆T= [(measured ICS at T1 - measured ICS at T2) / measured ICS at room] / (T1 - T2)
10.
11.
Parameter guaranteed by design; however, it is not production tested.
Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VBAT.
33480
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VBAT ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
High Over Current Shutdown Threshold 2
IOCHI2
11.9
14.9
17.9
A
Low Over Current Shutdown Threshold
IOCLO
5.6
6.7
7.7
A
IOL
0.05
0.2
0.5
PARKING LIGHT OUT1(CONTINUED)
Open Load Current Threshold in ON State (12)
Open Load Current Threshold in ON State with LED (13)
IOLLED
VOUT = VBAT - 0.5 V
Current Sense Full-Scale Range
(14)
A
mA
5.0
10.0
20.0
ICS FSR
–
6.0
–
A
Severe short-circuit impedance detection for Vbat=20V without artificial
network (15)
RSC1(OUT1)
TBD
–
–
mΩ
Severe short-circuit impedance detection for Vbat=20V with artificial
network L=10µH, R=20mohm (15)
RSC2(OUT1)
TBD
–
–
mΩ
VBAT = 13.5 V
–
–
10
VBAT = 7.0 V
–
–
15
–
–
17.0
–
–
20
LOW BEAM OUT2
Output Drain-to-Source ON Resistance (IOUT = 5.5 A, TA = 25°C)
Output Drain-to-Source ON Resistance (IOUT = 2.8 A, VBAT = 13.5 V,
RDS(ON)
RDS(ON)
TA = 150°C) (15)
Reverse Source-to-Drain ON Resistance (IOUT = -2.8 A, TA = 25°C) (16)
mΩ
RSD(ON)
VBAT = -12 V
High Over Current Shutdown Threshold 1(15)
mΩ
IOCHI1
mΩ
61.6
77.0
92.4
VBAT = 16 V, TA = -40°C
TBD
TBD
TBD
VBAT = 16 V, TA = 25°C
TBD
77.0
TBD
VBAT = 16 V, TA = 125°C
TBD
TBD
TBD
26.5
33.2
39.8
High Over Current Shutdown Threshold 2
IOCHI2
Low Over Current Shutdown Threshold
IOCLO
18.6
22.2
25.8
Optional H7 Bulb
12.4
14.8
17.2
0.1
0.4
1.0
Open Load Current Threshold in ON State with LED (18)
IOL
IOLLED
VOL = VBAT - 0.5 V
10.0
20.0
Optional Xenon Bulb
–
20.0
–
Optional H7 Bulb
–
13.3
–
Notes
12.
13.
14.
15.
16.
17.
18.
19.
A
mA
5.0
Current Sense Full-Scale Range(19)
A
A
Optional Xenon Bulb
Open Load Current Threshold in ON State (17)
A
ICS FSR
A
OLLED1, bit D0 in SI data is set to [0].
OLLED1, bit D0 in SI data is set to [1].
For typical value of ICS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is no more guaranteed.
Parameter guaranteed by design; however, it is not production tested.
Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VBAT..
OLLED2, bit D1 in SI data is set to [0].
OLLED2, bit D1 in SI data is set to [1].
For typical value of ICS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is no more guaranteed
33480
8
Analog Integrated Circuit Device Data
Freescale Semiconductor
STATIC ELECTRICAL CHARACTERISTICS
This paragraph is boilerplate - you may add to it but, can not change wording. You may change numeric values
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VBAT ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
RSC1(OUT2)
TBD
–
–
mΩ
RSC2(OUT2)
TBD
–
–
mΩ
VBAT = 13.5 V
–
–
10
VBAT = 7.0 V
–
–
15
LOW BEAM OUT2 (continued)
Severe short-circuit impedance detection for Vbat=20V without artificial
network (20)
Severe short-circuit impedance detection for Vbat=20V with artificial
network L=10µH, R=20mohm (20)
HIGH BEAM OUT3
Output Drain-to-Source ON Resistance (IOUT = 5.5 A, TA = 25°C)
Output Drain-to-Source ON Resistance (IOUT = 2.8 A, VBAT = 13.5 V,
TA = 150°C)
RDS(ON)25
mΩ
RDS(ON)150
mΩ
–
(20)
Reverse Source-to-Drain ON Resistance (IOUT = -2.8 A, TA = 25°C) (21)
–
17.0
RSD(ON)25
VBAT = -12 V
mΩ
–
–
20
IOCHI1
61.6
77.0
92.4
VBAT = 16 V, TA = -40°C
IOCHI1_40
TBD
TBD
TBD
VBAT = 16 V, TA = 25°C
IOCHI1_25
TBD
77.0
TBD
VBAT = 16 V, TA = 125°C
IOCHI1_125
TBD
TBD
TBD
IOCHI2
26.5
33.2
39.8
A
IOCLO
12.4
14.8
17.2
A
IOL
0.1
0.4
1.0
A
5.0
10.0
20.0
ICS FSR
–
13.3
–
A
RSC1(OUT3)
TBD
–
–
mΩ
RSC2(OUT3)
TBD
–
–
mΩ
High Over Current Shutdown Threshold 1
High Over Current Shutdown Threshold 2
Low Over Current Shutdown Threshold
Open Load Current Threshold in ON State
(22)
Open Load Current Threshold in ON State with LED
(23)
IOLLED
VOL = VBAT - 0.5 V
Current Sense Full-Scale Range (24)
Severe short-circuit impedance detection for Vbat=20V without artificial
network (20)
Severe short-circuit impedance detection for Vbat=20V with artificial
network L=10µH, R=20mohm (20)
A
mA
Notes
20. Parameter guaranteed by design; however, it is not production tested.
21. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VBAT.
22.
23.
24.
OLLED3, bit D2 in SI data is set to [0].
OLLED3, bit D2 in SI data is set to [1].
For typical value of ICS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is no more guaranteed.
33480
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VBAT ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
VBAT = 13.5 V
–
–
10
VBAT = 7.0 V
–
–
15
Unit
FOG LIGHT OUT4
Output Drain-to-Source ON Resistance (IOUT = 5.5 A, TA = 25°C)
Output Drain-to-Source ON Resistance (IOUT = 2.8 A, VBAT = 13.5 V,
TA = 150°C)
RDS(ON)25
RDS(ON)150
(25)
Reverse Source-to-Drain ON Resistance (IOUT = -2.8 A, TA = 25°C) (26)
VBAT = 16 V, TA = -40°C
mΩ
–
–
17.0
–
–
20
RSD(ON)25
VBAT = -12 V
High Over Current Shutdown Threshold 1 (25)
mΩ
mΩ
IOCHI1
61.6
77.0
92.4
IOCHI1_40
TBD
TBD
TBD
A
IOCHI1_25
TBD
77.0
TBD
IOCHI1_125
TBD
TBD
TBD
High Over Current Shutdown Threshold 2
IOCHI2
26.5
33.2
39.8
A
Low Over Current Shutdown Threshold
IOCLO
12.4
14.8
17.2
A
IOL
0.1
0.4
1.0
A
5.0
10.0
20.0
ICS FSR
–
13.3
–
A
RSC1(OUT4)
TBD
–
–
mΩ
RSC2(OUT4)
TBD
–
–
mΩ
VBAT = 13.5 V
–
–
35
VBAT = 7.0 V
–
–
55
VBAT = 16 V, TA = 25°C
VBAT = 16 V, TA = 125°C
Open Load Current Threshold in ON State (27)
Open Load Current Threshold in ON State with LED (28)
IOLLED
VOL = VBAT - 0.5 V
Current Sense Full-Scale Range (29)
Severe short-circuit impedance detection for Vbat=20V without artificial
network (25)
Severe short-circuit impedance detection for Vbat=20V with artificial
network L=10µH, R=20mohm (25)
mA
FLASHER OUT5
Output Drain-to-Source ON Resistance (IOUT = 2.8 A, TA = 25°C)
RDS(ON)25
mΩ
Notes
25. Parameter guaranteed by design; however, it is not production tested.
26. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VBAT.
27.
28.
29.
OLLED4, bit D3 in SI data is set to [0].
OLLED4, bit D3 in SI data is set to [1].
For typical value of ICS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is no more guaranteed.
33480
10
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VBAT ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
–
–
59.5
–
–
70
IOCHI1
27.7
34.6
38.9
VBAT = 16 V, TA = -40°C
IOCHI1_40
TBD
TBD
TBD
VBAT = 16 V, TA = 25°C
IOCHI1_25
TBD
34.6
TBD
IOCHI1_125
TBD
TBD
TBD
IOCHI2
11.9
14.9
17.9
A
IOCLO
5.6
6.7
7.7
A
IOL
0.05
0.2
0.5
A
5.0
10.0
20.0
ICS FSR
–
6.0
–
A
RSC1(OUT5)
TBD
–
–
mΩ
RSC2(OUT5)
TBD
–
–
mΩ
FET out Output High Level @ I = 1.0 mA
VH MAX
0.8
–
–
VCC
FET out Output Low Level @ I = -1.0 mA
VH MIN
–
0.2
0.4
V
FET in Input Full Scale Range Current
IFET in
–
5.0
–
mA
FET in Input Clamp Voltage
VCLIN
5.3
–
7.0
0.0
–
0.3
FLASHER OUT5 (CONTINUED)
Output Drain-to-Source ON Resistance (IOUT = 2.8 A, VBAT = 13.5 V,
TA = 150°C)
RDS(ON)150
(30)
Reverse Source-to-Drain ON Resistance (IOUT = -2.8 A, TJ = 25°C) (31)
RSD(ON)25
VBAT = -12 V
High Over Current Shutdown Threshold 1 (30)
VBAT = 16 V, TA = 125°C
High Over Current Shutdown Threshold 2
Low Over Current Shutdown Threshold
Open Load Current Threshold in ON State
(32)
Open Load Current Threshold in ON State with LED (33)
Severe short-circuit impedance detection for Vbat=20V without artificial
network (30)
Severe short-circuit impedance detection for Vbat=20V with artificial
network L=10µH, R=20mohm (30)
mΩ
IOLLED
VOL = VBAT - 0.5 V
Current Sense Full-Scale Range (33)
mΩ
A
mA
SPARE FETOUT / FETIN
IFET in= 5mA, CSNS open
Drop Voltage on FET in (FET in - CSNS)
IFET in= 5mA, CSNS = 5V
V
VDRIN
V
Notes
30. Parameter guaranteed by design; however, it is not production tested.
31. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VBAT.
32.
33.
34.
OLLED5, bit D4 in SI data is set to [0].
OLLED5, bit D4 in SI data is set to [1].
For typical value of ICS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is no more guaranteed.
33480
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VBAT ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Current Sense rising and falling Settling Time on resistive load only (Maximum
Value, 5%)
t R5 / t F5
–
2
10
µs
Current Sense rising and falling Settling Time on resistive load only (Maximum
Value, 1%)
t R1 / t R5
–
TBD
TBD
µs
0.2
0.4
0.8
0.2
0.4
0.8
0.2
0.4
0.8
0.2
0.4
0.8
0.8
1.0
1.2
0.8
1.0
1.2
POWER OUTPUTS TIMING (OUT1 to OUT5)
Driver Output Positive Slew Rate (30% to 70% @ VBAT = 14 V)
SRR
IOUT = 2.8 A for OUT1 and OUT5
IOUT = 5.5 A for OUT2, OUT3, and OUT4
Driver Output Negative Slew Rate (70% to 30% @ VBAT = 14 V)
SRF
IOUT = 2.8 A for OUT1 and OUT5
IOUT = 5.5 A for OUT2, OUT3, and OUT4
Driver Output Matching Slew Rate (SRR /SRF) (70% to 30% @ VBAT = 14 V
@25°C)
V/µs
V/µs
∆ SR
IOUT = 2.8 A for OUT1 and OUT5
IOUT = 5.5 A for OUT2, OUT3, and OUT4
Driver Output Turn-ON Delay (SPI ON Command [No PWM, CS Positive Edge]
to Output = 50% VBAT @ VBAT = 14 V) (
µs
t DLYON
IOUT = 2.8 A for OUT1 and OUT5
40
80
160 (TBC)
IOUT = 5.5 A for OUT2, OUT3, and OUT4
40
80
160 (TBC)
Driver Output Turn-OFF Delay (SPI OFF command [CS Positive Edge] to
Output = 50% VBAT @ VBAT = 14 V) (see Figure4, p14)
µs
t DLYOFF
IOUT = 2.8 A for OUT1 and OUT5
40
80
160 (TBC)
IOUT = 5.5 A for OUT2, OUT3, and OUT4
40
80
160 (TBC)
Driver Output Matching Time (t DLY(ON) - t DLY(OFF)) @ Output = 50% VBAT with
VBAT = 14 V, f PWM = 240 Hz, δPWM = 50%, @25°C
µs
∆ t RF
IOUT = 2.8 A for OUT1 and OUT5
IOUT = 5.5 A for OUT2, OUT3, and OUT4
- 25
0
25
- 25
0
25
PWM MODULE
PWM Frequency Range
f PWM
60.0
–
240.0
Hz
Clock Input Frequency Range
f CLK
7.68
–
30.72
kHz
PWM_MAX
4.0
–
96.0
%
PWM_LIN
6.2 (TBC)
–
96.0 (TBC)
%
t WDTO
50
75
100
ms
t SD
–
7
30
µs
Output PWM Duty Cycle maximum range for 11V<Vbat<18V (35)
Output PWM Duty Cycle linear range for 11V<Vbat<18V (36)
WATCHDOG TIMING
Watchdog Timeout (SPI Failure)
I/O PLAUSIBILITY CHECK TIMING
Fault Shutdown Delay Time (from Overtemperature or OCHI1 or OCHI2 or
OCLO Fault Detection to Output = 50% VBAT without round shaping feature
for turn off)
33480
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VBAT ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
I/O PLAUSIBILITY CHECK TIMING (CONTINUED)
ms
High Overcurrent Threshold Time 1
for OUT1 and OUT5
t OUT1
7
10
13
for OUT2:4
t OUT2
14
20
26
for OUT1 and OUT5
t OUT1
52.5
75
97.5
for OUT2:4
t OUT2
105
150
195
for OUT1 and OUT5
tAUTORST-T1
52.5
75
97.5
for OUT2
tAUTORST-T2
105
150
195
for OUT1 and OUT5
t OCHIARS
3.5
5.0
6.5
for OUT2
t OCHIARS
7.0
10.0
13.0
t LIMP
7.0
10.0
13.0
ms
t OLLED
105
150
195
ms
Flasher Toggle Timeout
t FLASHER
1.4
TBD
TBD
s
Ignition Toggle Timeout
t IGNITION
1.4
TBD
TBD
s
Clock Input Low Frequency Detection Range
f LCLK det
1.0
2.0
4.0
kHz
Clock Input High Frequency Detection Range
f HCLK det
100
200
400
kHz
ms
High Overcurrent Threshold Time 2
ms
Autorestart Period
ms
Autorestart Overcurrent Shutdown Delay Time
Limp Home Input pin Deglicher Time
Cyclic Open Load Detection Timing with LED (37)
Notes
35. The PWM ratio is measured at Vout = 50% of VBAT in nominal range of PWM frequency (from 60Hz to 200Hz). It is possible to put the
device fully on (PWM duty cycle = 100%) and fully off (PWM duty cycle = 0%). Between 4%-96%, OCHI1,2, OCLO and open load are
available in ON state.See Figure 4, Input Timing Switching Characteristics
36. Linear range is defined by output duty cycle to SPI duty cycle configuration +/-1 LSB. For values outside linear duty cycle range, a
calibration curve is available.
37. IOLLEDn bit (where “n” corresponds to respective outputs 1 through 5) in SI data is set to logic [1]. Refer to Table 8, Serial Input Address
and Configuration Bit Map, page 28.
33480
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VBAT ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
f SPI
–
–
3.0
MHz
t CS
–
–
300
ns
t LEAD
–
50
167
ns
t WSCLKh
–
–
167
ns
t WSCLKl
–
–
167
ns
SPI INTERFACE CHARACTERISTICS
Maximum Frequency of SPI Operation
Rising Edge of CS to Falling Edge of CS (Required Setup Time)
(38)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
Required High State Duration of SCLK (Required Setup Time)
(38)
Required Low State Duration of SCLK (Required Setup Time)
(38)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
(38)
(38)
t LAG
–
50
167
ns
SI to Falling Edge of SCLK (Required Setup Time)
(39)
t SI(SU
–
25
83
ns
Falling Edge of SCLK to SI (Required Setup Time)
(39)
t SI HOLD
–
25
83
ns
–
25
50
SO Rise Time
t RSO
CL = 200 pF
SO Fall Time
t FSO
CL = 200 pF
SI, CS, SCLK, Incoming Signal Rise Time
SI, CS, SCLK, Incoming Signal Fall Time
ns
(39)
(39)
ns
–
25
50
t RSI
–
–
50
ns
t FSI
–
–
50
ns
Time from Falling Edge of CS to SO Low Impedance
(40)
t SO(EN)
–
–
145
ns
Time from Rising Edge of CS to SO High Impedance
(41)
t SO(DIS)
–
65
145
ns
–
65
105
Time from Rising Edge of SCLK to SO Data Valid
0.2 Vcc ≤ SO ≥ 0.7 Vcc, CL = 200 pF
Notes
38.
39.
40.
41.
42.
(42)
t VALID
ns
Maximum setup time required for the 33480 is the minimum guaranteed time needed from the microcontroller.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at SO. 1.0 kΩ on pullup on CS.
Time required for output status data to be terminated at SO. 1.0 kΩ on pullup on CS.
Time required to obtain valid data out from SO following the rise of SCLK.
33480
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
TIMING DIAGRAMS
TIMING DIAGRAMS
VIH
V
IH
RSTB
RST
0.2
VDD
0.2
VDD
VIL
VIL
TwRSTB
t
tTCSB
CS
ENBL
TENBL
VIH
V
0.7
Vcc
0.7VDD
CS
CSB
IH
0.2
Vcc
0.7VDD
t WSCLKh
TwSCLKh
tTlead
LEAD
VIL
V
IL
t RSI
TrSI
t LAG Tlag
0.70.7VDD
Vcc
SCLK
SCLK
VIH
VIH
0.2 Vcc
0.2VDD
VIL
V
t TSIsu
SI(SU)
IL
t WSCLKl
TwSCLKl
tTfSI
FSI
t SI(HOLD)
TSI(hold)
SI
SI
VIH
V
0.7
Vcc
0.7 VDD
0.2VDD
0.2 Vcc
Don’t Care
Don’t Care
Valid
Valid
Don’t Care
IH
VIL
VIL
Figure 4. Input Timing Switching Characteristics
t FSI
t RSI
TrSI
TfSI
VOH
VOH
3.5 V
3.5V
50%
SCLK
SCLK
1.0VV
1.0
VOL
VOL
t SO(EN)
TdlyLH
SO
SO
0.7 V
VDD
cc
0.20.2
VDD
Vcc
Low-to-High
Low
to High
TrSO
t RSO
VOH
VOH
VOL
VOL
VALID
tTVALID
SO
TfSO
t FSO
SO
VOH
VOH
Vcc
VDD
High to Low 0.70.7
High-to-Low
0.2VDD
0.2 Vcc
TdlyHL
VOL
VOL
tSO(DIS)
Figure 5. SCLK Waveform and Valid SO Data Delay Time
33480
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33480 is designed for low-voltage automotive and
industrial lighting applications. Its five low RDS(ON) MOSFETs
(three 10 mΩ and two 35 mΩ) can control the high sides of
five separate resistive loads (bulbs). Programming, control,
and diagnostics are accomplished using a 16-bit SPI
interface.
FUNCTIONAL TERMINAL DESCRIPTION
SUPPLY VOLTAGE (VBAT)
The VBAT terminal of the 33480 is the power supply of the
device. In addition to its supply function, this tab contributes
to the thermal behavior of the device by conducting the heat
from the switching MOSFETs to the printed circuit board.
SUPPLY VOLTAGE (VCC)
This is an external voltage input terminal used to supply
the SPI digital portion of the circuit and the gate driver of the
external SMART MOSFET.
GROUND (GND)
This terminal is the ground of the device.
CLOCK INPUT (CLOCK)
The PWM frequency and timing are generated from clock
input by the PWM module. The clock input frequency is the
factor 27 = 128 of the PWM frequency (60 Hz to 240 Hz). The
OUT1:6 can be controlled in the range of 4% to 96% with a
resolution of 7 bits of duty cycle (bits D[6:0]).
The following table describes the PWM resolution.
On/Off
(Bit D7)
Duty cycle (7 bits
resolution)
Output state
0
X
OFF
1
0000000
PWM (1/128 duty cycle)
1
0000001
PWM (2/128 duty cycle)
1
0000010
PWM (3/128 duty cycle)
1
1111111
fully ON
The timing includes four programmable PWM switching
phases (0°, 90°, 180°, and 270°) to improve overall EMC
behavior of the light module.
The amplitude of the input current is divided by four while
the frequency is 4 times the original one. The two following
pictures illustrate this behavior.
The synchronization of the switching phases between
different corner light IC is provided by an SPI command in
combination with the CS input. The bit in the SPI is called
PWM sync (initialization register).
In Normal Mode, no PWM feature (100% duty cycle) is
provided in the following instances:
• with the following SPI configuration: D7:D0=FF.
• In case of clock input signal failure (out of f PWM), the
outputs state depends of D7 bit value (D7=1=ON) in
Normal Mode.
In Fail mode. The ouputs state depends of IGN and
Flasher terminals.
LIMP HOME INPUT (LIMP)
The Fail mode of the component can be activated by this
digital input port. The signal is “high active”, meaning the Fail
mode can be activated by a logic high signal at the input.
33480
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL TERMINAL DESCRIPTION
IGNITION INPUT (IGN)
The ignition input wakes the device. It also controls the Fail
mode activation. The signal is “high active”, meaning the
component is active in case of a logic high at the input.
FETout is not protected in case of short circuit or
undervoltage on Vbat.
In case of reverse battery, OUT6 is OFF.
FET IN INPUT (FETIN)
FLASHER INPUT (FLASHER)
The flasher input wakes the device. It also controls the Fail
Mode activation. The signal is “high active”, meaning the
component is active in case of a logic high at the input.
RESET INPUT (RSTB)
This input wakes the device when the RSTB terminal is at
logic [1]. It is also used to initialize the device configuration
and the SPI faults registers when the signal is low. All SI/SO
registers described Table 8 and Table 11 are reset. The fault
management is not affected by RSTB (see Figure 2).
CURRENT SENSE OUTPUT (CSNS)
The current sense output terminal is an analog current
output. The routing to the external resistor is SPI
programmable.
SPI PROTOCOL DESCRIPTION
The SPI interface has a full-duplex, three-wire
synchronous data transfer with four I/O lines associated with
it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO),
and Chip Select (CS).
The SI/SO terminals of the 33480 device follow a first-in,
first-out (D15 to D0) protocol, with both input and output
words transferring the most significant bit (MSB) first. All
inputs are compatible with 5.0 V CMOS logic levels, supplied
by Vcc.
The SPI lines perform the following functions:
SERIAL CLOCK (SCLK)
CHARGE PUMP (CP)
An external capacitor is connected between this terminal
and VBAT terminal. It is used as a tank for the internal charge
pump. Its value is 100 nF ± 20%, 25V maximum.
FET OUT OUTPUT (FETOUT)
This output terminal is used to control an external
MOSFET (OUT6).
The high level of the FETout Output is Vcc if Vbat and Vcc
are available in case of FETout is controlled ON.
CSB
CS
This input terminal gives the current recopy of the external
MOSFET. It can be routed on CSNS output by SPI command.
The SCLK terminal clocks the internal shift registers of the
33480 device. The SI terminal accepts data into the input shift
register on the falling edge of the SCLK signal, while the SO
terminal shifts data information out of the SO line driver on
the rising edge of the SCLK signal. It is important that the
SCLK terminal be in a logic low state whenever CS makes
any transition. For this reason, it is recommended the SCLK
terminal be in a logic [0] whenever the device is not accessed
(CS logic [1] state). SCLK has an internal pulldown, IDWN.
When CS is logic [1], signals at the SCLK and SI terminals
are ignored and SO is tri-stated (high impedance) (see
Figure 6).
CS
SCLK
SI
SO
D15
D14
D13
D12
D11
D10
D9
OD15 OD14 OD13 OD12 OD11 OD10 OD9
NOTES: 1.
2.
3.
D8
OD8
D7
OD7
D6
OD6
D5
OD5
D4
D3
OD4
OD3
D2
OD2
D1
D0
OD1 OD0
Notes
RSTB is in a logic1.
H state
the above
operation.
D15 during
: D0 relate
to the
most recent ordered entry of data into the device.
device.
DO, D1, D2, ... , and
D15 relate
to therelate
most recent
entry
of of
program
data fault
into the
LUX
IC
2. OD15
: OD0
to theordered
first 16
bits
ordered
and
status
data out of the device.
device.
OD0, OD1, OD2, ..., and OD15 relate to the first 16 bits of ordered fault and status data out of the LUX
IC
Figure 6. Single 16-Bit Word SPI Communication
33480
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FUNCTIONAL DESCRIPTION
FUNCTIONAL TERMINAL DESCRIPTION
SERIAL INPUT (SI)
CHIP SELECT (CS)
The SI terminal is a serial interface command data input
terminal. Each SI bit is read on the falling edge of SCLK. A
16-bit stream of serial data is required on the SI terminal,
starting with D15 to D0. SI has an internal pulldown, Idown.
The CS terminal enables communication with the master
device. When this terminal is in a logic [0] state, the device is
capable of transferring information to, and receiving
information from, the master device. The 33480 device
latches in data from the Input Shift registers to the addressed
registers on the rising edge of CS. The device transfers status
information from the power output to the Shift register on the
falling edge of CS. The SO output driver is enabled when CS
is logic [0]. CS should transition from a logic [1] to a logic [0]
state only when SCLK is a logic [0]. CS has an internal pullup,
IUP.
SERIAL OUTPUT (SO)
The SO data terminal is a tri-stateable output from the shift
register. The SO terminal remains in a high-impedance state
until the CS terminal is put into a logic [0] state. The SO data
is capable of reporting the status of the output, the device
configuration, and the state of the key inputs. The SO
terminal changes state on the rising edge of SCLK and reads
out on the falling edge of SCLK.
33480
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SLEEP MODE
The Sleep mode is the default mode of the 33480. This is
the state of the device after first applying battery voltage
(VBAT) and prior to any I/O transitions. This is also the state
of the device when IGN, FLASHER, and RSTB are logic [0]
(wake=0). In the Sleep mode, the outputs and all internal
circuitry are OFF to minimize current draw. In addition, all
SPI-configurable features of the device are reset. The 33480
will transit to two modes (Normal and Fail) depending on
wake and fail signals (see Fig13).
The transition to the other modes is according following
signals :
• Wake = IGN or IGN_ON or FLASHER or
FLASHER_ON or RSTB
• Fail = VCC fail or SPI fail or External limp
D7 bit
D0-D6 bits
Output
Overcurrent
FAIL MODE
The 33480 is in Fail mode when:
• Wake = 1
• Fail = 1.
In Fail mode :
NORMAL MODE
The 33480 is in Normal mode when:
• Wake = 1
• Fail = 0
In Normal operating mode the power outputs are under full
control of the SPI as follows:
• The outputs 1 to 6, including multiphase timing, are
controlled by the programmable PWM module.
• The outputs 1 to 5 are switched OFF in case of
undervoltage on Vbat.
• The outputs 1 to 5 are protected by the overcurrent
double window and overtemperature shutdown circuit.
• The digital diagnosis feature transfers status of the
smart outputs via SPI.
• The analog current sense output (current recopy
feature) can be routed by SPI.
• The SPI reports NM=1 in this mode.
The figure below describes the PWM, outputs and
overcurrent behavior in Normal Mode.
• The outputs are under control of external terminals (see
Table 5)
• The outputs are fully protected in case of overload,
overtemperature and undervoltage (on Vbat or on Vcc).
• Neither digital diagnosis feature (SPI) nor analog
current sense are available.
• Output 2 is configured in Xenon mode.
• In case of overload (OCHI2 or OCLO) conditions or
undervoltage on Vbat, the outputs are under control of
autorestart feature.
• In case of serious overload condition (OCHI1 or OT) the
corresponding output is latched OFF until a new wake
up event (wake=0 then 1).
IGN_ON
1.4 sec min
IGN (external)
OUT[1,2]
Overcurrent
Table 5. Limp Home Output State
Output 1
Parking Light
Output 2
Low Beam
Output 3
High Beam
Output 4
Fog Light
Output 5
Flasher
External Switch
Spare
IGN Terminal
IGN Terminal
OFF
OFF
FLASHER Terminal
OFF
33480
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
AUTORESTART STRATEGY
The autorestart circuitry is used to supervise the outputs
and reactivate high-side switches in case of overload or
undervoltage failure conditions to provide a high availability
of the outputs.
Autorestart feature is available in Fail mode when no
supervising intelligence of the microcontroller is available.
Autorestart is activated in case of overload condition (OCHI2
or OCLO) or undervoltage condition on VBat (see Fig10).
The autorestart switches ON the outputs. During ON state
of the switch OCHI1 window is enable for tochi_Auto then
after the output is protected by OCLO.
In case of OCHI1 or OT, the switch is latched OFF until
wake up (wake=0 then1).
In case of OCLO or undervoltage, the output switch OFF
and after autorestart period (150ms for 10mohm or 75ms for
35mhom) turn ON again.
In case of under voltage occurred in fail mode, it will be
latched twice: one latch for outputs 1 and 5 and the second
latch for output 2. That means the corresponding output is
switched on only after its autorestart period (tAUTORST-T1 or
tAUTORST-T2).
The Autorestart is not limited in time.
TRANSITION FAIL TO NORMAL MODE
To leave the fail mode, the fail condition must be removed
(fail=0). The microcontroller has to send a SPI command with
D10 must be to logic [1] to reset the watchdog bit ; the other
bits are not considered. The previous latched faults are reset
by the transition into Normal mode.
Output current
OCHI1
TRANSITION NORMAL TO FAIL MODE
To leave the Normal Mode, a fail condition must occur
(fail=1). The previous latched faults are reset by the transition
into Fail mode.
OCLO or UV fault
OCLO
tochi_auto
Auto period
time
Figure 7. Overcurrent window in case of Autorestart
33480
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
OPERATIONAL MODES
Sleep
(wake=0)
(fail=0) and (wake=1)
(wake=0)
(wake=1) and (fail=1) *
VBAT > VBATPOR
VBAT < VBATPOR
Power OFF
VBAT < VBATPOR
VBAT < VBATPOR
Normal
Fail
(fail=0) and (wake=1)
(fail=1) and (wake=1)
Notes:
* only available in case of Vcc fail condition
wake=(RSTB=1) OR (IGN_ON=1) OR (Flasher_ON=1)
fail=(Vcc_fail=1) OR (SPI_fail=1) OR (ext_limp=1)
Figure 8. Operating Modes State Machine
START-UP SEQUENCE
The following figure describes the wake-up block diagram.
The 33480 enters in Normal Mode after start-up if following
sequence is provided:
• Vbat and Vcc power supplies must be above their
undervoltage thresholds (Sleep mode).
• generate wake up event (wake=1) from 0 to 1 on RSTB.
The device switches to normal mode.
• apply PWM clock after maximum 200us (min 50us).
• send SPI command to the Device status register to
clear the clock fail flag to enable the PWM module to
start.
If the correct start-up sequence is not provided, the PWM
function is not guaranteed.
33480
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
OPERATIONAL MODES
Vbat
wake
Wake-up bar
Dig5V
Internal
regulator
IGN
Deglitcher
(Note*)
Vcc
Oscillator
500kHz
IGN_ON
SPI registers
Fault
management
PWM module
PWM freq
detector
reset
Flasher
Deglitcher
(Note*)
Vcc fail
SPI fail
External
Limp
Flasher_ON
OR
Fail
RSTB
Figure 9. Wake-up block diagram
Note*:
1.4 sec min
external
external_ON
external: IGN, Flasher
external_ON: IGN_ON, Flasher_ON
33480
22
Analog Integrated Circuit Device Data
Freescale Semiconductor
PROTECTION AND DIAGNOSIS FEATURES
PROTECTION AND DIAGNOSIS FEATURES
Output Protection Features
The 33480 provides the following protection features:
• Protection against transients on VBAT supply line (per
ISO 7637)
• Active clamp, including protection against negative
transients on output line
• Overtemperature
• Severe and resistive Overcurrent
• Open Load during ON state
These protections are provided for each output (OUT1:5).
Overtemperature detection
The 33480 provides overtemperature shutdown for each
output (OUT1:OUT5 ). It can occur when the output terminal
is in the ON or OFF state. An overtemperature fault condition
results in turning OFF the corresponding output. The fault is
latched and reported via SPI. To delatch the fault and be able
to turn ON again the outputs, the failure condition must be
removed (T< 175°C typically) and:
• if the device was in Normal Mode, the output
corresponding register (bit D7) must be rewritten.
Application of complete OCHI window (OCHI1+OCHI2
during t2) depends on toggling or not toggling D7 bit.
• if the device was in Fail Mode, the corresponding output
is locked until restart of the device: wake up from Sleep
Mode or VBATPOR.
The SPI fault report (OTS bit) is removed after a read
operation.
Overcurrent detections
The 33480 provides intelligent overcurrent shutdown (see
Figure 10) in order to protect the internal power transistors
and the harness in the event of overload (fuse characteristic).
Output current
OCHI (IOCHI1 and then IOCHI2) is only activated after
toggling D7 bit in Normal Mode. In Fail Mode, the control of
OCHI window is provided by the toggles: IGN_ON,
Flasher_ON. The current thresholds (IOCHI1 , IOCHI2 and
IOCLO) and the time (t1 and t2) are fixed numbers for each
driver. After t2, OCLO current threshold is set to protect in
steady state.
OUT2 is default loaded with the Xenon profile. The use of
H7 bulbs at this output requires SPI programming (Xenon
bit).
In case of overload (OCHI1 or OCHI2 or OCLO detection),
the corresponding output is disabled immediately. The fault is
latched and the status is reported via SPI. To delatch the
fault, the failure condition must be removed and:
For OCHI1:
• if the device was in Normal Mode: the output
corresponding register (bit D7) must be rewritten D7=1.
Application of complete OCHI window depends on
toggling or not toggling D7 bit.
• if the device was in Fail Mode, the failure is locked until
restart of the device: wake up from Sleep Mode or
VBATPOR.
For OCHI2 and OCLO:
• if the device was in Normal Mode: the output
corresponding register (bit D7) must be rewritten D7=1.
Application of complete OCHI window depends on
toggling or not toggling D7 bit.
• if the device was in Fail Mode, Autorestart is activated.
The device Autorestart feature provides a fixed duty
cycle and fixed period with OCHI1 window.
Autorestart feature resets OCHI2 or OCLO fault after
corresponding Autorestart period.
The SPI fault reports are removed after a read operation:
- OC bit=(OCHI1) or (OCHI2) fault
- OVL bit=(OCHI1) or (OCHI2) or (OCLO) fault
OCHI1
Overvoltage detection and active clamp
The 33480 provides an active gate clamp circuit in order to
limit the maximum drain to source voltage.
OCHI2
OCLO
t1
t2
time
In case of overload on an output the corresponding switch
(OUT[1 to 5]) is turned off which leads to high voltage at Vbat
with an inductive Vbat line. When Vbat voltage exceeds
VBAT_CLAMP threshold, the fast turn-off on the
corresponding output is deactivated and the drain to source
voltage is limited by the active clamp circuit (VCLAMP_DS).
Figure 10. Double overcurrent window in Normal Mode
33480
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
PROTECTION AND DIAGNOSIS FEATURES
The following diagrams (9&10) describe the faults
management in Normal Mode and Fail Mode .
(OCHI2=1) or (OT=1) or (UV=1) or (D7=0)
(OCHI1=1) or (OT=1) or (UV=1) or (D7=0)
D7=0 then 1 without fault
t1<t<t2 without fault
OFF
(rewrite D7=1) and (t<t1)
without fault
OCHI2
t>t2 without fault
OCHI1
OCLO
(t1<t<t2) and (rewrite D7=1)
(t>t2) and (rewrite D7=1)
Note: t1 and t2 please refer
to Figure 10.
(OCLO=1) or (OT=1) or (UV=1) or (D7=0)
Figure 11. Faults management in Normal Mode (for OUT[1:5] only)
33480
24
Analog Integrated Circuit Device Data
Freescale Semiconductor
PROTECTION AND DIAGNOSIS FEATURES
(OT=1) or
(OCHI1=1)
(external_ON=0)
OFF-latched
State
(OT=1)
(external_ON=0)
(OT=1)
(external_ON=1)
OFF
out: OFF
autorestart=0
(t>tOCHI2) and (autorestart=0)
(t>tOCHI1) and (autorestart=0)
OCHI2
out: external
OCHI1
out: external
OCLO
out: external
(t>tOCHI1_AUTO) and (autorestart=1)
(UV=1)
(UV=1)
and
(external_on=1)
(t>tautorestart)
(UV*=0)
and
(UV=1) or (OCHI2=1)
(OCLO=1) or
(UV=1)
(external_ON=0)
OFF Autorestart
out: OFF
autorestart=1
(external_ON=0)
1.4 sec min
external
external_ON
external: IGN, Flasher
external_ON: IGN_ON, Flasher_ON
Note: * See Autorestart strategy chapter.
Figure 12. Faults management in Fail Mode (for OUT[1:5] only)
Diagnosis
Open Load
The 33480 provides open load detection for each output
(OUT1:OUT5 ) when the output terminal is in the ON state.
Open load detection levels can be chosen by SPI to detect a
standard bulb, a Xenon bulb for OUT2 only, or LEDs (OLLED
bit). Open load for LEDs only is detected during each regular
switch-off transition for minimum 200µs (PWM depending
D[6:0] bits <> 7F) or periodically each t OLLED (fully-on,
D[6:0]=7F). To detect OLLED in fully on state, the output
must be on at least t OLLED. When an open load has been
detected, the output stays ON.
To delatch the diagnosis, the condition should be removed
and SPI read operation is needed (OL bit). In case of Power
on Reset on Vbat, the fault will be reset.
Current Sense
The 33480 diagnosis for load current (OUT1:6) is done
using the current sense (CSNS) terminal connected to an
external resistor. The routing of the current sense sources is
SPI programmable (MUX[2,0] bits).
33480
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
PROTECTION AND DIAGNOSIS FEATURES
The current recopy feature for OUT1:5 is disabled during
high overcurrent shutdown phase (t2) and is only enabled
during low overcurrent shutdown threshold. The current
recopy output delivers current only during ON time of the
output switch without overshoot (aperiodic settling).
The current recopy is not active in Fail Mode.
TEMPERATURE PREWARNING
The 33480 provides a temperature prewarning reported
via SPI (OTW bit) in Normal Mode. The information is
latched. To delatch, a read SPI command is needed. In case
of Power on Reset, the fault will be reset.
EXTERNAL TERMINAL STATUS
The 33480 provides the status of the FLASHER, IGN, and
CLOCK terminals via SPI in real time and in Normal Mode.
FAILURE HANDLING STRATEGY
A highly sophisticated failure handling strategy enables
light functionality even in case of failures inside the
component or the light module. Components are protected
against:
•
•
•
Reverse Polarity
Loss of Supply Lines
Fatal Mistreatment of Logic I/O Terminals
REVERSE POLARITY PROTECTION ON VBAT
In case of permanently reverse polarity operation, the
output transistors are turned ON (Rsd) to prevent thermal
overload and no protections are available.
external MOSFET (OUT6) can be controlled by SPI if Vcc
remains and is above to VCCUV. The fault is reported to UVF
bit (OD13). To delatch the fault, the undervoltage condition
should be removed and:
• The bit D7 must be rewritten to logic [1] in Normal Mode.
Application of OCHI window depends on toggling or not
toggling D7 bit. When the fault is delatched, the 33480
returns in the configuration it was just before the failure.
• If the device was in Fail mode, the fault will be delatched
by the Autorestart feature periodically.
In case of VBAT<VBATPOR (Power OFF state), all latched
faults are reset if VCC < VBAT. In case of VBAT is missing, all
outputs (out[1:6]) are OFF and no current is conducted from
Vcc to VBAT.
LOSS OF VCC (DIGITAL LOGIC SUPPLY LINE)
During loss of VCC (VCC < VCCUV ) and with wake=1, the
33480 is switched automatically into Fail mode (no deglich
time). The external SMART MOSFET is OFF. All SPI
registers are reset and must be reprogrammed when Vcc
goes above VCCUV.
LOSS OF GROUND (GND)
During loss of ground, the 33480 cannot operate the loads
(the outputs (1:5) are switched OFF) but is not destroyed by
the operating condition. Current limit resistors in the digital
input lines protect the digital supply against excessive current
(1kohm typical). The state of the external smart power switch
controlled by FET out is not guaranteed and the state of
external smart MOS is defined with external termination
resistor.
External diode on Vcc is necessary in order to not destroy
the 33480 in case of reverse polarity.
FATAL MISTREATMENT OF LOGIC I / O
TERMINALS
In case of negative transients on the VBAT line (per
ISO 7637), the VCC line is still operating, while the VBAT line
is negative. Therefore, the device is protected against latchup.
The digital I / Os are protected against fatal mistreatment
by signal plausibility check according to Table 6.
LOSS OF SUPPLY LINES
The 33480 is protected against loss of any supply line. The
detection of the supply line failure is provided inside the
device itself.
Table 6. Logic I / O Plausibility Check
Input / Output
Signal Check Strategy
LIMP
Debounce for 10 ms
(PWM) CLOCK
Frequency range
(bandpass filter)
SPI (MOSI, SCLK, CS)
WD, D10 bit internal toggle
LOSS OF VBAT
During undervoltage of VBAT (VBATPOR <VBAT<VBATUV)
and with active device (wake=1), the outputs [1-5] are
switched off and the external MOSFET remains in the
previous state. No current path from Vbat to Vcc. The
In case of LIMP input is set to logic [1] for a delay longer
than 10ms typical, the 33480 is switched into Fail mode. In
case of (PWM) Clock failure, no PWM feature is provided and
33480
26
Analog Integrated Circuit Device Data
Freescale Semiconductor
PROTECTION AND DIAGNOSIS FEATURES
the bit D7 defines the outputs state. In case of SPI failure, the
33480 is switched into Fail mode (see Fig13).
WD Bit D10
1
0
0
timeout
75ms window watchdog
D10 is toggled after
the window watchdog
75ms window watchdog
Fail Mode activation
Figure 13. Watchdog window
33480
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
FUNCTIONAL DESCRIPTION
PROTECTION AND DIAGNOSIS FEATURES
FUNCTIONAL DESCRIPTION
SERIAL INPUT COMMUNICATION
Table 7. SI Message Bit Assignment
SPI communication is accomplished using 16-bit
messages. A message is transmitted by the master starting
with the MSB, D15, and ending with the LSB, D0. Each
incoming command message on the SI terminal can be
interpreted using the bit assignment described in Table 7.
The 5 bits D15 : D11, called register address bits, are used to
select the command register. Bit D10 is the watchdog bit. The
remaining 10 bits, D9 : D0, are used to configure and control
the output and its protection features. Multiple messages can
be transmitted in succession to accommodate those
applications where daisy chaining is desirable or to confirm
transmitted data as long as the messages are all multiples of
16 bits. Any attempt made to latch in a message that is not
16 bits will be ignored.
Bit Sig
SI Msg Bit
MSB
D15 : D11
Message Bit Description
Register address bits.
D10
LSB
Watchdog in: toggled to satisfy watchdog
requirements.
D9 : D0
Used to configure inputs, outputs, device
protection features, and SO status content.
DEVICE REGISTER ADDRESSING
The register addresses (D15 : D11) and the impact of the
serial input registers on device operation are described in this
section. Table 8 summarizes the SI registers.
All SPI registers are reset (all bit equal 0) in case of RSTB
equal 0 or fail mode (Fail=1).
Table 8. Serial Input Address and Configuration Bit Map
SI Register
SI Address
SI Data
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MUX2
MUX1
MUX0
SOA1
SOA0
Initialization
0
0
0
0
0
WD
0
0
0
PWM
sync
Xenon
Config OL
0
0
0
0
1
WD
0
0
0
0
0
Unused
0
0
0
1
0
WD
0
0
0
0
0
0
0
0
0
0
Unused
0
0
0
1
1
WD
0
0
0
0
0
0
0
0
0
0
Control
OUT1
0
1
0
0
1
WD Phase2 Phase1
ONoff
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
Control
OUT2
0
1
0
1
0
WD Phase2 Phase1
ONoff
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
Control
OUT3
0
1
0
1
1
WD Phase2 Phase1
ONoff
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
Control
OUT4
0
1
1
0
0
WD Phase2 Phase1
ONoff
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
Control
OUT5
0
1
1
0
1
WD Phase2 Phase1
ONoff
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
Control
External
Switch
0
1
1
1
0
WD Phase2 Phase1
ONoff
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
RESET
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
Note: testmode address used only by FSL is
D[15:11]=01111 with RSTB voltage higher than 8V typ.
ADDRESS 00000 — INITIALIZATION
The Initialization register is used to read the various
statuses, choose one of the six outputs current recopy, load
the H7 bulbs profile for OUT2 only, and synchronize the
OLLED5 OLLED4 OLLED3 OLLED2 OLLED1
switching phases between different corner light devices. The
register bits D1 and D0 determine the content of the 16 bits
of the next SO data. (Refer to the section entitled Serial
Output Communication (Device Status Return Data)
beginning on page 30.) Table 9 describes the register of
initialization.
33480
28
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
PROTECTION AND DIAGNOSIS FEATURES
The watchdog timeout is specified by t WDTO parameter. As
long as the WD bit (D10) of an incoming SPI message is
toggled within the minimum watchdog timeout period
(WDTO), the device will operate normally. If an internal
watchdog timeout occurs before the WD bit is toggled, the
device will revert to Fail mode. All registers are cleared. To
exit the Fail mode, send valid SPI communication with
WD bit = 1.
Table 9. Initialization Register
SI Address
SI Data
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
WD
0
0
0
PWM
sync
Xenon
MUX2
MUX1
MUX0
SOA1
SOA0
x = Don’t care
D4, D3, D2 (MUX2, MUX1, MUX0) = 000, No current sense
D6 (PWM sync) = 0, No synchronization
D4, D3, D2 (MUX2, MUX1, MUX0) = 001, OUT1 current sense
D6 (PWM sync) = 1, Synchronization on CSB positive edge
D4, D3, D2 (MUX2, MUX1, MUX0) = 010, OUT2 current sense
D5 (Xenon) = 0, Xenon
D4, D3, D2 (MUX2, MUX1, MUX0) = 011, OUT3 current sense
D5 (Xenon) = 1, H7 Bulb
D4, D3, D2 (MUX2, MUX1, MUX0) = 100, OUT4 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 101, OUT5 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 110, External Switch current
sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 111, No current sense
ADDRESS 00001 — CONFIGURATION OL
The Configuration OL register is used to enable the open
load detection for LEDs in Normal Mode (OLLEDn in Table 8,
page 28). When bit D0 is set to logic [1], the open load
detection circuit for LED is activated for output 1. When bit D0
is set to logic [0], open load detection circuit for standard
bulbs is activated for output 1.
D7 = 0, D6 : D0 = XX output OFF.
D7 = 1, D6 : D0 = 00 output ON during 1/128.
D7 = 1, D6 : D0 = 1A output ON during 27/128 on PWM
period.
ADDRESS 00010
D7 = 1, D6 : D0 = 7F output continuous ON (no PWM).
This register is not used.
ADDRESS 01010 — CONTROL OUT2
ADDRESS 00011
Same description as OUT1.
This register is not used.
ADDRESS 01001 — CONTROL OUT1
Bits D9 and D8 control the switching phases as shown in
Table 10.
Table 10. Switching Phases
D9 : D8
Bit D7 at logic [1] turns ON OUT1. OUT1 is turned OFF
with bit D7 at logic [0]. This register allows the master to
control the duty cycle and the switching phases of OUT1. The
duty cycle resolution is given by bits D6 : D0.
PWM Phase
00
0°
01
90°
10
180°
11
270°
ADDRESS 011111 — CONTROL OUT3
Same description as OUT1.
ADDRESS 01100 — CONTROL OUT4
Same description as OUT1.
ADDRESS 01101 — CONTROL OUT5
Same description as OUT1.
33480
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
FUNCTIONAL DESCRIPTION
PROTECTION AND DIAGNOSIS FEATURES
ADDRESS 01110 — CONTROL EXTERNAL SWITCH
Same description as OUT1.
terminal is tri-stated and the fault status register is now able
to accept new fault status information.
The output status register correctly reflects the status of
the Initialization-selected register data at the time that the CS
is pulled to a logic [0] during SPI communication and / or for
the period of time since the last valid SPI communication,
with the following exceptions:
ADDRESS 01111 — TEST MODE
This register is reserved for test and is not available with
SPI during normal operation.
• The previous SPI communication was determined to be
invalid. In this case, the status will be reported as
though the invalid SPI communication never occurred.
• Battery transients below 6.0 V, resulting in an undervoltage shutdown of the outputs, may result in incorrect
data loaded into the status register.
SERIAL OUTPUT COMMUNICATION (DEVICE
STATUS RETURN
DATA)
When the CS terminal is pulled low, the output register is
loaded. Meanwhile, the data is clocked out MSB first as the
new message data is clocked into the SI terminal. The first
16 bits of data clocking out of the SO, and following a CS
transition, is dependant upon the previously written SPI word
(SOA1 and SOA0 defined in the last SPI initialization word).
SERIAL OUTPUT BIT ASSIGNMENT
The contents of bits OD15 : OD0 depend on bits D1: D0
from the most recent initialization command SOA[1:0] (refer
to Table 8, page 28), as explained in the paragraphs that
follow.
Any bits clocked out of the SO terminal after the first 16 will
be representative of the initial message bits clocked into the
SI terminal since the CS terminal first transitioned to a
logic [0]. This feature is useful for daisy chaining devices.
The register bits are reset by a read operation and also if
the fault is removed.
A valid message length is determined following a CS
transition of logic [0] to logic [1]. If the message length is
valid, the data is latched into the appropriate registers. A valid
message length is a multiple of 16 bits. At this time, the SO
Table 11 summarizes the SO register content. Bit OD10
reflects Normal mode (NM).
Table 11. Serial Output Bit Map Description
Status /
Mode
Previous
SI Data
SO
A1
SO Data
SO
OD15 OD14 OD13 OD12 OD11 OD10 OD9
A0
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
Output
Status
0
0
0
0
UVF
OTW
OTS
NM
OL5
OVL5
OL4
OVL4
OL3
OVL3
OL2
OVL2
OL1
OVL1
Overload
Status
0
1
0
1
UVF
OTW
OTS
NM
OC5
OTS5
OC4
OTS4
OC3
OTS3
OC2
OTS2
OC1
OTS1
Device
Status
1
0
1
0
UVF
OTW
OTS
NM
0
OV
X
X
X
RC
0
FLASHER
IGN
pin
CLOCK
pin
Test
Mode
1
1
1
1
UVF
OTW
OTS
NM
0
0
0
0
0
0
0
0
0
0
Reset
X
X
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
33480
30
Analog Integrated Circuit Device Data
Freescale Semiconductor
fail
FUNCTIONAL DESCRIPTION
PROTECTION AND DIAGNOSIS FEATURES
PREVIOUS ADDRESS SOA[1:0] = 00
If the previous two LSBs are 00, bits OD15 : OD0 reflect the
output status (Table 12).
Table 12. Output Status
OD15
OD14
OD13
OD12
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
0
0
UVF
OTW
OTS
NM
OL5
OVL5
OL4
OVL4
OL3
OVL3
OL2
OVL2
OL1
OVL1
OD13 (UVF) = Undervoltage Flag on Vbat
OD9, OD7, OD5, OD3, OD1 (OL5, OL4, OL3, OL2, OL1) = Open Load
Flag at Outputs 5 through 1, respectively.
OD8, OD6, OD4, OD2, OD0 (OVL5, OVL4, OVL3, OVL2, OVL1) =
Overload Flag for Outputs 5 through 1, respectively.This corresponds
to overtemperature or OCHI or OCLO faults.
OD12 (OTW) = Overtemperature Prewarning Flag
OD11 (OTS) = Overtemperature Flag for all outputs
OD10 (NM) = Normal mode
Note
A logic [1] at bits OD9:OD0 indicates a fault. If there is no fault, bits OD9:OD0 are logic [0].
OVL=OCHI1+OCHI2+OCLO
PREVIOUS ADDRESS SOA[1:0] = 01
If the previous two LSBs are 01, bits OD15 :O D0 reflect
reflect the temperature status (Table 13).
Table 13. Overload Status
OD15
OD14
OD13
OD12
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
0
1
UVF
OTW
OTS
NM
OC5
OTS5
OC4
OTS4
OC3
OTS3
OC2
OTS2
OC1
OTS1
OD13 (UVF) = Undervoltage Flag on Vbat
OD9, OD7, OD5, OD3, OD1 (OC5, OC4, OC3, OC2, OC1) = High
Overcurrent Shutdown Flag for Outputs 5 through 1, respectively
OD12 (OTW) = Overtemperature Prewarning Flag
OD8, OD6, OD4, OD2, OD0 (OTS5, OTS4, OTS3, OTS2, OTS1) =
Overtemperature Flag for Outputs 5 through 1, respectively
OD11 (OTS) = Overtemperature Flag for all outputs
OD10 (NM) = Normal mode
Note
A logic [1] at bits OD9:OD0 indicates a fault. If there is no fault, bits OD9:OD0 are logic [0].
OC=OCHI1+OCHI2
PREVIOUS ADDRESS SOA[1:0] = 10
If the previous two LSBs are 01, bits OD15 : OD0 reflect the
status of the 33480 (Table 14).
Table 14. Device Status
OD15
OD14
OD13
OD12
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
1
0
UVF
OTW
OTS
NM
0
0V
X
X
X
RC
0
OD13 (UVF) = Undervoltage Flag on Vbat
OD2
OD1
OD0
FLASH IGN pin CLOCK
ER pin
fail
OD12 (OTW) = Overtemperature Prewarning Flag
OD2 (FLASHER pin) = Indicates the FLASHER terminal state in real
time
OD11 (OTS) = Overtemperature Flag for all outputs
OD1 (IGN pin) = Indicates the IGN terminal state in real time
OD10 (NM) = Normal mode
OD0 (CLOCK fail) = Logic [1], which indicates a clock failure
OD4 (RC) = Logic [0] indicates a Front Corner Light Switch. Logic [1]
indicates a Rear Corner Light Switch
OD8 (Overvoltage) = Overvoltage Flag on Vbat in real time
PREVIOUS ADDRESS SOA[1:0] = 11
Null Data. No previous register Read Back command
received, so bits OD9 : OD0 are null.
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Freescale Semiconductor
31
TYPICAL APPLICATION
PROTECTION AND DIAGNOSIS FEATURES
TYPICAL APPLICATION
Figure 14 below shows full vehicle light functionality,
including fog lights, battery redundancy concept, light
substitution mode, and Fail mode.
H
Fo
g
Sp
ar
e
ar
t
Sp
gh
Li
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Fo eam
B
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ig am
H Be
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w
Lo a s h
Fl ht
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Li
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Li
g
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ig
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Lo Be
w am
F l Be
as am
Pa her
rk
in
g
Li
gh
t
g
in
rk
Pa
MOSI, MISO, SCLK
CP
100nF
MC33480
VBAT
Smart Corner
Light Switch
(Front Left)
VCC
CP
CS
CS
CLOCK
MC33480
CLOCK
RSTB
RSTB
IGN
VBAT
Smart Corner
Light Switch
(Front Right)
IGN
LIMP
LIMP
100nF
VCC
FLASHER
FLASHER
CSNS
CSNS
R
R
ea
rF
ea
og
rD
Li
Li
gh
ce riv
t
n e
St se Lig
op L
h
ig t
Fl Lig ht
as ht
Ta her
il
Li
gh
t
t
gh
t
Li
gh
og
Li
t
e
rF
riv igh
ea
R
rD eL t
h
ea s
R cen Lig
Li op er
h
St
s
a
Fl ht
g
Li
il
Ta
100nF
100nF
CP
MC33481
VBAT
V
CS
CLOCK
MC33481
CLOCK
RSTB
Smart Corner
Light Switch
(Rear Left)
VCC
CS
CP
VBAT
RSTB
IGN
Smart Corner
Light Switch
(Rear Right)
IGN
LIMP
LIMP
VCC
FLASHER
FLASHER
STOP
STOP
CSNS
CSNS
Microcontroller
Watchdog
VCC
(5.0 V)
WD
(5.0 V)
I
ii
Figure 14. Typical Application
S
Li h
Fl
h
V
33480
32
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATION
PROTECTION AND DIAGNOSIS FEATURES
EMC & EMI PERFORMANCES
The 33480 must pass successfully the Class5 of the norm
CISPR25.
The evaluation will be done on the Freescale board rev1.1.
Conditions to be defined.
RELIABILITY TESTS
See document SCLS_reliability test spec_V22.doc,
RevisionV2.2, Date September,23rd,2005.
33480
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
PACKAGING
PACKAGING DIMENSIONS
PACKAGING
PACKAGING DIMENSIONS
PNA SUFFIX
24-TERMINAL PQFN
PLASTIC PACKAGE
98ARL10596D
ISSUE B
33480
34
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS
33480
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
PACKAGING
PACKAGING DIMENSIONS
33480
36
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS
33480
Analog Integrated Circuit Device Data
Freescale Semiconductor
37
REVISION HISTORY
REVISION HISTORY
Revision
2.0
Date
12/2005
Description of Changes
•
•
Implemented Revision History page
Converted to Freescale format
33480
38
Analog Integrated Circuit Device Data
Freescale Semiconductor
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MC33480
Rev 2.0
1/2006
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