MC35XS3500, Smart Rear Corner Light Switch (Penta 35 mOhm) - Data Sheet

Freescale Semiconductor
Technical Data
Document Number: MC35XS3500
Rev. 8.0, 8/2013
Smart Rear Corner Light Switch
(Penta 35 mOhm)
35XS3500
The 35XS3500 is designed for low-voltage automotive and
industrial lighting applications. Its five low RDS(ON) MOSFETs (five
35 m) can control the high sides of five separate resistive loads
(bulbs and LEDs).
HIGH SIDE SWITCH
Programming, control and diagnostics are accomplished using a
16-bit SPI interface (3.3 V or 5.0 V). Each output has its own pulsewidth modulation (PWM) control via the SPI. The 35XS3500 has
highly sophisticated failure mode handling to provide high availability
of the outputs. Its multiphase control and output edge shaping
improves electromagnetic compatibility (EMC) behavior.
The 35XS3500 is packaged in a power-enhanced 12 x 12 mm
nonleaded PQFN package with exposed tabs.
Bottom View
Features
FK SUFFIX
98ART10511D
24-PIN PQFN
PB FREE
• Penta 35 m high side switches
• 16-bit SPI communication interface with daisy chain capability
• Current sense output with SPI-programmable multiplex switch
and board temperature feedback
• Digital diagnosis feature
• PWM module with multiphase feature including prescaler
• LEDs control including accurate current sensing and low dutycycle capability
• Fully protected switches
• Over-current shutdown detection
• Power net and reverse polarity protection
• Low-power mode
• Fail-safe mode functions including autorestart feature
• External smart power switch control including current recopy
12V
ORDERING INFORMATION
Device
(For Tape and Reel,
Add R2 Suffix)
MC35XS3500HFK
* MC35XS3500DHFK
12V
35XS3500
Watchdog
MCU
LIMP
FLASHER
STOP
IGN
RST
CLOCK
CS
VBAT
CP
OUT1
OUT2
OUT3
OUT4
OUT5
S0
FETIN
SI
SCLK
FETOUT
CSNS GND
Smart
Switch
Figure 1. 35XS3500 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2010-2013. All rights reserved.
Package
-40 to 125 °C
24 PQFN
* Recommended for all new designs
5.0V
VCC
Temperature
Range (TA)
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. MC35XS3500 Device Variations
Part Number
MC35XS3500HFK
MC35XS3500DHFK
Package
Temp.
24 PQFN
-40 to 125 °C
Comment
Initial release
D version is more robust against VBAT interrupt
35XS3500
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VCC
VBAT
VCC failure
detection
RUP
Internal
Regulator
CP
OV/UV/POR
detections
Charge
Pump
CS
SO
SI
SCLK
Gate Drive
drain/gate clamp
Logic
LED Control
RDWN
OUT1
Over-current
Detection
CLOCK
LIMP
STOP
Open Load
Detection
FLASHER
IGN
RST
Over-temperature
Detection
OUT1
OUT2
OUT2
RDWN
OUT3
OUT3
Over-temperature
Prewarning
OUT4
OUT4
OUT5
OUT5
Selectable Output Current
Recopy (Analog MUX)
CSNS
Temperature
Feedback
FETIN
Current Recopy
Synchronization
VCC
Driver for External
MOSFET
FETOUT
GND
Figure 2. 35XS3500 Simplified Internal Block Diagram
35XS3500
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
SCLK
CS
STOP
LIMP
CLOCK
FLASHER
RST
IGN
FETIN
8
7
6
5
4
3
2
1
CP
16
GND
17
OUT5
18
VCC
9
SO
13 12 11 10
FETOUT
SI
PIN CONNECTIONS
14
GND
24
CSNS
23
GND
22
OUT1
15
VBAT
19
20
21
OUT4
OUT3
OUT2
Figure 3. 35XS3500 Pin Connections (Transparent Package Top View)
Table 2. 35XS3500 Pin Definitions
Functional descriptions these pins can be found in the Functional Description section beginning on page 20.
Pin
Pin Name
Pin Function
Formal Name
Definition
1
FETIN
Input
External FET Input
2
IGN
Input
Ignition Input
(Active High)
3
RST
Input
Reset
This input wakes the device. It is also used to initialize the device
configuration and fault registers through the SPI. This pin has a passive
internal pull-down.
4
FLASHER
Input
Flasher Input
(Active High)
This input wakes the device. This pin has a passive internal pull-down.
5
CLOCK
Input
Clock Input
This pin state depends on RST logic level.
As long as RST input pin is set to logic [0], this pin is pulled up in order to
report wake event. Otherwise, the PWM frequency and timing are
generated from this digital clock input by the PWM module.
This pin has a passive internal pull-down.
6
LIMP
Input
Limp Home Input
(Active High)
The Fail mode can be activated by this digital input. This pin has an active
internal pull-down current source.
7
STOP
Input
Stop Light Input
(Active High)
8
CS
Input
Chip Select
(Active Low)
9
SCLK
Input
SPI Clock Input
This pin is the current sense recopy of the external MOSFET.
This input wakes the device. It also controls outputs 1 and 2 in case of
Fail mode activation. This pin has a passive internal pull-down.
This input wakes the device. This pin has a passive internal pull-down.
When this signal is high, SPI signals are ignored. Asserting this pin low
starts a SPI transaction. The transaction is signaled as completed when
this signal returns high. This pin has a passive internal pull-up resistance.
This input pin is connected to the master microcontroller providing the
required bit shift clock for SPI communication. This pin has a passive
internal pull-down resistance.
35XS3500
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
Table 2. 35XS3500 Pin Definitions (continued)
Functional descriptions these pins can be found in the Functional Description section beginning on page 20.
Pin
Pin Name
Pin Function
Formal Name
Definition
10
SI
Input
Master-Out Slave-In
This data input is sampled on the positive edge of the SCLK. This pin has
a passive internal pull-down resistance.
11
VCC
Input
Logic Supply
12
SO
Output
Master-In Slave-Out
SPI data sent to the MCU by this pin. This data output changes on the
negative edge of SCLK, and when CS is high. This pin is high-impedance.
13
FETOUT
Output
External FET Gate
This pin controls an external SMART MOSFET by logic level. This output
called OUT6.
If OUT6 is not used in the application, this output pin is set to logic high
when the current sense output becomes valid when CSNS sync SPI bit is
set to logic [1].
14, 17, 23
GND
Ground
Ground
This pin is the ground for the logic and analog circuitry of the device.(1)
15
VBAT
Input
Battery Input
Power supply pin.
16
CP
Output
Charge Pump
This pin is the connection for an external tank capacitor (for internal use
only).
18
19
20
21
22
OUT5
OUT4
OUT3
OUT2
OUT1
Output
Output
Output
Output
Output
Output 5
Output 4
Output 3
Output 2
Output 1
24
CSNS
Output
Current Sense Output
SPI Logic power supply.
Protected 35 m high side power output to the load.
This pin is used to output a current proportional to OUT1:OUT5, FET in
current, and it is used externally to generate a ground-referenced voltage
for the microcontroller to monitor output current. Moreover, this pin can
report a voltage proportional to the temperature on the GND flag.
OUT1:OUT5, FET in current sensing and Temperature feedback choice is
SPI programmable.
Notes
1. The pins 14, 17, and 23 must be shorted on the board.
35XS3500
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Rating
Symbol
Value
Unit
ELECTRICAL RATINGS
Over-voltage Test Range
Maximum Operation Voltage
Load Dump (400 ms) at 25 °C
VBAT
Reverse Polarity Voltage Range
2.0 Min at 25 °C
VBAT
VCC Supply Voltage
VCC
Output Voltage
Positive
Negative (ground disconnected)
VOUT
Digital Input Current in Clamping Mode (SI, SCLK, CS, IGN, FLASHER,
STOP, LIMP)
FETIN Input Current
SO and FETOUT Output Voltage
Outputs clamp energy using single pulse method (L = 2.0 mH; R = 0 ;
VBAT = 14 V at 150 °C initial)
ESD Voltage(2)
Human Body Model (HBM) OUT[1:5], VPWR, and GND
Charge Device Model (CDM)
Corner Pins (1,13,19,21)
All Other Pins (2-12, 14-18, 20, 22-24)
V
28
40
V
- 18
-0.3 to 5.5
V
V
40
-16
IIN
±1.0
mA
IFETIN
+10
-1.0
mA
VSO
- 0.3 to VCC + 0.3
V
E
30
mJ
VESD
V
± 2000
± 8000
± 750
± 500
THERMAL RATINGS
Operating Temperature
Ambient
Junction
°C
TA
TJ
- 40 to 125
- 40 to 150
Peak Package Reflow Temperature During Reflow(3), (4)
TPPRT
Note 4
°C
Storage Temperature
TSTG
- 55 to 150
°C
RJC
1.0
C/W
THERMAL RESISTANCE
Thermal Resistance, Junction to Case(5)
Notes
2. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ) and the Charge Device
Model.
3. Pin soldering temperature limit is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
4. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
5. Typical value is guaranteed per design.
35XS3500
6
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions 3.0 V  VCC  5.5 V, 7.0 V  VBAT  20 V, -40C  TA  125C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
7.0
–
20
6.0
–
28
VBATUV
5.0
5.5
6.0
V
VBATCLAMP_OV
27.5
30
32.5
V
VBATCLAMP
40
–
48
V
Battery Supply Power on Reset(9)
If VBAT < 5.5 V, VBAT = VCC
VBATPOR1
2.0
–
3.0
If VBAT < 5.5 V, VBAT = 0
VBATPOR2
2.0
–
4.0
IBATSLEEP1
IBATSLEEP2
IBAT
–
–
–
0.5
0.5
10
5.0
5.0
20
A
A
mA
VCC
3.0
–
5.5
V
VCCUV
2.2
2.5
2.8
V
POWER INPUT (VBAT, VCC)
Battery Supply Voltage Range
Full Performance and Short-circuit
VBAT
Extended Voltage Range(6)
Battery Supply Under-voltage (UV flag is set ON)
Battery Voltage Clamp (OV flag is set ON)
Battery Voltage Clamp
V
V
VBAT Supply Current at 25 °C and VBAT =12 V and VCC = 5.0 V
Sleep State Current, Outputs Open
Sleep State Current, Outputs Grounded
Normal Mode, IGN = 5.0 V, RST = 5.0 V, Outputs Open
Digital Voltage Range, Full Performance
Digital Supply Under-voltage (VCC Failure)
Sleep Current Consumption on VCC at 25 °C and VBAT = 12 V
Output OFF
Supply Current Consumption on VCC and VBAT = 12 V
A
ICCSLEEP
–
0.2
5.0
–
–
2.6
–
–
5.0
ICC
No SPI
3.0 MHz SPI Communication
mA
LOGIC INPUT/ OUTPUT (IGN, CS, CSNS, SI, SCLK, CLOCK, SO, FLASHER, RST, LIMP, STOP)
Input High Logic Level(7)
VIH
2.0
–
–
V
Input Low Logic Level(7)
VIL
–
–
0.8
V
VIGNTH
1.0
2.2
V
Ignition Threshold Level (IGN, FLASHER, STOP and RST)
Input Clamp Voltage (IGN, FLASHER, LIMP, STOP, CS, SCLK, SI, RST)
I = 1.0 mA
VCL_POS
Input Forward Voltage (IGN, FLASHER, LIMP, STOP, CS, SCLK, SI, RST)
I = 1.0 mA
VCL_NEG
7.5
–
13
V
- 2.0
–
-0.3
V
RUP
100
200
400
k
Input Passive Pull-down Resistance on SI, SCLK, FLASHER, IGN, FOG,
CLOCK, LIMP and RST pins(8)
RDWN
100
200
500
k
SO High-state Output Voltage
IOH = 1.0 mA
VSOH
0.8
0.95
–
0.8
0.95
–
Input Passive Pull-up Resistance on CS pin(8)
CLOCK Output Voltage reporting wake-up event (ICLOCK=1.0 mA)
Notes
6.
7.
8.
9.
VCLOCKH
VCC
VCC
In extended mode, the functionality is guaranteed but not the electrical parameters.
Valid for RST, SI, SCLK, CLOCK, FLASHER, STOP, and LIMP pins.
Valid for the following input voltage range: VCC = -0.3 to +0.3 V.
Please refer to Loss of VBAT section for more details.
35XS3500
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.0 V  VCC  5.5 V, 7.0 V  VBAT  20 V, -40C  TA  125C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LOGIC INPUT/ OUTPUT (IGN, CS, CSNS, SI, SCLK, CLOCK, SO, FLASHER, RST, LIMP, STOP) (CONTINUED)
SO Low-state Output Voltage
IOL = -1.6 mA
VSOL
SO Tri-state Leakage Current
CS > 0.7 VCC
ISOLEAK
CSNS Tri-state Leakage Current
VCC = 5.5 V, CSNS = 4.5 V
VCC = 5.0 V, CSNS = 5.5 V
VCC = 5.0 V, CSNS = 3.0 V
Current Sense Output Clamp Voltage
ICSNS < 10.0 mA
V
–
0.2
0.4
- 1.0
0.0
1.0
- 5.0
- 10
- 1.0
0.0
0.0
0.0
1.0
1.0
1.0
5.0
6.0
7.0
–
–
0
20
2.0
25
- 22
–
-16
A
A
ICSNSLEAK
VCSNS
V
OUTPUT (OUT 1:5)
Output Leakage Current in OFF state
Sleep mode, Outputs Grounded
Normal mode, Outputs Grounded
Output Negative Clamp Voltage
IOUT = -500 mA, Outputs OFF
Current Sense Output Precision(10)
Full-Scale Range (FSR) for LED Control bit = 0
0.75 FSR
0.50 FSR
0.25 FSR 
0.10 FSR
Full-Scale Range (FSR) for LED Control bit = 1
0.187 FSR = 0.75 FSRLED
0.125 FSR = 0.50 FSRLED
0.062 FSR = 0.25 FSRLED
0.025 FSR = 0.10 FSRLED
A
IOUTLEAK
VOUT
V
ICS / ICS
%
-14
-15
-17
-22
-
14
15
17
22
-13
-13
-20
-30
-
13
13
20
30
-6.0
-
6.0
-6.0
–
6.0
%
–
± 280
± 400
ppm/
°C
%
Current Sense Output Precision
Over-temperature Range [-40;125 °C], VBAT Range [10 V-16 V] and FSR
Range [25%-100%], calculated with one calibration point (Taken at 25 °C,
VBAT = 13.5 V and 50% FSR)(12)
Current Sense Output Precision with one calibration point (50% FSRLED,
VBAT = 13.5 at 25 °C(12)
Temperature Drift of Current Sense Output(11)
VBAT = 13.5 V, IOUT = 2.8 A reference taken at TA = 25 °C
ICS / T
Notes
10. 10 V < VBAT < 16 V. (ICS / ICS = (measured ICS- targeted ICS)/ targeted ICS with targeted ICS = 5.0 mA
11.
Based on statistical data. Not production tested. ICS / T = [(measured at ICS at T1 - measured at ICS at T2) measured at ICS at room]/
(T1 - T2)
12.
Based on statistical analysis covering 99.74% of parts.
35XS3500
8
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.0 V  VCC  5.5 V, 7.0 V  VBAT  20 V, -40C  TA  125C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
65
–
–
40
–
–
TOTS
155
175
195
°C
TOTSWARN
110
125
140
°C
VOUT_TH
0.475
0.5
0.525
VBAT
OUTPUT (OUT 1:5) (CONTINUED)
Minimum Output Current Reported in CSNS for OUT[1-5](13)
10 V VBAT 16 V
Minimum Output Current Reported in CSNS for OUT[1-5] in LED Mode(13)
10 V VBAT 16 V
Over-temperature Shutdown
Thermal Prewarning(14)
Output Voltage Threshold
I35MIN(CSNS)
mA
I35MIN(CSNS) LED
mA
TAIL LIGHT (OUT1)
Output Drain-to-Source ON Resistance (IOUT = 2.8 A, TA = 25 °C)
RDS(ON)
m
VBAT = 13.5 V
–
–
35
VBAT = 7.0 V
–
–
55
Output Drain-to-Source ON Resistance (IOUT = 2.8 A, VBAT = 13.5 V, 
TA = 150
RDS(ON)
°C)(14)
Reverse Output ON Resistance (IOUT = -2.8 A, VBAT = -12 V, TA = 25 °C)(15)
RSD(ON)
m
–
–
59.5
–
–
70
–
–
–
–
70
110
–
–
119
28.0
30.2
35.0
36.0
43.5
41.8
29.4
35.0
40.6
m
TAIL LIGHT (OUT1)
Output Drain-to-Source ON Resistance (IOUT = 1.5 A, TA = 25 °C) for LED
Control = 1
VBAT = 13.5 V
RDS(ON)25_LED
m
VBAT = 7.0 V
Output Drain-to-Source ON Resistance (IOUT = 1.5 A, VBAT = 13.5 V,
RDS(ON)150_LED
TA = 150 °C) for LED Control = 1
m
High Over-current Shutdown Threshold 1
VBAT = 16 V, TA = -40 °C
VBAT = 16 V, TA = 25 °C
VBAT = 16 V, TA = 125 °C
IOCHI1
28.3
33.8
39.3
High Over-current Shutdown Threshold 2
IOCHI2
12.3
15.4
18.5
A
Low Over-current Shutdown Threshold
IOCLO
5.7
7.2
8.9
A
IOL
0.05
0.2
0.5
A
Open Load Current Threshold in ON State(16)
Open Load Current Threshold in ON State with LED(17)
VOL = VBAT - 0.5 V
IOLLED
Current Sense Full-scale Range(18)
ICS FSR
A
mA
4.0
10
20
–
6.0
–
A
Notes
13. Output current value computed after leakage current removal (open load condition)
14. Parameter guaranteed by design; however it is not production tested.
15. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VBAT.
16.
17.
18.
OLLED1, bit D0 in SI data is set to [0]
OLLED1, bit D0 in SI data is set to [1]
For a typical value of ICS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is not guaranteed.
35XS3500
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.0 V  VCC  5.5 V, 7.0 V  VBAT  20 V, -40C  TA  125C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Current Sense Full-scale Range (19) depending on LED Control = 1
ICS FSR_LED
–
1.6
–
A
Severe Short-circuit Impedance Range (19)
RSC1(OUT1)
350
–
–
m
TAIL LIGHT (OUT1) (CONTINUED)
LICENSE LIGHT (OUT2)
Output Drain-to-Source ON Resistance (IOUT = 2.8 A, TA = 25 °C)
RDS(ON)
m
VBAT = 13.5 V
–
–
35
VBAT = 7.0 V
–
–
55
Output Drain-to-Source ON Resistance (IOUT = -2.8 A, VBAT = -13.5 V,
RDS(ON)
(20)
TA = 25 °C)
Reverse Output ON Resistance (IOUT = 2.8 A, VBAT = 12 V, TA = 150 °C)(21)
Output Drain-to-Source ON Resistance (IOUT =1.5 A, TA = 25 °C) for LED
Control = 1
VBAT = 13.5 V
RSD(ON)
m
–
–
59.5
–
–
70
–
–
–
–
70
110
–
–
119
28.0
30.2
35.0
36.0
43.5
41.8
29.4
35.0
40.6
28.3
33.8
39.3
RDS(ON)25_LED
m
m
VBAT = 7.0 V
Output Drain-to-Source ON Resistance (IOUT = 1.5 A, VBAT = 13.5 V,
RDS(ON)150_LED
TA = 150 °C) for LED Control = 1
m
High Over-current Shutdown Threshold 1
VBAT = 16 V, TA = -40 °C
VBAT = 16 V, TA = 25 °C
VBAT = 16 V, TA = 125 °C
IOCHI1
High Over-current Shutdown Threshold 2
IOCHI2
12.3
15.4
18.5
A
Low Over-current Shutdown Threshold
IOCLO
5.7
7.2
8.9
A
IOL
0.05
0.2
0.5
A
4.0
10
20
Open Load Current Threshold in ON State(22)
A
Open Load Current Threshold in ON State with LED(23)
VOL = VBAT - 0.5 V
IOLLED
mA
Current Sense Full-Scale Range(24)
ICS FSR
–
6.0
–
A
Current Sense Full-Scale Range(20) depending on LED Control = 1
ICS FSR_LED
–
1.6
–
A
Severe short-circuit impedance range(20)
RSC1(OUT2)
350
–
–
m
Notes
19. Output current value computed after leakage current removal (open load condition)
20. Parameter guaranteed by design; however, it is not production tested.
21. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VBAT.
22.
23.
24.
OLLED2, bit D0 in SI data is set to [0]
OLLED2, bit D0 in SI data is set to [1]
For typical value of ICS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is not guaranteed.
35XS3500
10
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.0 V  VCC  5.5 V, 7.0 V  VBAT  20 V, -40C  TA  125C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
VBAT = 13.5 V
–
–
35
VBAT = 7.0 V
–
–
55
–
–
59.5
–
–
70
–
–
–
–
70
110
–
–
119
28.0
30.2
35.0
36.0
43.5
41.8
29.4
35.0
40.6
28.3
33.8
39.3
Unit
TAIL LIGHT (OUT3)
Output Drain-to-Source ON Resistance (IOUT = 2.8 A, TA = 25 °C)
Output Drain-to-Source ON Resistance (IOUT = 2.8 A, VBAT = 13.5 V,
RDS(ON)25
RDS(ON)150
TA = 150 °C)(25)
Reverse Source-to-Drain ON Resistance (IOUT = -2.8 A, VBAT = -12 V,
m
RSD(ON)25
m
m
TA = 25 °C)(26)
Output Drain-to-Source ON Resistance (IOUT = 1.5 A, TA = 25 °C) for LED
Control = 1
VBAT = 13.5 V
RDS(ON)25_LED
m
VBAT = 7.0 V
Output Drain-to-Source ON Resistance (IOUT = 1.5 A, VBAT = 13.5 V,
RDS(ON)150_LED
TA = 150 °C) for LED Control = 1
m
High Over Current Shutdown Threshold 1
VBAT = 16 V, TA = -40 °C
VBAT = 16 V, TA = 25 °C
VBAT = 16 V, TA = 125 °C
IOCHI1
High Over-current Shutdown Threshold 2
IOCHI2
12.3
15.4
18.5
A
Low Over-current Shutdown Threshold
IOCLO
5.7
7.2
8.9
A
IOL
0.05
0.2
0.5
A
4.0
10
20
Open Load Current Threshold in ON State(27)
A
Open Load Current Threshold in ON State with LED(28)
VOL = VBAT - 0.5 V
IOLLED
mA
Current Sense Full-scale Range(29)
ICS FSR
–
6.0
–
A
Current Sense Full-scale Range(25) depending on LED Control = 1
ICS FSR_LED
–
1.6
–
A
Severe short-circuit impedance range(25)
RSC1(OUT3)
350
–
–
m
Notes
25. Parameter guaranteed by design; however, it is not production tested.
26. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VBAT.
27.
28.
29.
OLLED3, bit D2 in SI data is set to [0]
OLLED3, bit D2 in SI data is set to [1]
For a typical value of ICS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is not guaranteed.
35XS3500
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.0 V  VCC  5.5 V, 7.0 V  VBAT  20 V, -40C  TA  125C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
VBAT = 13.5 V
–
–
35
VBAT = 7.0 V
–
–
55
–
–
59.5
Unit
STOP LIGHT (OUT4)
Output Drain-to-Source ON Resistance (IOUT = 2.8 A, TA = 25 °C)
Output Drain-to-Source ON Resistance (IOUT = 2.8 A, VBAT = 13.5 V,
RDS(ON)25
RDS(ON)150
TA = 150 °C)(30)
Output Drain-to-Source ON Resistance (IOUT = 1.5 A, TA = 25 °C) for LED
Control = 1
VBAT = 13.5 V
m
m
RDS(ON)25_LED
m
–
–
–
–
70
110
–
–
119
RDS(ON)25
–
–
70
m
High Over-current Shutdown Threshold 1
VBAT = 16 V, TA = -40 °C
VBAT = 16 V, TA = 25 °C
VBAT = 16 V, TA = 125 °C
IOCHI1
28.0
30.2
35.0
36.0
43.5
41.8
A
29.4
35.0
40.6
28.3
33.8
39.3
High Over-current Shutdown Threshold 2
IOCHI2
12.3
15.4
18.5
A
Low Over-current Shutdown Threshold
IOCLO
5.7
7.2
8.9
A
IOL
0.05
0.2
0.5
A
4.0
10
20
VBAT = 7.0 V
Output Drain-to-Source ON Resistance (IOUT =1.5 A, VBAT = 13.5 V,
RDS(ON)150_LED
TA = 150 °C) for LED Control = 1
Reverse Source-to-Drain ON Resistance (IOUT = -2.8 A, VBAT = -12 V,
m
TA = 25 °C)(31)
Open Load Current Threshold in ON State(32)
Open Load Current Threshold in ON State with LED(33)
VOL = VBAT - 0.5 V
IOLLED
mA
Current Sense Full-scale Range(34)
ICS FSR
–
6.0
–
A
Current Sense Full-scale Range(30) depending on LED Control = 1
ICS FSR_LED
–
1.6
–
A
Severe Short-circuit Impedance Range(30)
RSC1(OUT4)
350
m
Notes
30. Parameter guaranteed by design; however, it is not production tested.
31. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VBAT.
32.
33.
34.
OLLED3, bit D2 in SI data is set to [0]
OLLED3, bit D2 in SI data is set to [1]
For a typical value of ICS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is not guaranteed.
35XS3500
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.0 V  VCC  5.5 V, 7.0 V  VBAT  20 V, -40C  TA  125C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
VBAT = 13.5 V
–
–
35
VBAT = 7.0 V
–
–
55
–
–
59.5
–
–
70
Unit
FLASHER (OUT5)
Output Drain-to-Source ON Resistance (IOUT = 2.8 A, TA = 25 °C)
Output Drain-to-Source ON Resistance (IOUT = 2.8 A, VBAT = 13.5 V,
TA = 150
RDS(ON)25
RDS(ON)150
°C)(35)
Reverse Source-to-Drain ON Resistance (IOUT = -2.8 A, VBAT = -12 V,
m
RSD(ON)25
m
m
TA = 25 °C)(36)
Output Drain-to-Source ON Resistance (IOUT =1.5 A, TA = 25 °C) for LED
Control = 1
VBAT = 13.5 V
RDS(ON)25_LED
VBAT = 7.0 V
Output Drain-to-Source ON Resistance (IOUT = 1.5 A, VBAT = 13.5 V,
m
–
–
–
–
70
110
–
–
119
28.0
30.2
35.0
36.0
43.5
41.8
29.4
35.0
40.6
28.3
33.8
39.3
RDS(ON)150_LED
TA = 150 °C) for LED Control = 1
m
High Over-current Shutdown Threshold 1
VBAT = 16 V, TA = -40 °C
VBAT = 16 V, TA = 25 °C
VBAT = 16 V, TA = 125 °C
IOCHI1
High Over-current Shutdown Threshold 2
IOCHI2
12.3
15.4
18.5
A
Low Over-current Shutdown Threshold
IOCLO
5.7
7.2
8.9
A
IOL
0.05
0.2
0.5
A
4.0
10
20
Open Load Current Threshold in ON State(37)
A
Open Load Current Threshold in ON State with LED(38)
VOL = VBAT - 0.5 V
IOLLED
mA
Current Sense Full-scale Range(39)
ICS FSR
–
6.0
–
A
Current Sense Full-scale Range(35) depending on LED Control = 1
ICS FSR_LED
–
1.6
–
A
Severe Short-circuit Impedance Range(35)
RSC1(OUT5)
350
–
–
m
Notes
35. Parameter guaranteed by design; however, it is not production tested.
36. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VBAT.
37.
38.
39.
OLLED3, bit D2 in SI data is set to [0]
OLLED3, bit D2 in SI data is set to [1]
For a typical value of ICS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is not guaranteed.
35XS3500
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.0 V  VCC  5.5 V, 7.0 V  VBAT  20 V, -40C  TA  125C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
FETOUT Output High Level at I = 1.0 mA
VH MAX
0.8
–
–
VCC
FETOUT Output Low Level at I = 1.0 mA
VH MIN
–
0.2
0.4
V
FETIN Input Full Scale Range Current
IFET IN
–
5.0
–
mA
FETIN Input Clamp Voltage
VCLIN
5.3
–
7.0
V
Drop Voltage between FETIN and CSNS for MUX[2:0] = 110
IFET IN = 5 mA, 5.5 V > CSNS > 0.0 V
VDRIN
0.0
–
0.4
- 1.0
- 1.0
–
–
5.0
1.0
VT_FEED
920
1025
1140
mV
Analog Temperature Feedback Derating with 5.0 k > RCSNS > 500 (40)
VDT_FEED
10.9
11.3
11.7
mV/ °C
Analog Temperature Feedback Precision(40)
VDT_ACC
-15
–
15
°C
VDT_ACC_CAL
-5.0
–
5.0
°C
SPARE (FETOUT , FETIN)
FETIN Leakage Current when external current switch sense is enabled
4.5 V > VFET IN > 0 V, 5.5 V > VCC > 4.5 V, CSNS open
V
A
IFETINLEAK
3.0 V > VFET IN > 0 V, 4.5 V > VCC > 0, CSNS open
TEMPERATURE OF GND FLAG
Analog Temperature Feedback at TA = 25 °C with 5.0 k > RCSNS > 500 
Analog Temperature Feedback Precision with calibration point at 25 °C(40)
Notes
40. Parameter guaranteed by design; however, it is not production tested.
35XS3500
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.5 V  VCC  5.5 V, 7.0 V  VBAT  20 V, -40C  TA  125C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUTS TIMING (OUT1:5)
Current Sense Valid Time on resistive load only(41)
SR bit = 0
SR bit = 1
t CSNS(VAL)
Current Sense Synchronization Time on FETOUT
SR bit = 0
SR bit = 1
t CSNS(SYNC)
s
–
90
150
–
45
75
–
130
185
–
70
110
–
10
30
SR bit = 0, IOUT = 2.8 A
0.10
0.25
0.56
SR bit = 1, IOUT = 0.7 A
0.20
0.40
0.80
0.10
0.25
0.56
0.20
0.40
0.80
0.8
1.0
1.2
Current Sense Settling Time on resistive load only
(41)
Driver Output Positive Slew Rate (30% to 70% at VBAT = 14 V)
Driver Output Negative Slew Rate (70% to 30% at VBAT = 14 V)
SR bit = 0, IOUT = 2.8 A
t CSNS(SET)
SRR
SRF
SR bit = 1, IOUT = 0.7 A
Driver Output Matching Slew Rate (SRR/SRF)(70% to 30% at VBAT = 14 V
at 25 °C)
Driver Output Turn-ON Delay (SPI ON Command [No PWM, CS Positive
Edge] to Output = 50% VBAT at VBAT = 14 V)
s
V/s
V/s
SR
s
t DLYON
SR bit = 0, IOUT = 2.8 A
50
–
120
SR bit = 1, IOUT = 0.7 A
25
–
65
Driver Output Turn-OFF Delay (SPI OFF command [CS Positive Edge] to
Output = 50% VBAT at VBAT = 14 V)
s
t DLYOFF
SR bit = 0, IOUT = 2.8 A
50
–
120
SR bit = 1, IOUT = 0.7 A
25
–
65
Driver Output Matching Time (t DLY(ON) - t DLY(OFF)) at Output = 50% VBAT
with VBAT = 14 V, f PWM = 240 Hz, PWM = 50%, at 25 °C
SR bit = 0, IOUT = 2.8 A for OUT1/2/3/4/5
SR bit = 1, IOUT = 0.7 A for OUT1/2/3/4/5
s
s
t RF
-40
-23
–
20
–
7.0
Notes
41. Not production tested.
35XS3500
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V  VCC  5.5 V, 7.0 V  VBAT  20 V, -40C  TA  125C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Nominal PWM Frequency Range(44)
f PWM
30
–
400
Hz
Clock Input Frequency Range
f CLK
7.68
–
51.2
kHz
PWM_MAX
4.0
–
96
%
Output PWM Duty Cycle linear range for 11 V<VBAT<18 V(43), (44)
PWM_LIN
5.5
–
96
%
Output PWM Duty Cycle range for full diagnostic for 11 V<VBAT<18 V(45)
200 Hz Output PWM frequency
400 Hz Output PWM frequency
PWM_DIAG
5.5
–
96
11
–
90
t WDTO
50
75
100
ms
Fault Shutdown Delay Time (from Over-temperature or OCHI1 or OHCI2 or
OCLO Fault Detection to Output = 50% VBAT without round shaping feature
for turn off)
t SD
–
7.0
30
s
Under-voltage Deglitch Time(46)
t UV
0.8
1.25
2.0
s
High Over-current Threshold Time 1
t1
7.0
10
13.5
ms
High Over-current Threshold Time 2
t2
52.5
75
97.5
ms
tAUTORST
52.5
75
97.5
ms
t OCSH_AUTO
3.5
5.0
6.5
ms
t LIMP
7.0
10.0
13.0
ms
t OLLED
105
150
195
ms
Flasher Toggle Timeout
t FLASHER
1.4
2.3
3.0
s
Ignition Toggle Timeout
t IGNITION
1.4
2.3
3.0
s
tSTOP
1.4
2.3
3.0
s
Clock Input Low Frequency Detection Range
f LCLK DET
1.0
2.0
4.0
kHz
Clock Input High Frequency Detection Range
f HCLK DET
100
200
400
kHz
PWM MODULE
Output PWM Duty Cycle maximum range for 11 V<VBAT<18 V(42), (44)
%
WATCHDOG TIMING
Watchdog Timeout (SPI Failure)
I /O PLAUSIBILITY CHECK TIMING
Autorestart Period
Autorestart Over-current Shutdown Delay Time
Limp Home Input pin Deglicher Time
Cyclic Open Load Detection Timing with LED(47)
Stop Toggle Timeout
Notes
42. The PWM ratio is measured at VOUT = 50% of VBAT in nominal range of frequency. It is possible to put the device fully on (PWM duty
cycle = 100%) and fully off (PWN duty cycle = 0%). Between 4%-96%, OCLO1,2, OCLO and open load are available in ON state. See
Input Timing Switching Characteristics on page 18.
43. Linear range is defined by output duty cycle to SPI duty cycle configuration +/- LSB. For values outside the linear duty cycle range, a
calibration curve is available.
44. Not production tested.
45. Full diagnostic corresponds to the availability of the following features: output current sensing, output status and openload detection.
Not production tested.
46. This time is measured from the VBAT(UV) level to the fault reporting. Parameter guaranteed in testmode.
47.
OLLEDn bit (where “n” corresponds to respective outputs 1 through 5) in SI data is set to logic [1]. Refer to Table 9, Serial Input Address
and Configuration Bit Map.
35XS3500
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V  VCC  5.5 V, 7.0 V  VBAT  20 V, -40C  TA  125C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
f SPI
–
–
3.0
MHz
t CS
–
–
1.0
us
t LEAD
–
–
500
ns
Required High State Duration of SCLK (Required Setup Time)(48)
t WSCLKH
–
–
167
ns
Required Low State Duration of SCLK (Required Setup Time)(48)
t WSCLKl
–
–
167
ns
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)(48)
t LAG
–
50
167
ns
SI to Falling Edge of SCLK (Required Setup Time)(49)
t SI SU
–
25
83
ns
Falling Edge of SCLK to SI (Required Setup Time)(49)
t SI HOLD
–
25
83
ns
SPI INTERFACE CHARACTERISTICS
Maximum Frequency of SPI Operation
Rising Edge of CS to Falling Edge of CS (Required Setup Time)
(48)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)(48)
SO Rise Time
CL = 80 pF
t RSO
SO Fall Time
CL = 80 pF
t FSO
SI, CS, SCLK, Incoming Signal Rise Time(50)
SI, CS, SCLK, Incoming Signal Fall Time(50)
ns
–
25
50
–
25
50
t RSI
–
–
50
ns
t FSI
–
–
50
ns
Time from Falling Edge of CS to SO Low-impedance(51)
t SO(EN)
–
–
145
ns
Time from Rising Edge of CS to SO High-impedance(52)
t SO(DIS)
–
65
145
ns
Notes
48.
49.
50.
51.
52.
ns
Maximum setup time required for the 35XS3500 is the minimum guaranteed time needed from the microcontroller.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at SO. 1.0 kon pull-up on CS.
Time required for output status data to be terminated at SO. 1.0 kon pull-up on CS.
Time required to obtain valid data out from SO following the rise of SCLK.
35XS3500
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
VIL
VIL
TwRSTB
t
tTCSB
CS
ENBL
TENBL
VIH
V
90%
VCC
0.7VDD
CS
CSB
IH
10%
VCC
0.7VDD
t WSCLKH
TwSCLKh
tTlead
LEAD
VIL
V
IL
t RSI
TrSI
t LAG Tlag
90%
VCC
0.7VDD
SCLK
SCLK
VIH
VIH
10% VCC
0.2VDD
VIL
V
t SI(SU)
TSIsu
IL
t WSCLKL
TwSCLKl
tTfSI
FSI
t SI(HOLD)
TSI(hold)
SI
SI
VIH
V
90%
VCC
0.7 VDD
0.2VDD
10% VCC
Don’t Care
Don’t Care
Valid
Valid
Don’t Care
IH
VIL
VIL
Figure 4. Input Timing Switching Characteristics
t FSI
t RSI
TrSI
TfSI
VOH
VOH
2.0 V
3.5V
50%
SCLK
SCLK
1.0VV
0.8
VOL
VOL
t SO(EN)
TdlyLH
SO
SO
90%
VCC
0.7 VDD
0.210%
VDDVCC
Low-to-High
Low
to High
TrSO
t RSO
VOH
VOH
VOL
VOL
VALID
tTVALID
SO
TfSO
t FSO
SO
VOH
VOH
VCC
VDD
High to Low 0.790%
High-to-Low
0.2VDD
10% VCC
TdlyHL
VOL
VOL
tSO(DIS)
Figure 5. SCLK Waveform and Valid SO Data Delay Time
35XS3500
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
CS
High logic level
Low logic level
Time
VOUT[1:5]
VPWR
RPWM
50%VPWR
Time
t DLY(ON)
VOUT[1:5]
70% VPWR
t DLY(OFF)
SR F
SR R
30% VPWR
Time
Figure 6. Output Slew Rate and Time Delays
CS
High logic level
Low logic level
Time
IOUT[1:5]
IMAX
Time
t DLY(ON)
ICSNS
t CSNS(SET)
t DLY(OFF)
t CSNS(VAL)
Time
VFETOUT
t CSNS(SYNC)
High logic level
with CSNS sync bit = 1
Low logic level
Time
Figure 7. Current Sensing Time Delays
35XS3500
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 35XS3500 is designed for low-voltage automotive and
industrial lighting applications. Its five low RDS(ON) MOSFETs
(five 35 m) can control the high sides of five separate
resistive loads (bulbs). Programming, control, and
diagnostics are accomplished using a 16-bit SPI interface.
FUNCTIONAL PIN DESCRIPTION
Supply Voltage (VBAT)
The VBAT pin of the 35XS3500 is the power supply of the
device. In addition to its supply function, this tab contributes
to the thermal behavior of the device by conducting the heat
from the switching MOSFETs to the printed circuit board.
Supply Voltage (VCC)
This is an external voltage input pin used to supply the SPI
digital portion of the circuit and the gate driver of the external
SMART MOSFET.
The amplitude of the input current is divided by four while
the frequency is four times the original one. The two following
pictures illustrate the behavior.
Ch.1
Ch.2
Ch.3
Ch.4
Total
Ground (GND)
This pin is the ground of the device.
0°
90°
180°
270°
0°
0°
90°
180°
270°
0°
Clock Input (CLOCK) and PWM Module
When the part is in Normal Mode (RST=1), the PWM
frequency and timing are generated from the rising edge of
clock input by the PWM module. The clock input frequency is
the selectable factor 27 = 128 or 28 = 256 of the PWM
frequency per output, depending PR bit value.
The OUT1:6 can be controlled in the range of 4% to 96%
with a resolution of 7 bits of duty cycle (bits D[6:0]).
Ch.1
Ch.2
Ch.3
Ch.4
Total
The following table describes the PWM resolution.
On/Off (Bit
D7)
Duty cycle (7 bits
resolution)
Output state
0
X
OFF
1
0000000
PWM (1/128 duty cycle)
1
0000001
PWM (2/128 duty cycle)
1
0000010
PWM (3/128 duty cycle)
1
1111111
fully ON
Table 6. PWM Resolution
The timing includes four programmable PWM switching
phases (0°, 90°, 180°, and 270°) to improve overall EMC
behavior of the light module.
The synchronization of the switching phases between
different corner light IC is provided by a SPI command in
combination with the CS input. The bit in the SPI is called
PWM sync (initialization register).
In Normal mode, No PWM feature (100% duty cycle) is
provided in the following instances:
• with the following SPI configuration: D7:D0=FF.
• In case of clock input signal failure (out of fPWM), the
outputs state depends on the D7 bit value (D7=1+ON)
in Normal mode.
In Fail mode. The outputs state depends on the IGN,
STOP and Flasher pins.
If RST=0, this pin reports the wake-up event for wake=1
when VBAT and VCC are in operational voltage range.
35XS3500
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
Limp Home (LIMP)
FETOUT Output (FETOUT)
The Limp Home mode of the component can be activated
by this digital input port. The signal is “high active”, meaning
the Fail mode can be activated by a logic high signal at the
input.
This output pin is used to control an external MOSFET
(OUT6).
Ignition Input (IGN)
The Ignition input wakes the device. It also controls the
Fail Home mode activation. The signal is “high active”,
meaning the component is active in case of a logic high at the
input.
Flasher Input (FLASHER)
The Flasher input wakes the device. It also controls the
Fail mode activation. The signal is “high active”, meaning the
component is active in case of a logic high at the input.
Reset Input (RST)
This input wakes the device when the RST pin is at
logic [1]. It is also used to initialize the device configuration
and the SPI fault registers when the signal is low. All SI/SO
registers described in Table 9 and Table are reset. The fault
management is not affected by RST (see Figure 2).
Current Sense Output (CSNS)
The current sense output pin is an analog current output or
a voltage proportional to the temperature on the GND flag.
The routing to the common resistor is SPI programmable.
This current sense monitoring may be synchronized in
case of the OUT6 is not used. So, the current sense
monitoring can be synchronized with a rising edge on the
FETOUT pin (tCSNS(SYNC)) if CSNS sync SPI bit is set to logic
[1]. Connection of the FETOUT pin to a MCU input pin allows
the MCU to sample the CSNS pin during a valid time-slot.
Since this falling edge is generated at the end of this timeslot,
upon a switch-off command, this feature may be used to
implement maximum current control.
Charge Pump (CP)
An external capacitor is connected between this pin and
the VBAT pin. It is used as a tank for the internal charge
pump. Its typical value is 100 nF ± 20%, 25 V maximum.
The high level of the FETOUT Output is VCC if VBAT and
VCC are available in case of FETOUT is controlled ON.
FETOUT is not protected in case of a short-circuit or
under-voltage on VBAT.
In case of a reverse battery, OUT6 is OFF.
FETIN Input (FETIN)
This input pin gives the current recopy of the external
MOSFET. It can be routed on the CSNS output by a SPI
command.
SPI Protocol Description
The SPI interface has a full-duplex, three-wire
synchronous data transfer with four I /O lines associated with
it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO),
and Chip Select (CS).
The SI/SO pins of the 35XS3500 device follow a first-in,
first-out (D15 to D0) protocol, with both input and output
words transferring the most significant bit (MSB) first. All
inputs are compatible with 5.0 V CMOS logic levels supplied
by VCC.
The SPI lines perform the following functions:
Serial Clock (SCLK)
The SCLK pin clocks the internal shift registers of the
35XS3500 device. The SI pin accepts data into the input shift
register on the falling edge of the SCLK signal, while the SO
pin shifts data information out of the SO line driver on the
rising edge of the SCLK signal. It is important that the SCLK
pin be in a logic low state whenever CS makes any transition.
For this reason, it is recommended that the SCLK pin be in a
logic [0] whenever the device is not accessed (CS logic [1]
state). SCLK has a passive pull-down, RDWN. When CS is
logic [1], signals at the SCLK and SI pins are ignored and SO
is tri-stated (high-impedance) (see Figure 8).
35XS3500
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
CSB
CS
CS
SCLK
SI
D15
SO
D14
D13
D12
D11
D10
D9
OD15 OD14 OD13 OD12 OD11 OD10 OD9
Notes
NOTES: 1.
2.
3
D8
OD8
D7
OD7
D6
OD6
D5
D4
OD5
D3
OD4
OD3
D2
OD2
D1
D0
OD1 OD0
RSTB
is in a logic
H state
during
the above
operation.
1.
D15:D0
relate
to the
most
recent
ordered entry of data into the device.
device.
DO,OD15:OD0
D1, D2, ... , and
D15 relate
to first
the most
recentofordered
entry
of program
data into
the LUX
IC the device.
2.
relate
to the
16 bits
ordered
fault
and status
data
out of
device.
OD0 OD1 OD2
and OD15 relate to the first 16 bits of ordered fault and status data out of the LUX
IC
Figure 8. Single 16-Bit Word SPI Communication
Serial Input (SI)
Chip Select (CS)
The SI pin is a serial interface command data input pin.
Each SI bit is read on the falling edge of SCLK. A 16-bit
stream of serial data is required on the SI pin, starting with
D15 to D0. SI has a passive pull-down, RDOWN.
The CS pin enables communication with the master
device. When this pin is in a logic [0] state, the device is
capable of transferring information to, and receiving
information from, the master device. The 35XS3500 device
latches in data from the Input Shift registers to the addressed
registers on the rising edge of CS. The device transfers
status information from the power output to the Shift register
on the falling edge of CS. The SO output driver is enabled
when CS is logic [0]. CS should transition from a logic [1] to a
logic [0] state only when SCLK is a logic [0]. CS has a
passive pull-up, RUP.
Serial Output (SO)
The SO data pin is a tri-state output from the shift register.
The SO pin remains in a high-impedance state until the CS
pin is put into a logic [0] state. The SO data is capable of
reporting the status of the output, the device configuration,
and the state of the key inputs. The SO pin changes state on
the rising edge of SCLK and reads out on the falling edge of
SCLK.
STOP Input (STOP)
The STOP input wakes the device. It also controls the Fail
mode activation. The signal is “high active“, meaning the
component is active in case of a logic high at the input.
35XS3500
22
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Sleep Mode
The Sleep mode is the default mode of the 35XS3500.
This is the state of the device after first applying battery
voltage (VBAT) and prior to any I /O transitions. This is also the
state of the device when IGN, RST, FLASHER, and STOP
are logic [0]. In the Sleep mode, the output and all internal
circuitry are OFF to minimize current draw. In addition, all
SPI-configurable features of the device are reset. The
35XS3500 will transit to two modes (Normal and Fail)
depending on wake and fail signals (see Table 18).
The transition to the other modes is according to the
following signals:
• Wake = IGN or IGN_ON or FLASHER or
FLASHER_ON or STOP or STOP_ON or RST
• Fail = VCC fail or SPI fail or External limp
Normal Mode
The 35XS3500 is in Normal mode when:
• Wake = 1
• Fail = 0
In Normal operating mode the power outputs are under full
control of the SPI as follows:
• The outputs 1 to 6, including multiphase timing, and
selectable slew-rate, are controlled by the
programmable PWM module.
• The output 4 is activated directly by the STOP external
pin in case the STOP_en bit is set to a logic [1].
• The outputs 1 to 5 are switched OFF in case of undervoltage on VBAT.
• The outputs 1 to 5 are protected by the selectable overcurrent double window and over-temperature shutdown
circuit.
• The digital diagnosis feature transfers status of the
smart outputs via the SPI.
• The analog current sense output (current recopy
feature) can be rerouted by the SPI.
• The outputs can be configured to control LED loads:
RDS(ON) is increased by a factor of 2 and the current
recopy ratio is scaled by a factor of 4.
• The SPI reports NM=1 in this mode.
The following figure describes the PWM, outputs and overcurrent behavior in Normal mode.
D7 bit
D0-D6 bits
Output
Over-current
Fail Mode
The 35XS3500 is in Fail mode when:
• Wake = 1
• Fail = 1
In Fail mode:
• The outputs are under control of the external pins (see
Table 6).
• The outputs are fully protected in case of overload,
over-temperature and under-voltage (on BVAT or on
VCC).
• The SPI reports continuously the content of address 11,
disregard to previous requested output data word.
• Neither digital diagnosis feature (SPI) nor analog
current sense are available.
• In case of overload (OCHI2 or OCLO) conditions or
under-voltage on VBAT, the outputs are under control
of the autorestart feature.
• In case of a serious overload condition (OCHI1 or OT)
the corresponding output is latched OFF until a new
wake-up event (wake = 0 then 1)
IGN_ON
1.4 sec min
IGN (external)
OUT[1,2]
Over-current
Table 7. Limp Home Output State
Output 1
Tail Light
Output 2
License Light
Output 3
Rear Drive Light
Output 4
Stop Light
Output 5
Flasher
External Switch
Rear Fog Light
IGN Pin
OFF
OFF
STOP Pin
FLASHER Pin
OFF
35XS3500
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Autorestart Strategy
The Autorestart is not limited in time.
The autorestart circuitry is used to supervise the outputs
and reactivate high side switches in case of overload or
under-voltage failure conditions, and provide a high
availability of the outputs.
This autorestart is available in Fail mode when no
supervising intelligence of the microcontroller is available.
Autorestart is activated in case of an overload condition
(OCHI2 or OCLO) or under-voltage condition on VBAT (Table
9, Over-current window in case of Autorestart).
The autorestart switches ON the outputs. During the ON
state of the switch OCHI1, the window is enabled for
tochi_Auto, then after the output is protected by OCLO.
Transition Fail to Normal Mode
To leave the Fail mode, the fail condition must be removed
(fail=0). The microcontroller has to toggle the SPI D10 bit (0
to 1) to reset to the watchdog bit; the other bits are not
considered. The previous latched faults are reset by the
transition into Normal mode.
Transition Normal to Fail Mode
To leave the Normal mode, a fail condition must occur
(fail=1). The previous latched faults are reset by the transition
into Fail mode.
If the SI is shorted to VCC, the device transmits to Fail
Safe mode until the WD bit toggles through the SPI (from [0]
to [1]).
Output current
All settings are according to predefined values (all bits set
to logic [0]).
OCHI1
START-UP SEQUENCE
OCLO or UV fault
OCLO
tochi_auto
Auto period
time
Figure 9. Over-current window in case of Autorestart
In case of OCHI1 or OT, the switch is latched OFF until
wake up (wake=0, then 1).
In case of OCLO or under-voltage, the output switch is
OFF. After the autorestart period (75 ms) is turned ON again.
In case an under-voltage occurred in Fail mode, it will be
latched and delatched after the auto restart period
(tAUTORST).
The 35XS3500 enters into Normal mode after start-up if
the following sequence is provided:
• VBAT and VCC power supplies must be above their
under-voltage thresholds (Sleep mode).
• Generate a wake-up event (wake=1) from 0 to 1 on
RST. The device switches to Normal mode.
• Apply the PWM clock after a maximum of 200 s (min.
50 s).
• Send a SPI command to the device status register to
clear the clock fail flag and enable the PWM module to
start.
If the correct startup sequence is not provided, the PWM
function is not guaranteed.
Figure 10 describes the wake-up block diagram.
POWER OFF MODE
The 35XS3500 is in Power OFF mode when the battery
voltage is below VBATPOR[1,2] thresholds. For more details,
please refer to Loss of VBAT paragraph.
35XS3500
24
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Sleep
(wake=0)
(fail=0) and (wake=1)
(wake=1) and (fail=1) *
(wake=0)
VBAT > VBATPOR[1,2]
VBAT < VBATPOR[1,2]
VBAT < VBATPOR[1,2]
Power OFF
VBAT < VBATPOR[1,2]
Normal
Fail
(fail=0) and (wake=1)
(fail=1) and (wake=1)
Notes:
* only available in case of VCC fail condition
wake=(RST=1) OR (IGN_ON=1) OR (Flasher_ON=1) OR (Stop_ON=1)
fail=(VCC_fail=1) OR (SPI_fail=1) OR (ext_limp=1)
Figure 10. Operating Modes State Machine
35XS3500
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
VBAT
wake
Wake-up bar
IGN
Deglitcher
VBAT
VCC
Internal
regulator
IGN_ON
Dig2.5V
FLASHER
FOG
Flasher_ON
Deglitcher
Oscillator
Fog_ON
Fault
management
Deglitcher
PWM freq
detector
SPI registers
VCC fail
SPI fail
External
Limp
RST
PWM module
OR
reset
Fail
VCC
OR
CLOCK
UVF
1.4 sec min
external
external_ON
external: IGN, FLASHER, FOG
external_ON: IGN_ON, FLASHER_ON, FOG_ON
Figure 11. Wake-up Block Diagram
35XS3500
26
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
Serial Input Communication

Table 8. SI Message Bit Assignment
SPI communication compliant to 3.3 and 5.0 V is
accomplished using 16-bit messages. A message is
transmitted by the master starting with the MSB, D15, and
ending with the LSB, D0. Each incoming command message
on the SI pin can be interpreted using the bit assignment
described in Table 8. The 5 bits D15 : D11, called register
address bits, are used to select the command register. Bit
D10 is the watchdog bit. The remaining 10 bits, D9 : D0, are
used to configure and control the output and its protection
features. Multiple messages can be transmitted in
succession to accommodate those applications where daisy
chaining is desirable or to confirm transmitted data as long as
the messages are all multiples of 16 bits. Any attempt made
to latch in a message that is not 16 bits will be ignored.
Bit Sig
SI Msg Bit
MSB
D15 : D11
Register address bits.
D10
LSB
Message Bit Description
Watchdog in: toggled to satisfy watchdog
requirements.
D9 : D0
Used to configure inputs, outputs, device
protection features, and SO status content.
Device Register Addressing
The register addresses (D15 : D11) and the impact of the
serial input registers on device operation are described in this
section. Table 9 summarizes the content of the SI registers.
All SPI registers are reset (all bits equal 0) in case of RST
equals 0 or fail mode (Fail=1).
Table 9. Serial Input Address and Configuration Bit Map
SI Address
SI Data
SI Register D1 D1 D1 D1 D1
D10
5
4
3
2
1
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
STOPen
PWM
sync
0
MUX2
MUX1
MUX0
SOA1
SOA0
LED
LED
LED
Initializatio
n
0
0
0
0
0
WD
Config OL
0
0
0
0
1
WD
Config
Prescaler
0
0
0
1
0
WD
0
Config SR
0
0
0
1
0
WD
1
Config
CSNS
0
0
0
1
1
WD
Control
OUT1
0
1
0
0
1
WD
Control
OUT2
0
1
0
1
0
Control
OUT3
0
1
0
1
Control
OUT4
0
1
1
Control
OUT5
0
1
Control
External
Switch
0
1
LED
LED
Control OLLED5 OLLED4 OLLED3 OLLED2 OLLED1
1
Control3
Control
2
PR1
PR2
PR3
0
0
0
PR4
PR5
PR6
SR1
SR2
SR3
0
0
0
SR4
SR5
0
0
0
0
0
NO_OC
HI5
NO_OC
HI4
NO_OC
HI3
NO_OC
HI2
NO_OC
HI1
Phase2
Phase1
ONoff
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
WD
Phase2
Phase1
ONoff
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
1
WD
Phase2
Phase1
ONoff
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
0
0
WD
Phase2
Phase1
ONoff
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
1
0
1
WD
Phase2
Phase1
ONoff
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
1
1
0
WD
Phase2
Phase1
ONoff
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
Control5 Control4
CSNS
sync
35XS3500
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 9. Serial Input Address and Configuration Bit Map
RESET
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
Note: testmode address used only by FSL is D[15:11]=01111 with RST voltage higher than 8.0 V typ.
ADDRESS 00000 — Initialization
The Initialization register is used to read the various
statuses, choose one of the six outputs current recopy,
enable the STOP pin, and synchronize the switching phases
between different corner light devices. The register bits D1
and D0 determine the content of the 16 bits of SO data.
(Refer to the section entitled Serial Output Communication
(Device Status Return Data)) Bits D9 : D2 are described in
Table .
The watchdog timeout is specified by the t WDTO
parameter. As long as the WD bit (D10) of an incoming SPI
message is toggled within the minimum watchdog timeout
period (WDTO), the device will operate normally. If an
internal watchdog timeout occurs before the WD bit is
toggled, the device will revert to Fail mode. All registers are
cleared. To exit the Fail mode, send valid SPI communication
with WD bit = 1.
Table 10. Initialization Register
SI Address
D15
0
D14
0
D13
0
SI Data
D12
0
D11
0
D10
WD
D9
0
D8
0
x = Don’t care
D6 (PWM sync) = 0, No synchronization
D6 (PWM sync) = 1, Synchronization on CSB positive edge
D7 (STOPen) = 0, STOP pin does not control the output 4.
D7 (STOPen) = 1, STOP pin controls the output 4.
ADDRESS 00001 — Configuration OL
The Configuration OL register is used to enable the open
load detection for LEDs in Normal mode (OLLEDn in Table 9)
and to active the LED Control.
When bit D0 is set to logic [1], the open load detection
circuit for LED is activated for output 1. When bit D0 is set to
logic [0], open load detection circuit for standard bulbs is
activated for output 1.
When bit D5 is set to logic [1], the LED Control is activated
for output 1.
D7
D6
D5
D4
D3
D2
D1
D0
STOPen
PWM
sync
0
MUX2
MUX1
MUX0
SOA1
SOA0
D4, D3, D2 (MUX2, MUX1, MUX0) = 000, No current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 001, OUT1 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 010,current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 011, OUT3 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 100, OUT4 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 101, OUT5 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 110, External Switch current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 111, Temperature analog
feedback
ADDRESS 00010 — CONFIGURATION PRESCALER
AND SR
Two configuration registers are available at this address.
The Configuration Prescaler when D9 bit is set to logic [0] and
Configuration SR when D9 bit is set to logic [1].
The Configuration Prescaler register is used to enable the
PWM clock prescaler per output. When the corresponding
PR bit is set to logic [1], the clock prescaler (reference clock
divided by 2) is activated for the dedicated output.
The SR Prescaler register is used to increase the output
slew-rate by a factor of 2. When the corresponding SR bit is
set to logic [1], the output switching time is divided by 2 for the
dedicated output.
35XS3500
28
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
ADDRESS 00011 — CONFIGURATION CSNS
The Configuration Current Sense register is used
todisable the high over-current shutdown phase (OCHI1 and
OCHI2 dynamic levels) in order to activate immediately the
current sense analog feedback.
When bit D9 is set to logic [1], the current sense
synchronization signal is reported on FETOUT output pin.
When the corresponding NO_OCHI bit is set to logic [1],
the output is only protected with OCLO level. And the current
sense is immediately available if it is selected through SPI, as
described in Figures 13. The NO_OCHI bit per output is
automatically reset at each corresponding ON off bit
transition from logic [1] to [0] and in case of over-temperature
or over-current fault. All NO_OCHI bits are also reset in case
of under-voltage fault detection.
ADDRESS 01001 — Control OUT1
Bits D9 and D8 control the switching phases as shown in
Table 11.
Table 11. Switching Phases
D9 : D8
PWM Phase
00
0°
01
90°
10
180°
11
270°
Bit D7 at logic [1] turns ON OUT1. OUT1 is turned OFF
with bit D7 at logic [0]. This register allows the master to
control the duty cycle and the switching phases of OUT1. The
duty cycle resolution is given by bits D6 : D0.
D7 = 0, D6 : D0 = XX output OFF.
D7 = 1, D6 : D0 = 00 output ON during 1/128.
D7 = 1, D6 : D0 = 1 A output ON during 27/128 on PWM
period.
D7 = 1, D6 : D0 = 7 F output continuous ON (no PWM).
ADDRESS 01010 — Control OUT2
Same description as OUT1.
ADDRESS 011111 — Control OUT3
Same description as OUT1.
ADDRESS 01100 — Control OUT4
Same description as OUT1.
ADDRESS 01101 — Control OUT5
Same description as OUT1.
ADDRESS 01110 — Control External Switch
Same description as OUT1.
ADDRESS 01111 — Test Mode
This register is reserved for test and is not available with
the SPI during normal operation.
Serial Output Communication (Device Status
Return Data)
When the CS pin is pulled low, the output register is
loaded. Meanwhile, the data clocks out the MSB first as the
new message data is clocked into the SI pin. The first 16 bits
of data clocking out of the SO, and following a CS transition,
is dependant upon the previously written SPI word (SOA1
and SOA0 defined in the last SPI initialization word).
Any bits clocked out of the SO pin after the first 16 will be
representative of the initial message bits clocked into the SI
pin, since the CS pin first transitioned to a logic [0]. This
feature is useful for daisy chaining devices.
A valid message length is determined following a CS
transition of logic [0] to logic [1]. If the message length is
valid, the data is latched into the appropriate registers. A valid
message length is a multiple of 16 bits. At this time, the SO
pin is tri-stated and the fault status register is now able to
accept new fault status information.
The output status register correctly reflects the status of
the Initialization-selected register data at the time that the CS
is pulled to a logic [0] during SPI communication and / or for
the period of time since the last valid SPI communication,
with the following exceptions:
• The previous SPI communication was determined to be
invalid. In this case, the status will be reported as
though the invalid SPI communication never occurred.
• Battery transients below 6.0 V, resulting in an undervoltage shutdown of the outputs, may result in incorrect
data loaded into the SPI register, except the UVF fault
reporting (OD13).
Serial Output Bit Assignment
The contents of bits OD15 : OD0 depend on bits D1: D0
from the most recent initialization command SOA[1:0] (refer
to Table 12), as explained in the paragraphs that follow.
The register bits are reset by a read operation and also if
the fault is removed.
Table 12 summarizes the SO register content. Bit OD10
reflects Normal mode (NM).
35XS3500
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 12. Serial Output Bit Map Description
Previous
SI Data
Status /
Mode
SO Data
SO SO OD1 OD1
OD1
OD1
OD13
OD11
A1 A0
5
4
2
0
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
Output
Status
0
0
0
0
UVF OTW OTS
NM
OL5
OVL5
OL4
OVL4
OL3
OVL3
OL2
OVL2
OL1
OVL1
Overloa
d Status
0
1
0
1
UVF OTW OTS
NM
OC5
OTS5
OC4
OTS4
OC3 OTS3
OC2
OTS2
OC1
OTS1
Device
Status
1
0
1
0
UVF OTW OTS
NM
0
OV
STOP
pin
FLASHER
pin
IGN
pin
CLOC
K fail
Output
Status
1
1
1
1
Reset
X
X
0
0
UVF OTW OTS
0
0
0
STOP IGN_ FLAS
_ON
ON HER_
ON
RC
NM
0
0
X
X
X
OUT5
OUT4
OUT3
OUT2
OUT1
1
0
0
0
0
0
0
0
0
0
0
Previous Address SOA[1:0] = 00
If the previous two LSBs are 00, bits OD15 : OD0 reflect the
output status (Table 13).
Table 13. Output Status
OD15
OD14
OD13
OD12
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
0
0
UVF
OTW
OTS
NM
OL5
OVL5
OL4
OVL4
OL3
OVL3
OL2
OVL2
OL1
OVL1
OD13 (UVF) = Under-voltage Flag on VBAT
OD9, OD7, OD5, OD3, OD1 (OL5, OL4, OL3, OL2, OL1) = Open Load
Flag at Outputs 5 through 1, respectively.
OD8, OD6, OD4, OD2, OD0 (OVL5, OVL4, OVL3, OVL2,
OVL1) = Overload Flag for Outputs 5 through 1, respectively.This
corresponds to over-temperature or OCHI or OCLO faults.
OD12 (OTW) = Over-temperature Prewarning Flag
OD11 (OTS) = Over-temperature Flag for all outputs
OD10 (NM) = Normal mode
Note
A logic [1] at bits OD9:OD0 indicates a fault. If there is no fault, bits OD9:OD0 are logic [0].
OVL=OCHI1+OCHI2+OCLO
Previous Address SOA[1:0] = 01
If the previous two LSBs are 01, bits OD15 :O D0 reflect
reflect the temperature status (Table 14).
Table 14. Overload Status
OD15
OD14
OD13
OD12
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
0
1
UVF
OTW
OTS
NM
OC5
OTS5
OC4
OTS4
OC3
OTS3
OC2
OTS2
OC1
OTS1
OD13 (UVF) = Under-voltage Flag on VBAT
OD12 (OTW) = Over-temperature Prewarning Flag
OD11 (OTS) = Over-temperature Flag for all outputs
OD10 (NM) = Normal mode
OD9, OD7, OD5, OD3, OD1 (OC5, OC4, OC3, OC2, OC1) = High
Over-current Shutdown Flag for Outputs 5 through 1, respectively
OD8, OD6, OD4, OD2, OD0 (OTS5, OTS4, OTS3, OTS2,
OTS1) = Over-temperature Flag for Outputs 5 through 1, respectively
Note
A logic [1] at bits OD9:OD0 indicates a fault. If there is no fault, bits OD9:OD0 are logic [0].
OC=OCHI1+OCHI2
Previous Address SOA[1:0] = 10
If the previous two LSBs are 01, bits OD15 : OD0 reflect the
status of the 35XS3500 (Table 15).
35XS3500
30
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 15. Device Status
OD15
OD14
OD13
OD12
OD11
OD10
OD9
OD8
1
0
UVF
OTW
OTS
NM
0
OV
OD13 (UVF) = Under-voltage Flag on VBAT
OD12 (OTW) = Over-temperature Prewarning Flag
OD11 (OTS) = Over-temperature Flag for all outputs
OD10 (NM) = Normal mode
OD8 (Over-voltage) = Over-voltage Flag on VBAT in real time
OD7 = Indicates the state of internal STOP_ON signal, as described
in Figures 11
OD7
OD6
OD5
STOP_ IGN_ON FLASH
ON
ER_ON
OD4
OD3
RC
STOP
pin
OD2
OD1
OD0
FLASH IGN pin CLOCK
ER pin
fail
OD6 = Indicates the state of internal IGN_ON signal
OD5 = Indicates the state of internal FLASHER_ON signal
OD4 (RC) = Logic [0] indicates a Front Corner Light Switch. Logic [1]
indicates a Rear Corner Light Switch
OD3 (STOP pin) = Indicates the STOP pin state in real time
OD2 (FLASHER pin) = Indicates the FLASHER pin state in real time
OD1 (IGN pin) = Indicates the IGN pin state in real time
OD0 (CLOCK fail) = Logic [1], which indicates a clock failure
Previous Address SOA[1:0] = 11
If the previous two LSBs are 11, bits OD15 : OD0 reflect the
status of the 35XS3500 (Table 15).
Table 16. Output Status
OD15
OD14
OD13
OD12
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
1
1
UVF
OTW
OTS
NM
0
0
X
X
X
OUT5
OUT4
OUT3
OUT2
OUT1
OD13 (UVF) = Under-voltage Flag on VBAT
OD12 (OTW) = Over-temperature Prewarning Flag
OD11 (OTS) = Over-temperature Flag for all outputs
OD10 (NM) = Normal mode
OD4 (OUT5) = Logic [0] indicates the OUT5 voltage is lower than
VOUT_TH. Logic [1] indicates the OUT5 voltage is higher than
VOUT_TH
Protection and Diagnosis
Output Protection Features
The 35XS3500 provides the following protection features:
• Protection against transients on VBAT supply line (per
ISO 7637)
• Active clamp, including protection against negative
transients on output line
• Over-temperature
• Severe and resistive over-current
• Open Load during ON state
These protections are provided for each output (OUT1:5).
OD3 (OUT4) = Logic [0] indicates the OUT4 voltage is lower than
VOUT_TH. Logic [1] indicates the OUT4 voltage is higher than VOUT_TH
OD2 (OUT3) = Logic [0] indicates the OUT3 voltage is lower than
VOUT_TH. Logic [1] indicates the OUT3 voltage is higher than VOUT_TH
OD1 (OUT2) = Logic [0] indicates the OUT2 voltage is lower than
VOUT_TH. Logic [1] indicates the OUT2 voltage is higher than VOUT_TH
OD0 (OUT1) = Logic [0] indicates the OUT5 voltage is lower than
VOUT_TH. Logic [1] indicates the OUT1 voltage is higher than VOUT_TH
latched and reported via the SPI. To delatch the fault and be
able to turn the outputs ON again, the failure condition must
be removed (T< 175 °C typically) and:
• if the device was in Normal mode, the output
corresponding register (bit D7) must be rewritten. 
Application of the complete OCHI window
(OCHI1+OCHI2 during t2) depends on toggling or not
toggling D7 bit.
• if the device was in Fail mode, the corresponding output
is locked until device restart: wake up from Sleep mode
or VBATPOR1.
The SPI fault report (OTS bit) is removed after a read
operation.
Over-temperature detection
Over-current detections
The 35XS3500 provides over-temperature shutdown for
each output (OUT1:OUT5 ). It can occur when the output pin
is in the ON or OFF state. An over-temperature fault condition
results in turning OFF the corresponding output. The fault is
The 35XS3500 provides intelligent over-current shutdown
(see Figure 12) in order to protect the internal power
transistors and the harness in the event of overload (fuse
characteristic).
35XS3500
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
• if the device was in Normal mode: the output
corresponding register (bit D7) must be rewritten D7=1.
Application of complete OCHI window depends on
toggling or not toggling D7 bit.
• if the device was in Fail mode, the failure is locked until
restart of the device: wake-up from Sleep mode or
VBATPOR1.
Output current
OCHI1
OCHI2
OCLO
t1
t2
time
Figure 12. Double Over-current Window in Normal Mode
OCHI (IOCHI1 and then IOCHI2) is only activated after
toggling the D7 bit in Normal mode. During the output
switching, the severe short-circuit condition provided on the
module connector is reported as an OCHI fault. In Fail mode,
the control of OCHI window is provided by the toggles:
IGN_ON, Flasher_ON. The current thresholds (IOCHI1, IOCHI2
and IOCLO) and the time (t1 and t2) are fixed numbers for each
driver. After t2, the OCLO current threshold is set to protect in
steady state. t1 and t2 times are compared to “on” state
duration (tON) of the output. In case of the output is controlled
in PWM mode during the inrush period, the tON corresponds
to the sum of each “on” state duration in order to expand
dynamically the transient over-current profile.
In case of an overload (OCHI1 or OCHI2 or OCLO
detection), the corresponding output is disabled immediately.
The fault is latched and the status is reported via the SPI. To
delatch the fault, the failure condition must be removed and:
For OCHI1:
For OCHI2 and OCLO:
• if the device was in Normal mode: the output
corresponding register (bit D7) must be rewritten D7=1.
Application of complete OCHI window depends on
toggling or not toggling D7 bit.
• if the device was in Fail mode, autorestart is activated.
The device autorestart feature provides a fixed duty
cycle and fixed period with OCHI1 window.
autorestart feature resets OCHI2 or OCLO fault after
corresponding Autorestart period.
The SPI fault reports are removed after a read operation:
- OC bit=(OCHI1) or (OCHI2) fault
- OVL bit=(OCHI1) or (OCHI2) or (OCLO) fault
Over-voltage detection and active clamp
The 35XS3500 provides an active gate clamp circuit, in
order to limit the maximum drain to source voltage.
In case of overload on an output, the corresponding switch
(OUT[1 to 5]) is turned off which leads to a high voltage at
VBAT, with an inductive VBAT line. The maximum VBAT
voltage is limited at VBATCLAMP by active clamp circuitry
through the load. In case of open load condition, the positive
transient pulses (ISO 7637 pulse 2 and inductive battery line)
shall be handled by the application.
Figures 13 and 14 describe the faults management in
Normal mode and Fail mode.
35XS3500
32
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
(OCHI2=1) or (OT=1) or (UV=1) or (D7=0)
Note: t1 and t2 please refer to Figure 12.
t1<tON<t2 and (NO_OCHI=0)
without fault
(OCHI1=1) or (OT=1) or (UV=1) or (D7=0)
D7=0 then 1 without fault
and (NO_OCHI=0)
tON=t1 without fault
OFF
OCHI2
(rewrite D7=1) and
(tON<t1) without fault and
(NO_OCHI=0)
OCHI1
tON=t2 without fault
(NO_OCHI=1) without fault
(NO_OCHI=1) without fault
OCLO
tON<t1 and (NO_OCHI=0) without fault
tON>t1 without fault and (rewrite D7=1) and (NO_OCHI=0)
(tON>t2) and (rewrite D7=1) without fault
D7=0 then 1 without fault and (NO_OCHI=1)
(OCLO=1) or (OT=1) or (UV=1) or (D7=0)
Figure 13. Faults Management in Normal Mode (for OUT[1:5] only)
35XS3500
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
(OT=1) or
(OCHI1=1)
(external_ON=0)
OFF-latched
State
(OT=1)
(external_ON=0)
(OT=1)
(external_ON=1)
OFF
out: OFF
autorestart=0
(t>tOCHI1) and (autorestart=0)
(t>tOCHI2) and (autorestart=0)
OCHI2
out: external
OCHI1
out: external
OCLO
out: external
(t>tOCHI1_AUTO) and (autorestart=1)
(UV=1)
and
(external_on=1)
(t>tautorestart) and (UV*=0)
(UV=1) or (OCHI2=1)
(UV=1)
(OCLO=1)
(UV=1)
(external_ON=0)
or
OFF Autorestart
out: OFF
autorestart=1
(external_ON=0)
1.4 sec min
external
external_ON
external: IGN, Flasher, Stop
external_ON: IGN_ON, Flasher_ON, Stop_ON
Note: * See Autorestart strategy chapter.
Figure 14. Faults Management in Fail Mode (for OUT[1:5] only)
DIAGNOSIS
Open Load
The 35XS3500 provides open load detection for each
output (OUT1:OUT5 ) when the output pin is in the ON state.
Open load detection levels can be chosen by the SPI to
detect a standard bulb or LEDs (OLLED bit). Open load for
LEDs only is detected during each regular switch-off state or
periodically each t OLLED (fully-on, D[6:0] = 7F). To detect
OLLED in fully on state, the output must be on at least t OLLED.
When an open load has been detected, the output stays ON.
To delatch the diagnosis, the condition should be removed
and a SPI read operation is needed (OL bit). In case of a
Power on Reset on VBAT, the fault will be reset.
Current Sense
The 35XS3500 diagnosis for load current (OUT1:6) is
done using the current sense (CSNS) pin connected to an
external resistor. The CSNS resistance value is defined in
function to VCC voltage value. It is recommended to use
resistor 500  < RCSNS < 5.0 k. Typical value is 1.0 k for
5.0 V application. The routing of the current sense sources is
SPI programmable (MUX[2,0] bits).
The current recopy feature for OUT1:5 is disabled during
a high over-current shutdown phase (t2) and is only enabled
during low over-current shutdown thresholds. The current
recopy output delivers current only during ON time of the
output switch without overshoot (aperiodic settling).
The current recopy is not active in Fail mode.
35XS3500
34
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
With a calibration strategy, the output current sensing
precision can be improved significantly. One calibration point
at 25 °C for 50% of FSR allows removing part to part
contribution. So, the calibrated part precision goes down to 
+/-6.0% over [20% - 75%] output current FSR, over voltage
range (10 to 16 V) and temperature range (-40 to 125 °C).
The board temperature feedback is not active in Fail
mode.
With a calibration strategy, the temperature monitoring
precision can be improved. So, one calibration point at 25 °C
allows removing part to part contribution, as presented in
Figure 17.
With dedicated calibration points, the current recopy
allows diagnosing lamp damage in paralleling operations, like
as flasher topology. The Figure 15 summaries test results
covering 99.74% of parts (device ageing not included) for
Standard lamps and LEDs.
typ
2.5
min
max
CSNS feedback (V)
2
1.5
1
0.5
0
-40
-20
0
20
40
60
80
100
Board tem perature (°C)
120
140
160
180
Figure 17. Analog Temperature Precision with
Calibration Strategy
Output Status
Orange = LED mode
Blue = lamp mode (default mode)
Figure 15. Current Sense Precision with Calibration
Strategy
Board Temperature Feedback
The 35XS3500 provides a voltage proportional to the
temperature on the GND flag. This analog feedback is
available in CSNS output pin for MUX[2,0] bits set to “111”,
as described in Figure 16.
max
CSNS feedback (V)
The 35XS3500 provides a temperature prewarning
reported via the SPI (OTW bit) in Normal mode. The
information is latched. To delatch, a read SPI command is
needed. In case of a Power on Reset, the fault will be reset.
External Pin Status
min
Failure Handling Strategy
2
A highly sophisticated failure handling strategy enables
light functionality even in case of failures inside the
component or the light module. Components are protected
against:
• Reverse Polarity
• Loss of Supply Lines
• Fatal Mistreatment of Logic I/O Pins
1.5
1
0.5
0
-40
Temperature Prewarning
The 35XS3500 provides the status of the FLASHER, IGN,
STOP, and CLOCK pins via the SPI in real time and in
Normal mode.
typ
2.5
The 35XS3500 provides the state of OUT1:OUT5 outputs
in real time through SPI. The OUT bit is set to logic [1] when
the corresponding output voltage is closed to half of battery.
This bit allows synchronizing current sense and diagnosing
short-circuit between OUT and VBAT pins.
-20
0
20
40
60
80
100
Board tem perature (°C)
120
140
160
180
Figure 16. Analog Temperature Precision
35XS3500
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Reverse Polarity Protection on VBAT
In case of a permanently reverse polarity operation, the
output transistors are turned ON (RSD) to prevent thermal
overloads and no protections are available.
provided for RST is set to logic [1]. The SPI pull-up and
pull-down current resistors are available. This fault
condition can be diagnosed with UVF fault in OD13
reporting bit. The previous device configuration is
maintained. No current is conducted from VCC to VBAT.
An external diode on VCC is necessary in order to not to
destroy the 35XS3500 in cases of reverse polarity.
Loss of VCC (Digital Logic Supply Line)
In case of negative transients on the VBAT line (per
ISO 7637), the VCC line is still operating, while the VBAT line
is negative. Without loads on OUT1:5 terminal, an external
clamp between VBAT and GND is mandatory to avoid
exceeding maximum rating. The maximum external clamp
voltage shall be between the reverse battery condition and 
-20 V.
During loss a of VCC (VCC < VCCUV ) and with wake=1, the
35XS3500 is switched automatically into Fail mode (no
deglich time). The external SMART MOSFET is OFF. All SPI
registers are reset and must be reprogrammed when VCC
goes above VCCUV. The device will transit in OFF mode if
VBAT < VBATPOR2.
Therefore, the device is protected against latch-up with or
without load on OUT outputs.
LOSS OF VCC AND VBAT
Loss of Supply Lines
The 35XS3500 is protected against the loss of any supply
line. The detection of the supply line failure is provided inside
the device itself.
If the external VBAT and VCC supplies are disconnected (or
not within specification: (VCC and VBAT) < VBATPOR1), all SPI
register contents are reset with default values corresponding
to all SPI bits are set to logic [0] and all latched faults are also
reset.
Loss of Ground (GND)
Loss of VBAT
During an under-voltage of VBAT
(VBATPOR1 <VBAT<VBATUV) and with an active device
(wake=1), the outputs [1-5] are switched off immediately. No
current path exists from VBAT to VCC. The external MOSFET
(OUT6) can be controlled by the SPI if VCC remains and is
above to VCCUV. The fault is reported to the UVF bit (OD13).
To delatch the fault, the under-voltage condition should be
removed and:
• the bit D7 must be rewritten to a logic [1] in Normal
mode. Application of the OCHI window depends on
toggling or not toggling the D7 bit. When the fault is
delatched, the 35XS3500 returns to the configuration it
was just before the failure.
• if the device was in Fail mode, the fault will be delatched
periodically by the Autorestart feature.
In case of VBAT<VBATPOR1 (Power OFF state), the
behavior depends on VCC:
• all latched faults are reset if VCC < VCCUV,
• all latched faults are maintained under VCC in nominal
conditions. In case VBAT is disconnected, OUT[1:5]
outputs are OFF. OUT6 output state depends on the
previous SPI configuration. The SPI configuration,
reporting (if VBAT was previously in the nominal voltage
range for at least 35 sec), and daisy-chain features are
During a loss of ground, the 35XS3500 cannot operate the
loads (the outputs (1:5) are switched OFF), but is not
destroyed by the operating condition. Current limit resistors in
the digital input lines protect the digital supply against
excessive current (1.0 kohm typical). The state of the
external smart power switch controlled by FETOUT is not
guaranteed, and the state of the external smart MOS is
defined with an external termination resistor.
Fatal Mistreatment of Logic I / O Pins
The digital I / Os are protected against fatal mistreatment
by a signal plausibility check according to Table 17.
Table 17. Logic I / O Plausibility Check
Input / Output
Signal Check Strategy
LIMP
Debounce for 10 ms
(PWM) CLOCK
Frequency range
(bandpass filter)
SPI (MOSI, SCLK, CS)
WD, D10 bit internal toggle
In case the LIMP input is set to a logic [1] for a delay longer
than 10 ms typical, the 35XS3500 is switched into Fail mode.
In case of a (PWM) Clock failure, no PWM feature is
provided, and the bit D7 defines the outputs state. In case of
a SPI failure, the 35XS3500 is switched into Fail mode
(Figure 18)
35XS3500
36
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
.
WD Bit D10
1
0
0
timeout
75ms window watchdog
D10 is toggled after
the window watch-
75ms window watchdog
Fail Mode activation
Figure 18. Watchdog Window
35XS3500
Analog Integrated Circuit Device Data
Freescale Semiconductor
37
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
Figure 19 shows full vehicle light functionality, including fog lights, battery redundancy concept, light substitution mode, and
Limp Home mode.
Sp
ar
e
Li
H
g
ig ht
h
Lo Be
w am
Fl Be
as am
Pa her
rk
in
g
Li
gh
t
Fo
g
g
in
rk
e
ar
t
Sp
gh
Li
g
Fo e a m
B
h
ig am
H Be
er
w
Lo lash
F ht
g
Li
Pa
MOSI, MISO, SCLK
CP
100nF
10XS3535
VBAT
Smart Corner
Light Switch
(Front Left)
VCC
CP
CS
CLOCK
CS
CLOCK
RST
RST
IGN
IGN
VBAT
VCC
FOG
CSNS
ea
rF
og
r
Li
Li Dr
gh
ce i v
t
ns e L
St e
i
g
op L
ig ht
L
Fl ig ht
as ht
Ta her
il
Li
gh
t
t
gh
t
Li
gh
og
Li
t
e
rF
riv igh
ea
R
rD eL t
h
ea s
R cen Lig
Li op er
St sh
a
Fl h t
g
Li
il
Ta
ea
R
100nF
Smart Corner
Light Switch
(Front Right)
LIMP
FLASHER
LIMP
FLASHER
FOG
CSNS
R
10XS3535
100nF
100nF
CP
35XS3500
VBAT
Smart Corner
Light Switch
(Rear Left)
VCC
VBAT
CS
CS
CLOCK
CLOCK
RST
IGN
RST
IGN
LIMP
FLASHER
LIMP
FLASHER
STOP
STOP
CSNS
CSNS
Microcontroller
Watchdog
VCC
(5.0V)
WD
(5.0V)
Ignition
CP
35XS3500
VBAT
Smart Corner
Light Switch
(Rear Right)
VCC
Stop Light
Flasher
VBAT
Figure 19. Typical Application
35XS3500
38
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
EMC & EMI PERFORMANCES
The 35XS3500 will be compliant to CISPR25 Class5 in
Standby mode with 22 nF decoupling capacitor on OUT[1:5].
35XS3500
Analog Integrated Circuit Device Data
Freescale Semiconductor
39
PACKAGING
PACKAGING DIMENSIONS
PACKAGING
PACKAGING DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the 98ART10511D
listed below. Dimension shown are provided for reference ONLY.
FK SUFFIX
24-PIN PQFN
98ART10511D
ISSUE 0
35XS3500
40
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS
FK SUFFIX
24-PIN PQFN
98ART10511D
ISSUE 0
35XS3500
Analog Integrated Circuit Device Data
Freescale Semiconductor
41
PACKAGING
PACKAGING DIMENSIONS
FK SUFFIX
24-PIN PQFN
98ART10511D
ISSUE 0
35XS3500
42
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS
FK SUFFIX
24-PIN PQFN
98ART10511D
ISSUE 0
35XS3500
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
REVISION HISTORY
REVISION HISTORY
Revision
Date
Description of Changes
5/2010
•
Initial Release
2.0
7/20101
•
•
Changed PN to MC35XS3500PNA
Changed classification to Advance Information
3.0
9/2010
•
•
•
Added Minimum Output Current Reported in CSNS for OUT[1-5](13) to Table 3.
Added Minimum Output Current Reported in CSNS for OUT[1-5] in LED Mode(13) to Table 3.
Added Note: Output current value computed after leakage current removal (open load condition) to
Table 3.
4.0
5/2011
•
Added Under-voltage Deglitch Time parameter.
5.0
4/2012
•
•
Added Orderable Part Number PC35XS3500HFK
Corrected errors in Table 12 and Table 15
6.0
6/2012
•
•
•
•
Removed MC35XS3500PNA
Updated PC35XS3500HFK to MC35XS3500HFK
Added (4)
Updated Under-voltage Deglitch Time t UV parameter in Table 5, Dynamic Electrical Characteristics
on page 15
Updated Freescale form and style
1.0
•
7.0
12/2012
•
•
8.0
8/2013
•
•
•
Added “if VBAT was previously in the nominal voltage range for at least 35 sec” to Loss of VBAT
Section.
Added MC35XS3500DHFK to the ordering information.
Changed CSNS condition for CSNS Tri-state Leakage Current
Changed Driver Output Matching Time (t DLY(ON) - t DLY(OFF)) at Output = 50% VBAT with
VBAT = 14 V, f PWM = 240 Hz, PWM = 50%, at 25 °C
Corrected conditions for FETIN Leakage Current when external current switch sense is enabled
35XS3500
44
Analog Integrated Circuit Device Data
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Document Number: MC35XS3500
Rev. 8.0
8/2013