Low Power, 12.65 mW, 2.3 V to 5.5 V, Programmable Waveform Generator AD9833-EP Enhanced Product FEATURES GENERAL DESCRIPTION Digitally programmable frequency and phase 12.65 mW power consumption at 3 V 0 MHz to 12.5 MHz output frequency range 28-bit resolution: 0.1 Hz at 25 MHz reference clock Sinusoidal, triangular, and square wave outputs 2.3 V to 5.5 V power supply No external components required 3-wire SPI interface Power-down option 10-lead MSOP package Enhanced product features Supports defense and aerospace applications (AQEC) Temperature range: −55°C to +125°C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Enhanced product change notification Qualification data available upon request The AD9833-EP is a low power, programmable waveform generator capable of producing sine, triangular, and square wave outputs. Waveform generation is required in various types of sensing, actuation, and time domain reflectometry (TDR) applications. The output frequency and phase are software programmable, allowing easy tuning. No external components are needed. The frequency registers are 28 bits wide. With a 25 MHz clock rate, a resolution of 0.1 Hz can be achieved; with a 1 MHz clock rate, the AD9833-EP can be tuned to 0.004 Hz resolution. The AD9833-EP is written to via a 3-wire serial interface. This serial interface operates at clock rates up to 40 MHz and is compatible with DSP and microcontroller standards. The device operates with a power supply from 2.3 V to 5.5 V. The AD9833-EP has a power-down function (SLEEP). This function allows sections of the device that are not being used to be powered down, thus minimizing the current consumption of the part. For example, the DAC can be powered down when a clock output is being generated. APPLICATIONS The AD9833-EP is available in a 10-lead MSOP package. Additional application and technical information can be found in the AD9833 data sheet. Frequency stimulus/waveform generation Liquid and gas flow measurement Sensory applications: proximity, motion, defect detection Line loss/attenuation Test and medical equipment Sweep/clock generators Time domain reflectometry (TDR) applications FUNCTIONAL BLOCK DIAGRAM AGND DGND VDD CAP/2.5V ON-BOARD REFERENCE REGULATOR MCLK AVDD/ DVDD FULL-SCALE CONTROL 2.5V FREQ0 REG PHASE ACCUMULATOR (28-BIT) MUX FREQ1 REG 12 SIN ROM COMP 10-BIT DAC MUX MSB PHASE0 REG PHASE1 REG MUX DIVIDE BY 2 R 200Ω SERIAL INTERFACE AND CONTROL LOGIC SCLK AD9833-EP 11545-001 FSYNC VOUT MUX CONTROL REGISTER SDATA Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9833-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................5 Applications ....................................................................................... 1 ESD Caution...................................................................................5 General Description ......................................................................... 1 Pin Configuration and Function Descriptions..............................6 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................7 Revision History ............................................................................... 2 Outline Dimensions ....................................................................... 10 Specifications..................................................................................... 3 Ordering Guide .......................................................................... 10 Timing Characteristics ................................................................ 4 REVISION HISTORY 8/13—Revision 0: Initial Version Rev. 0 | Page 2 of 12 Enhanced Product AD9833-EP SPECIFICATIONS VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, RSET = 6.8 kΩ for VOUT, unless otherwise noted. Table 1. Parameter1 SIGNAL DAC SPECIFICATIONS Resolution Update Rate VOUT Maximum VOUT Minimum VOUT Temperature Coefficient DC Accuracy Integral Nonlinearity Differential Nonlinearity DDS SPECIFICATIONS (SFDR) Dynamic Specifications Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Wideband (0 to Nyquist) Narrow-Band (±200 kHz) Clock Feedthrough Wake-Up Time LOGIC INPUTS Input High Voltage, VINH Min Typ Max 10 53.5 0.65 38 200 ±1.0 ±0.5 LSB LSB 60 −66 dB dBc fMCLK = 25 MHz, fOUT = fMCLK/4096 fMCLK = 25 MHz, fOUT = fMCLK/4096 −60 −78 −60 1 dBc dBc dBc ms fMCLK = 25 MHz, fOUT = fMCLK/50 fMCLK = 25 MHz, fOUT = fMCLK/50 2.3 V to 2.7 V power supply 2.7 V to 3.6 V power supply 4.5 V to 5.5 V power supply 2.3 V to 2.7 V power supply 2.7 V to 3.6 V power supply 4.5 V to 5.5 V power supply 3 V V V V V V μA pF −53.5 1.7 2.0 2.8 0.5 0.7 0.8 10 Input Current, IINH/IINL Input Capacitance, CIN POWER SUPPLIES VDD IDD Low Power Sleep Mode Test Conditions/Comments Bits MSPS V mV ppm/°C 25 Input Low Voltage, VINL fMCLK = 25 MHz, fOUT = fMCLK/4096 2.3 5.5 5.5 4.5 0.5 V mA mA IDD code dependent; see Figure 7 DAC powered down, MCLK running Operating temperature range is −55°C to +125°C; typical specifications are at 25°C. VDD 100nF 10nF CAP/2.5V REGULATOR COMP 12 SIN ROM VOUT 10-BIT DAC 20pF AD9833-EP Figure 2. Test Circuit Used to Test Specifications Rev. 0 | Page 3 of 12 11545-002 1 Unit AD9833-EP Enhanced Product TIMING CHARACTERISTICS VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.1 Table 2. Parameter t1 t2 t3 t4 t5 t6 t7 t8 min t8 max t9 t10 t11 1 Limit at TMIN to TMAX 40 16 16 25 10 10 5 10 t4 − 5 5 3 5 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min ns min ns min Description MCLK period MCLK high duration MCLK low duration SCLK period SCLK high duration SCLK low duration FSYNC to SCLK falling edge setup time FSYNC to SCLK hold time Data setup time Data hold time SCLK high to FSYNC falling edge setup time Guaranteed by design, not production tested. Timing Diagrams t1 11545-003 MCLK t2 t3 Figure 3. Master Clock t5 t11 t4 SCLK t7 t6 t8 FSYNC t10 SDATA D15 D14 D2 D1 Figure 4. Serial Timing Rev. 0 | Page 4 of 12 D0 D15 D14 11545-004 t9 Enhanced Product AD9833-EP ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to AGND VDD to DGND AGND to DGND CAP/2.5V Digital I/O Voltage to DGND Analog I/O Voltage to AGND Operating Temperature Range Storage Temperature Range Maximum Junction Temperature MSOP Package θJA Thermal Impedance θJC Thermal Impedance Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature Rating −0.3 V to +6 V −0.3 V to +6 V −0.3 V to +0.3 V 2.75 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −55°C to +125°C −65°C to +150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 206°C/W 44°C/W 300°C 220°C Rev. 0 | Page 5 of 12 AD9833-EP Enhanced Product PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD 2 CAP/2.5V 3 DGND 4 MCLK 5 AD9833-EP 9 AGND TOP VIEW (Not to Scale) 8 FSYNC 7 SCLK 6 SDATA 11545-005 10 VOUT COMP 1 Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 Mnemonic COMP VDD 3 CAP/2.5V 4 5 DGND MCLK 6 7 8 SDATA SCLK FSYNC 9 10 AGND VOUT Description DAC Bias Pin. This pin is used for decoupling the DAC bias voltage. Positive Power Supply for the Analog and Digital Interface Sections. The on-board 2.5 V regulator is also supplied from VDD. VDD can have a value from 2.3 V to 5.5 V. A 0.1 µF and a 10 µF decoupling capacitor should be connected between VDD and AGND. The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated from VDD using an on-board regulator when VDD exceeds 2.7 V. The regulator requires a decoupling capacitor of 100 nF typical, which is connected from CAP/2.5V to DGND. If VDD is less than or equal to 2.7 V, CAP/2.5V should be tied directly to VDD. Digital Ground. Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The output frequency accuracy and phase noise are determined by this clock. Serial Data Input. The 16-bit serial data-word is applied to this input. Serial Clock Input. Data is clocked into the AD9833-EP on each falling edge of SCLK. Active Low Control Input. FSYNC is the frame synchronization signal for the input data. When FSYNC is taken low, the internal logic is informed that a new word is being loaded into the device. Analog Ground. Voltage Output. The analog and digital output from the AD9833-EP is available at this pin. An external load resistor is not required because the device has a 200 Ω resistor on board. Rev. 0 | Page 6 of 12 Enhanced Product AD9833-EP TYPICAL PERFORMANCE CHARACTERISTICS 5.5 –40 VDD = 3V TA = 25°C TA = 25°C –45 5.0 VDD = 5V –50 SFDR (dBc) VDD = 3V 4.0 MCLK/7 –55 –60 3.5 MCLK/50 –65 0 5 10 15 MCLK FREQUENCY (MHz) 20 25 –70 11545-006 3.0 5 7 Figure 6. Typical Current Consumption (IDD) vs. MCLK Frequency for fOUT = MCLK/10 6 9 11 13 15 17 19 MCLK FREQUENCY (MHz) 21 23 25 11545-009 IDD (mA) 4.5 Figure 9. Wideband SFDR vs. MCLK Frequency 0 VDD = 5V VDD = 3V –10 VDD = 3V TA = 25°C 5 –20 –30 SFDR (dB) IDD (mA) 4 3 2 fMCLK = 10MHz –40 fMCLK = 18MHz fMCLK = 1MHz –50 –60 –70 1 10k 100k 1M 10M fOUT (Hz) –90 0.001 –45 –70 –50 SNR (dB) –65 –75 MCLK/7 MCLK/50 –60 –85 –65 –90 10 15 MCLK FREQUENCY (MHz) 20 10 100 25 Figure 8. Narrow-Band SFDR vs. MCLK Frequency VDD = 3V TA = 25°C fOUT = MCLK/4096 –55 –80 11545-008 SFDR (dBc) –40 5 1 Figure 10. Wideband SFDR vs. fOUT/fMCLK for Various MCLK Frequencies VDD = 3V TA = 25°C 0 0.1 fOUT/fMCLK Figure 7. Typical IDD vs. fOUT for fMCLK = 25 MHz –60 0.01 –70 1.0 5.0 10.0 MCLK FREQUENCY (MHz) 12.5 Figure 11. SNR vs. MCLK Frequency Rev. 0 | Page 7 of 12 25.0 11545-011 1k 11545-007 0 100 11545-010 fMCLK = 25MHz –80 AD9833-EP Enhanced Product 1000 0 950 –10 –20 900 VDD = 2.3V –30 POWER (dB) 800 750 VDD = 5.5V 700 –40 –50 –60 650 –70 600 –80 550 –90 25 TEMPERATURE (°C) 105 –100 11545-012 500 –40 0 RWB 1k VWB 300 FREQUENCY (Hz) 5M ST 50 SEC 11545-015 WAKE-UP TIME (µs) 850 Figure 15. Power vs. Frequency, fMCLK = 10 MHz, fOUT = 1.43 MHz = fMCLK/7, Frequency Word = 0x2492492 Figure 12. Wake-Up Time vs. Temperature 0 1.250 –10 1.225 –20 UPPER RANGE –30 POWER (dB) VREF (V) 1.200 1.175 LOWER RANGE 1.150 –40 –50 –60 –70 –80 1.125 –90 105 0 RWB 1k 0 –10 –10 –20 –20 –30 –30 POWER (dB) 0 –40 –50 –60 5M ST 50 SEC –40 –50 –60 –70 –70 –80 –80 –90 –90 VWB 30 FREQUENCY (Hz) 100k ST 100 SEC 0 RWB 100 Figure 14. Power vs. Frequency, fMCLK = 10 MHz, fOUT = 2.4 kHz, Frequency Word = 0x000FBA9 VWB 30 FREQUENCY (Hz) 100k ST 100 SEC Figure 17. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 6 kHz, Frequency Word = 0x000FBA9 Rev. 0 | Page 8 of 12 11545-017 –100 0 RWB 100 11545-014 –100 VWB 300 FREQUENCY (Hz) Figure 16. Power vs. Frequency, fMCLK = 10 MHz, fOUT = 3.33 MHz = fMCLK/3, Frequency Word = 0x5555555 Figure 13. VREF vs. Temperature POWER (dB) –100 11545-016 25 TEMPERATURE (°C) 11545-013 1.100 –40 AD9833-EP 0 0 –10 –10 –20 –20 –30 –30 POWER (dB) –40 –50 –60 –60 –70 –80 –80 –90 –90 0 RWB 1k 11545-018 VWB 100 FREQUENCY (Hz) 1M ST 100 SEC 12.5M ST 100 SEC Figure 21. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 3.857 MHz = fMCLK/7, Frequency Word = 0x2492492 Figure 18. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 60 kHz, Frequency Word = 0x009D495 0 –10 –10 –20 –20 –30 –30 POWER (dB) 0 –40 –50 –60 –40 –50 –60 –70 –70 –80 –80 –90 –90 –100 –100 VWB 300 FREQUENCY (Hz) 12.5M ST 100 SEC 0 RWB 1k 11545-019 0 RWB 1k Figure 19. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 600 kHz, Frequency Word = 0x0624DD3 0 –20 –30 –40 –50 –60 –70 –80 VWB 300 FREQUENCY (Hz) 12.5M ST 100 SEC 11545-020 –90 0 RWB 1k VWB 300 FREQUENCY (Hz) 12.5M ST 100 SEC Figure 22. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 8.333 MHz = fMCLK/3, Frequency Word = 0x5555555 –10 –100 VWB 300 FREQUENCY (Hz) 11545-021 –100 0 RWB 300 POWER (dB) –50 –70 –100 POWER (dB) –40 11545-022 POWER (dB) Enhanced Product Figure 20. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 2.4 MHz, Frequency Word = 0x189374D Rev. 0 | Page 9 of 12 AD9833-EP Enhanced Product OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 5.15 4.90 4.65 6 1 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 6° 0° 0.23 0.13 COMPLIANT TO JEDEC STANDARDS MO-187-BA 0.70 0.55 0.40 091709-A 0.15 0.05 COPLANARITY 0.10 Figure 23. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9833SRMZ-EP-RL7 1 Temperature Range −55°C to +125°C Package Description 10-Lead MSOP Z = RoHS Compliant Part. Rev. 0 | Page 10 of 12 Package Option RM-10 Branding DMR Enhanced Product AD9833-EP NOTES Rev. 0 | Page 11 of 12 AD9833-EP Enhanced Product NOTES ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11545-0-8/13(0) Rev. 0 | Page 12 of 12