AN-1070 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Programming the AD9833/AD9834 by Liam Riordan INTRODUCTION outputs while the AD9833 is being initialized, the RESET bit should be set to 1 until the part is ready to begin generating an output. The RESET bit does not reset the phase, frequency, or control register. These registers will contain invalid data, and, therefore, should be set to a known value by the user. The RESET bit should then be set to 0 to begin generating an output. The data appears on the DAC output eight MCLK cycles after RESET is set to 0. This application note describes how to program a sinusoidal waveform on the output of the AD9833/AD9834 parts. The sequence involves entering reset mode, entering data into the Freq0 register, and exiting reset mode. PROGRAMMING THE AD9833/AD9834 When the AD9833/AD9834 is powered up, the part should be reset. This resets appropriate internal registers to 0 to provide an analog output of midscale. To avoid spurious DAC FUNCTIONAL BLOCK DIAGRAM AVDD AGND DGND DVDD REFOUT CAP/2.5V REGULATOR MCLK VCC 2.5V ON-BOARD REFERENCE FULL-SCALE CONTROL FSELECT 28-BIT FREQ0 REG PHASE ACCUMULATOR (28-BIT) MUX 28-BIT FREQ1 REG Σ 12 FS ADJUST SIN ROM 10-BIT DAC MUX COMP IOUT IOUTB MSB 12-BIT PHASE0 REG 12-BIT PHASE1 REG MUX MUX DIVIDED BY 2 16-BIT CONTROL REGISTER MUX SIGN BIT OUT SERIAL INTERFACE AND CONTROL LOGIC COMPARATOR VIN FSYNC SCLK SDATA PSELECT SLEEP RESET Figure 1. AD9834 Functional Block Diagram Rev. 0 | Page 1 of 4 08955-001 AD9834 AN-1070 Application Note TABLE OF CONTENTS Introduction ...................................................................................... 1 Functional Block Diagram ...............................................................1 Programming the AD9833/AD9834 .............................................. 1 More on Programming the AD9833/AD9834...............................3 Rev. 0 | Page 2 of 4 Application Note AN-1070 MORE ON PROGRAMMING THE AD9833/AD9834 Command Sequence Explained A simple example is the best method to explain how to program the AD9833/ AD9834. Refer to the AD9833 or the AD9834 data sheet for more details. 0x2100—Control Register • Basic Example The aim is to generate a 400 Hz output frequency using the AD9833 with a 25 MHz MCLK. • The dial-up code for this is defined by the equation FreqReg = 0x50C7—Frequency Register 0 LSB f OUT × 2 28 • f MCLK Thus, for this example, Freq 0 = 400 Hz. FreqReg = • 400 Hz × 2 28 25 MHz = 4295 decimal = 0x10C7 = 0001 0000 1100 0111 • • Table 1. Binary 0010 0001 0000 0000 0101 0000 1100 0111 0100 0000 0000 0000 1100 0000 0000 0000 0010 0000 0000 0000 DB15 and DB14 are set to 0 and 1, respectively, which is the Frequency Register 0 address. The remaining 14 bits are the 14 LSBs of data: 0x10C7 = 01 0000 1100 0111 0x4000—Frequency Register 0 MSB The required initialization sequence is shown in Table 1. Hexadecimal 0x2100 0x50C7 0x4000 0xC000 0x2000 DB13 is set to 1. This allows a complete word to be loaded into a frequency register in two consecutive writes. The first write contains 14 LSBs. The second write contains 14 MSBs. RESET bit DB8 is set to 1. This resets internal registers to 0, which corresponds to an analog output of midscale. DB15 and DB14 are set to 0 and 1, respectively, which is the Frequency Register 0 address. The remaining 14 bits are the 14 MSBs of data and are all 0s in this case. 0xC000—Phase Register 0 • • DB15, DB14, and DB13 are set to 110, with DB12 set to don’t care (X), respectively, which is the address for Phase Register 0. The remaining 12 bits are the data bits and are all 0s in this case. 0x2000—Exit Reset • Rev. 0 | Page 3 of 4 A signal appears at the output of the DAC seven MCLK cycles after RESET is set to 0. AN-1070 Application Note NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AN08955-0-3/10(0) Rev. 0 | Page 4 of 4