NXP ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic

NXP ultra-low-power
CMOS logic
74AUP1G/2G/3Gxxx
Advanced, ultra-low-power CMOS logic
Designed for high-performance, low-power applications, these low-voltage, Si-gate CMOS devices
provide logic solutions with very low static and dynamic power dissipation.
Key features
` Very low dynamic power dissipation (CPD)
` tpd of 2.5 ns at Vcc of 2.5 V
` Wide supply voltage range (0.8 to 3.6 V)
` Schmitt-trigger action on all inputs
` Low-threshold input options
` 1.9 mA balanced output drive
` Overvoltage-tolerant I/O
` Fully specified (-40 to +85 and -40 to +125 °C)
` Automotive options (-Q100 suffix)
` Pb-free, RoHS-compliant and Dark Green
Benefits
` Low propagation delay
` Suitable for mixed-voltage applications
` High noise immunity
` Extended battery life
` Wide range of functions
` Simplified board layout, mechanical stability
Applications
` Cellular handsets and smartphones
` MP3 players and portable video players
` DSCs and digital camcorders
` Portable devices (laptops, tablets, GPS)
` Consumer entertainment (LCD TVs, DVD+R/W systems,
STBs)
` Portable instrumentation
The AUP family of Si-gate CMOS devices uses advanced
process technology and next-generation packaging
technology to create extremely small functions that consume
very little power. The devices are available with one (1G),
two (2G), or three (3G) gates.
AUP devices are available in standard, configurable, and
combination formats. Special variants are also available,
including dual-supply voltage-level translators and devices
with low-threshold inputs.
LONGER BATTERY LIFE
On average, the AUP family consumes 30% less power than
competing logic families. AUP devices extend battery life
by ensuring low power consumption, without sacrificing
performance, across the entire Vcc range in static and dynamic
modes. The typical power dissipation capacitance (CPD ) at
1.8 V is only 3.5 pF and at 3.3 V is only 4.3 pF, while the typical
propagation delay at 2.5 V is only 2.5 ns.
To save even more battery power, the devices are fully
specified for partial power-down applications that use the
IOFF feature. The IOFF circuitry disables the output, preventing
the damage caused by backflow current passing through the
device when it is powered down.
AUP
ULP
Configurable-logic devices have Schmitt-trigger inputs with
fully specified hysteresis, giving them even better noise
immunity than the standard part types.
COMBINATION LOGIC
Combination logic offers two or more unique functions in
a single package. The functions are either stand alone or
internally cascaded.
AUC
1200
Battery life (minutes)
AUP configurable-logic devices provide design flexibility by
integrating nine different functions, including non-standard
logic functions, in a single device. Other advantages of
configurable logic include reduced PCB space and lower cost.
These devices can also reduce the number of types in a bill of
materials, simplifying inventory management.
Figure 1a illustrates standalone operation, with the buffer and
the inverter having no internal connection. Figure 1b illustrates
the cascaded option, with the output of the AND gate
internally applied as an input to the OR gate.
900
600
300
0
1.8
2.0
2.2
2.4
2.6
Operating VCC (V)
2.8
3.0
1
1A
1Y
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3
2A
2Y
4
3.2
MIXED-VOLTAGE APPLICATIONS
Optimized for 1.8 V applications and operating over a wide
supply range of 0.8 to 3.6 V, AUP devices are ideally suited for
use in mixed-voltage applications. Inputs that are tolerant to
3.6 V enable a device supplied at 1.8 V to interface between
3.3 and 1.8 V systems. Options with low-threshold inputs (1T)
can interface between 1.2 and 3.3 V systems when supplied
with 3.3 V. The portfolio also includes dual-supply voltagelevel translators in uni- and bidirectional formats. Schmitttrigger action at all inputs improves noise immunity and makes
the circuit tolerant to slower input rise and fall times across the
entire range of supply voltage.
CONFIGURABLE LOGIC
A configurable-logic device is a single device that can be
configured as any one of up to nine different functions.
Examples include standard AND, OR, NAND, NOR, buffers,
inverters, and multiplexers, as well as non-standard functions
such as a NAND gate with one input inverted.
aaa-002988
Figure 1a: stand alone combination logic
A
B
C
1
3
6
4
Y
001aad943
Figure 1b: internally cascaded combination logic
Solutions based on combination logic have lower total
cost, including pick and place cost, and reduced PCB area.
Combination logic also helps to optimize and simplify the PCB
layout and signal routing.
AUP portfolio
SOT1226 (GX)
SOT1203 (GS)
SOT1202 (GS)
SOT1116 (GN)
SOT1115 (GN)
SOT1089 (GF)
SOT1081 (GF)
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SOT996-2 (GD)
SOT891 (GF)
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SOT902-2 (GM)
SOT886 (GM)
SOT833-1 (GT)
SOT765-1 (DC)
SOT753 (GV)
SOT363 (GW)
SOT353-1 (GW)
Dual supply translator
Power-off protection
(IOFF)
Open-drain output
3.6 V tolerant I/O's
Package (suffix)
Schmitt trigger action
Features
Schmitt trigger inputs
Description
Low threshold inputs
Type number
Configurable
74AUP1G57
Single configurable multi-function gate
74AUP1G58
Single configurable multi-function gate
74AUP1G97
Single configurable multi-function gate
74AUP1G98
Single configurable multi-function gate
74AUP1T57
Single configurable multi-function gate
74AUP1T58
Single configurable multi-function gate
74AUP1T97
Single configurable multi-function gate
74AUP1T98
Single configurable multi-function gate
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Combination
74AUP1G0832
Single 3-input AND-OR gate
74AUP1G3208
Single 3-input OR-AND gate
74AUP1G885
Single dual-function gate
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74AUP1Z04
X-tal driver with enable
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74AUP1Z125
X-tal driver with enable; 3-state
74AUP2G0604
Inverter; open drain and inverter
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Buffer and inverter
Dual supply buffer/line driver; 3-state
74AUP3G0434
Dual inverter and single buffer
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74AUP3G3404
Dual buffer and single inverter
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74AUP1G04
Single inverter
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74AUP1G06
Single inverter; open drain
74AUP1G07
Single buffer; open drain
74AUP1G125
Single buffer/line driver; 3-state
74AUP1G126
Single buffer/line driver; 3-state
74AUP1G14
Single inverter; Schmitt trigger
74AUP1G17
Single buffer; Schmitt trigger
74AUP1G240
Single inverter/line driver; 3-state
74AUP1G34
Single buffer
74AUP1GU04
Single unbuffered inverter
74AUP1T34
Single translating buffer
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74AUP2G3404
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74AUP2T1326GF
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Buffers/inverters
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74AUP2G125
Dual buffer/line driver; 3-state
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74AUP2G126
Dual buffer/line driver; 3-state
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74AUP2G14
Dual inverter; Schmitt trigger
74AUP2G157
Single 2-input multiplexer
74AUP2G17
Dual buffer; Schmitt trigger
74AUP2G240
Dual inverter/line driver; 3-state
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74AUP2G241
Dual buffer/line driver; 3-state
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74AUP2G34
Dual buffer
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Dual unbuffered inverter
Triple inverter
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More information available at
www.nxp.com/products/logic/gates/configurable_multiple_function_gates/
www.nxp.com/products/logic/gates/combination/
www.nxp.com/products/logic/buffers_inverters_drivers/
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Dual buffer; open drain
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74AUP2G07
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Dual inverter
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Dual inverter; open drain
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74AUP2G04
74AUP2GU04
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74AUP2G06
74AUP3G04
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AUP portfolio (continued)
SOT1226 (GX)
SOT1203 (GS)
SOT1202 (GS)
SOT1116 (GN)
SOT1115 (GN)
SOT1089 (GF)
SOT1081 (GF)
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SOT996-2 (GD)
SOT891 (GF)
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SOT902-2 (GM)
SOT886 (GM)
SOT833-1 (GT)
SOT765-1 (DC)
SOT753 (GV)
SOT363 (GW)
SOT353-1 (GW)
Dual supply translator
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Power-off protection (IOFF)
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Open-drain output
3.6 V tolerant I/O's
Package (suffix)
Schmitt trigger action
Features
Schmitt trigger inputs
Description
Low threshold inputs
Type number
Gates
74AUP1G00
Single 2-input NAND gate
74AUP1G02
Single 2-input NOR gate
74AUP1G08
Single 2-input AND gate
74AUP1G09
Single 2-input AND gate; open drain
74AUP1G11
Single 3-input AND gate
74AUP1G132
Single 2-input NAND gate; Schmitt trigger
74AUP1G32
Single 2-input OR-gate
74AUP1G332
Single 3-input OR-gate
74AUP1G38
Single 2-input NAND-gate; open drain
74AUP1G386
Single 3-input EXCLUSIVE-OR gate
74AUP1G86
Single 2-input EXCLUSIVE-OR gate
74AUP2G00
Dual 2-input NAND gate
74AUP2G02
Dual 2-input NOR gate
74AUP2G08
Dual 2-input AND gate
74AUP2G132
Dual 2-input NAND gate; Schmitt trigger
74AUP2G32
Dual 2-input OR gate
74AUP2G38
Dual 2-input NAND gate; open drain
74AUP2G86
Dual 2-input EXCLUSIVE-OR gate
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Flip-flops
74AUP1G175
Single D-type flip-flop with reset
74AUP1G374
Single D-type flip-flop; 3-state
74AUP1G74
Single D-type flip-flop with set and reset
74AUP1G79
Single D-type flip-flop
74AUP1G80
Single D-type flip-flop
74AUP2G79
Dual D-type flip-flop
74AUP2G80
Dual D-type flip-flop
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Latches
74AUP1G373
Single D-type transparent latch; 3-state
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Multiplexers
74AUP1G157
Single 2-input multiplexer
74AUP1G158
Single 2-input multiplexer; inverting
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Demultiplexers
74AUP1G18
Single 1-of-2 demultiplexer; 3-state
74AUP1G19
Single 1-of-2 decoder/demultiplexer
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Transceivers
74AUP1T45
Single translating transceiver; 3-state
More information available at
www.nxp.com/products/logic/gates/
www.nxp.com/products/logic/flip_flops/
www.nxp.com/products/logic/latches_registered_drivers/
www.nxp.com/products/logic/digital_multiplexers/
www.nxp.com/products/logic/decoders_demultiplexers/
www.nxp.com/products/logic/level_shifters_translators/
www.nxp.com/products/logic/transceivers/
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More about the AUP family
www.nxp.com/products/logic/family/AUP/
PACKAGES
AUP devices are available in PicoGate and MicroPak packages, which are roughly ten times smaller than a conventional SO14
package. PicoGate and MicroPak products reduce time-to-market by making it easy to implement last-minute changes. They also
improve the cost-effectiveness of crowded layouts, because they simplify routing and eliminate dependences in intricate linelayout patterns.
The AUP family operates over an extended temperature range (-40 to +125 °C), so they’re suitable for a wide range of
applications, including portable, consumer, military, and automotive (-Q100 variants). Multi-pin packages with 5, 6, or 8 pins
make it easy to select the right combination of features, packages, and performance.
NXP’s new Diamond package (suffix GX) is over 25 percent smaller than our XSON package (suffix GN), which was previously
the world’s smallest package. Yet, while this game-changing Diamond package is a tiny 0.8 mm square by only 0.35 mm high, its
breakthrough design retains the traditional 0.5 mm pad pitch, so it eliminates the need for expensive step-down solder masks
and allows simplified PCB assembly.
Package summary
Package suffix
Package
GW
GV
GX
GW
GM
GF
GN
GS
5-pin
5-pin
5-pin
6-pin
6-pin
6-pin
6-pin
6-pin
SOT353-1
SOT753
SOT1226
SOT363
SOT886
SOT891
SOT1115
SOT1202
Width (mm)
2.10
2.75
0.80
2.10
1.00
1.00
1.00
1.00
Length (mm)
2.00
2.90
0.80
2.00
1.45
1.00
0.90
1.00
Height (mm)
1.00
1.00
0.35
1.00
0.50
0.50
0.35
0.35
Pitch (mm)
0.65
0.95
0.50
0.65
0.50
0.35
0.35
0.35
Package suffix
Package
DC
GT
GM
GD
GF
GN
GS
GF
8-pin
8-pin
8-pin
8-pin
8-pin
8-pin
8-pin
10-pin
SOT765-1
SOT833-1
SOT902-2
SOT996-2
SOT1089
SOT1116
SOT1203
SOT1081-2
Width (mm)
3.10
1.00
1.60
3.00
1.00
1.00
1.00
1.00
Length (mm)
2.00
1.95
1.60
2.00
1.35
1.20
1.35
1.70
Height (mm)
1.00
0.50
0.50
0.50
0.50
0.35
0.35
0.50
Pitch (mm)
0.50
0.50
0.50
0.50
0.35
0.30
0.35
0.35
www.nxp.com
© 2014 NXP Semiconductors N.V.
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner. The information presented in this document does not form part of any quotation or contract,
is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by
the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: October 2014
Document order number: 9397 750 17458
Printed in the Netherlands