AN11052 Pin FMEA for AUP family Rev. 1 — 6 May 2011 Application note Document information Info Content Keywords FMEA, AUP, CMOS, low power, 3 V systems Abstract This application note provides a Failure Modes and Effects Analysis (FMEA) for the device pins of the NXP Semiconductors’ AUP family under typical failure situations AN11052 NXP Semiconductors Pin FMEA for AUP family Revision history Rev Date Description v.1 20110506 initial version Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] AN11052 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 6 May 2011 © NXP B.V. 2011. All rights reserved. 2 of 7 AN11052 NXP Semiconductors Pin FMEA for AUP family 1. Introduction The NXP ultra-low-power (AUP) CMOS logic 74AUP1G/2G3Gxxx family is designed for high-performance, low-power applications. These low-voltage, Si-gate CMOS devices offer the industry’s lowest dynamic power consumption in a logic device. 2. AUP family overview The NXP 74AUP1G/2G/3Gxxx family of Si-gate CMOS devices uses advanced process technology and next-generation packaging technology to create extremely small devices that consume very little power. The devices are available in single- (1Gxx), dual- (2Gxx) and triple-gate (3Gxx) formats. AUP devices offer the industry’s lowest power dissipation capacitance (CPD), yet maintain low propagation delays (tPD) and superior ESD protection. Typical CPD at 1.8 V and 3.3 V is only 4.3 pF, while the tPD at a VCC of 2.5 V is only 2.5 ns. Operating over a very wide supply range of 0.8 V to 3.6 V, AUP devices are ideally suited for use in mixed-voltage applications. Schmitt-trigger action at all inputs improves noise immunity by making the circuit tolerant to slower input rise and fall times across the entire range of supply voltage. The devices extend battery life by ensuring very low power consumption that is 30 % lower than competing logic functions. To save even more battery power, the devices are fully specified for partial power-down applications that use the IOFF feature. The IOFF circuitry disables the output, preventing damage caused by backflow current passing through the device when it is powered down. AUP devices are available in PicoGate and MicroPak packages, which are roughly ten times smaller than a conventional SO14 package. PicoGate and MicroPak products reduce time-to-market by making it easy to implement last-minute changes. They also improve the cost-effectiveness of crowded layouts by simplifying routing and eliminating dependencies in intricate line-layout patterns. The AUP family operates over an extended temperature range (−40 °C to +125 °C) that is suitable for a wide range of applications, including portable, consumer, automotive, and military. Multi-pin (5-, 6- and 8-pin) packages make it easy to select the right combination of features. 3. Pin FMEA This application note provides a Failure Modes and Effects Analysis (FMEA) for the device pins of the NXP Semiconductors’ AUP family under typical failure situations such as a short-circuit to VCC or GND or to a neighboring pin, or if a pin is left open. Some AUP family devices have special functions, such as translators and level-shifters, that can have different behaviors. A failure is classified according to its effect on the AUP device and the functionality of the application; see Table 1. AN11052 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 6 May 2011 © NXP B.V. 2011. All rights reserved. 3 of 7 AN11052 NXP Semiconductors Pin FMEA for AUP family Table 1. Classification of failure effects Class Failure effect A damage to device affects application functionality B no damage to device may affect application functionality C no damage to device no affect to application functionality Table 2. Pin Class Remarks Input B normal operating condition, no damage, no leakage, may affect functionality Output C if output defined HIGH, no damage, no leakage, no output level change Output A if output defined LOW, short-circuits and high currents can damage device, output level changes GND B short-circuits and high currents can damage device, will affect functionality Table 3. Class Remarks Input B normal operating condition, no damage, no leakage, may affect functionality Output C if output defined LOW, no damage, no leakage, no output level change Output A if output defined HIGH, short-circuits and high currents can damage device, output level changes VCC B no damage to device, will affect functionality FMEA matrix for pin left open Pin Class Remarks Input B undefined operating condition, no damage, increases leakage, may affect functionality Output C normal operating condition, no damage, no leakage GND B undefined operating condition, no damage, increases leakage, will affect functionality VCC B undefined operating condition, no damage, increases leakage (only for I/O types), will affect functionality Table 5. Application note FMEA matrix for pin short-circuit to GND Pin Table 4. AN11052 FMEA matrix for pin short-circuit to VCC FMEA matrix for pin short-circuits between neighbor pins Pin Class Remarks Input to input C if inputs have same voltage levels: no damage, no leakage B if inputs have different voltage levels: leakage increases, will affect functionality All information provided in this document is subject to legal disclaimers. Rev. 1 — 6 May 2011 © NXP B.V. 2011. All rights reserved. 4 of 7 AN11052 NXP Semiconductors Pin FMEA for AUP family Table 5. FMEA matrix for pin short-circuits between neighbor pins …continued Pin Class Remarks Input to output A if input and output have different voltage levels, can cause high current and can damage device, will affect functionality C if input and output have same voltage levels, no damage, no leakage Input to GND - see Table 3 Input to VCC - see Table 2 Output to output C if outputs have same voltage levels, no damage, no leakage A if outputs have different voltage levels, can cause high current and can damage device, will affect functionality Output to input - same effect as ‘input to output’ condition Output to GND - see Table 3 Output to VCC - see Table 2 GND to VCC - not applicable, these pins are not neighbors 4. Abbreviations Table 6. AN11052 Application note Abbreviations Acronym Description AUP Advanced Ultra-low Power CMOS Complementary Metal-Oxide Semiconductor EDP Electronic Data Processing ESD ElectroStatic Discharge FMEA Failure Modes and Effects Analysis LVC Low-Voltage CMOS TTL Transistor-Transistor Logic All information provided in this document is subject to legal disclaimers. Rev. 1 — 6 May 2011 © NXP B.V. 2011. All rights reserved. 5 of 7 AN11052 NXP Semiconductors Pin FMEA for AUP family 5. Legal information 5.1 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 5.2 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product AN11052 Application note design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 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In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customer’s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose. 5.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 1 — 6 May 2011 © NXP B.V. 2011. All rights reserved. 6 of 7 AN11052 NXP Semiconductors Pin FMEA for AUP family 6. Contents 1 2 3 4 5 5.1 5.2 5.3 6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . AUP family overview . . . . . . . . . . . . . . . . . . . . . Pin FMEA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 5 6 6 6 6 7 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 6 May 2011 Document identifier: AN11052