ANALOG IP BLOCK CDAC10 - CMOS 10-Bit D/A CONVERTER DATA SHEET PROCESS DESCRIPTION C35B3 (0.35um) The CDAC10 is a 10-bit high-resolution high-speed CMOS digital-to-analog converter (DAC). The CDAC10 uses a segmented current steering architecture combined with a simple and fast decoding logic to achieve a very high update rate, 10-bit of intrinsic static accuracy, and good dynamic characteristics. The CDAC10 is a differential current output DAC with a typical fullscale current of 20mA. The output currents can be used to directly drive two external resistors to obtain two complementary output voltages, or they can be used to drive an external transformer (or amplifier) to obtain a single-ended output voltage. FEATURES ! Small Area: < 1.05mm2 ! ! ! ! ! ! ! Size: x = 1550µm y = 680µm Supply Voltage: 3.0V to 3.6V Junction Temp. Range: –40 to 125°C Resolution: 10-Bit Update Rate: 200MS/s Diff. Current Outputs: 10 to 25mA Power Dissipation of 153mW @ 3.3V Supply Voltage in LS mode VDDD VDDS VDDA VSSD VSSS VSSA VRES CURRENT SOURCE ARRAY B1 B0 6 MSB SWITCHES 4 LSB SWITCHES B6 B5 B4 B3 B2 ROW DECODER B9 B8 B7 INPUT REGENERATION COLUMN DECODER CLK IOUTN Revision B, 11.09.02 4 LSB CURRENT SOURCES BIAS GENERATION IOUTP VBIASC IBIAS Page 1 of 12 Datasheet : CDAC10 - C35 TECHNICAL DATA FOR HS MODE (Tjunction=–40 to 125°C, VDDA=VDDD=+3.0V to +3.6V, fclk=200MHz, RL=50Ω, unless otherwise specified) DC SPECIFICATIONS Symbol Parameter Resolution DNL INL Conditions Min 10 Typ Max Units bit Differential Linearity Error –1 ±0.4 +1 LSB Integral Linearity Error –1 ±0.4 +1 LSB Conditions Min –IFS/16 Typ –IFS/16 Max –IFS/16 Units mA Conditions Min –5 Typ 0 Max +5 Units %FS REFERENCE INPUT Symbol IBIAS Parameter Reference Current ANALOG OUTPUT Symbol OFFSETB Parameter Offset Error FSERR Full-Scale Error –10 2 +10 %FS IFS Full-Scale Output Current 10 20 25 mA VFS Output Compliance Range 1 1.25 V Rout Output Resistance Cout Output Capacitance foutmax Max. Output Signal Frequency 30 kΩ 15 pF 30 MHz Max Units dBc AC ACCURACY (fclk=200MHz) Symbol THD Parameter Total Harmonic Distortion Conditions fout=1MHz Min Typ –73 THD Total Harmonic Distortion fout=10MHz –55 dBc THD Total Harmonic Distortion fout=30MHz –55 dBc SFDR Spurious Free Dynamic Range fout=1MHz 70 dBc SFDR Spurious Free Dynamic Range fout=10MHz 58 dBc SFDR Spurious Free Dynamic Range fout=30MHz 56 dBc AC ACCURACY (fclk=100MHz) Symbol THD Parameter Total Harmonic Distortion Conditions fout=0.5MHz Min THD Total Harmonic Distortion fout=5MHz –60 dBc THD Total Harmonic Distortion fout=15MHz –60 dBc SFDR Spurious Free Dynamic Range fout=0.5MHz 72 dBc SFDR Spurious Free Dynamic Range fout=5MHz 66 dBc 61 dBc –62 dBc 62 dBc SFDR Spurious Free Dynamic Range fout=15MHz TT-IMD Two-Tone Third Order Intermodulation Distortion fout1=10MHz fout2=11MHz TT-SFDR Two-Tone Spurious Free Dynamic Range fout1=10MHz 1) fout2=11MHz 1) 1) Typ –78 Max Both signals, fout1 and fout2, have an amplitude of –6dB full scale. Revision B, 11.09.02 Page 2 of 12 Units dBc Datasheet : CDAC10 - C35 DYNAMIC PERFORMANCE Symbol Ts Parameter Settling Time (0.1%) Conditions Min Typ 380 Max Units ns Tr Output Rise Time (10% - 90%) 1.6 ns Tf Output Fall Time (90% - 10%) 1.6 ns Tpd Output Propagation Delay 2.5 ns GA Glitch Area 10 pVs DIGITAL INPUTS Symbol Parameter Digital Input Level Conditions Digital Input Codes Min Typ CMOS levels Max Units Unsigned binary: 000h - FFFh POWER REQUIREMENTS Symbol VDDA VDDD Parameter Pos. Analog Supply Voltage Conditions ref. VSSA Min 3.0 Pos. Digital Supply Voltage ref. VSSD 3.0 Typ 3.3 Max 3.6 Units V 3.3 3.6 V Static Supply Current Digital 0 0 mA IDDAstat 1) Static Supply Current Analog 43 50 mA Pdissstat 1) 2) Static Total Power Consumption 146 186 mW IDDDdyn 3) Dynamic Supply Current Digital 23 31 mA IDDAdyn Dynamic Supply Current Analog 43 50 mA Pdissdyn 2) 3) Dynamic Total Power Consumption 222 297 mW IDDDstat 1) TIMING CHARACTERISTICS Symbol Tclk Parameter Clock Period fclk Master Clock Frequency Conditions Min 5 Typ 5 Max Units ns 200 200 MHz 200 200 Ur Update Rate Tsu Setup Time Data to Clock 0.5 0.5 ns Th Hold Time Clock to Data 1 1 ns 1) 2) 3) All digital input signals and the clock are set to a static level (Low or High). Including the bias current IBIAS. The measurement includes 11 digital input pads (ICP). Revision B, 11.09.02 Page 3 of 12 MS/s Datasheet : CDAC10 - C35 TYPICAL PERFORMANCE CHARACTERISTICS FOR HS MODE DNL [LSB] DNL [LSB] (Tjunction =25°C, VDDA=VDDD=+3.3V, IBIAS=–1.25mA, unless otherwise specified) Digital Code Digital Code SFDR [dBc] INL 1) SFDR [dBc] DNL 1) Output Signal Frequency [Hz] Output Signal Frequency [Hz] Output Signal Frequency [Hz] Spectrum @5MHz 2) 1) 2) 3) SFDR vs. Output Signal Frequency 1) FFT [dBc] FFT [dBc] SFDR vs. Output Signal Frequency 2) Output Signal Frequency [Hz] Two-Tone IMD @10MHz and 11MHz 2) 3) fclk=200MHz fclk=100MHz Both signals, fout1 and fout2, have an amplitude of –6dB full scale. Revision B, 11.09.02 Page 4 of 12 Datasheet : CDAC10 - C35 TECHNICAL DATA FOR LS MODE (Tjunction=–40 to 125°C, VDDA=VDDD=+3.0V to +3.6V, fclk=200MHz, RL=25Ω, unless otherwise specified) DC SPECIFICATIONS Symbol Parameter Resolution Conditions Min 10 Typ Max Units bit DNL Differential Linearity Error –1 ±0.4 +1 LSB INL Integral Linearity Error –1 ±0.4 +1 LSB Conditions Min –IFS/16 Typ –IFS/16 Max –IFS/16 Units mA Conditions Min –5 Typ 0 Max +5 Units %FS REFERENCE INPUT Symbol IBIAS Parameter Reference Current ANALOG OUTPUT Symbol OFFSETB Parameter Offset Error FSERR Full-Scale Error –10 3 +10 %FS IFS Full-Scale Output Current 10 20 25 mA VFS Output Compliance Range 0.5 0.625 V Rout Output Resistance Cout Output Capacitance foutmax Max. Output Signal Frequency 30 kΩ 15 pF 30 MHz Max Units dBc AC ACCURACY (fclk=200MHz) Symbol THD Parameter Total Harmonic Distortion Conditions fout=1MHz Min Typ –71 THD Total Harmonic Distortion fout=10MHz –54 dBc THD Total Harmonic Distortion fout=30MHz –48 dBc SFDR Spurious Free Dynamic Range fout=1MHz 72 dBc SFDR Spurious Free Dynamic Range fout=10MHz 58 dBc SFDR Spurious Free Dynamic Range fout=30MHz 50 dBc AC ACCURACY (fclk=100MHz) Symbol THD Parameter Total Harmonic Distortion Conditions fout=0.5MHz THD Total Harmonic Distortion fout=5MHz –58 dBc THD Total Harmonic Distortion fout=15MHz –56 dBc SFDR Spurious Free Dynamic Range fout=0.5MHz 72 dBc SFDR Spurious Free Dynamic Range fout=5MHz 63 dBc SFDR Spurious Free Dynamic Range fout=15MHz 58 dBc TT-IMD Two-Tone Third Order Intermodulation Distortion fout1=10MHz fout2=11MHz –60 dBc TT-SFDR Two-Tone Spurious Free Dynamic Range fout1=10MHz 1) fout2=11MHz 60 dBc 1) Min 1) Typ –78 Max Both signals, fout1 and fout2, have an amplitude of –6dB full scale. Revision B, 11.09.02 Page 5 of 12 Units dBc Datasheet : CDAC10 - C35 DYNAMIC PERFORMANCE Symbol Ts Parameter Settling Time (0.1%) Conditions Min Typ 70 Max Units ns Tr Output Rise Time (10% - 90%) 600 ps Tf Output Fall Time (90% - 10%) 600 ps Tpd Output Propagation Delay 2.5 ns GA Glitch Area 10 pVs DIGITAL INPUTS Symbol Parameter Digital Input Level Conditions Digital Input Codes Min Typ CMOS levels Max Units Unsigned binary: 000h - FFFh POWER REQUIREMENTS Symbol VDDA VDDD Parameter Pos. Analog Supply Voltage Conditions ref. VSSA Min 3.0 Pos. Digital Supply Voltage ref. VSSD 3.0 Typ 3.3 Max 3.6 Units V 3.3 3.6 V Static Supply Current Digital 0 0 mA IDDAstat 1) Static Supply Current Analog 22 30 mA Pdissstat 1) 2) Static Total Power Consumption 73 109 mW IDDDdyn 3) Dynamic Supply Current Digital 23 31 mA IDDAdyn Dynamic Supply Current Analog 22 30 mA Pdissdyn 2) 3) Dynamic Total Power Consumption 153 225 mW IDDDstat 1) TIMING CHARACTERISTICS Symbol Tclk Parameter Clock Period fclk Master Clock Frequency Conditions Min 5 Typ 5 Max Units ns 200 200 MHz 200 200 Ur Update Rate Tsu Setup Time Data to Clock 0.5 0.5 ns Th Hold Time Clock to Data 1 1 ns 1) 2) 3) All digital input signals and the clock are set to a static level (Low or High). Including the bias current IBIAS. The measurement includes 11 digital input pads (ICP). Revision B, 11.09.02 Page 6 of 12 MS/s Datasheet : CDAC10 - C35 TYPICAL PERFORMANCE CHARACTERISTICS FOR LS MODE DNL [LSB] DNL [LSB] (Tjunction=25°C, VDDA=VDDD=+3.3V, IBIAS=–1.25mA, unless otherwise specified) Digital Code Digital Code SFDR [dBc] INL 1) SFDR [dBc] DNL 1) Output Signal Frequency [Hz] Output Signal Frequency [Hz] Output Signal Frequency [Hz] Spectrum @5MHz 2) 1) 2) 3) SFDR vs. Output Signal Frequency 1) FFT [dBc] FFT [dBc] SFDR vs. Output Signal Frequency 2) Output Signal Frequency [Hz] Two-Tone IMD @10MHz and 11MHz 2) 3) fclk=200MHz fclk=100MHz Both signals, fout1 and fout2, have an amplitude of –6dB full scale. Revision B, 11.09.02 Page 7 of 12 Datasheet : CDAC10 - C35 SYMBOL PINLIST Pin CLK Description Clock Input Type DIN Cap 1pF B[9:0] Digital Input Data DIN 1pF IBIAS Reference Current AIN VBIASC Reserved AIN IOUTP IOUTN Differential Current Outputs AOUT VRES Mode Select LS, HS S VDDD Pos. Digital Supply S VSSD Neg. Digital Supply S VDDA1 Pos. Analog Supply S VDDA2 Pos. Analog Supply S VSSA Neg. Analog Supply S VDDS Digital Power Supply for N-Well Shielding S VSSS Substrate Supply S THEORY OF OPERATION POWER SUPPLIES The macro cell CDAC10 is a 10-bit digital to analog converter based on a current steering architecture. CDAC10 features a 6+4 bit segmented architecture, where the 6 most significant bits are implemented with 64 unity decoded cells, and the 4 least significant bits are implemented with 4 binary weighted cells. External loads are to be connected outside the CDAC10 and are recommended as terminations for high-speed operation. The full-scale output range is defined by the bias current applied to the IBIAS pin. The converter requires a single +3.3V power supply. The supplies for analog and digital are separated. They may be connected together. There are also two special pins: VDDS must be connected to the digital supply and VSSS must be connected to the star point of the ground. However, for maximum noise immunity it is recommended to wire all supplies on chip to separated pins, especially when the block is embedded in a large digital circuit. The supplies may then be connected together on PC-board level. The proper use of blocking capacitors in the application is important! OPERATING MODES REFERENCE CURRENT There are two operating modes possible with CDAC10 . One is the low swing mode (LS). VRES is shorted to VSSA and the output The reference current is equal to –1/16 of the desired full-scale current. For best performance a value of 20mA is recommended. It is important to note that the external current reference circuit must be able to sink the reference current. The proper use of blocking capacitors in the application is important! resistor RL is 25Ω. The full-scale output voltage at IOUTP and IOUTN should not exceed 0.625V. The other one is the high swing mode (HS). VRES is connected to VDDA and the output resistor RL is 50Ω. The full-scale output voltage at IOUTP and IOUTN should not exceed 1.25V. In both cases VBIASC must be left open. Revision B, 11.09.02 Page 8 of 12 Datasheet : CDAC10 - C35 CODE TABLE The digital representation of the data bus is described in the following table. VFS = IFS * RL , VLSB = 2 * VFS 1023 , VOUT = (−511.5 + Code ) * VLSB Input Code 11 1111 1111 Output Voltage: VOUTP-VOUTN 511.5*VLSB 11 1111 1110 510.5*VLSB … … 10 0000 0001 1.5*VLSB 10 0000 0000 0.5*VLSB 01 1111 1111 –0.5*VLSB 01 1111 1110 –1.5*VLSB … … 00 0000 0001 –510.5*VLSB 00 0000 0000 –511.5*VLSB FUNCTIONAL BLOCK DIAGRAM VDDD VDDS VDDA VSSD VSSS VSSA VRES CURRENT SOURCE ARRAY COLUMN DECODER B5 B4 B3 B2 B1 B0 6 MSB SWITCHES B6 4 LSB SWITCHES B7 ROW DECODER B8 INPUT REGENERATION B9 CLK IOUTN Revision B, 11.09.02 4 LSB CURRENT SOURCES BIAS GENERATION IOUTP VBIASC IBIAS Page 9 of 12 Datasheet : CDAC10 - C35 TIMING DIAGRAM OF CDAC10 The latch of each input bit line is transparent during the time the clock is low. In order to avoid wrong data at the output of the DAC the specified setup time (Tsu) and hold time (Th) must be met. At the falling edge of the CLK signal, the pre-selected current cells are connected in parallel. After the specified propagation delay (Tpd), the converter output lines start changing towards their final value. From this point on, the converter achieves the final value within the specified settling time. The CDAC10 operates according to the following timing diagram. Tsu Th CLK B[9:0] Data Valid 90% IOUTP 10% Tpd Tr Ts Tclk IOUTN 90% 10% Tpd Revision B, 11.09.02 Tf Ts Page 10 of 12 Datasheet : CDAC10 - C35 TYPICAL APPLICATION APPLICATION The CDAC10 is suitable for applications requiring very high update rates and medium resolutions, such as direct digital synthesis, high-speed communications, and instrumentation. ! ! ! ! ! ! ! WLL, Cellular Base Station Digital Microwave Links Direct Digital Synthesis (DDS) Arbitrary Waveform Generation (AWG) Medical/Ultrasound High-Speed Instrumentation and Control Video, Digital TV VDDA VDDD VDDA +3.3V VDDA 100uF 3.3uF 4.7nF 200pF 10pF Digital Pattern Vout Generation Block VSSA 50Ω 100MHz +3.3V 50Ω 1.25mA VDDD 22uF 3.3uF 4.7nF 200pF 10pF 6.6uF 680pF 330pF 10pF VSSD GROUND Configuration: HS mode @ fclk=100MHz VDDA VDDD +3.3V VDDA 100uF 3.3uF 4.7nF 200pF 10pF Digital Pattern Vout Generation Block VSSA 25Ω 200MHz +3.3V 1.25mA VDDD 22uF 3.3uF 4.7nF 200pF 10pF 6.6uF 680pF 330pF 10pF VSSD GROUND Configuration: LS mode @ fclk=200MHz Revision B, 11.09.02 Page 11 of 12 25Ω Datasheet : CDAC10 - C35 Contact Copyright austriamicrosystems AG A 8141 Schloss Premstätten, Austria T. +43 (0) 3136 500 5333 F. +43 (0) 3136 500 5755 [email protected] Copyright © 2002 austriamicrosystems. Trademarks registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. To the best of its knowledge, austriamicrosystems asserts that the information contained in this publication is accurate and correct. Revision B, 11.09.02 Page 12 of 12