ANALOG IP BLOCK ADC1220 - CMOS 12-Bit Pipelined A/D CONVERTER DATA SHEET PROCESS DESCRIPTION C35B3 (0.35um) The ADC1220 is a high-speed pipeline ADC core cell achieving sampling rates up to 20 MS/s. A S/H circuit is built-in to provide low jitter noise and a fully differential input. The reference voltages are internally generated from a bandgap reference that must be supplied to the cell or must be supplied externally to the cell. A power down capability is included for very low power dissipation in stand-by mode. FEATURES ! Small Area: 3.87 mm2 ! ! Size x = 2261.5 µm y = 1711.55 µm Supply Voltage 3.0 - 3.6 V ! ! ! ! ! ! ! ! Junction Temp. Range: −40 to +125 °C Resolution 12-Bit Maximum Sampling Rate 20 MS/s Sample and Hold Input Stage 2 Vpp or 3 Vpp Input Signal Range Fully Differential Input Power Dissipation 380 mW Power Down Mode VDDA VDDA2 SVDDA SVDDD VDDD2 VDDD SWIB Bias Current Generation IB_EXT ONADC VBG ONREF VREFP REF. GEN. VREFN VCM VBYSHP VBYSHN VINP VINN Pipeline ADC S/H Digital Error Correction Output Register B11 B0 CTRSH EN8, EN16 LWJIT Timing Generation CLKOUT CLKIN GNDA Revision B, 08.09.02 GNDA2 SGNDA SGNDD GNDD2 GNDD Page 1 of 12 Datasheet : ADC1220 – C35 TECHNICAL DATA (Tjunction = –40 to 125 °C, VDDA = VDD = +3.0 V to +3.6 V, fclk = 20 MHz, VCM = VDDA/2, VREFP and VREFN or VBG as specified, unless otherwise specified) DC ACCURACY Symbol Parameter Resolution (No missing Code) DNL Differential Linearity Error Conditions Min 12 Typ 12 Max 12 Units Bit –0.9 ±0.5 +1 LSB INL Integral Linearity Error –2.0 ±0.5 +2.0 LSB OFF Offset Error –10 0 10 LSB GAINERR Gain Error +15 18 +50 LSB REFERENCE CHARACTERISTICS Symbol VBG Parameter ext. Bandgap Reference Voltage VCM Common Mode Voltage VREFP Pos. Reference Voltage VREFN Neg. Reference Voltage Conditions Op.Mode 1 Min Typ 1) 1.25 Max 2) 1.875 Units V 1.5 VDDA/2 1.8 V VCM+0.4VBG Op.Mode 4 V VCM-0.4VBG 1 VREF Difference between VREFP and VREFN Rbg ext. Bandgap Ref. Impedance Op.Mode 1 10 Ibg ext. Bandgap Ref. Input Current Op.Mode 1 48.0 Ccm Comm. Mode Impedance Rrefp Pos. Reference Impedance Crefp (For external VREF generation) Rrefn Neg. Reference Impedance Crefn (For external VREF generation) Op.Mode 4 Op.Mode 4 1 V 1) 1.5 2) V kΩ 3) 239.0 4) µA 100 pF 4.3 kΩ 30 pF 4.3 kΩ 30 pF ANALOG INPUT Symbol Vind Parameter Diff. Input Voltage Range, related to VCM Rin Input Impedance Conditions Cin Finmax 1) 2) Typ Max VREF 5) 100 Max. Input Signal Frequency pF 10 MHz For 2 Vpp input signal range. For 3 Vpp input signal range. VBG = 1.25 V and VDDA = 3.3 V 4) VBG = 1.875 V and VDDA = 3.3 V It is strongly recommended not to overdrive the inputs of the ADC1220. Revision B, 08.09.02 Units V MΩ 4.5 3) 5) Min 5) –VREF Page 2 of 12 Datasheet : ADC1220 – C35 AC ACCURACY (2 Vpp input signal range) Symbol THD Parameter Total Harmonic Distortion Conditions fin = 180 kHz Min Typ –83.00 Max Units dB THD Total Harmonic Distortion fin = 4.5 MHz –83.00 dB THD Total Harmonic Distortion fin = 9.5 MHz –81.50 dB SFDR Spurious Free Dynamic Range fin = 180 kHz 80.50 dB SFDR Spurious Free Dynamic Range fin = 4.5 MHz 80.00 dB SFDR Spurious Free Dynamic Range fin = 9.5 MHz 76.00 dB SNR Signal to Noise Ratio fin = 180 kHz 68.80 dB SNR Signal to Noise Ratio fin = 4.5 MHz 67.50 dB SNR Signal to Noise Ratio fin = 9.5 MHz 66.00 dB SINAD Signal to (Noise+Dist.) Ratio fin = 180 kHz 68.70 dB SINAD Signal to (Noise+Dist.) Ratio fin = 4.5 MHz 67.40 dB SINAD Signal to (Noise+Dist.) Ratio fin = 9.5 MHz 65.85 dB ENOB Effective Number of Bits fin = 180 kHz 11.10 Bit ENOB Effective Number of Bits fin = 4.5 MHz 10.90 Bit ENOB Effective Number of Bits fin = 9.5 MHz 10.65 Bit TT-IMD Two-Tone third order Intermodulation Distortion fin1 = 4 MHz fin2 = 4.5 MHz –80.00 dBc TT-SFDR Two-Tone Spurious Free Dynamic Range fin1 = 4 MHz 1) fin2 = 4.5 MHz 77.80 dBc FPBW Full Power Bandwidth 50 MHz 1) AC ACCURACY (3 Vpp input signal range) Symbol THD Parameter Total Harmonic Distortion Conditions fin = 180 kHz THD Total Harmonic Distortion fin = 4.5 MHz Min Typ –82.60 Max –78.90 Units dB dB THD Total Harmonic Distortion fin = 9.5 MHz –76.40 dB SFDR Spurious Free Dynamic Range fin = 180 kHz 82.40 dB SFDR Spurious Free Dynamic Range fin = 4.5 MHz 80.30 dB SFDR Spurious Free Dynamic Range fin = 9.5 MHz 76.60 dB SNR Signal to Noise Ratio fin = 180 kHz 70.40 dB SNR Signal to Noise Ratio fin = 4.5 MHz 68.50 dB SNR Signal to Noise Ratio fin = 9.5 MHz 66.50 dB SINAD Signal to (Noise+Dist.) Ratio fin = 180 kHz 70.10 dB SINAD Signal to (Noise+Dist.) Ratio fin = 4.5 MHz 68.10 dB SINAD Signal to (Noise+Dist.) Ratio fin = 9.5 MHz 66.00 dB ENOB Effective Number of Bits fin = 180 kHz 11.35 Bit ENOB Effective Number of Bits fin = 4.5 MHz 11.00 Bit ENOB Effective Number of Bits fin = 9.5 MHz 10.67 Bit 1) TT-IMD Two-Tone third order Intermodulation Distortion fin1 = 4 MHz fin2 =4.5 MHz –75.50 dBc TT-SFDR Two-Tone Spurious Free Dynamic Range fin1 = 4 MHz 1) fin2 = 4.5 MHz 75.50 dBc FPBW Full Power Bandwidth 50 MHz 1) Both signals, fin1 and fin2, have an amplitude of –7 dBc full scale Revision B, 08.09.02 Page 3 of 12 Datasheet : ADC1220 – C35 DIGITAL INPUTS AND OUTPUTS Symbol VDD VSS VIL VIH VOL VOH B[11:0] Parameter Pos. digital Supply Voltage Neg. digital Supply Voltage Digital Input Level Conditions VDD = VDDA GND = GNDA Min 3.0 0 GND 0.7 VDD Digital Output Level Output Code Typ 3.3 0 Max 3.6 0 0.3 VDD VDD Units V V V V V V HEX HEX Typ 3.3 0 Max 3.6 0 Units V V GND VDD 000 FFF Vind = –VREF Vind = VREF POWER REQUIREMENTS Symbol VDDA VSSA Parameter Pos. analog Supply Voltage Neg. analog Supply Voltage Conditions VDD = VDDA GND = GNDA 1) Supply Current Digital Supply Current Analog Supply Power Consumption Total Power Dissipation Powerup Mode Op. Mode 1 Op. Mode 1 Op. Mode 1 Op. Mode 1 3.4 111.7 380 380 6.8 223.4 760 760 mA mA mW mW IDDD IDDA 2) Psup 2) IREF 2) 2) Supply Current Digital Supply Current Analog Supply Power Consumption Reference Current Op. Mode 4 Op. Mode 4 Op. Mode 4 Op. Mode 4 3.4 92 315 1 6.8 184 630 2 mA mA mW Pdiss_tot 2) Total Power Dissipation Powerup Mode Op. Mode 4 318 636 mA mW Power Consumption Power Down Mode Op. Mode 0 180 360 µW Typ Max 20 Units MHz IDDD IDDA 1) Psup 1) Pdiss_tot 1) Pdiss_pd 3) Min 3.0 0 TIMING CHARACTERISTICS Symbol fclk Parameter CLK Frequency 1/Ts Sampling Rate Jclk Clock Jitter Tsd Clock falling edge to sampling instant delay Clock falling edge to data out delay Input Clock falling edge to output Clock delay Clock duty cycle Data Latency 4) Power Up Delay Tod Tclkd 1) 2) 3) 4) Conditions Min 1 fclk MS/sec 4 ⋅ 10 −5 fin 47.5 1.6 nsec 10.5 9.5 nsec nsec 50 5 40 52.5 In Op. Mode 1 (internal references) with VREF = 1 V at 20 MHz clock frequency. In Op. Mode 4 (external references) with VREF = 1 V at 20 MHz clock frequency. After 10 µs power down. The digital output codes of the ADC are not valid during the first few clock cycles after a power up. Revision B, 08.09.02 psec Page 4 of 12 % CLK cycle CLK cycle Datasheet : ADC1220 – C35 TYPICAL PERFORMANCE CHARACTERISTICS INL [LSB] DNL [LSB] (T = 25 °C, VDDA = VDD = +3.3 V, fclk = 20 MHz, VBG = 1.25 V, VCM = VDDA/2, Op. Mode 1, unless otherwise specified) Digital Code Digital Code FFT [dBc] INL @ 180 kHz FFT [dBc] DNL @ 180 kHz Input Signal Frequency [Hz] Spectrum @ 9.5 MHz 1) 2) FFT [dBc] ENOB [Bit] Spectrum @ 180 kHz Input Signal Frequency [Hz] 1) Input Signal Frequency [Hz] Two-Tone IMD @ 4.0 MHz and 4.5 MHz 1) 3) 1) The spectrum consists of 16384 pins. 2) Measured with a 9.5 MHz band-pass filter 3) Measured with a 4.5 MHz low-pass filter. Revision B, 08.09.02 Input Signal Frequency [Hz] ENOB vs. Input Signal Frequency Page 5 of 12 Datasheet : ADC1220 – C35 SYMBOL PINLIST Pin VINP Function Pos. Input Voltage I/O I Type Analog VINN Neg. Input Voltage I Analog VBYSHP S&H Bypass Pos. Input Voltage I Analog VBYSHN S&H Bypass Neg. Input Voltage I Analog VCM Input for Common Mode Voltage I Analog VREFP Output or bypass of Internal Pos. Reference Voltage I/O Analog VREFN Output or bypass of Internal Neg. Reference Voltage I/O Analog VBG Input for Bandgap Reference Voltage I Analog IB_EXT Output for monitoring internal bias current generation when SWIB = "1" or input for I/O Analog injection of external bias current (10µA) when SWIB = "0" THEORY OF OPERATION CLKIN Clock Input I Digital CLKOUT Clock Output O Digital B11 to B0 Digital Output Bits (B11 = MSB, B0 = LSB) O Digital ONADC Power Down Input for ADC (ONADC = 1 ⇔ normal operation) I Digital ONREF Power Down Input for Reference Generator I Digital I Digital (ONREF = 1 ⇔ normal operation) CTRSH S&H Power Down and Bypass SWIB Bias current control pin; if High, the ADC uses internal bias current; otherwise it enables the external current input. I Digital LWJIT Jitter Reduction I Digital I Digital I Digital Analog pos. Power Supply I Supply GNDA Analog neg. Power Supply I Supply VDDA2 Secondary pos. Analog Power Supply I Supply VGNDA2 Secondary neg. Analog Power Supply I Supply SVDDA Substrate pos. Analog Power Supply I Supply SGNDA Substrate neg. Analog Power Supply I Supply VDDD Digital pos. Power Supply I Supply GNDD Digital neg. Power Supply I Supply VDDD2 Secondary Digital pos. Power Supply I Supply (CTRSH = 0 ⇔ normal operation) The ADC1220 is a low-power 12-bit ADC capable of sampling at 20 MS/s. It uses a fully differential pipelined architecture with a first 3.5-bit stage, followed by seven 1.5-bit per stage and digital error correction to achieve improved linearity performance. A dedicated wide-band input sampleand-hold amplifier (S/H) is built-in to provide lowjitter, sub-sampling capability with inherent frequency down-conversion and a fully differential input. The raw digital words are synchronized by a chain of delay stages and overlapped and processed by the digital error correction logic to produce the 12-bit digital output code. Revision B, 08.09.02 (LWJIT = 0 ⇔ normal operation) EN8 Enables Decimation factor of 8 (EN8 = 0 ⇔ normal operation) EN16 Enables Decimation factor of 16 (EN16 = 0 ⇔ normal operation) VDDA GNDD2 Secondary Digital neg. Power Supply I Supply SVDDD Substrate Digital pos. Power Supply I Supply SGNDD Substrate Digital neg. Power Supply I Supply Page 6 of 12 Datasheet : ADC1220 – C35 OPERATING MODES The modes of operation are summarized in the table bellow, and described in detail as follows. Configuration Mode 0 Objective Complete Power Down ONADC 0 SWIB X ONREF X CTRSH X EN8 X EN16 X LWJIT X 1 Normal conversion 1 1 1 0 0 0 0 2 Normal conversion with external VREF 1 1 0 0 0 0 0 3 Normal conversion with external Ibias 1 0 1 0 0 0 0 4 Normal conversion with external VREF and Ibias 1 0 0 0 0 0 0 5 Modes 1 to 4 with S&H bypass 1 X X 1 0 0 0 6 Modes 1 to 5 with decimation by a factor of 8 1 X X X 1 0 0 7 Modes 1 to 5 with decimation by a factor of 16 1 X X X 0 1 0 8 Modes 1 to 7 with clock jitter reduction 1 X X X X X 1 Mode 0 - Power Down In this mode all the circuitry is in power-down. The power dissipation is reduced to a minimum value. Mode 1 - Normal Conversion This is the normal conversion mode of the converter. The external bandgap reference voltage VBG determines the values of the reference voltages VREFP and VREFN. The bias current is internally generated and the reference voltages are internally buffered. The common mode voltage VCM must be supplied externally. Mode 2 through Mode 5 - Conversion Mode with different Bypassing options These conversion modes allow different bypassing options for the bias current generator, for the buffer of the reference voltage and the S&H. In case of S&H bypass the input signal must be fully differential because of the pipeline fully differential architecture. Modes 6 and 7 - Conversion Mode with different Decimation factors These conversion modes allow output data decimation factors of 8 and 16 with any of the previous modes, in order to reduce the digital Output Pads switching noise. Mode 8 - Conversion Mode with Clock jitter reduction This conversion mode allows the test of an internal clock with reduced jitter with any of the previous modes. Revision B, 08.09.02 Page 7 of 12 Datasheet : ADC1220 – C35 POWER SUPPLIES The converter requires a single +3.3 V power supply. The supplies for analog and digital are separated. For maximum noise immunity it is recommended to wire them on chip to separated pins, especially when the block is embedded in a large digital circuit. The supplies may then be connected together on PC-board level. The proper use of blocking capacitors in the application is important! REFERENCE VOLTAGES If ONREF is set to high the converter needs an external bandgap reference VBG that defines the dynamic range of the input signal as described in the technical data section. If ONREF is set to low the external voltage references VREFP and VREFN define the dynamic range of the input signal. The proper use of blocking capacitors in the application is important! SYSTEM REQUIREMENTS The ADC is sensitive to ground noise. So all parts of the whole system except the ADC should be quiet during the conversions. To minimize ground noise coming from digital output pads the connection of a series resistor should be used to limit the switching current. In the test circuit a series resistor of 1 kΩ is used for the digital output bus. CONVERSION MODE Fully Differential Mode It is recommended to use the ADC1220 as a Fully Differential Converter. Both inputs VINP and VINN should be balanced around VCM. CODE TABLES The digital representation of the data bus in both conversion modes is described in the following table. VREF = VREFP − VREFN , 1LSB = VREFP − VREFN 4096 Offset Binary Revision B, 08.09.02 Output Code 1111 1111 1111 Input Voltage: VIN-VINB 2047 LSB … VREF 1111 1111 1110 2046 LSB … 2047 LSB … … 1000 0000 0001 1 LSB … 2 LSB 1000 0000 0000 0 … 1 LSB 0111 1111 1111 –1 LSB … 0 0111 1111 1110 –2 LSB … –1 LSB … … 0000 0000 0001 –2047 LSB … –2046 LSB 0000 0000 0000 –VREF … –2047 LSB Page 8 of 12 Datasheet : ADC1220 – C35 FUNCTIONAL BLOCK DIAGRAM In x0 S/H x1 MDAC 1 x2 MDAC 2 FLASH 1 x3 MDAC 3 FLASH 2 4b FLASH 3 2b 2b x4 x5 MDAC 4 FLASH 4 2b MDAC 5 FLASH 5 2b x6 MDAC 6 x7 MDAC 7 FLASH 6 x8 MDAC 8 FLASH 7 2b 2b FLASH 8 2b x9 FLASH 9 2b D1 D2 Clk D1 D3 D2 D1 D4 D3 D2 D1 D5 D4 D3 D2 D1 D6 D5 D4 D3 D2 D1 D7 D6 D5 D4 D3 D2 D1 D8 D7 D6 D5 D4 D3 D2 D1 12b Out Digital Error Correction Logic TIMING DIAGRAM OF ADC1220 The sampling rate of the ADC1220 is defined by the frequency of the CLK signal. The input signal voltage of the ADC is sampled in the falling edge of CLK. As the conversion stages operate in a staggered fashion in alternate phases of CLK, the duty-cycle of this signal must be 50%. The results are latched in the output register on the falling edge of CLK, with a latency of 5 CLK periods. The conversion timing is shown in Diagram 1. Cycle 1 2 5 6 CLK Stage 0 (S&H) Stage 1 Sample of X0(1) Hold of X1(1) Sample of X0(2) Hold of X1(2) Sample of X0(8) Hold of X1(8) Sample of X0(9) Hold of X1(9) Sample & Quant. of X1(1) Amplification of X2(1) Sample & Quant. of X1(2) Amplification of X2(7) Sample & Quant. of X1(8) Amplification of X2(8) Sample & Quant. of X1(9) Sample & Quant. of X2(1) Amplification of X3(1) Amplification of X3(7) Sample & Quant. of X2(8) Amplification of X3(8) Stage 2 Sample & Quant. of X2(7) Sample & Quant. of X9(1) Stage 9 Sample & Quant. of X9(2) Digital Output b[X(1)] Tsd Ts Tod Latency of 5 CLK cycles Diagram 1: Timing of the pipelining operation Revision B, 08.09.02 Page 9 of 12 Datasheet : ADC1220 – C35 The Diagram 2 presents the timing of the CLKOUT signal in normal operation (mode 0) and with decimation factors of 8 (mode 5) and 16 (mode 6). In all test modes that do not have a decimation factor specified, the CLKOUT signal is identical to that in normal operation mode. Timing Diagram 2: Timing of the CLKOUT signal operation in normal operation (a) and with decimation factor of 8 (b) and of 16 (c) Revision B, 08.09.02 Page 10 of 12 Datasheet : ADC1220 – C35 TYPICAL APPLICATION APPLICATION The ADC1220 is targeted for general purpose sampling ADC functions where high-speed conversion rates and medium precision are of critical importance. ! ! ! ! ! 1)2)3)4) +3.3V CPK1 10uF 2) 100nF 2) 100pF +3.3V VDDA 2) Video Imaging Data acquisition systems High-speed data transmission Communications VDDA VDDD VDDD CPK1 CPK1 VSSA VSSD B<11:0> 4) 2) CPK2 3.3uF 100nF 2) 100pF VIN 2) VDDD 1.65V 4) CPK2 200pF 1) 200pF 1.25V 1) 3) CPK2 20MHz VSSA VSSD GROUND Configuration: Op. Mode 1 at 20 MS/sec, 2 Vpp input signal range +3.3V CPK2 2) 3.3uF 100nF 2) 100pF 2) CPK1 10uF 2) 100nF 2) 100pF +3.3V VDDA 2) CPK1 VSSA VDDD VDDA VDDD CPK1 VSSD 10uA CPK2 B<11:0> 4) VIN VDDD 2.4V 3) CPK2 0.9V 3) CPK2 1.65V 4) CPK2 200pF 1) 200pF 1) CPK2 20MHz VSSA VSSD GROUND Configuration: Op. Mode 4 at 20 MS/sec, 3 Vpp input signal range 1) 2) 3) 4) The value of the capacitor depends on the input frequency. For SMD capacitors use the type NPO and for normal capacitors use the type MKT for best performance. For SMD capacitors use the type NPO and for normal capacitors use the type MKT for best performance. The accuracy of both reference voltages must be higher than the retion of the ADC. In typical applications both voltages are filtered by a second order low pass filter (fc = 5 Hz) and buffered with an AD711. The accuracy of both input voltages must be higher than the resolution of the ADC. In typical applications both voltages are filtered. For low inncies the input voltages are buffered with a AD8138 and for high frequencies a transformer is used. Revision B, 08.09.02 Page 11 of 12 Datasheet : ADC1220 – C35 Contact Copyright austriamicrosystems AG A 8141 Schloss Premstätten, Austria T. +43 (0) 3136 500 5333 F. +43 (0) 3136 500 5755 [email protected] Copyright © 2002 austriamicrosystems. Trademarks registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. To the best of its knowledge, austriamicrosystems asserts that the information contained in this publication is accurate and correct. Revision B, 08.09.02 Page 12 of 12