V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E VARISCITE LTD. VAR-SOM-AM43 v1.1 Datasheet Texas Instruments Sitara AM437x -based System-on-Module 1 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E VA R I SC IT E LT D. VAR-SOM-AM43 Datasheet © 2015 Variscite Ltd. All Rights Reserved. No part of this document may be photocopied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means whether, electronic, mechanical, or otherwise without the prior written permission of Variscite Ltd. No warranty of accuracy is given concerning the contents of the information contained in this publication. To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by Variscite Ltd., its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document. Variscite Ltd. reserves the right to change details in this publication without notice. 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Variscite Ltd. 4 Hamelacha Street Lod P.O.B 1121 Airport City, 70100 ISRAEL Tel: +972 (9) 9562910 Fax: +972 (9) 9589477 2 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E Document Revision History Revision Date Notes 1.0 20/01/2015 Initial 3 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E Table of Contents Document Revision History ......................................................................................................3 About this Document.......................................................................................................7 Overview .............................................................................................................................. 7 VAR-SOM-AM43 Features Summary.................................................................................... 7 VAR-SOM-AM43 Block Diagram ........................................................................................... 9 Main Hardware Components ......................................................................................... 10 TEXAS INSTRUMENTS AM437x ARM® Cortex™-A9 ............................................................ 10 Overview ............................................................................................................................ 10 Functional Block Diagram................................................................................................... 17 MEMORY ............................................................................................................................ 18 RAM .................................................................................................................................... 18 Non-volatile Storage Memory ............................................................................................ 18 NAND Flash......................................................................................................................... 18 eMMC ................................................................................................................................. 18 EEPROM.............................................................................................................................. 18 Ethernet PHY AR8033-AL1A-R ............................................................................................ 18 Audio codec via the TLV320AIC3106.................................................................................. 19 Wi-Fi & Bluetooth............................................................................................................... 19 TPS65218 PMIC .................................................................................................................. 20 External Connectors ...................................................................................................... 22 SoM Connector Pin-out ...................................................................................................... 23 SO-DIMM 204 Pin Mux ....................................................................................................... 29 Interface Details ............................................................................................................ 51 Overview ............................................................................................................................ 51 Display Interfaces ............................................................................................................... 51 Ethernet.............................................................................................................................. 53 On board 1G PHY................................................................................................................ 54 Optional ROUTE OUT RGMII interface. .............................................................................. 55 USB 2.0 ............................................................................................................................... 56 USB 2.0 HOST ..................................................................................................................... 56 USB 2.0 On-the-Go ............................................................................................................. 56 MMC/SD/SDIO ................................................................................................................... 57 4 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E MMC0 Signals ..................................................................................................................... 57 MMC1 Signals ..................................................................................................................... 57 MMC2 Signals ..................................................................................................................... 58 Audio .................................................................................................................................. 59 TLV320AIC3106 Audio codec ............................................................................................. 59 MCASP0 (Multichannel Audio Serial Port) ......................................................................... 59 Camera ............................................................................................................................... 60 CPI Camera interface #0. .................................................................................................... 60 CPI Camera interface #1. .................................................................................................... 61 UART Interfaces.................................................................................................................. 61 UART0 Interface ................................................................................................................. 62 UART1 Interface ................................................................................................................. 62 UART2 Interface ................................................................................................................. 62 UART3 Interface ................................................................................................................. 63 UART5 Interface ................................................................................................................. 63 SPI ....................................................................................................................................... 64 QSPI .................................................................................................................................... 65 I2C....................................................................................................................................... 66 CAN ..................................................................................................................................... 67 Analog to Digital Convertor (ADC0) ................................................................................... 68 Touch Screen ...................................................................................................................... 68 Analog Inputs ..................................................................................................................... 69 General Purpose I/O........................................................................................................... 70 PWM0................................................................................................................................. 71 General System Control ..................................................................................................... 72 Boot Options ...................................................................................................................... 72 System Control ................................................................................................................... 72 PRU-ICSS ............................................................................................................................. 73 PRU-ICSS0 Interface ........................................................................................................... 73 PRU-ICSS1 Interface ........................................................................................................... 75 JTAG .................................................................................................................................... 79 Wi-Fi and Bluetooth ........................................................................................................... 79 Power ................................................................................................................................. 80 Power Supply pins .............................................................................................................. 80 5 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E GND pins............................................................................................................................. 80 Absolute Maximum Characteristics ................................................................................ 80 Operating Characteristics............................................................................................... 81 Normal Operational Conditions ......................................................................................... 81 Power Consumption ........................................................................................................... 81 DC Electrical Characteristics ............................................................................................... 81 Environmental Specifications ......................................................................................... 83 Mechanical Specifications .............................................................................................. 84 Drawing .............................................................................................................................. 84 SoM Fastening .................................................................................................................... 85 Literature ...................................................................................................................... 85 RoHS compliance ........................................................................................................... 85 Ordering Information .................................................................................................... 86 Warranty Terms ............................................................................................................ 86 Disclaimer of Warranty ...................................................................................................... 86 Limitation on Liability ......................................................................................................... 86 About Variscite.............................................................................................................. 87 Contact Information ........................................................................................................... 87 6 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E About this Document Overview The VAR-SOM-AM43 is a highly integrated cost-effective System-on-Module that perfectly fits various embedded and industrial products and segment. It is based on AM437x 1GHz ARM® Cortex™-A9 multipurpose processor from TEXAS INSTRUMENTS Sitara™ family. The VAR-SOM-AM43 provides an ideal building block for simple integration with a wide range of products in target markets requiring rich connectivity in a compact, cost effective SoM with low power consumption. Variscite also provides a complete hardware and software development kit (DVK) for the SoM in the form of a carrier board with 204-pin edge connector for the VAR-SOM-AM43 and an optional TFT display and touch panel. The carrier board of the VAR-SOM-AM43 is ideal not only as reference for the customer to develop its own custom board but also as a cost effective solution for production. Details of this carrier board and development kit can be found inside the VARAM43CustomBoard datasheet and the related documentation inside Variscite website: www.variscite.com Supporting products: VAR-AM43CustomBoard – evaluation board Carrier -Board, compatible with VAR-SOM-AM43 Schematics O.S support Linux (Yocto) Contact Variscite support services for further information: mail to: [email protected]. VAR-SOM-AM43 Features Summary High performance up to 1000-MHz ARM® Cortex™-A9 32-Bit RISC Microprocessor NEON™ SIMD Coprocessor and Vector Floating Point (VFPv3) Coprocessor SGX530 Graphics Engine 4 x 200MHz 32-bits RISC co-processors programmable real-time unit (PRU) Up to 1 GB DDR3 RAM Up to 32GB eMMC storage Up to 512MB NAND Flash for storage memory / boot 7 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E LCD Display Up to 1400x1050 Parallel, 24-Bit RGB interface Capacitive touch panel and 4/5-wire resistive touch panel interface On-board 10/100/1000 Mbps Ethernet PHY Second 10/100/1000 Mbps Ethernet RGMII Interface Certified WLAN (802.11 a/b/g/n) module with optional MIMO Bluetooth 4.0/BLE USB: – 1 x USB 2.0 host with integrated PHY – 1 x USB 2.0 OTG with integrated PHY 2 x CAN bus Serial interfaces (4xSPI, 3xI2C, 5xUART, HDQ/1-Wire, QSPI) Camera input, 12bit Audio: – 1 x stereo line-in – 1 x stereo line-out – 1 x stereo Digital Microphone-in – 1 x stereo Analog Microphone-in – Multichannel Audio Serial Port (McASP) 8 x ADC – inputs Backlight PWM Single 3.3 V power supply 67.6 mm x 38.6 mm x 3 mm DDR3 SODIMM 204pins footprint 8 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E VAR-SOM-AM43 Block Diagram SO-DIMM 204 Pin VAR-SOM-AM43 eMMC MMC1 SLC NAND Flash NANDF DDR3 X2 DDR EEPROM POWER In/ VIO Out 24-bit LCD 24-bit LCD ADC0/4 wire Touch ADC0 (8ch) I2C0 eCAP0 Backlight PWM Parallel Cam 1 Parallel Camera HOST USB HOST OTG JTAG Connector JTAG Wi-Fi + BT SD/MMC2 MCASP0 UART3 EMAC0 AM437x RGMII2 McASP0 D. Audio CAN0/1 I2C0 POWER In/ VIO Out AUDIO CODEC DMIC Analog Mic Line In Line Out Audio 2x CAN BUS GPIO GPIO SD/MMC0/1/2 Up to 3x MMC SPI0/1/2/3/4 Up to 5xSPI UART0/1/2/3/5 Up to 5x UART I2C0/1/2 9 G.Ethernet EMAC1 McASP1 PMIC USB OTG 10/100/1000 Mbps Ethernet PHY Up to 3xI2C V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E Main Hardware Components This section summarizes the main hardware building blocks of the VAR-SOM-AM43 TEXAS INSTRUMENTS AM437x ARM® Cortex™-A9 Overview The AM437x microprocessors based on the ARM Cortex-A9 are enhanced with image, graphics processing, peripherals and industrial interface options. The AM437x microprocessor contains the following subsystems, controller and interfaces: TEXAS INSTRUMENTS AM437x ARM® Cortex™-A9 Highlights - Up to 1000-MHz ARM® Cortex™-A9 32-Bit RISC Microprocessor NEON™ SIMD Coprocessor and Vector Floating Point (VFPv3) Coprocessor 32KB of Both L1 Instruction and Data Cache 256KB of L2 Cache or L3 RAM - 32-Bit LPDDR2, DDR3, and DDR3L Support - General-Purpose Memory Support (NAND, NOR, SRAM) Supporting Up to 16-bit ECC - SGX530 Graphics Engine - Display Subsystem - Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) - Real-Time Clock (RTC) - Up to Two USB 2.0 High-Speed Dual-Role (Host or OTG) Ports with integrated PHY - 10, 100, and 1000 Ethernet Switch Supporting Up to Two Ports - Serial Interfaces: Two Controller Area Network (CAN) Ports Six UARTs, Two McASPs, Five McSPI, Three I2C Ports, One QSPI and One HDQ or 1-Wire - Security Crypto Hardware Accelerators (AES, SHA, RNG, DES and 3DES) Secure Boot - Two 12-Bit Successive Approximation Register (SAR) ADCs - Up to Three 32-Bit Enhanced Capture Modules (eCAP) - Up to Three Enhanced Quadrature Encoder Pulse Modules (eQEP) - Up to Six Enhanced High-Resolution PWM Modules (eHRPWM) 10 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E MPU Subsystem - Up to 1000-MHz ARM Cortex-A9 32-Bit RISC Microprocessor - 32KB of Both L1 Instruction and Data Cache - 256KB of L2 Cache (Option to Configure as L3 RAM) - 256KB of On-Chip Boot ROM - 64KB On-Chip RAM - Secure Control Module (SCM) - Emulation and Debug JTAG Embedded Trace Buffer Interrupt Controller On-Chip Memory (Shared L3 RAM) - 256KB of General Purpose On-Chip Memory Controller (OCMC) RAM - Accessible to All Masters - Supports Retention for Fast Wakeup - Up to 512KB of Total Internal RAM (256KB of ARM Memory Configured as L3 RAM + 256KB of OCMC RAM) External Memory Interfaces (EMIF) - DDR Controllers: LPDDR2: 266-MHz Clock (LPDDR2-533 Data Rate) DDR3 and DDR3L: 400-MHz Clock (DDR 800 Data Rate) 32-Bit Data Bus 2GB of Total Addressable Space Supports One x32, Two x16, or Four x8 Memory Device Configurations General-Purpose Memory Controller (GPMC) - Flexible 8- and 16-Bit Asynchronous Memory Interface with Up to Seven Chip Selects (NAND, NOR, Muxed-NOR, and SRAM) - Uses BCH Code to Support 4-, 8-, or 16-Bit ECC - Uses Hamming Code to Support 1-Bit ECC Error Locator Module (ELM) - Used with the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm - Supports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH Algorithms Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) - Supports Protocols such as EtherCAT ®, PROFIBUS, PROFINET, and EtherNet/IP™, EnDat 2.2, and More - Two Programmable Real-Time Units (PRUs) Subsystems Each core is a 32-Bit Load and Store RISC Processor Capable of Running at 200 MHz 11 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E 12KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Instruction RAM with Single-Error Detection (Parity) 8KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Data RAM with Single-Error Detection (Parity) Single-Cycle 32-Bit Multiplier with 64-Bit Accumulator Enhanced GPIO Module Provides Shift-In and Shift-Out Support and Parallel Latch on External Signal - 12KB (PRU-ICSS1 only) of Shared RAM with Single-Error Detection (Parity) - Three 120-Byte Register Banks Accessible by Each PRU - Interrupt Controller Module (INTC) for Handling System Input Events - Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS - Peripherals Inside the PRU-ICSS One UART Port with Flow Control Pins, Supports Up to 12 Mbps One Enhanced Capture (eCAP) Module Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT One MDIO Port Industrial Communication is Supported by Two PRU-ICSS Subsystems Power Reset and Clock Management (PRCM) Module - Controls the Entry and Exit of Deep-Sleep Modes - Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing - Clocks Integrated High-Frequency Oscillator Used to Generate a Reference Clock (19.2, 24, 25, and 26 MHz) for Various System and Peripheral Clocks Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB, and Peripherals (MMC and SD, UART, SPI, I2C), L3, L4, Ethernet, GFX (SGX530), and LCD Pixel Clock) - Power Two Non-Switchable Power Domains (RTC and Wake-Up Logic (WAKE-UP)) Three Switchable Power Domains (MPU Subsystem, SGX530 (GFX), Peripherals and Infrastructure (PER)) Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation and Performance (Adaptive Voltage Scaling (AVS)) Dynamic Voltage Frequency Scaling (DVFS) Real-Time Clock (RTC) - Real-Time Date (Day, Month, Year, and Day of Week) and Time (Hours, Minutes, and Seconds) Information - Internal 32.768-kHz Oscillator, RTC Logic, and 1.1-V Internal LDO - Independent Power-On-Reset (RTC_PWRONRSTn) Input 12 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E - Dedicated Input Pin (RTC_WAKEUP) for External Wake Events - Programmable Alarm Can Generate Internal Interrupts to the PRCM for Wake Up or Cortex- A9 for Event Notification - Programmable Alarm Can Be Used with External Output (RTC_PMIC_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains Peripherals - Up to Two USB 2.0 High-Speed OTG Ports with Integrated PHY - Up to Two Industrial Gigabit Ethernet MACs (10, 100, and 1000 Mbps) Integrated Switch Each MAC Supports MII, RMII, and RGMII and MDIO Interfaces Ethernet MACs and Switch Can Operate Independent of Other Functions IEEE 1588v2 Precision Time Protocol (PTP) - Up to Two Controller-Area Network (CAN) Ports Supports CAN Version 2 Parts A and B - Up to Two Multichannel Audio Serial Ports (McASP) Transmit and Receive Clocks Up to 50 MHz Up to Four Serial Data Pins Per McASP Port with Independent TX and RX Clocks Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats) FIFO Buffers for Transmit and Receive (256 Bytes) - Up to Six UARTs All UARTs Support IrDA and CIR Modes All UARTs Support RTS and CTS Flow Control UART1 Supports Full Modem Control - Up to Five Master and Slave McSPI Serial Interfaces McSPI0-McSPI2 Supports Up to Four Chip Selects McSPI3-McSPI4 Supports Up to Two Chip Selects - Up to 48 MHz One Quad-SPI Supports eXecute In Place (XIP) from Serial NOR FLASH - One Dallas 1-Wire® and HDQ Serial Interface - Up to Three MMC, SD, and SDIO Ports 1-, 4-, and 8-Bit MMC, SD, and SDIO Modes 1.8- or 3.3-V Operation on All Ports Up to 48-MHz Clock Supports Card Detect and Write Protect Complies with MMC4.3 and SD and SDIO 2.0 Specifications 13 V A R - S O M - A M 4 3 - S Y S T E M O N M O D U L E Up to Three I2C Master and Slave Interfaces Standard Mode (Up to 100 kHz) Fast Mode (Up to 400 kHz) - Up to Six Banks of General-Purpose I/O (GPIO) 32 GPIOs per Bank (Multiplexed with Other Functional Pins) GPIOs Can be Used as Interrupt Inputs (Up to Two Interrupt Inputs per Bank) - Up to Three External DMA Event Inputs That Can Also be Used as Interrupt Inputs - Twelve 32-Bit General-Purpose Timers DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks DMTIMER4–DMTIMER7 are Pinned Out - One Public Watchdog Timer - One Free Running High Resolution 32-kHz Counter (synctimer32K) - SGX530 3D Graphics Engine Tile-Based Architecture Delivering Up to 20M Poly/sec Universal Scalable Shader Engine is a Multi- Threaded Engine Incorporating Pixel and Vertex Shader Functionality Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0 Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0, and OpenVG 1.0 Fine-Grained Task Switching, Load Balancing, and Power Management Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction Programmable High-Quality Image Anti- Aliasing Fully Virtualized Memory Addressing for OS Operation in a Unified Memory Architecture - Display Subsystem Display Modes - Programmable Pixel Memory Formats (Palletized: 1-, 2-, 4-, and 8-Bit Per Pixel; RGB 16- and 24-Bit Per Pixel; and YUV 4:2:2) - 256 x 24-Bit Entries Palette in RGB - Up to 2048 x 2048 Resolution Display Support - Four Types of Displays Are Supported: Passive and Active Colors; Passive and Active Monochromes - 4- and 8-Bit Monochrome Passive Panel Interface Support (15 Grayscale Levels Supported Using Dithering Block) - RGB 8-Bit Color Passive Panel Interface Support (3,375 Colors Supported for Color Panel Using Dithering Block) - RGB 12-, 16-, 18-, and 24-Bit Active Panel Interface Support (Replicated or Dithered Encoded Pixel Values) - Remote Frame Buffer (Embedded in the LCD Panel) Support through the RFBI Module 14 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E - Partial Refresh of the Remote Frame Buffer through the RFBI Module - Partial Display - Multiple Cycles Output Format on 8-, 9-, 12-, and 16-Bit Interface (TDM) Signal Processing - - Overlay and Windowing Support for One Graphics Layer (RGB or CLUT) and Two Video Layers (YUV4:2:2, RGB16, and RGB24) - RGB 24-bit Support on the Display Interface, Optionally Dithered to RGB 18-Bit Pixel Output Plus 6-Bit Frame Rate Control (Spatial and Temporal) - Transparency Color Key (Source and Destination) - Synchronized Buffer Update - Gamma Curve Support - Multiple-Buffer Support - Cropping Support - Color Phase Rotation Two 12-Bit Successive Approximation Register (SAR) ADCs (ADC0, ADC1) 867K Samples Per Second Input Can Be Selected from Any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch ADC0 Can Be Configured to Operate as a 4-, 5-, or 8-Wire Resistive Touch Screen Controller (TSC) - Up to Three 32-Bit Enhanced Capture Modules (eCAP) Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs - Up to Six Enhanced High-Resolution PWM Modules (eHRPWM) Dedicated 16-Bit Time-Base Counter with Time and Frequency Controls Configurable as Six Single-Ended, Six Dual- Edge Symmetric, or Three Dual-Edge Asymmetric Outputs Up to Three 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules Device Identification - Factory Programmable Electrical Fuse Farm (FuseFarm) Production ID Device Part Number (Unique JTAG ID) Device Revision (Readable by Host ARM) Feature Identification Debug Interface Support - JTAG and cJTAG for ARM (Cortex-A9 and PRCM) and PRU-ICSS Debug - Supports Real-Time Trace Pins (for Cortex-A9) - 64KB Embedded Trace Buffer (ETB) - Supports Device Boundary Scan 15 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E Supports IEEE 1500 DMA - On-Chip Enhanced DMA Controller (EDMA) Has Three Third-Party Transfer Controllers (TPTC) and One Third-Party Channel Controller (TPCC), Which Supports Up to 64 Programmable Logical Channels and Eight QDMA Channels - EDMA is Used for: Transfers to and from On-Chip Memories Transfers to and from External Storage (EMIF, General-Purpose Memory Controller, and Slave Peripherals) Inter-Processor Communication (IPC) - Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between the Cortex-A9, PRCM, and PRU-ICSS Boot Modes Boot Mode is Selected via Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin Camera - Dual Port 8- and 10-Bit BT656 Interface - Dual Port 8- and 10-Bit Including External Syncs - Single Port 12-Bit - YUV422/RGB422 and BT656 Input Format - RAW Format - Pixel Clock Rate Up to 75 MHz Package - 491-pin BGA Package (17x17 mm) (ZDN Suffix), 0.65-mm Ball Pitch with Via Channel Array Technology to Enable Low-Cost Routing 16 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E Functional Block Diagram 17 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E MEMORY RAM The VAR-SOM-AM43 is available with up to 8Gbit of DDR3 memory. Non-volatile Storage Memory NAND Flash The VAR-SOM-AM43 is available with up to 512MB (4Gbit) of SLC NAND FLASH memory. The NAND flash is used for flash disk purposes, O.S. run-time-image and the bootloader (boot from NAND). First block (block address 00h) of the memory device is guaranteed to be valid without ECC (up to 1,000 PROGRAM/ERASE cycles). eMMC The VAR-SOM-AM43 is available with up to Up to 32GB of storage. EEPROM The VAR-SOM-AM43 is available with a 4KB, I2C EEPROM (I2C0) for future revisions. Ethernet PHY AR8033-AL1A-R On-board, Atheros AR8033-AL1A-R, is a single 10/100/1000 BASE-T IEEE 802.3 compliant Ethernet physical layer transceiver. Features: • 10/100/1000 BASE-T IEEE 802.3 compliant • Supports 1000 BASE-T PCS and auto-negotiation with next page support • Supports RGMII and/or SGMII interfaces to MAC devices • Supports Fiber and Copper combo mode when MAC interface works in RGMII mode • Supports additional IEEE 1000 BASE-X and 100 BASE-FX with Integrated SerDes • RGMII timing modes support internal delay and external delay on Rx path • Supports Atheros Green ETHOS® power saving modes with internal automatic DSP power saving scheme • Supports IEEE 802.3az (Energy Efficient Ethernet) • Supports SmartEEE which allows MAC/ SoC devices without 802.3az support to function as the complete 802.3az system • Supports Wake-on-LAN (WoL) to detect magic packet and notify the sleeping system to wake up • Fully integrated digital adaptive equalizers, echo cancellers, and Near End Crosstalk (NEXT) cancellers • Supports Synchronous Ethernet with selectable recovered clock output • Robust Cable Discharge Event (CDE) protection of ±6 kV n Error-free operation over up to 140 meters of CAT5 cable • Automatic channel swap (ACS) • Automatic MDI/MDIX crossover • Automatic polarity correction • IEEE 802.3u compliant Auto-Negotiation 18 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E • Jumbo Frame support up to 10KB (full duplex) • Multiple loopback modes for diagnostics n Robust Surge Protection with ±750 V/ differential mode and ±4 kV/common mode • Cable Diagnostic Test (CDT) • Single power supply: 3.3V, optional for external regulator for core voltage n 6mm x 6mm, 48 pin QFN package • Industry temperature (I-temp) option available. Audio codec via the TLV320AIC3106 The Texas Instrument’s TLV320AIC3106 is a low-power, highly integrated stereo audio codec. Extensive register-based power control is included, enabling stereo 48-kHz DAC playback as low as 15mW. VAR-SOM-AM43 exposes most of the audio interfaces of the TLV320AIC3106. • Stereo Audio DAC - 102-dBA Signal-to-Noise Ratio - 16/20/24/32-Bit Data - Supports Rates From 8 kHz to 96 kHz - 3D/Bass/Treble/EQ/De-Emphasis Effects • Stereo Audio ADC - 92-dBA Signal-to-Noise Ratio - Supports Rates From 8 kHz to 96 kHz - Digital Signal Processing and Noise Filtering Available During Record • Programmable Input/output Analog Gains • Automatic Gain Control (AGC) for Record • Programmable Microphone Bias Level • Concurrent Digital Microphone and Analog Microphone Support Available Wi-Fi & Bluetooth The VAR-SOM-AM43 contains a certified high performance WL183xMOD 2.4/5 GHz IEEE 802.11 a/b/g/n with optional MIMO, Bluetooth 4.0 + BLE module. Features: - WLAN With Integrated RF Front-End Module (FEM), Power Amplifier (PA), Crystal, RF Switches, Filters, Passives, and Power Management on a Single Module - Wi-Fi-Bluetooth Single Antenna Coexistence - Dual-Mode Bluetooth and Bluetooth Low Energy - HCI Transport for Bluetooth over UART and SDIO for WLAN - Temperature Compensation Mechanism to Ensure Minimal Variation in RF Performance Over the Entire Temperature Range - WLAN Baseband Processor and RF Transceiver Supporting IEEE Std 802.11a, 802.11b, 802.11g, and 802.11n - Supports 4-Bit SDIO Host Interface Including High-Speed (HS) and V3 Modes - Optional 2x2 MIMO and 40-MHz Channels for High Throughput - Wi-Fi Direct Concurrent Operation (Multi-Channel, Multi-Role) - Support of Bluetooth 4.0 as well as CSA2 19 V A R - S O M - A M 4 3 - S Y S T E M O N M O D U L E Includes Concurrent Operation and Built-In Coexisting and Prioritization Handling of Bluetooth-BLE and WLAN Dedicated Audio Processor Supporting SBC Encoding + A2DP Up to 100-Mbps Throughput and Up to 1.4X the Range Versus a Single Antenna Configuration With 2X2 MIMO, 40-MHz Channel Bandwidth and MRC Lowest Wi-Fi Power Consumption in Connected Idle (< 800 uA) TPS65218 PMIC The Texas Instrument’s TPS65218 is an integrated power-management IC dedicated to applications processors as the AM437x. The device provides: BATTERY BACKUP SUPPLIES Two low-quiescent current, high efficiency step-down converters for battery backup domain - DCDC5: 1.0V output - DCDC6: 1.8V output VIN range from 2.2V to 5.5V Can be 7supplied from system power or coin-cell backup battery BUCK CONVERTERS (DCDC1, 2, 3) Three adjustable step-down converter with integrated switching FETs - DCDC1 : 1.1V default up to 1.8A (Core) - DCDC2 : 1.1V default up to 1.8A (MPU) - DCDC3 : 1.2V default up to 1.8A (DDR) VIN range from 2.7V to 5.5V Adjustable output voltage range 0.85V-3.5V 100% Duty Cycle for Lowest Dropout LOW VOLTAGE LOAD SWITCH (LS1) VIN range from 1.2V to 3.3V 350mA current limit HIGH-VOLTAGE LOAD SWITCH (LS3) VIN range from 1.8V to 10.0V 100mA / 500mA selectable current limit SUPERVISOR Built-in supervisor function monitors - DCDC1, DCDC2, DCDC3 to +/-4% - DCDC4 and LDO1 to +/-5% PROTECTION / DIAGNOSTICS / CONTROL Under voltage lockout Over temperature warning / shutdown Always-on push-button monitor Separate power-good output for backup and main supplies Open-drain interrupt output pin 20 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E User programmable default voltages and power sequencing I2C interface (Address 0x24h) TPS65218 features are utilized internally by the VAR-SOM-AM43 and are not exposed to the VAR-SOM-AM43 204 pin connector. 21 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E External Connectors The VAR-SOM-AM43 exposes a 204-pin, DDR3 SODIMM mechanical standard interface. Recommended Mating connector for baseboard interfacing is JAE MM80-204B1-1 or TE Connectivity 2-2013289-1or equivalent. Pin#: Pin Number on the SO-DIMM204 connector Pin Name: Default VAR- SOM-AM43 Pin Name Type: Pin Type & Description: I – In O – Out DS – Differential Signal A – Analog Power – Power Pin PD- Internal Pull Down PU - internal pull up Pin Group: Pin functionality group AM437x Ball: AM437x ball number Mode (Tables 3.2 & 3.4): AM437x PinMux mode option 22 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E SoM Connector Pin-out Pin# Pin Name 1 RGMII2_TD0[1] [7] Type O Pin Group / Function RGMII Transmit Data bit 0 Ball# E7 2 UART3_TXD_CON[5] O UART Transmit Data H24 3 RGMII2_TD1[1] [7] O RGMII Transmit Data bit 1 D7 I UART Receive Data H25 O RGMII Transmit Data bit 2 A4 O UART Request to Send K24 O RGMII Transmit Data bit 3 C6 I UART Clear to Send H22 O RGMII Transmit Clock E8 4 5 6 [5] UART3_RXD_CON RGMII2_TD2 [1] [7] [5] UART3_RTS_CON [1] [7] 7 RGMII2_TD3 8 UART3_CTS_CON[5] 9 RGMII2_TCLK 10 GND 11 [1] [7] Power RGMII2_TCTL O RGMII Transmit Control C3 [1] [7] I RGMII Receive Clock F6 I CAMERA1 Data Pixel Clock AE21 I RGMII Receive Control C5 I CAMERA1 data bus AE24 I RGMII Receive Data bit 0 D8 I CAMERA1 Data Horizontal Detect AD25 I RGMII Receive Data bit 1 G8 12 RGMII2_RCLK 13 CAM1_PCLK [1] [7] 14 RGMII2_RCTL 15 CAM1_DATA7 [1] [7] 16 RGMII2_RD0 17 CAM1_HSYNC 18 RGMII2_RD1 19 GND Digital GND [1] [7] [1] [7] Power [1] [7] 20 RGMII2_RD2 21 CAM1_DATA6 [1] [7] 22 RGMII2_RD3 23 CAM1_DATA5 24 GND 25 CAM1_WEN_GPIO4_13 26 CAM1_VSYNC 27 Digital GND I RGMII Receive Data bit 2 B4 I CAMERA1 data bus AD23 I RGMII Receive Data bit 3 F7 I CAMERA1 data bus AE23 Power I Digital GND CAMERA1 Data Write Enable AB25 I/O CAMERA1 Data Vertical Detect AC23 CAM1_FIELD_GPIO4_12 I CAMERA1 Data Field Indicator AC25 28 CAM1_DATA4 I CAMERA1 data bus AD22 29 GND 30 CAM1_DATA3 31 MDI_A_P 32 CAM1_DATA9 33 MDI_A_M 34 CAM1_DATA2 35 GND 36 CAM1_DATA1 37 MDI_B_P Power I I/ODS I I/ODS I Power I I/ODS Digital GND CAMERA1 data bus AE22 Media-dependent interface 0, Plus 11 CAMERA1 data bus AE18 Media-dependent interface 0, Minus 12 CAMERA1 data bus AD21 Digital GND CAMERA1 data bus AC21 Media-dependent interface 1, Plus 14 23 V A R - S O M - A M 4 3 38 CAM1_DATA0 39 MDI_B_M S Y S T E M O N M O D U L E I I/ODS [6] 40 ETH_MDIO_CLK 41 GND 42 ETH_MDIO_DATA[6] 43 MDI_C_P 44 O Power I/O CAMERA1 data bus AB20 Media-dependent interface 1, Minus 15 MII Management CLK B17 Digital GND MII Management DATA A17 I/ODS Media-dependent interface 2, Plus 17 GND Power Digital GND 45 MDI_C_M I/ODS Media-dependent interface 2, Minus 18 46 CAM1_DATA8 CAMERA1 data bus AB18 47 GND 48 CAM1_DATA10 49 MDI_D_P 50 CAM1_DATA11 51 MDI_D_M 52 AM437X_MMC0_SDCD 53 GND 54 MCASP0_ACLKX_SPI1_SCLK 55 LED_ACT O 56 GPIO5_4 I/O 57 LED_LINK_1000 58 MCASP0_AHCLKR_SPI1_CS0 59 LED_LINK_10_100 O 60 MCASP0_AHCLKX I/O 61 UART0_CTSN 62 MCASP0_AXR1 63 I Power I I/ODS I I/ODS I Power I/O Digital GND CAMERA1 data bus Y18 Media-dependent interface 3, Plus 20 CAMERA1 data bus AA18 Media-dependent interface 3, Minus 21 MMC/SD/SDIO Card Detect R25 Digital GND McASP0 Transmit Bit Clock N24 LED output for 10/100/1000 BASE-T activity 23 Digital Input/Output P25 LED output for 1000 BASE-T link 24 McASP0 Receive Master Clock M24 LED output for 10/100 BASE-T link 26 McASP0 Transmit Master Clock L24 UART Clear to Send L25 I/O McASP0 Serial Data (IN/OUT) M25 AM437X_USB0_VBUS_DET I USB0 OTG VBUS Detect Input F24 64 UART0_RTSN O UART Request to Send J25 65 AM437X_USB1_DRVVBUS O USB1 DRIVER ENABLE F25 66 UART0_RXD I UART Receive Data K25 67 UART0_TXD O UART Transmit Data J24 68 AM437X_LCD_BACKLIGHT O LCD BACKLIGHT PWM G24 69 I2C1_SDA I/O I2C1 Data T21 70 I2C1_SCL I/O I2C1 Clock T20 71 UART2_TXD_GPIO0_3 UART Transmit Data T22 72 GND O I/O I O Power Digital GND 73 [3] AM437X_LCD_HSYNC O LCD horizontal sync A23 74 AM437X_LCD_VSYNC[3] O LCD vertical sync B23 75 AM437X_LCD_DATA0 [3] O LCD data B22 76 AM437X_LCD_AC_BIAS_EN O LCD AC bias enable A24 24 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E 77 AM437X_LCD_DATA2[3] O LCD data B21 78 AM437X_LCD_PCLK O LCD pixel clock A22 AM437X_LCD_DATA5 [3] O LCD data B20 80 AM437X_LCD_DATA1 [3] O LCD data A21 81 AM437X_LCD_DATA9[3] O LCD data B19 82 AM437X_LCD_DATA4 [3] O LCD data A20 83 SPI2_CS0 I/O SPI Chip Select T23 84 SPI2_D0 I/O SPI Data P22 85 GND 86 UART2_RXD _GPIO0_2 87 AM437X_USB1_DP I/ODS 88 AM437X_USB0_ID I 89 AM437X_USB1_DM 90 SPI2_D1 91 AM437X_USB1_VBUS Power 92 MCASP0_FSX/SPI1_D0 I/O 93 GND 94 SPI2_SCLK 95 AM437X_USB0_DP 96 79 Power I Digital GND UART Receive Data P23 USB_DIFF V24 USB0 OTG ID U24 I/ODS USB_DIFF V25 I/O SPI Data P20 USB1 VBUS T25 McASP0 Transmit Frame Sync N22 Power SPI Clock N20 I/ODS USB0 OTG Data Pair W25 GND Power Digital GND 97 AM437X_USB0_DM I/ODS USB0 OTG Data Pair W24 98 AM437X_USB0_DRVVBUS USB0 OTG DRIVER ENABLE G21 99 AM437X_USB0_VBUS Power USB0 OTG VBUS U23 100 VBAT_3P3V Power SOM Power Supply Input 101 GND Power Digital GND 102 VBAT_3P3V Power SOM Power Supply Input 103 VBAT_3P3V Power SOM Power Supply Input 104 VBAT_3P3V Power SOM Power Supply Input 105 VBAT_3P3V Power SOM Power Supply Input 106 GND Power Digital GND 107 VBAT_3P3V Power SOM Power Supply Input 108 GND Power Digital GND [4] I/O Digital GND O General Purpose Input output (see note [4] ) C10 ADC0 Power supply Output 1.8V AB12 CAN1 Transmit K21 ADC0 Analog Ground AC15 I/O General Purpose Input output D25 I/O General Purpose Input output E24 109 GPIO2_5 I/O 110 VDDA_ADC 111 AM437X_DCAN1_TX 112 GNDA_ADC Power GPIO5_8[7] Power I/O 113 114 115 GPIO5_13 [7] 25 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E 116 GPIO1_12[7] I/O General Purpose Input output E25 117 MCASP0_ACLKR I/O McASP0 Receive Bit Clock L23 118 GND Digital GND GND 119 AM437X_DCAN1_RX I/O CAN1 Receive L21 120 AM437X_DCAN0_RX I/O CAN0 Receive L22 121 GND 122 MCASP0_FSR Power Power I/O [3] 123 AM437X_LCD_DATA10 124 AM437X_DCAN0_TX 125 MCASP0_AXR0/SPI1_D1 126 127 128 LCD data A18 I/O CAN0 Transmit K22 I/O McASP0 Serial Data (IN/OUT) H23 O O LCD data A19 AM437X_LCD_DATA6 [3] O LCD data C20 AM437X_LCD_DATA7 [3] O LCD data E19 O LCD data B18 130 GND [3] Power GPIO0_30 [4] [7] AM437X_LCD_DATA3 [3] AM437X_LCD_DATA13 134 VDDSHV11 GPIO1_14 136 AM437X_AIN5 A2 O LCD data C21 O LCD data D19 Power [7] 135 GPIO1_15 [3] I/O A [7] I/O [4] Digital GND General Purpose Input output (see notes [4] [7] ) I/O 133 137 K23 AM437X_LCD_DATA8 AM437X_LCD_DATA11 132 McASP0 Receive Frame Sync [3] 129 131 Digital GND Power Domain VDDSHV9 and VDDSHV11 General Purpose Input output B11 Analog input AC13 General Purpose Input output A11 [4] 138 GPIO2_3 I/O General Purpose Input output (see note 139 AM437X_MMC0_DAT1 I/O MMC/SD/SDIO data bus C2 140 AM437X_MMC0_DAT2 I/O MMC/SD/SDIO data bus B2 141 AM437X_MMC0_CLK O MMC/SD/SDIO clock D1 O LCD data C19 MMC/SD/SDIO data bus B1 LCD data D17 MMC/SD/SDIO command D2 LCD data C17 [3] 142 AM437X_LCD_DATA12 143 AM437X_MMC0_DAT3 [3] 144 AM437X_LCD_DATA15 145 AM437X_MMC0_CMD 146 AM437X_LCD_DATA14[3] 147 AM437X_MMC0_DAT0 148 149 I/O O I/O O I/O MMC/SD/SDIO data bus C1 I/O General Purpose Input output R24 [7] I/O General Purpose Input output P24 I/O General Purpose Input output GPIO5_5 GPIO5_6 GPIO1_13 151 GPIO0_31 [4] [7] 152 AM437X_AIN2 A Touch screen Y plus / analog I 153 MIC_IN_L AI MIC3 input 154 E10 [7] [7] 150 ) [4] GPIO2_2 I/O I/O C11 General Purpose Input output (see notes General Purpose Input output (see note 26 [4] [7] ) B3 Y13 11 [4] ) A9 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E 155 AM437X_AIN1 A Touch screen X minus / analog I Y12 156 AM437X_AIN6 A Analog input AD13 157 MICDET I Microphone detect 12 158 AM437X_AIN3 A Touch screen Y minus / analog I AA13 159 MICBIAS O Microphone bias voltage output 13 160 AM437X_AIN0 A Touch screen X plus / analog I AA12 161 MIC_IN_R AI MIC3 input 14 162 AM437X_AIN4 A Analog input AB13 163 AM437X_AIN7 A Analog input AE13 164 ADC0_VREFP AI Analog Positive Reference Input AD14 165 GND 166 ADC0_VREFN Power [4] AI Digital GND Analog Negative Reference Input AE14 [4] 167 GPIO2_4 I/O General Purpose Input output (see note 168 LINEIN_RP AI AUDIO Line Input Right 5 169 GPIO1_7[4] I/O General Purpose Input output (see note [4] ) B8 170 AGND_AUD Power 171 LOWPWR_RSTN O RESET OUTPUT build by pins Y23 & H20 172 LINEIN_LP AI AUDIO Line Input Left 3 173 GPIO4_8 I/O Digital Input/Output AD24 174 LINEOUT_RP AO AUDIO Line Output Right 31 175 AM437X_PORZN I/O Power On Reset Y23 176 LINEOUT_LP AO AUDIO Line Output Left [4] GPIO1_4 178 DMIC_CLK O Digital Microphone CLK 179 AM437X_LCD_DATA16 O LCD data 180 DMIC_DATA 182 183 D10 Audio Ground 177 181 I/O ) General Purpose Input output (see note 29 [4] ) B7 AC24 I/O Digital Microphone DATA [4] I/O General Purpose Input output (see note [4] ) A7 [2] I/O I2C0 Clock Y22 GPIO1_5 I2C0_SCL [4] GPIO1_6 [2] I/O General Purpose Input output (see note I/O I2C0 Data [4] ) C8 184 I2C0_SDA 185 GND 186 AM437X_LCD_DATA21 O LCD data AC18 187 AM437X_LCD_DATA19 O LCD data AC20 188 AM437X_LCD_DATA17 O LCD data Power [4] AB24 Digital GND AA19 [4] 189 GPIO1_3 I/O General Purpose Input output (see note 190 GPIO4_28 I/O Digital Input/Output AE20 191 GPIO1_2[4] I/O General Purpose Input output (see note [4] ) B6 192 GPIO4_29 I/O Digital Input/Output AD20 193 [4] GPIO1_1 I/O General Purpose Input output (see note 27 [4] ) ) A6 A5 V A R - S O M - A M 4 3 194 S Y S T E M GPIO4_26 [4] O N M O D U L E I/O Digital Input/Output AE19 [4] 195 GPIO1_0 I/O General Purpose Input output (see note 196 GPIO4_27 I/O Digital Input/Output AD19 197 AM437X_LCD_DATA22 O LCD data AD18 198 AM437X_LCD_DATA18 O LCD data AB19 199 AM437X_LCD_DATA23 O LCD data AE17 200 GND 201 AM437X_LCD_DATA20 202 GND Power Digital GND 203 GND Power Digital GND 204 GND Power Digital GND Power O ) B5 Digital GND LCD data Notes: 1. Do not use when on-board Wi-Fi module is mounted 2. I2C0 is internally used by PMIC (0x34h), EEPROM IC (0x1Bh) and AUDIO CODEC IC (0x50h). Pin function cannot be altered 3. LCD signals are sampled on POR for selecting System boot configurations. 4. GPMC Bus signal internally used by Nand flash. Can be configured and used as GPIO only if Nand flash is not used. 5. UART3 and SOM pins 2, 4, 6 and 8 are used for on-SOM Bluetooth if enabled 6. ETH_MDIO_CLK / ETH_MDIO_DATA signals are internally used by on-SOM 10/100/1000 Ethernet PHY. Do not alter pins functionality if Ethernet PHY is mounted. 7. Pin is referenced to 1.8V rail. 28 AD17 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E SO-DIMM 204 Pin Mux The table below summarizes the additional available functionality for each pin in the SO-DIMM 200 connector. Pin BALL SIGNAL NAME MODE NUMBER NUMBER gpmc_a5 0x0 gmii2_txd0 0x1 rgmii2_td0 0x2 rmii2_txd0 0x3 1 E7 gpmc_a21 0x4 pr1_mii1_txd0 0x5 eQEP1B_in 0x6 gpio1_21 0x7 uart3_txd 0x0 pr0_pru0_gpo19 0x4 2 H24 pr0_pru0_gpi19 0x5 ehrpwm4B 0x6 gpio5_3 0x7 gpmc_a4 0x0 gmii2_txd1 0x1 rgmii2_td1 0x2 rmii2_txd1 0x3 3 D7 gpmc_a20 0x4 pr1_mii1_txd1 0x5 eQEP1A_in 0x6 gpio1_20 0x7 uart3_rxd 0x0 pr0_pru0_gpo18 0x4 4 H25 pr0_pru0_gpi18 0x5 ehrpwm4A 0x6 gpio5_2 0x7 gpmc_a3 0x0 gmii2_txd2 0x1 rgmii2_td2 0x2 mmc2_dat2 0x3 5 A4 gpmc_a19 0x4 pr1_mii1_txd2 0x5 ehrpwm1B 0x6 gpio1_19 0x7 uart3_rtsn 0x0 6 K24 hdq_sio 0x1 29 V A R - S O M - A M 4 3 7 C6 8 H22 9 E8 11 C3 12 F6 S Y S T E M O N M O D U L E pr0_pru1_gpo19 pr0_pru1_gpi19 ehrpwm5B gpio5_1 gpmc_a2 gmii2_txd3 rgmii2_td3 mmc2_dat1 gpmc_a18 pr1_mii1_txd3 ehrpwm1A gpio1_18 uart3_ctsn spi4_cs1 pr0_pru1_gpo18 pr0_pru1_gpi18 ehrpwm5A gpio5_0 gpmc_a6 gmii2_txclk rgmii2_tclk mmc2_dat4 gpmc_a22 pr1_mii_mt1_clk eQEP1_index gpio1_22 gpmc_a0 gmii2_txen rgmii2_tctl rmii2_txen gpmc_a16 pr1_mii1_txen ehrpwm1_tripzone_input gpio1_16 gpmc_a7 gmii2_rxclk rgmii2_rclk mmc2_dat5 gpmc_a23 pr1_mii_mr1_clk eQEP1_strobe 30 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x2 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 V A R - S O M - A M 4 3 13 AE21 14 C5 15 AE24 16 D8 17 AD25 S Y S T E M O N M O D U L E gpio1_23 cam1_pclk xdma_event_intr6 spi1_cs3 pr0_pru1_gpo3 spi2_sclk pr0_pru1_gpi3 ehrpwm1A gpio4_11 gpmc_a1 gmii2_rxdv rgmii2_rctl mmc2_dat0 gpmc_a17 pr1_mii1_rxdv ehrpwm0_synco gpio1_17 cam1_data7 uart1_dtrn uart2_rtsn mmc2_dat3 pr0_pru1_gpo15 pr0_pru1_gpi15 pr1_edio_data_in1 gpio4_21 gpmc_a11 gmii2_rxd0 rgmii2_rd0 rmii2_rxd0 gpmc_a27 pr1_mii1_rxd0 mcasp0_axr1 gpio1_27 cam1_hd xdma_event_intr4 spi0_cs3 pr0_pru1_gpo1 spi2_cs0 pr0_pru1_gpi1 ehrpwm0A gpio4_9 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 31 V A R - S O M - A M 4 3 18 G8 20 B4 21 AD23 22 F7 23 AE23 S Y S T E M O N M O D U L E gpmc_a10 gmii2_rxd1 rgmii2_rd1 rmii2_rxd1 gpmc_a26 pr1_mii1_rxd1 mcasp0_axr0 gpio1_26 gpmc_a9 gmii2_rxd2 rgmii2_rd2 mmc2_dat7 gpmc_a25 pr1_mii1_rxd2 mcasp0_fsx gpio1_25 rmii2_crs_dv cam1_data6 uart1_dcdn uart2_ctsn mmc2_dat2 pr0_pru1_gpo14 pr0_pru1_gpi14 pr1_edio_data_in0 gpio4_20 gpmc_a8 gmii2_rxd3 rgmii2_rd3 mmc2_dat6 gpmc_a24 pr1_mii1_rxd3 mcasp0_aclkx gpio1_24 cam1_data5 uart1_dsrn uart2_txd mmc2_dat1 pr0_pru1_gpo13 pr0_pru1_gpi13 pr1_edio_latch_in gpio4_19 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 32 V A R - S O M - A M 4 3 25 AB25 26 AC23 27 AC25 28 AD22 30 AE22 S Y S T E M O N M O D U L E cam1_wen xdma_event_intr8 pr1_edio_sof cam0_data11 spi2_d1 cam1_data11 EMU11 gpio4_13 ehrpwm3B cam1_vd xdma_event_intr5 spi1_cs2 pr0_pru1_gpo2 spi2_cs2 pr0_pru1_gpi2 ehrpwm0B gpio4_10 cam1_field xdma_event_intr7 ext_hw_trigger cam0_data10 spi2_cs1 cam1_data10 ehrpwm1B gpio4_12 ehrpwm3A cam1_data4 uart1_rin uart2_rxd mmc2_dat0 pr0_pru1_gpo12 pr0_pru1_gpi12 pr1_edc_latch1_in gpio4_18 uart0_dcdn cam1_data3 uart1_rtsn spi3_sclk mmc2_cmd pr0_pru1_gpo11 pr0_pru1_gpi11 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x0 0x1 0x2 0x3 0x4 0x5 33 V A R - S O M - A M 4 3 32 AE18 34 AD21 36 AC21 38 AB20 40 B17 42 A17 S Y S T E M O N M O D U L E pr1_edc_latch0_in gpio4_17 cam0_data0 cam1_data9 I2C1_SDA pr0_pru1_gpo16 pr0_pru1_gpi16 ehrpwm0_synco gpio5_19 cam1_data2 uart1_ctsn spi3_cs0 mmc2_clk pr0_pru1_gpo10 pr0_pru1_gpi10 ehrpwm1_tripzone_input gpio4_16 cam1_data1 uart1_txd spi3_d1 I2C2_SCL ehrpwm0_synci gpio4_15 cam1_data0 uart1_rxd spi3_d0 I2C2_SDA ehrpwm0_tripzone_input gpio4_14 mdio_clk timer5 uart5_txd uart3_rtsn mmc0_sdwp mmc1_clk mmc2_clk gpio0_1 pr1_mdio_mdclk mdio_data timer6 uart5_rxd 34 0x6 0x7 0x0 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x6 0x7 0x0 0x1 0x2 0x3 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x0 0x1 0x2 V A R - S O M - A M 4 3 46 AB18 48 Y18 50 AA18 52 R25 54 N24 S Y S T E M O N M O D U L E uart3_ctsn mmc0_sdcd mmc1_cmd mmc2_cmd gpio0_0 pr1_mdio_data cam0_data1 cam1_data8 I2C1_SCL pr0_pru1_gpo17 pr0_pru1_gpi17 ehrpwm3_synco gpio5_20 cam0_data2 mmc1_clk cam1_data10 qspi_clk gpio4_24 cam0_data3 mmc1_cmd cam1_data11 qspi_csn gpio4_25 spi0_cs1 uart3_rxd eCAP1_in_PWM1_out mmc0_pow xdma_event_intr2 mmc0_sdcd EMU4 gpio0_6 ehrpwm2A timer0 mcasp0_aclkx ehrpwm0A spi0_cs3 spi1_sclk mmc0_sdcd pr0_pru0_gpo0 pr0_pru0_gpi0 gpio3_14 0x3 0x4 0x5 0x6 0x7 0x8 0x0 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x7 0x0 0x1 0x2 0x3 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 35 V A R - S O M - A M 4 3 56 P25 58 M24 60 L24 61 L25 62 M25 63 F24 64 J25 S Y S T E M O N M O D U L E spi4_sclk ehrpwm0_synci gpio5_4 mcasp0_ahclkr ehrpwm0_synci mcasp0_axr2 spi1_cs0 eCAP2_in_PWM2_out pr0_pru0_gpo3 pr0_pru0_gpi3 gpio3_17 mcasp0_ahclkx eQEP0_strobe mcasp0_axr3 mcasp1_axr1 EMU4 pr0_pru0_gpo7 pr0_pru0_gpi7 gpio3_21 gpio0_3 uart0_ctsn uart4_rxd dcan1_tx I2C1_SDA spi1_d0 timer7 pr1_edc_sync0_out gpio1_8 mcasp0_axr1 eQEP0_index mcasp1_axr0 EMU3 pr0_pru0_gpo6 pr0_pru0_gpi6 gpio3_20 gpio0_2 pr1_mii1_col gpio5_9 uart0_rtsn uart4_txd dcan1_rx 0x0 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x9 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x3 0x4 0x5 0x6 0x7 0x9 0x5 0x7 0x0 0x1 0x2 36 V A R - S O M - A M 4 3 65 F25 66 K25 67 J24 68 G24 69 T21 S Y S T E M O N M O D U L E I2C1_SCL spi1_d1 spi1_cs0 pr1_edc_sync1_out gpio1_9 USB1_DRVVBUS gpio3_13 gpio0_25 uart0_rxd spi1_cs0 dcan0_tx I2C2_SDA eCAP2_in_PWM2_out pr0_pru1_gpo4 pr0_pru1_gpi4 gpio1_10 uart0_txd spi1_cs1 dcan0_rx I2C2_SCL eCAP1_in_PWM1_out pr0_pru1_gpo5 pr0_pru1_gpi5 gpio1_11 eCAP0_in_PWM0_out uart3_txd spi1_cs1 pr1_ecap0_ecap_capin_apwm_o spi1_sclk mmc0_sdwp xdma_event_intr2 gpio0_7 ehrpwm2B timer1 spi0_d1 mmc1_sdwp I2C1_SDA ehrpwm0_tripzone_input pr1_uart0_rxd pr0_uart0_rxd pr1_edio_data_out0 37 0x3 0x4 0x5 0x6 0x7 0x0 0x7 0x9 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0x0 0x1 0x2 0x3 0x4 0x5 0x6 V A R - S O M - A M 4 3 70 T20 71 T22 73 A23 74 B23 75 B22 S Y S T E M O N M O D U L E gpio0_4 ehrpwm1A spi0_cs0 mmc2_sdwp I2C1_SCL ehrpwm0_synci pr1_uart0_txd pr0_uart0_txd pr1_edio_data_out1 gpio0_5 ehrpwm1B spi0_d0 uart2_txd I2C2_SCL ehrpwm0B pr1_uart0_rts_n pr0_uart0_rts_n EMU3 gpio0_3 dss_hsync gpmc_a9 gpmc_a2 pr1_edio_data_in3 pr1_edio_data_out3 pr0_pru1_gpo7 pr0_pru1_gpi7 gpio2_23 dss_vsync gpmc_a8 gpmc_a1 pr1_edio_data_in2 pr1_edio_data_out2 pr0_pru1_gpo6 pr0_pru1_gpi6 gpio2_22 dss_data0 gpmc_a0 pr1_mii_mt0_clk ehrpwm2A pr1_pru0_gpo0 pr1_pru0_gpi0 0x7 0x8 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x5 0x6 38 V A R - S O M - A M 4 3 76 A24 77 B21 78 A22 79 B20 80 A21 81 B19 S Y S T E M O N M O D U L E gpio2_6 dss_ac_bias_en gpmc_a11 gpmc_a4 pr1_edio_data_in5 pr1_edio_data_out5 pr0_pru1_gpo9 pr0_pru1_gpi9 gpio2_25 dss_data2 gpmc_a2 pr1_mii0_txd3 ehrpwm2_tripzone_input pr1_pru0_gpo2 pr1_pru0_gpi2 gpio2_8 dss_pclk gpmc_a10 gpmc_a3 pr1_edio_data_in4 pr1_edio_data_out4 pr0_pru1_gpo8 pr0_pru1_gpi8 gpio2_24 dss_data5 gpmc_a5 pr1_mii0_txd0 eQEP2B_in pr1_pru0_gpo5 pr1_pru0_gpi5 gpio2_11 dss_data1 gpmc_a1 pr1_mii0_txen ehrpwm2B pr1_pru0_gpo1 pr1_pru0_gpi1 gpio2_7 dss_data9 gpmc_a13 ehrpwm0_synco 39 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x5 0x6 0x7 0x0 0x1 0x2 V A R - S O M - A M 4 3 82 A20 83 T23 84 P22 86 P23 90 P20 92 N22 S Y S T E M O N M O D U L E mcasp0_fsx uart5_rxd pr1_mii0_rxd2 uart2_rtsn gpio2_15 dss_data4 gpmc_a4 pr1_mii0_txd1 eQEP2A_in pr1_pru0_gpo4 pr1_pru0_gpi4 gpio2_10 spi2_cs0 I2C1_SDA ehrpwm2_tripzone_input gpio3_25 gpio0_23 spi2_d0 ehrpwm5_tripzone_input gpio3_22 gpio0_20 spi0_sclk uart2_rxd I2C2_SDA ehrpwm0A pr1_uart0_cts_n pr0_uart0_cts_n EMU2 gpio0_2 spi2_d1 ehrpwm1_tripzone_input gpio3_23 gpio0_21 mcasp0_fsx ehrpwm0B spi1_cs2 spi1_d0 mmc1_sdcd pr0_pru0_gpo1 pr0_pru0_gpi1 gpio3_15 40 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x5 0x6 0x7 0x0 0x1 0x6 0x7 0x9 0x0 0x6 0x7 0x9 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x6 0x7 0x9 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 V A R - S O M - A M 4 3 94 N20 98 G21 109 C10 111 K21 114 D25 115 E24 116 E11 117 L23 S Y S T E M O N M O D U L E spi2_sclk I2C1_SCL ehrpwm4_tripzone_input gpio3_24 gpio0_22 USB0_DRVVBUS gpio0_18 gpio5_27 gpmc_be0n_cle spi1_cs3 timer5 qspi_d3 pr1_mii1_rxlink gpmc_a5 spi3_cs1 gpio2_5 uart1_rxd mmc1_sdwp dcan1_tx I2C1_SDA pr1_uart0_rxd pr1_pru0_gpi16 gpio0_14 pr1_mii0_col gpio5_8 pr1_mii1_rxlink gpio5_13 gpmc_ad12 dss_data19 mmc1_dat4 mmc2_dat0 eQEP2A_in pr1_mii0_txd2 pr1_pru0_gpi10 gpio1_12 mcasp0_aclkx pr1_pru0_gpo10 mcasp0_aclkr eQEP0A_in mcasp0_axr2 mcasp1_aclkx 41 0x0 0x1 0x6 0x7 0x9 0x0 0x7 0x9 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x5 0x6 0x7 0x5 0x7 0x5 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0x0 0x1 0x2 0x3 V A R - S O M - A M 4 3 119 L21 120 L22 122 K23 123 A18 124 K22 S Y S T E M O N M O D U L E mmc0_sdwp pr0_pru0_gpo4 pr0_pru0_gpi4 gpio3_18 gpio0_18 gpio1_30 uart1_txd mmc2_sdwp dcan1_rx I2C1_SCL pr1_uart0_txd pr1_pru0_gpi16 gpio0_15 uart1_rtsn timer5 dcan0_rx I2C2_SCL spi1_cs1 pr1_uart0_rts_n pr1_edc_latch1_in gpio0_13 mcasp0_fsr eQEP0B_in mcasp0_axr3 mcasp1_fsx EMU2 pr0_pru0_gpo5 pr0_pru0_gpi5 gpio3_19 gpio0_19 dss_data10 gpmc_a14 ehrpwm1A mcasp0_axr0 pr1_mii0_rxd1 uart3_ctsn gpio2_16 uart1_ctsn timer6 dcan0_tx I2C2_SDA 0x4 0x5 0x6 0x7 0x9 0x7 0x0 0x1 0x2 0x3 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x9 0x0 0x1 0x2 0x3 0x5 0x6 0x7 0x0 0x1 0x2 0x3 42 V A R - S O M - A M 4 3 125 H23 126 A19 127 C20 128 E19 129 B18 S Y S T E M O N M O D U L E spi1_cs0 pr1_uart0_cts_n pr1_edc_latch0_in gpio0_12 mcasp0_axr0 ehrpwm0_tripzone_input spi1_cs3 spi1_d1 mmc2_sdcd pr0_pru0_gpo2 pr0_pru0_gpi2 gpio3_16 dss_data8 gpmc_a12 ehrpwm1_tripzone_input mcasp0_aclkx uart5_txd pr1_mii0_rxd3 uart2_ctsn gpio2_14 dss_data6 gpmc_a6 pr1_edio_data_in6 eQEP2_index pr1_edio_data_out6 pr1_pru0_gpo6 pr1_pru0_gpi6 gpio2_12 dss_data7 gpmc_a7 pr1_edio_data_in7 eQEP2_strobe pr1_edio_data_out7 pr1_pru0_gpo7 pr1_pru0_gpi7 gpio2_13 dss_data11 gpmc_a15 ehrpwm1B mcasp0_ahclkr mcasp0_axr2 43 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 V A R - S O M - A M 4 3 131 A2 132 C21 133 D19 135 B11 137 A11 S Y S T E M O N M O D U L E pr1_mii0_rxd0 uart3_rtsn gpio2_17 spi3_cs1 gpmc_wait0 gmii2_crs gpmc_csn4 rmii2_crs_dv mmc1_sdcd pr1_mii1_crs uart4_rxd gpio0_30 gpio5_30 dss_data3 gpmc_a3 pr1_mii0_txd2 ehrpwm0_synco pr1_pru0_gpo3 pr1_pru0_gpi3 gpio2_9 dss_data13 gpmc_a17 eQEP1B_in mcasp0_fsr mcasp0_axr3 pr1_mii0_rxer uart4_rtsn gpio0_9 spi3_d0 gpmc_ad14 dss_data17 mmc1_dat6 mmc2_dat2 eQEP2_index pr1_mii0_txd0 pr1_pru0_gpi16 gpio1_14 mcasp0_axr0 gpmc_ad15 dss_data16 mmc1_dat7 0x5 0x6 0x7 0x8 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x9 0x0 0x1 0x2 0x3 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x0 0x1 0x2 44 V A R - S O M - A M 4 3 138 E10 139 C2 140 B2 141 D1 142 C19 S Y S T E M O N M O D U L E mmc2_dat3 eQEP2_strobe pr1_ecap0_ecap_capin_apwm_o gpio1_15 mcasp0_axr1 spi3_cs1 gpmc_oen_ren spi0_cs2 timer7 qspi_d1 gpio2_3 mmc0_dat1 gpmc_a22 uart5_ctsn uart3_rxd uart1_dtrn pr0_pru0_gpo10 pr0_pru0_gpi10 gpio2_28 mmc0_dat2 gpmc_a21 uart4_rtsn timer6 uart1_dsrn pr0_pru0_gpo9 pr0_pru0_gpi9 gpio2_27 mmc0_clk gpmc_a24 uart3_ctsn uart2_rxd dcan1_tx pr0_pru0_gpo12 pr0_pru0_gpi12 gpio2_30 dss_data12 gpmc_a16 eQEP1A_in mcasp0_aclkr mcasp0_axr2 pr1_mii0_rxlink 45 0x3 0x4 0x5 0x7 0x8 0x9 0x0 0x1 0x2 0x3 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 V A R - S O M - A M 4 3 143 B1 144 D17 145 D2 146 C17 147 C1 S Y S T E M O N M O D U L E uart4_ctsn gpio0_8 spi3_sclk mmc0_dat3 gpmc_a20 uart4_ctsn timer5 uart1_dcdn pr0_pru0_gpo8 pr0_pru0_gpi8 gpio2_26 dss_data15 gpmc_a19 eQEP1_strobe mcasp0_ahclkx mcasp0_axr3 pr1_mii0_rxdv uart5_rtsn gpio0_11 spi3_cs0 mmc0_cmd gpmc_a25 uart3_rtsn uart2_txd dcan1_rx pr0_pru0_gpo13 pr0_pru0_gpi13 gpio2_31 dss_data14 gpmc_a18 eQEP1_index mcasp0_axr1 uart5_rxd pr1_mii_mr0_clk uart5_ctsn gpio0_10 spi3_d1 mmc0_dat0 gpmc_a23 uart5_rtsn uart3_txd 0x6 0x7 0x8 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x0 0x1 0x2 0x3 46 V A R - S O M - A M 4 3 148 R24 149 P24 150 C11 151 B3 154 A9 167 D10 169 B8 S Y S T E M O N M O D U L E uart1_rin pr0_pru0_gpo11 pr0_pru0_gpi11 gpio2_29 spi4_d0 ehrpwm3_synci gpio5_5 spi4_d1 ehrpwm0_tripzone_input gpio5_6 gpmc_ad13 dss_data18 mmc1_dat5 mmc2_dat1 eQEP2B_in pr1_mii0_txd1 pr1_pru0_gpi11 gpio1_13 mcasp0_fsx pr1_pru0_gpo11 gpmc_wpn gmii2_rxerr gpmc_csn5 rmii2_rxerr mmc2_sdcd pr1_mii1_rxer uart4_txd gpio0_31 gpio5_31 gpmc_advn_ale spi0_cs3 timer4 qspi_d0 gpio2_2 gpmc_wen spi1_cs2 timer6 qspi_d2 gpio2_4 gpmc_ad7 mmc1_dat7 47 0x4 0x5 0x6 0x7 0x0 0x6 0x7 0x0 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x9 0x0 0x1 0x2 0x3 0x7 0x0 0x1 0x2 0x3 0x7 0x0 0x1 V A R - S O M - A M 4 3 173 AD24 175 Y23 177 B7 179 AC24 181 A7 182 Y22 183 C8 184 AB24 186 AC18 S Y S T E M O N M O D U L E gpio1_7 cam1_data8 xdma_event_intr3 spi0_cs2 pr0_pru1_gpo0 spi2_d0 pr0_pru1_gpi0 EMU10 gpio4_8 uart0_rtsn porz gpmc_ad4 mmc1_dat4 gpio1_4 cam1_data9 dss_data16 pr0_pru0_gpo17 spi2_cs3 pr0_pru0_gpi17 EMU9 gpio4_7 uart0_ctsn gpmc_ad5 mmc1_dat5 gpio1_5 I2C0_SCL timer7 uart2_rtsn eCAP1_in_PWM1_out gpio3_6 gpmc_ad6 mmc1_dat6 gpio1_6 I2C0_SDA timer4 uart2_ctsn eCAP2_in_PWM2_out gpio3_5 cam0_field dss_data21 cam0_data10 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x0 0x0 0x1 0x7 0x0 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x0 0x1 0x7 0x0 0x1 0x2 0x3 0x7 0x0 0x1 0x7 0x0 0x1 0x2 0x3 0x7 0x0 0x2 0x3 48 V A R - S O M - A M 4 3 187 AC20 188 AA19 189 A6 190 AE20 191 B6 192 AD20 193 A5 194 AE19 S Y S T E M O N M O D U L E spi2_sclk cam1_data10 EMU4 gpio4_2 cam0_pclk dss_data19 pr0_pru0_gpo14 spi2_cs0 pr0_pru0_gpi14 EMU6 gpio4_4 I2C2_SDA cam0_data9 dss_data17 pr0_pru0_gpo16 spi2_cs3 pr0_pru0_gpi16 EMU8 gpio4_6 gpmc_ad3 mmc1_dat3 gpio1_3 cam0_data6 mmc1_dat2 qspi_d2 ehrpwm1A gpio4_28 gpmc_ad2 mmc1_dat2 gpio1_2 cam0_data7 mmc1_dat3 qspi_d3 ehrpwm1B gpio4_29 gpmc_ad1 mmc1_dat1 gpio1_1 cam0_data4 mmc1_dat0 cam1_wen 0x4 0x5 0x6 0x7 0x0 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x0 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x7 0x0 0x1 0x3 0x6 0x7 0x0 0x1 0x7 0x0 0x1 0x3 0x6 0x7 0x0 0x1 0x7 0x0 0x1 0x2 49 V A R - S O M - A M 4 3 195 B5 196 AD19 197 AD18 198 AB19 199 AE17 201 AD17 S Y S T E M O N M O D U L E qspi_d0 ehrpwm3A gpio4_26 gpmc_ad0 mmc1_dat0 gpio1_0 cam0_data5 mmc1_dat1 qspi_d1 ehrpwm3B gpio4_27 cam0_vd dss_data22 pr1_edio_outvalid spi2_d1 EMU11 EMU3 gpio4_1 cam0_data8 dss_data18 pr0_pru0_gpo15 spi2_cs2 pr0_pru0_gpi15 EMU7 gpio4_5 I2C2_SCL cam0_hd dss_data23 pr1_edio_sof spi2_cs1 EMU10 EMU2 gpio4_0 cam0_wen dss_data20 cam0_data11 spi2_d0 cam1_data11 EMU5 gpio4_3 0x3 0x6 0x7 0x0 0x1 0x7 0x0 0x1 0x3 0x6 0x7 0x0 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x0 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x2 0x3 0x4 0x5 0x6 0x7 50 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E Interface Details Overview This chapter describes in detail the VAR-SOM-AM43 interfaces, referring to the default SoM pin names. However, many additional interfaces are available when different pin modes are selected by the user. PinMux Table 3.2 details the additional possible options for each pin on the VAR-SOM-AM43 connectors. The following list describes this chapter’s column header tables: Signal: VAR-SOM-AM43 original pin name Pin#: Pin Number on the SO-DIMM204 connector Type: Pin Type & Direction: I – In O – Out DS – Differential Signal A – Analog P – Power Pin Description: Short Pin functionality description Display Interfaces The general features of the DSS module include: • Display Controller - Display Modes • Programmable pixel memory formats (Palletized: 1, 2, 4, 8-bit per pixel; RGB 16, and 24-bit per pixel; and YUV 4:2:2) • Programmable display size (up to 2048 x 2048) • 256 x 24-bit entries palette in RGB • Programmable pixel rate (up to 80 MHz) - Display Support • Four types of displays are supported: Passive and Active colors, Passive and Active monochromes. • 4-/8-bit Monochrome Passive panel interface support (15 grayscale levels supported using dithering block) • RGB 8-bit Color Passive panel interface support (3,375 colors supported for color panel using dithering block). • RGB 12/16/18/24-bit Active panel interface support (replicated or dithered encoded pixel values). • Remote Frame Buffer (embedded in the LCD panel) support through the RFBI module • Partial refresh of the remote frame buffer through the RFBI module 51 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E • Partial display • Multiple cycles output format on 8/9/12/16bit interface (TDM) - Signal Processing • Overlay and Windowing support for one Graphics layer (RGB or CLUT) and two Video layers (YUV 4:2:2, RGB16 and RGB24) • RGB 24-bit support on the display interface, optionally dithered to RGB 18-bit pixel output + 6Bit Frame rate Control (spatial and temporal) • Transparency color key (source and destination) • Synchronized buffer update • Gamma Curve Support • Multiple-buffer support • Cropping Support • Merge capability of the DMA FIFO for use by a single pipeline in case of DVFS • Color Phase rotation - Interrupt line and DMA line trigger signals • The LCD DMA is a secure transaction initiator on the L3 interconnect. • Remote Frame Buffer Interface - Access to RFB’s “direct MPU interface” • Sending commands to the RFB panel. • Sending data to the RFB panel, received from the Display controller or from the MPU (through the L4 OCP slave port) • Reading data/status from the RFB to the OCP slave port. - RFB interface • 8/9/12/16-bit parallel interface (up to QVGA@30fps at nominal voltage) • Two programmable configurations for two devices connected to the RFBI module. • Tearing Effect control logic (Horizontal Synchronization (HSync) and Vertical Synchronization (VSync) embedded in a single signal (TE) or using two signals (HS+VS)). - Data formats • Programmable pixel memory formats (12-, 16-, 18- and 24-bit-per-pixel modes in RGB format) • Programmable output formats on one/multiple cycles per pixel (data from Display controller and from L4) (TDM) The VAR-SOM-AM43 provides the logic to display a video frame from the memory frame buffer on a LCD panel using an up to 24-bit parallel RGB bus. DSI signals: SIGNAL NAME dss_data0 dss_data1 dss_data2 dss_data3 dss_data4 dss_data5 dss_data6 Pin# 75 80 77 132 82 79 C20 Description LCD_data B0 LCD_data B1 LCD_data B2 LCD_data B3 LCD_data B4 LCD_data B5 LCD_data B6 52 Type O O O O O O O V A R - S O M - A M 4 3 S Y S T E M dss_data7 dss_data8 dss_data9 dss_data10 dss_data11 dss_data12 dss_data13 dss_data14 dss_data15 dss_data16 dss_data17 dss_data18 dss_data19 dss_data20 dss_data21 dss_data22 dss_data23 dss_pclk dss_vsync dss_hsync dss_ac_bias_en ECAP0_IN_PWM0_OUT 128 126 81 123 129 142 133 146 144 179 188 198 187 201 186 197 199 78 74 73 76 68 O N M O D U L E LCD_data B7 LCD_data G0 LCD_data G1 LCD_data G2 LCD_data G3 LCD_data G4 LCD_data G5 LCD_data G6 LCD_data G7 LCD_data R0 LCD_data R1 LCD_data R2 LCD_data R3 LCD_data R4 LCD_data R5 LCD_data R6 LCD_data R7 LCD pixel clock LCD vertical sync LCD horizontal sync LCD AC bias enable CS Backlight PWM O O O O O O O O O O O O O O O O O O O O O O Ethernet The AM43 SOM includes two EMAC designed to support 10/100/1000 Mbps Ethernet/IEEE 802.3 networks. The general features of the ethernet switch subsystem are: • Two 10/100/1000 Ethernet ports with GMII, RMII and RGMII interfaces • Wire rate switching (802.1d) • Non Blocking switch fabric • Flexible logical FIFO based packet buffer structure • Four priority level QOS support (802.1p) • CPPI 3.1 compliant DMA controllers • Support for IEEE 1588v2 Clock Synchronization (2008 Annex D, E, and F) - Timing FIFO and time stamping logic inside the SS • Device Level Ring (DLR) Support • Address Lookup Engine - 1024 addresses plus VLANs Wire rate lookup VLAN support Host controlled time-based aging Spanning tree support 53 V A R - S O M - A M 4 3 - S Y S T E M O N M O D U L E L2 address lock and L2 filtering support MAC authentication (802.1x) Receive or destination based Multicast and Broadcast limits MAC address blocking Source port locking OUI host accept/deny feature • Flow Control Support (802.3x) • EtherStats and 802.3Stats RMON statistics gathering (shared) • Support for external packet dropping engine • CPGMAC_SL transmit to CPGMAC_SL receive Loopback mode (digital loopback) supported • CPGMAC_SL receive to CPGMAC_SL transmit Loobback mode (FIFO loopback) supported • Maximum frame size 2016 bytes (2020 with VLAN) • 8k (2048 x 32) internal CPPI buffer descriptor memory • MDIO module for PHY Management • Programmable interrupt control with selected interrupt pacing • Emulation Support. • Programmable transmit Inter-Packet Gap (IPG) • Reset isolation On board 1G PHY The onboard Ethernet PHY AR8033 exports the differential pairs to the edge connector. 11 pins for signals +5 pins for GND between the differential pairs to be routed to the edge connector. The Mode pins of the AR8033 are set to 1G at wake up (0010 1000Base, 50ohms, RGMII). 54 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E Gigabit Ethernet Signals: AM437X SIGNAL NAME GND MDI_A+ MDI_AGND MDI_B+ MDI_BGND MDI_C+ MDI_CGND MDI_D+ MDI_DGND LED_ACT LED_LINK_10_100 LED_LINK_1000 DESCRIPTION ground signal Media-dependent interface _A+ Media-dependent interface _Aground signal Media-dependent interface _B+ Media-dependent interface _Bground signal Media-dependent interface _C+ Media-dependent interface _Cground signal Media-dependent interface _D+ Media-dependent interface _Dground signal LED output for 10/100/1000 BASE-T activity LED output for 10/100 BASE-T link LED output for 1000 BASE-T link pin 29 31 33 35 37 39 41 43 45 47 49 51 53 55 59 57 Optional ROUTE OUT RGMII interface. In a configuration without a Wi-Fi module RGMII2 Interface will be routed out. Optional additional Gigabit Ethernet signals: AM437X SIGNAL NAME RGMII2_RCLK RGMII2_RCTL RGMII2_RD0 RGMII2_RD1 RGMII2_RD2 RGMII2_RD3 RGMII2_TCLK RGMII2_TCTL RGMII2_TD0 RGMII2_TD1 RGMII2_TD2 RGMII2_TD3 BALL # F6 C5 D8 G8 B4 F7 E8 C3 E7 D7 A4 C6 DESCRIPTION RGMII2_RCLK RGMII2_RCTL RGMII2_RD0 RGMII2_RD1 RGMII2_RD2 RGMII2_RD3 RGMII2_TCLK RGMII2_TCTL RGMII2_TD0 RGMII2_TD1 RGMII2_TD2 RGMII2_TD3 PIN# 12 14 16 18 20 22 9 11 1 3 5 7 ETH_MDIO_DATA A17 ETH_MDIO_DATA 42 ETH_MDIO_CLK B17 ETH_MDIO_CLK 40 55 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E AM437X SIGNAL NAME DESCRIPTION MDIO_DATA MDIO_MDCLK Valid configuration PINs 1 2 3 MDIO Data B12 A17 D24 MDIO Clock A12 B17 C24 USB 2.0 The SOM provides with 2 USB I/F, USB0 is used as OTG, and USB1 is used as host interface. USB 2.0 HOST USB HOST1 signals: AM437X PINS DESCRIPTION PIN # USB1_DM USB1 Data minus 89 USB1_DP USB1 Data plus 87 USB1_DRVVBUS USB1 Active high VBUS control output 65 USB1_VBUS USB1 VBUS 91 AM437X SIGNAL NAME DESCRIPTION PIN # USB0_DM USB0 Data minus 97 USB0_DP USB0 Data plus 95 USB0_DRVVBUS USB0 Active high VBUS control output 98 USB0_ID USB0 OTG ID (Micro-A or Micro-B Plug) 88 USB0_VBUS USB0 VBUS 99 USB 2.0 On-the-Go USB0 OTG signals: AM437X_USB0_VBUS_DET GPIO5_9, USB0_VBUS_DET 56 63 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E MMC/SD/SDIO The general features of the MMCSD host controller IP are: • Built-in 1024-byte buffer for read or write • Two DMA channels, one interrupt line • Clock support - 96-MHz functional clock source input up to 384Mbit/sec (48MByte/sec) in MMC mode 8-bit data transfer up to 192Mbit/sec (24MByte/sec) in High-Speed SD mode 4-bit data transfer up to 24Mbit/sec (3MByte/sec) in Default SD mode 1-bit data transfer • Support for SDA 3.0 Part A2 programming model • Serial link supports full compliance with: - MMC command/response sets as defined in the MMC standard specification v4.3. SD command/response sets as defined in the SD Physical Layer specification v2.00 SDIO command/response sets and interrupt/read-wait suspend-resume operations as defined in the SD part E1 specification v 2.00 SD Host Controller Standard Specification sets as defined in the SD card specification Part A2 v2.00 MMC0 Signals SDMMC0 Interface signals: AM437X SIGNAL NAME MMC0_CLK MMC0_CMD MMC0_DAT0 MMC0_DAT1 MMC0_DAT2 MMC0_DAT3 MMC0_SDCD DESCRIPTION Valid configuration PINs SD Card Clock SD Card Command SD Card Data Bus SD Card Data Bus SD Card Data Bus SD Card Data Bus SD Card Detect 141 145 147 139 140 143 42 141 145 147 139 140 143 42 141 145 147 139 140 143 42 141 145 147 139 140 143 54 141 145 147 139 140 143 54 141 145 147 139 140 143 54 MMC0_SDWP SD Card Write Protect 40 40 40 40 40 40 MMC0_POW SD Card Power Switch Control 52 117 68 52 117 68 MMC1 Signals SDMMC1 Interface signals: AM437X SIGNAL NAME MMC1_CLK MMC1_CMD MMC1_DAT0 MMC1_DAT1 MMC1_DAT2 DESCRIPTION Valid configuration PINs MMC/SD/SDIO Clock MMC/SD/SDIO Command MMC/SD/SDIO Data Bus MMC/SD/SDIO Data Bus MMC/SD/SDIO Data Bus 48 50 194 196 190 57 48 50 194 196 190 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E MMC1_DAT3 MMC1_SDCD MMC/SD/SDIO Data Bus SD Card Detect MMC1_SDWP SD Write Protect 192 131 192 92 69 111 MMC2 Signals SDMMC2 Interface signals: AM437X SIGNAL NAME MMC2_CLK MMC2_CMD MMC2_DAT0 MMC2_DAT1 MMC2_DAT2 MMC2_DAT3 DESCRIPTION PINs MMC/SD/SDIO Clock MMC/SD/SDIO Command MMC/SD/SDIO Data Bus MMC/SD/SDIO Data Bus MMC/SD/SDIO Data Bus MMC/SD/SDIO Data Bus MMC2_SDCD SD Card Detect MMC2_SDWP SD Write Protect 34 30 28 23 21 15 151/125 119/70 58 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E Audio TLV320AIC3106 Audio codec Audio interfaces are featured by an on-board Texas Instrument’s feature-rich TLV320AIC3106 audio codec device. Please refer to the TLV320AIC3106 data sheet for detailed electrical characteristics of relevant interfaces. Main supported features are: • Stereo line in • Stereo line out • Stereo headphones driver • Digital microphone • Analog microphone Audio interface Signals: SIGNAL NAME CODEC PIN# DESCRIPTION PIN# LINEOUT_RP 31 RIGHT LINE OUTPUT (+) 174 LINEOUT_LP 29 LEFT LINE OUTPUT (+) 176 MIC_IN_R 14 MIC3 INPUT RIGHT 161 MIC_IN_L 11 153 MICBIAS 13 MICDET 12 LINEIN1_LP 3 LINEIN1_RP 5 DMIC_CLK 35 DMIC_DATA 34 MIC3 INPUT LEFT MICROPHONE BIAS VOLTAGE OUTPUT MICROPHONE DETECT LINE1 ANALOG LEFT INPUT (+) LINE1 ANALOG RIGHT INPUT (+) DIGITAL MICROPHONE CLOCK DIGITAL MICROPHONE DATA 159 157 172 168 178 180 MCASP0 (Multichannel Audio Serial Port) The interface is shared with the on board Wi-Fi module McASP0 Signals: AM437X SIGNAL NAME MCASP0_ACLKX ZDN BALL # N24 MCASP0_FSX N22 MCASP0_AXR0 H23 MCASP0_AXR1 M25 DESCRIPTION McASP0 Transmit Bit Clock McASP0 Transmit Frame Sync McASP0 Serial Data (IN/OUT) McASP0 Serial Data (IN/OUT) _RD0 59 PIN# 54 92 125 62 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E Camera CPI Camera interface #0. The general features of the VPFE module include: • A buffer memory for interfacing to the DMA at the chip level and preventing the CCDC module from overflowing. • Support for conventional Bayer pattern and Foveon sensor formats • Generates HD/VD timing signals and field ID to an external timing generator or can synchronize to the external timing generator • Support for progressive and interlaced sensors (hardware support for up to 2 fields and firmware support for higher number of fields, typically 3-, 4-, and 5-field sensors) • Support for up to the lesser of 75 MHz or 1/2 dma_ocp_clk sensor clock in the normal mode • Support for REC656/CCIR-656 standard (YCbCr 422 format, either 8- or 16-bit) • Support for YCbCr 422 format, either 8- or 16-bit with discrete H and VSYNC signals. • Support for up to 16-bit input • Generates optical black clamping signals • Support for digital clamping and black level compensation • Support for 10-bit to 8-bit A-law compression • Support for a low-pass filter prior to writing to SDRAM. If this filter is enabled, 2 pixels each in the left and right edges of each line are cropped from the output. • Support for generating output to range from 16-bits to 8-bits wide • Support for downsampling via programmable culling patterns • Ability to control output to the SDRAM via an external write enable signal • Support for up to 16K pixels (image size) in both the horizontal and vertical direction Parallel Camera Interface #0 signals: AM437X SIGNAL NAME Cam0_data0 Cam0_data1 Cam0_data2 Cam0_data3 Cam0_data4 Cam0_data5 Cam0_data6 Cam0_data7 Cam0_data8 Cam0_data9 Cam0_data10 Cam0_data11 Cam0_hd Cam0_pclk Cam0_vd Cam0_wen Cam0_field DESCRIPTION Camera data Camera data Camera data Camera data Camera data Camera data Camera data Camera data Camera data Camera data Camera data Camera data CCD Data Horizontal Detect CCD Data Pixel Clock CCD Data Vertical Detect CCD Data Write Enable CCD Data Field Indicator 60 PINs 32 46 48 50 194 196 190 192 198 188 27 25 199 187 197 201 186 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E CPI Camera interface #1. Parallel Camera Interface #1 signals: AM437X SIGNAL NAME cam1_data0 cam1_data1 cam1_data2 cam1_data3 cam1_data4 cam1_data5 cam1_data6 cam1_data7 cam1_data8 cam1_data9 cam1_data10 cam1_data11 cam1_hd cam1_pclk cam1_vd cam1_wen cam1_field DESCRIPTION Camera data Camera data Camera data Camera data Camera data Camera data Camera data Camera data Camera data Camera data Camera data Camera data CCD Data Horizontal Detect CCD Data Pixel Clock CCD Data Vertical Detect CCD Data Write Enable CCD Data Field Indicator 38 36 34 30 28 23 21 15 173 179 186 201 17 13 26 25 27 Valid configuration PINs 38 38 38 38 36 36 36 36 34 34 34 34 30 30 30 30 28 28 28 28 23 23 23 23 21 21 21 21 15 15 15 15 173 46 173 173 179 32 179 179 48 48 186 48 50 50 201 50 17 17 17 17 13 13 13 13 26 26 26 26 25 25 194 194 27 27 27 27 38 36 34 30 28 23 21 15 46 32 48 50 17 13 26 194 27 UART Interfaces The general features of the UART/IrDA module when operating in UART mode are: • 16C750 compatibility • Baud rate from 300 bps up to 3.6864 Mbps • Auto-baud between 1200 bps and 115.2 Kbps • Software/Hardware flow control - Programmable Xon/Xoff characters Programmable Auto-RTS and Auto CTS • Programmable serial interface characteristics - 5, 6, 7, or 8-bit characters Even, odd, mark (always 1), space (always 0), or no parity (non-parity bit frame) bit generation and detection 1, 1.5, or 2 stop bit generation • False start bit detection • Line break generation and detection • Modem control functions (CTS, RTS, DSR, DTR, RI, and DCD) • Fully prioritized interrupt system controls • Internal test and loopback capabilities 61 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E The SOM includes five UART I/F routed out. UART0 Interface UART0 signals: AM437X SIGNAL NAME UART0_ CTSn[2] UART 0_ RTSn[2] UART 0_ RXD UART 0_ TXD UART 0_DCDn DESCRIPTION Valid configuration PINs UART Clear to Send UART Request to Send UART Receive Data UART Transmit Data 61 64 66 67 179 173 UART Data Carrier Detect 28 28 66 67 UART1 Interface UART1 signals: Valid configuration PINs AM437X SIGNAL DESCRIPTION NAME UART 1_ CTSn[2] [2] UART 1_ RTSn 2 UART Clear to Send 34 124 UART Request to Send 30 120 [2] UART Receive Data 38 111 [2] UART Transmit Data 36 119 UART 1_RXD UART 1_TXD 1 UART1 full modem Interface signals: AM437X SIGNAL DESCRIPTION NAME UART 1_ CTSn[2] PINs UART Clear to Send 34 UART 1_ RTSn UART Request to Send 30 UART 1_RXD[2] UART Receive Data 38 UART Transmit Data 36 UART Data Terminal Ready 15 UART1_DSRn UART Data Set Ready 23 UART 1_DCDn[2] UART Data Carrier Detect 21 UART Ring Indicator 28 [2] UART 1_TXD [2] [2] UART 1_DTRn [2] [2] UART1_RIn UART2 Interface UART2 signals: Valid configuration PINs AM437X SIGNAL DESCRIPTION NAME [2] [2] UART 2_ CTSn UART 2_ RTSn 1 2 3 4 UART Clear to Send 184 126 184 126 UART Request to Send 182 81 182 81 62 V A R - S O M - A M 4 3 UART 2_RXD[2] UART 2_TXD [2] S Y S T E M O N M O D U L E UART Receive Data 86 86 141 141 UART Transmit Data 71 71 145 145 UART3 Interface UART3 signals: AM437X SIGNAL NAME [2] UART 3_ CTSn UART 3_ RTSn[2] UART 3_RXD[2] UART 3_TXD[2] DESCRIPTION 1 123 129 52 68 UART Clear to Send UART Request to Send UART Receive Data UART Transmit Data 2 42 40 52 68 Valid configuration PINs 3 4 5 141 141 123 145 145 129 52 139 139 68 147 147 6 42 40 139 147 UART5 Interface UART5 signals: Valid configuration PINs AM437X SIGNAL DESCRIPTION NAME [2] [2] UART 5_ CTSn UART 5_ RTSn UART 5_RXD [2] UART 5_TXD[2] 1 2 3 4 5 6 UART Clear to Send 139 146 B14 139 146 B14 UART Request to Send 147 144 B13 147 144 B13 UART Receive Data 81 81 81 42 42 42 UART Transmit Data 126 126 126 40 40 40 Notes: 1. UART0 Signals are used by default as a low level debug port 2. Refer to PinMux Table 3.2 for RTS/CTS Options 3. UART3 and SOM pins 2, 4, 6 and 8 are used for on-SOM Bluetooth if enabled 63 7 8 6 4 2 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E SPI The general features of the SPI controller are: • Buffered receive/transmit data register per channel (1 word deep) • Multiple SPI word access with one channel using a FIFO • Two DMA requests per channel, one interrupt line • Single interrupt line, for multiple interrupt source events • Serial link interface supports: - Full duplex / Half duplex Multi-channel master or single channel slave operations Programmable 1-32 bit transmit/receive shift operations. Wide selection of SPI word lengths continuous from 4 to 32 bits • Up to four SPI channels • SPI word Transmit / Receive slot assignment based on round robin arbitration • SPI configuration per channel (clock definition, enable polarity and word width) • Clock generation supports: - Programmable master clock generation (operating from fixed 48-MHz functional clock input) Selectable clock phase and clock polarity per chip select. The SOM includes four SPI I/F routed out. SPI0 signals: AM437X SIGNAL NAME Valid configuration PINs DESCRIPTION 1 2 3 SPI0_SCLK SPI Clock 86 86 86 SPI0_D0 SPI Data 71 71 71 SPI0_D1 SPI Data 69 69 69 SPI0_CS0 SPI Chip Select 70 70 70 SPI0_CS1 SPI Chip Select 52 52 52 SPI0_CS2 SPI Chip Select 173 138 SPI0_CS3 SPI Chip Select 17 154 54 SPI1 signals: AM437X SIGNAL NAME Valid configuration PINs DESCRIPTION 1 2 3 4 SPI1_SCLK SPI Clock 68 68 54 54 SPI1_D0 SPI Data 61 61 92 92 SPI1_D1 SPI Data 64 64 125 125 SPI1_CS0 SPI Chip Select 124 66 66 SPI1_CS1 SPI Chip Select 120 67 67 SPI1_CS2 SPI Chip Select 167 26 26 SPI1_CS3 SPI Chip Select 109 13 64 68 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E SPI2 signals: AM437X SIGNAL NAME Valid configuration PINs DESCRIPTION 1 2 3 4 SPI2_SCLK SPI Clock 186 13 94 94 SPI2_D0 SPI Data 201 173 84 84 SPI2_D1 SPI Data 197 25 90 90 SPI2_CS0 SPI Chip Select 187 187 187 83 SPI2_CS1 SPI Chip Select SPI2_CS2 SPI Chip Select 198 198 198 SPI2_CS3 SPI Chip Select 188 188 188 SPI3 signals: AM437X SIGNAL NAME Valid configuration PINs DESCRIPTION 1 2 3 4 SPI3_SCLK SPI Clock 142 142 SPI3_D0 SPI Data 133 133 SPI3_D1 SPI Data 146 146 SPI3_CS0 SPI Chip Select SPI3_CS1 SPI Chip Select 109 137 137 109 SPI3_CS2 SPI Chip Select No No No No SPI3_CS3 SPI Chip Select No No No No QSPI The main features of the QSPI include: • Programmable divider for serial data clock generation • Six pin interface (DCLK, CS_N, DOUT, DIN, QDIN1, QDIN2) • Programmable data length (No. of bits from 1-32) • 4 external chip select signals • Support for 3-, 4- or 6-pin SPI interface - 3-pin mode uses spi_dout as inout/spi_din not used 4-pin mode for dual read uses spi_dout as in/spi_din as in 6-pin mode uses spi_dout as in/spi_din as in/spi_qdin0 as in/spi_qdin1 as in • Programmable transfer or frame size (No. of words from 1 to 4096) • Optional interrupt generation on word or frame completion • Programmable CS_N to DOUT delay from 0 to 3 DCLKs • Programmable signal polarities • Programmable active clock edge • Software controllable interface allowing for any type of SPI transfer • Control through OCP configuration port access 65 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E QSPI signals: AM437X SIGNAL NAME DESCRIPTION PINs QSPI3_CLK SPI Clock 48 QSPI_CSN SPI Chip Select 50 QSPI_D0 SPI Data 194 QSPI_D1 SPI Data 196 QSPI_D2 SPI Data 190 QSPI_D3 SPI Data 192 I2C The general features of the I2C controller are: • Compliant with Philips I2C specification version 2.1 • Supports standard mode (up to 100K bits/s) and fast mode (up to 400K bits/s). • Multimaster transmitter/slave receiver mode • Multimaster receiver/slave transmitter mode • Combined master transmit/receive and receive/transmit modes • 7-bit and 10-bit device addressing modes • Built-in 32-byte FIFO for buffered read or writes in each module • Programmable clock generation • Two DMA channels, one interrupt line The SOM includes three I2C I/F: The I2C0 is used for on SOM devices and also routed to the external connector. I2C0 signals: SIGNAL NAME I2C0_SCL I2C0_SDA DESCRIPTION I2C Clock I2C Data PIN PERIPHERAL ADDRESS 182 PMIC 0X00100100 184 EEPROM 0X1010000 CODEC 0X0011011 I2C1 signals: AM437X SIGNAL NAME DESCRIPTION I2C1_SCL I2C1_SDA Valid configuration PINs 1 2 3 4 5 I2C Clock 70 64 119 46 94 I2C Data 69 61 111 32 83 I2C2 signals: AM437X SIGNAL NAME DESCRIPTION I2C2_SCL I2C2_SDA Valid configuration PINs 1 2 3 4 5 I2C Clock T22 J24 L22 AC21 AB19 I2C Data P23 K25 K22 AB20 AC20 66 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E CAN The general features of the DCAN controller are: • Supports CAN protocol version 2.0 part A, B (ISO 11898-1) • Bit rates up to 1 MBit/s • Dual clock source • 16, 32, 64 or 128 message objects (instantiated as 64 on this device) • Individual identifier mask for each message object • Programmable FIFO mode for message objects • Programmable loop-back modes for self-test operation • Suspend mode for debug support • Software module reset • Automatic bus on after Bus-Off state by a programmable 32-bit timer • Message RAM parity check mechanism • Direct access to Message RAM during test mode • CAN Rx / Tx pins configurable as general purpose IO pins • Two interrupt lines (plus additional parity-error interrupt line) • RAM initialization • DMA suppor The SOM includes two CAN I/F.4 signals are routed to the edge connector. CAN0 signals: AM437X SIGNAL NAME DESCRIPTION DCAN0_TX DCAN0_RX Valid configuration PINs 1 2 DCAN Receive Data 66 124 DCAN Transmit Data 67 120 3 CAN1 signals: AM437X SIGNAL NAME DESCRIPTION DCAN1_TX DCAN1_RX Valid configuration PINs 1 2 3 DCAN Receive Data 141 61 111 DCAN Transmit Data 145 64 119 67 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E Analog to Digital Convertor (ADC0) The touchscreen controller and analog-to-digital converter subsystem (TSC_ADC_SS or ADC0) contains a single-channel ADC connected to an 8-to-1 analog multiplexer which operates as a general-purpose analog-to-digital converter (ADC) with optional support for interleaving touchscreen (TS) conversions for a 4-wire, 5-wire, or 8-wire resistive panel. The TSC_ADC_SS can be configured for use in one of the following applications: • 8 general-purpose ADC channels • 4-wire TSC with 4 general-purpose ADC channels • 5-wire TSC with 3 general-purpose ADC channels • 8-wire TSC The SOM routes all 8bit of ADC0 to the edge connector. ADC0 signals: SIGNAL NAME ADC0_AIN0 ADC0_AIN1 Pin# 160 155 Description Analog Input Analog Input Type A A ADC0_AIN2 152 Analog Input A ADC0_AIN3 158 Analog Input A ADC0_AIN4 162 Analog Input A ADC0_AIN5 136 Analog Input A ADC0_AIN6 156 Analog Input A ADC0_AIN7 163 Analog Input A AGND 166 Analog Negative Reference Input AP ADC0 positive /negative reference inputs, ADC0_VREFP, ADC0_VREFN should be supplied either from VDDA_ADC, GNDA_ADC Respectively or from an external source. ADC0_VREFP, ADC0_VREFN signals: SIGNAL NAME ADC0_VREFP ADC0_VREFN ADC0_VREFP+ ADC0_VREFN Pin# 164 166 Min 1.15V 0 Nom Max 1.8 0.65 1.8 Touch Screen 4-wire Touch Screen signals: ADC0 Controller Pin# Touch Panel ADC0_AIN0 160 XPUL ADC0_AIN1 155 XNUR ADC0_AIN2 152 YPLL ADC0_AIN3 158 YNLR 68 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E • Touchscreen Resistance: 6 kOHm max. • Drive Current: 25 mA max. • Pen Touch Detect: 2 kOHm max. Analog Inputs • Full-scale Input Range: 1.8V • Differential Non-Linearity (DNL): ±1LSB • Integral Non-Linearity (INL): ±2LSB • Gain Error: ±2LSB • Offset Error: ±2LSB • Sampling Rate: 800KSPS • Conversion Time: 15 Clock Cycles Analog to Digital Convertor inputs signals: SIGNAL NAME Pin# Description Type ADC0_AIN4 162 Analog Input A ADC0_AIN5 136 Analog Input A ADC0_AIN6 156 Analog Input A ADC0_AIN7 163 A AGND 166 Analog Input Analog Negative Reference Input 69 AP V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E General Purpose I/O The SOM provides IO pins which can be used as GPIOs. GPIO signals: SIGNAL NAME GPIO0_2 GPIO0_2 GPIO0_3 GPIO0_3 GPIO0_4 GPIO0_5 GPIO0_6 GPIO0_7 GPIO0_8 GPIO0_9 GPIO0_10 GPIO0_11 GPIO0_12 GPIO0_13 GPIO0_14 GPIO0_15 GPIO0_18 GPIO0_18 GPIO0_19 GPIO0_20 GPIO0_21 GPIO0_22 GPIO0_23 GPIO0_25 GPIO0_30[1] GPIO0_31[1] GPIO1_0[1] GPIO1_1[1] GPIO1_2[1] GPIO1_3[1] GPIO1_4[1] GPIO1_5[1] GPIO1_6[1] GPIO1_7[1] GPIO1_8 GPIO1_9 GPIO1_10 GPIO1_11 GPIO1_12[1] PIN# BALL# 62 86 71 60 69 70 52 68 142 133 146 144 124 120 111 119 98 117 122 84 90 94 83 65 131 151 195 193 191 189 177 181 183 169 61 64 66 67 116 M25 P23 T22 L24 T21 T20 R25 G24 C19 D19 C17 D17 K22 L22 K21 L21 G21 L23 K23 P22 P20 N20 T23 F25 A2 B3 B5 A5 B6 A6 B7 A7 C8 B8 L25 J25 K25 J24 E11 SIGNAL NAME GPIO1_22 GPIO1_23 GPIO1_24 GPIO1_25 GPIO1_26 GPIO1_27 GPIO2_2[1] GPIO2_3[1] GPIO2_4[1] GPIO2_5[1] GPIO2_6 GPIO2_7 GPIO2_8 GPIO2_9 GPIO2_10 GPIO2_11 GPIO2_12 GPIO2_13 GPIO2_14 GPIO2_15 GPIO2_16 GPIO2_17 GPIO2_22 GPIO2_23 GPIO2_24 GPIO2_25 GPIO2_26 GPIO2_27 GPIO2_28 GPIO2_29 GPIO2_30 GPIO2_31 GPIO3_5 GPIO3_6 GPIO3_13 GPIO3_14 GPIO3_15 GPIO3_16 GPIO3_17 PIN# BALL# 9 12 22 20 18 16 154 138 167 109 75 80 77 132 82 79 127 128 126 81 123 129 74 73 78 76 143 140 139 147 141 145 184 182 65 54 92 125 58 70 E8 F6 F7 B4 G8 D8 A9 E10 D10 C10 B22 A21 B21 C21 A20 B20 C20 E19 A19 B19 A18 B18 B23 A23 A22 A24 B1 B2 C2 C1 D1 D2 AB24 Y22 F25 N24 N22 H23 M24 SIGNAL NAME GPIO4_1 GPIO4_2 GPIO4_3 GPIO4_4 GPIO4_5 GPIO4_6 GPIO4_7 GPIO4_8 GPIO4_9 GPIO4_10 GPIO4_11 GPIO4_12 GPIO4_13 GPIO4_14 GPIO4_15 GPIO4_16 GPIO4_17 GPIO4_18 GPIO4_19 GPIO4_20 GPIO4_21 GPIO4_24 GPIO4_25 GPIO4_26 GPIO4_27 GPIO4_28 GPIO4_29 GPIO5_0 GPIO5_1 GPIO5_2 GPIO5_3 GPIO5_4 GPIO5_5 GPIO5_6 GPIO5_8 GPIO5_9 GPIO5_13 GPIO5_19 GPIO5_20 PIN# BALL# 197 186 201 187 198 188 179 173 17 26 13 27 25 38 36 34 30 28 23 21 15 48 50 194 196 190 192 8 6 4 2 56 148 149 114 63 115 32 46 AD18 AC18 AD17 AC20 AB19 AA19 AC24 AD24 AD25 AC23 AE21 AC25 AB25 AB20 AC21 AD21 AE22 AD22 AE23 AD23 AE24 Y18 AA18 AE19 AD19 AE20 AD20 H22 K24 H25 H24 P25 R24 P24 D25 F24 E24 AE18 AB18 V A R - S O M - A M 4 3 GPIO1_13[1] GPIO1_14[1] GPIO1_15[1] GPIO1_16 GPIO1_17 GPIO1_18 GPIO1_19 GPIO1_20 GPIO1_21 150 135 137 11 14 7 5 3 1 S Y S T E M C11 B11 A11 C3 C5 C6 A4 D7 E7 O N M O D U L E GPIO3_18 GPIO3_19 GPIO3_20 GPIO3_21 GPIO3_22 GPIO3_23 GPIO3_24 GPIO3_25 GPIO4_0 117 122 62 60 84 90 94 83 199 L23 K23 M25 L24 P22 P20 N20 T23 AE17 GPIO5_23 GPIO5_24 GPIO5_27 GPIO5_30[1] GPIO5_31 149 148 98 131 151 D11 F11 G21 A2 B3 [1]Note: The following pins are GPMC Bus signal internally used and routed to the external connector. They can be configured and used as GPIOs only when NAND is not in use. PWM0 The SOM uses PWM0 output for control the LCD backlight. PWM0 signals: AM437X SIGNAL NAME AM437X_LCD_BACKLIGHT ZDN BALL # G24 DESCRIPTION Auxiliary PWM0 output 71 PIN# 68 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E General System Control Boot Options Boot Mode is selected via Boot. Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin: - DSS_DATA[15:0] terminals are respectively SYSBOOT[15:0] inputs. - DSS_VSYNC terminal is SYSBOOT[16] input. - DSS_HSYNC terminal is SYSBOOT[17] input. - DSS_AC_BIAS_EN is SYSBOOT[18] input. All the pins routed out for SYSTEM BOOT configuration on the rising edge of PWRONRSTn. Boot Sequence configuration signals: Configuration PINS Value Description 0 0 0 0 0 b SYSBOOT [4:0] 0 0 0 0 1 b 0 0 1 0 0 B SYSBOOT [5] 1b SYSBOOT [6] 0b SYSBOOT [7] SYSBOOT [8] SYSBOOT [9] SYSBOOT [11] SYSBOOT [13:12] SYSBOOT [15:14] SYSBOOT [17] SYSBOOT [18] 0b 0b 0b 1b 00b 01b 1b 0b BOOT_SEQUENCE: NAND,USB1,MMC0,USB0 BOOT_SEQUENCE: MMC0,MMC1,USB1,USB0 BOOT_SEQUENCE: MMC1,MMC0,USB1,USB0 0b-MII, 1b-RMII 0b-ECC DONE BY ROM, 1b-ECC DONE BY NAND DON'T CARE FOR NAND – WAIT MUX OPTION 0 DON'T CARE 1B – MUXED DEVICE 00b- SET FOR NORMAL OPERATION 24MHZ CLOCK 1b- CLKOUT1 ENABLE (TO CODEC 12MHZ) System Control The signal AM437X_PORZn reset input of the SOM. The signal SYS_RESETn produce reset to all internal SOM and external devices in case program reset or manual reset from AM437X_PORZn Power Control signals: SIGNAL NAME TPS65218 and AM437x pins AM437X_PORZN Y23, 8 LOWPWR_RSTN PORZ & GPIO0_24 DESCRIPTION Power on Reset. Output of PMIC and Input of SOM from External Reset. System RESET from POWER RESET and SOFTWARE sources. 72 EDGE CONNECTOR 175 171 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E PRU-ICSS PRU-ICSS0 Interface PRU-ICSS0-PRU0/General Purpose Inputs Signals: SIGNAL NAME DESCRIPTION TYPE ZDN PIN PR0_PRU0_GPI0 PRU-ICSS0 PRU0 DATA IN I N24 54 PR0_PRU0_GPI1 PRU-ICSS0 PRU0 DATA IN I N22 92 PR0_PRU0_GPI10 PRU-ICSS0 PRU0 DATA IN I C2 139 PR0_PRU0_GPI11 PRU-ICSS0 PRU0 DATA IN I C1 147 PR0_PRU0_GPI12 PRU-ICSS0 PRU0 DATA IN I D1 141 PR0_PRU0_GPI13 PRU-ICSS0 PRU0 DATA IN I D2 145 PR0_PRU0_GPI14 PRU-ICSS0 PRU0 DATA IN I AC20 187 PR0_PRU0_GPI15 PRU-ICSS0 PRU0 DATA IN I AB19 198 PR0_PRU0_GPI16 I AA19 188 PR0_PRU0_GPI17 PRU-ICSS0 PRU0 DATA IN CAPTURE PRU-ICSS0ENABLE PRU0 DATA IN I AC24 179 PR0_PRU0_GPI18 PRU-ICSS0 PRU0 DATA IN I H25 4 PR0_PRU0_GPI19 PRU-ICSS0 PRU0 DATA IN I H24 2 PR0_PRU0_GPI2 PRU-ICSS0 PRU0 DATA IN I H23 125 PR0_PRU0_GPI3 PRU-ICSS0 PRU0 DATA IN I M24 58 PR0_PRU0_GPI4 PRU-ICSS0 PRU0 DATA IN I L23 117 PR0_PRU0_GPI5 PRU-ICSS0 PRU0 DATA IN I K23 122 PR0_PRU0_GPI6 PRU-ICSS0 PRU0 DATA IN I M25 62 PR0_PRU0_GPI7 PRU-ICSS0 PRU0 DATA IN I L24 60 PR0_PRU0_GPI8 PRU-ICSS0 PRU0 DATA IN I B1 143 PR0_PRU0_GPI9 PRU-ICSS0 PRU0 DATA IN I B2 140 PRU-ICSS0-PRU0/General Purpose Outputs Signals: SIGNAL NAME DESCRIPTION TYPE ZDN PIN PR0_PRU0_GPO0 PRU-ICSS0 PRU0 DATA OUT O N24 54 PR0_PRU0_GPO1 PRU-ICSS0 PRU0 DATA OUT O N22 92 PR0_PRU0_GPO10 PRU-ICSS0 PRU0 DATA OUT O C2 139 PR0_PRU0_GPO11 PRU-ICSS0 PRU0 DATA OUT O C1 147 PR0_PRU0_GPO12 PRU-ICSS0 PRU0 DATA OUT O D1 141 PR0_PRU0_GPO13 PRU-ICSS0 PRU0 DATA OUT O D2 145 PR0_PRU0_GPO14 PRU-ICSS0 PRU0 DATA OUT O AC20 187 PR0_PRU0_GPO15 PRU-ICSS0 PRU0 DATA OUT O AB19 198 PR0_PRU0_GPO16 PRU-ICSS0 PRU0 DATA OUT O AA19 188 PR0_PRU0_GPO17 PRU-ICSS0 PRU0 DATA OUT O AC24 179 PR0_PRU0_GPO18 PRU-ICSS0 PRU0 DATA OUT O H25 187 73 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E PR0_PRU0_GPO19 PRU-ICSS0 PRU0 DATA OUT O H24 2 PR0_PRU0_GPO2 PRU-ICSS0 PRU0 DATA OUT O H23 125 PR0_PRU0_GPO3 PRU-ICSS0 PRU0 DATA OUT O M24 58 PR0_PRU0_GPO4 PRU-ICSS0 PRU0 DATA OUT O L23 117 PR0_PRU0_GPO5 PRU-ICSS0 PRU0 DATA OUT O K23 122 PR0_PRU0_GPO6 PRU-ICSS0 PRU0 DATA OUT O M25 62 PR0_PRU0_GPO7 PRU-ICSS0 PRU0 DATA OUT O L24 60 PR0_PRU0_GPO8 PRU-ICSS0 PRU0 DATA OUT O B1 143 PR0_PRU0_GPO9 PRU-ICSS0 PRU0 DATA OUT O B2 140 ZDN PIN AD24 173 PRU-ICSS0-PRU1/General Purpose Inputs Signals: SIGNAL NAME DESCRIPTION PR0_PRU1_GPI0 PRU-ICSS0 PRU1 DATA IN TYPE I[3] PR0_PRU1_GPI1 PRU-ICSS0 PRU1 DATA IN I AD25 17 PR0_PRU1_GPI10 PRU-ICSS0 PRU1 DATA IN I AD21 34 PR0_PRU1_GPI11 PRU-ICSS0 PRU1 DATA IN I AE22 30 PR0_PRU1_GPI12 PRU-ICSS0 PRU1 DATA IN I AD22 28 PR0_PRU1_GPI13 PRU-ICSS0 PRU1 DATA IN I AE23 23 PR0_PRU1_GPI14 PRU-ICSS0 PRU1 DATA IN I AD23 21 PR0_PRU1_GPI15 PRU-ICSS0 PRU1 DATA IN I AE24 15 PR0_PRU1_GPI16 I AE18 32 PR0_PRU1_GPI17 PRU-ICSS0 PRU1 DATA IN CAPTURE ENABLE PRU-ICSS0 PRU1 DATA IN I AB18 46 PR0_PRU1_GPI18 PRU-ICSS0 PRU1 DATA IN I H22 8 PR0_PRU1_GPI19 PRU-ICSS0 PRU1 DATA IN I K24 6 PR0_PRU1_GPI2 PRU-ICSS0 PRU1 DATA IN I AC23 26 PR0_PRU1_GPI3 PRU-ICSS0 PRU1 DATA IN I AE21 13 PR0_PRU1_GPI4 PRU-ICSS0 PRU1 DATA IN I K25 66 PR0_PRU1_GPI5 PRU-ICSS0 PRU1 DATA IN I J24 67 PR0_PRU1_GPI6 PRU-ICSS0 PRU1 DATA IN I B23 74 PR0_PRU1_GPI7 PRU-ICSS0 PRU1 DATA IN I A23 73 PR0_PRU1_GPI8 PRU-ICSS0 PRU1 DATA IN I A22 78 PR0_PRU1_GPI9 PRU-ICSS0 PRU1 DATA IN I A24 76 PRU-ICSS0-PRU1/General Purpose Outputs Signals: SIGNAL NAME DESCRIPTION TYPE ZDN PIN PR0_PRU1_GPO0 PRU-ICSS0 PRU1 DATA OUT O AD24 173 PR0_PRU1_GPO1 PRU-ICSS0 PRU1 DATA OUT O AD25 17 PR0_PRU1_GPO10 PRU-ICSS0 PRU1 DATA OUT O AD21 34 74 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E PR0_PRU1_GPO11 PRU-ICSS0 PRU1 DATA OUT O AE22 30 PR0_PRU1_GPO12 PRU-ICSS0 PRU1 DATA OUT O AD22 28 PR0_PRU1_GPO13 PRU-ICSS0 PRU1 DATA OUT O AE23 23 PR0_PRU1_GPO14 PRU-ICSS0 PRU1 DATA OUT O AD23 21 PR0_PRU1_GPO15 PRU-ICSS0 PRU1 DATA OUT O AE24 15 PR0_PRU1_GPO16 PRU-ICSS0 PRU1 DATA OUT O AE18 32 PR0_PRU1_GPO17 PRU-ICSS0 PRU1 DATA OUT O AB18 46 PR0_PRU1_GPO18 PRU-ICSS0 PRU1 DATA OUT O H22 8 PR0_PRU1_GPO19 PRU-ICSS0 PRU1 DATA OUT O K24 6 PR0_PRU1_GPO2 PRU-ICSS0 PRU1 DATA OUT O AC23 26 PR0_PRU1_GPO3 PRU-ICSS0 PRU1 DATA OUT O AE21 13 PR0_PRU1_GPO4 PRU-ICSS0 PRU1 DATA OUT O K25 66 PR0_PRU1_GPO5 PRU-ICSS0 PRU1 DATA OUT O J24 67 PR0_PRU1_GPO6 PRU-ICSS0 PRU1 DATA OUT O B23 74 PR0_PRU1_GPO7 PRU-ICSS0 PRU1 DATA OUT O A23 73 PR0_PRU1_GPO8 PRU-ICSS0 PRU1 DATA OUT O A22 78 PR0_PRU1_GPO9 PRU-ICSS0 PRU1 DATA OUT O A24 76 SIGNAL NAME DESCRIPTION TYPE ZDN PIN PR0_UART0_CTS_N UART CLEAR TO SEND I P23 86 PR0_UART0_RTS_N UART REQUEST TO SEND O T22 71 PR0_UART0_RXD UART RECEIVE DATA I T21 69 PR0_UART0_TXD UART TRANSMIT DATA O T20 70 PRU-ICSS0/UART0 Signals: PRU-ICSS1 Interface PRU-ICSS1-PRU0/General Purpose Inputs Signals: SIGNAL NAME DESCRIPTION TYPE ZDN PIN PR1_PRU0_GPI0 PRU-ICSS1 PRU0 DATA IN I B22 75 PR1_PRU0_GPI1 PRU-ICSS1 PRU0 DATA IN I A21 80 PR1_PRU0_GPI10 PRU-ICSS1 PRU0 DATA IN I E11 116 PR1_PRU0_GPI11 PRU-ICSS1 PRU0 DATA IN I C11 150 PR1_PRU0_GPI16 PRU-ICSS1 PRU0 DATA IN CAPTURE ENABLE I B11, C24, D24, K21, L21 111, 119, 135, PR1_PRU0_GPI2 PRU-ICSS1 PRU0 DATA IN I B21 77 PR1_PRU0_GPI3 PRU-ICSS1 PRU0 DATA IN I C21 132 PR1_PRU0_GPI4 PRU-ICSS1 PRU0 DATA IN I A20 82 PR1_PRU0_GPI5 PRU-ICSS1 PRU0 DATA IN I B20 79 75 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E PR1_PRU0_GPI6 PRU-ICSS1 PRU0 DATA IN I C20 127 PR1_PRU0_GPI7 PRU-ICSS1 PRU0 DATA IN I E19 128 PR1_PRU0_GPI8 PRU-ICSS1 PRU0 DATA IN I B9 NO PR1_PRU0_GPI9 PRU-ICSS1 PRU0 DATA IN I F10 NO PRU-ICSS1-PRU0/General Purpose Outputs Signals: SIGNAL NAME DESCRIPTION TYPE ZDN PIN PR1_PRU0_GPO0 PRU-ICSS1 PRU0 DATA OUT O B22 75 PR1_PRU0_GPO1 PRU-ICSS1 PRU0 DATA OUT O A21 80 PR1_PRU0_GPO10 PRU-ICSS1 PRU0 DATA OUT O E11 116 PR1_PRU0_GPO11 PRU-ICSS1 PRU0 DATA OUT O C11 150 PR1_PRU0_GPO2 PRU-ICSS1 PRU0 DATA OUT O B21 77 PR1_PRU0_GPO3 PRU-ICSS1 PRU0 DATA OUT O C21 132 PR1_PRU0_GPO4 PRU-ICSS1 PRU0 DATA OUT O A20 82 PR1_PRU0_GPO5 PRU-ICSS1 PRU0 DATA OUT O B20 79 PR1_PRU0_GPO6 PRU-ICSS1 PRU0 DATA OUT O C20 127 PR1_PRU0_GPO7 PRU-ICSS1 PRU0 DATA OUT O E19 128 PR1_PRU0_GPO8 PRU-ICSS1 PRU0 DATA OUT O B9 NO PR1_PRU0_GPO9 PRU-ICSS1 PRU0 DATA OUT O F10 NO SIGNAL NAME DESCRIPTION TYPE PR1_ECAP0_ECAP_CAP IN_APWM_O ENHANCED CAPTURE INPUT OR AUXILIARY PWM OUT IO SIGNAL NAME DESCRIPTION PR1_EDC_LATCH0_IN DATA IN TYPE I[3] AE22, K22 30, 124 PR1_EDC_LATCH1_IN DATA IN I AD22, L22 28, 120 PR1_EDC_SYNC0_OUT DATA OUT O L25 61 PR1_EDC_SYNC1_OUT DATA OUT O J25 64 PR1_EDIO_DATA_IN0 DATA IN I AD23 21 PR1_EDIO_DATA_IN1 DATA IN I AE24 15 PR1_EDIO_DATA_IN2 DATA IN I B23 74 PR1_EDIO_DATA_IN3 DATA IN I A23 73 PR1_EDIO_DATA_IN4 DATA IN I A22 78 PR1_EDIO_DATA_IN5 DATA IN I A24 76 PR1_EDIO_DATA_IN6 DATA IN I B9, C20 120 PR1_EDIO_DATA_IN7 DATA IN I E19 128 PR1_EDIO_DATA_OUT 0 PR1_EDIO_DATA_OUT DATA OUT O T21 69 DATA OUT O T20 70 PRU-ICSS1/eCAP Signal: ZDN A11, G24 137, 68 PRU-ICSS1/ECAT Signal: 1 76 ZDN PIN V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E PR1_EDIO_DATA_OUT 2 PR1_EDIO_DATA_OUT DATA OUT O B23 74 DATA OUT O A23 73 3 PR1_EDIO_DATA_OUT 4 PR1_EDIO_DATA_OUT DATA OUT O A22 78 DATA OUT O A24 76 5 PR1_EDIO_DATA_OUT 6 PR1_EDIO_DATA_OUT DATA OUT O B9, C20 120 DATA OUT O E19 128 7 PR1_EDIO_LATCH_IN LATCH IN I AE23 23 PR1_EDIO_OUTVALID DATA OUT VALID O AD18 197 PR1_EDIO_SOF START OF FRAME O AB25, AE17 25,199 SIGNAL NAME DESCRIPTION TYPE ZDN PIN PR1_MDIO_DATA MDIO DATA IO A17 42 PR1_MDIO_MDCLK MDIO CLK O B17 40 SIGNAL NAME DESCRIPTION TYPE PR1_MII0_COL MII COLLISION DETECT I D25 114 PR1_MII0_CRS MII CARRIER SENSE I B12, G20 NO PR1_MII0_RXD0 MII RECEIVE DATA BIT 0 I B18 129 PR1_MII0_RXD1 MII RECEIVE DATA BIT 1 I A18 123 PR1_MII0_RXD2 MII RECEIVE DATA BIT 2 I B19 81 PR1_MII0_RXD3 MII RECEIVE DATA BIT 3 I A19 126 PR1_MII0_RXDV MII RECEIVE DATA VALID I D17 144 PR1_MII0_RXER MII RECEIVE DATA ERROR I D19 133 PR1_MII0_RXLINK MII RECEIVE LINK I C19 142 PR1_MII0_TXD0 MII TRANSMIT DATA BIT 0 O B11, B20 135, 79 PR1_MII0_TXD1 MII TRANSMIT DATA BIT 1 O A20, C11 82, 150 PR1_MII0_TXD2 MII TRANSMIT DATA BIT 2 O C21, E11 PR1_MII0_TXD3 MII TRANSMIT DATA BIT 3 O B21, D11 132, 116 77 PR1_MII0_TXEN MII TRANSMIT ENABLE O A21, F11 80 PR1_MII_MR0_CLK MII RECEIVE CLOCK I C17 146 PR1_MII_MT0_CLK MII TRANSMIT CLOCK I B10, B22 75 SIGNAL NAME DESCRIPTION TYPE ZDN PIN PR1_MII1_COL MII COLLISION DETECT I F24 63 PR1_MII1_CRS MII CARRIER SENSE I A2 131 PR1_MII1_RXD0 MII RECEIVE DATA BIT 0 I D8 16 PR1_MII1_RXD1 MII RECEIVE DATA BIT 1 I G8 18 PRU-ICSS1/MDIO Signal: PRU-ICSS1/MII0 Signals: ZDN PIN PRU-ICSS1/MII1 Signals: 77 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E PR1_MII1_RXD2 MII RECEIVE DATA BIT 2 I B4 20 PR1_MII1_RXD3 MII RECEIVE DATA BIT 3 I F7 22 PR1_MII1_RXDV MII RECEIVE DATA VALID I C5 14 PR1_MII1_RXER MII RECEIVE DATA ERROR I B3 151 PR1_MII1_RXLINK MII RECEIVE LINK I C10,E24 PR1_MII1_TXD0 MII TRANSMIT DATA BIT 0 O E7 109,115 5 1 PR1_MII1_TXD1 MII TRANSMIT DATA BIT 1 O D7 3 PR1_MII1_TXD2 MII TRANSMIT DATA BIT 2 O A4 5 PR1_MII1_TXD3 MII TRANSMIT DATA BIT 3 O C6 7 PR1_MII1_TXEN MII TRANSMIT ENABLE O C3 11 PR1_MII_MR1_CLK MII RECEIVE CLOCK I F6 12 PR1_MII_MT1_CLK MII TRANSMIT CLOCK I E8 9 SIGNAL NAME DESCRIPTION TYPE ZDN PIN PR1_UART0_CTS_N UART CLEAR TO SEND I K22, P23 124, 86 PR1_UART0_RTS_N UART REQUEST TO SEND O L22, T22 120, 71 PR1_UART0_RXD UART RECEIVE DATA I K21, T21 111, 69 PR1_UART0_TXD UART TRANSMIT DATA O L21, T20 119, 70 PRU-ICSS1/UART0 Signals: 78 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E JTAG The SoM includes JTAG interface to provide a debug and test control. Seven signals are routed from the APQ directly to J4 (1.27 pitch 5x2 pin header Sullins P/N: GRPB052VWVN-RC or compatible). JTAG Signals: AM437x SIGNAL NAME Ground Power JTAG PIN# 1 ZDN BALL GND DESCRIPTION JTAG_TRSTN Y25 JTAG TEST RESET (ACTIVE LOW) 2 JTAG_EMU0 JTAG_TMS GND JTAG_TDI JTAG_EMU1 JTAG_TCK N23 Y24 Y20 T24 AA25 MISC EMULATION PIN JTAG TEST MODE SELECT Ground Power JTAG TEST DATA INPUT MISC EMULATION PIN JTAG TEST CLOCK 3 4 5 6 7 8 SYS_RESETn G22 System Reset 9 JTAG_TDO AA24 JTAG TEST DATA OUTPUT 10 Wi-Fi and Bluetooth The VAR-SOM-AM43 contains a certified high performance WL183xMOD 2.4/5 GHz IEEE 802.11 a/b/g/n Bluetooth 4.0 + BLE module. The module has two antennas connections through U.FL JACK connectors. Antenna cable connected to module must have 50-Ω impedance. 79 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E Power Power Supply pins Power Signals: SIGNAL NAME TPS65218 and AM437x pins VDDA_ADC AB12 Power input for PMIC VIN and V3_3SW voltage VDDSHV9, VDDSHV11Power domains Output voltage ADC0 Power supply Output ADC0_VREFP AD14 Analog Positive Reference Input VBAT VDDSHV11 H8,H9,H11,G11 EDGE CONNECTOR 100,102,103, 104,105,107 DESCRIPTION 134 110 164 GND pins GND Pins: EDGE CONNECTOR 10,19,24,29,35,41,44,47,53,72, 85,93,96,101,106,108,118,121,130, 165,185, 200,202,203,204 SIGNAL NAME TYPE DESCRIPTION GND Ground Power Power AGND_AUD Audio Ground Reference GND for audio signals 170 ADC0 Analog Ground 112 Analog Negative Reference Input 166 GNDA_ADC ADC0_VREFN ADC0 Analog Ground ADC0 Analog Ground Reference Absolute Maximum Characteristics SIGNAL NAME Min Main Power Supply, VBAT Typ Max Unit 3.8 V -0.3 3.3 Digital IOs: -0.5V 1.8, 3.3 VIO + 0.3 V V Analog IOs: -0.5V 1.8 V1.8D + 0.3V V ADC0_VREFP 164 1.15V 1.8 V ADC0_VREFN 166 0 0.65 V 80 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E Operating Characteristics Normal Operational Conditions Unless otherwise specified, all DC and AC specifications in this data sheet are valid for the following voltages and temperature ranges. Parameter Symbol Min. Typical Max. Units Input Power Supply 3.3V 3.15 3.3 3.45 VDC Power Consumption Min Typ Max Unit Main Power Supply – Excluding Wi-Fi 4.95 W Wi-Fi transmit 1.0 W Gbit Ethernet 0.4 W Max Unit DC Electrical Characteristics Min Parameter Typ LVCMOS pins (VDDSHVx = 3.3 V; x=1-11) 1.17 VIH VIL V 0.63 VOH 1.35 V VOL 0.45 LVCMOS pins (VDDSHVx = 1.8 V; x=1-11) 2 VIH VIL V V 0.8 VOH V 2.85 V V VOL 0.45 V 1.8 V Max Unit Analog IOs: AIN 0-7 VDC 0 EXCEPTIONS Min Typ TCK (VDDSHV3 = 3.3 V) 2.15 VIH VIL V 0.46 81 V V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E VHYS 0.4 V 1.35 V PWRONRSTn (VDDSHV3 = 1.8 V or 3.3 V)(1) VIH VIL 0.5 VHYS 0.07 Parameter V V Min Typ Max Unit Voltage range for USB VBUS comparator input 0.000 5.000 5.250 V USB1_VBUS Voltage range for USB VBUS comparator input 0.000 5.000 5.250 V USB0_ID Voltage range for the USB ID input (1) V USB1_ID Voltage range for the USB ID input (1) V SUPPLY NAME DESCRIPTION USB0_VBUS (1) This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring the voltage to determine if the terminal is connected to VSSA_USB with a resistance less than 10 Ω or greater than 100 kΩ. The terminal should be connected to ground for USB host operation or open-circuit for USB peripheral operation, and should never be connected to any external voltage source. 82 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E Environmental Specifications Parameter MIN MAX Commercial Operating temperature 0°C +70 °C Extended Operating temperature -20°C +70 °C Industrial Operating temperature -40°C +85 °C Referring MIL-HDBK-217F-2 Parts Count Reliability Prediction Method Model: 50Deg Celsius, Class B-1, GM 50Deg Celsius, Class B-1, GB 121 Khrs > 1400 Khrs > Shock Resistance 50G/20 ms Vibration 20G/0 - 600 Hz Note: Extended and Industrial Temperature is only based on the operating temperature grade of the SoM components. Customer should consider specific thermal design for the final product based upon the specific environmental and operational conditions. 83 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E Mechanical Specifications Drawing CAD file are available for download at http://www.variscite.com/ 84 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E SoM Fastening For extra mechanical strength, required for operating in extreme vibration & shock conditions, The VAR-SOM-AM43 can be fasten to the carrier board, using the two mechanical holes. All the holes are to be located symmetrically. The holes plated inside and connected to GND. In TOP side a pad has diameter 180mil (accordance to top of screw). In BOTTOM side a pad has diameter 244mil (according to STANDOFF). A drill diameter 85mil. The STANDOFF has good thermal and electrical conductivity. It help for the SOM cooling, good GND connection and reduce EMI. Part Standoff Screw Washer Washer Description SMT SPACER M2x0.4mm, H=3mm M2x0.4mm, length = 4mm FLAT M2 STEEL SPLIT LOCK M2 STEEL Manufacturer, PN PennEngineering, P/N: SMTSO-M2-3-ET Essentra Components, NSE-1207-M2-4 B&F Fastener Supply, MFWZ 002 B&F Fastener Supply, MLWZ 002 Literature 1. AM437x ARM® Cortex™-A9 Microprocessors (MPUs), (literature number SPRS851) 2. AM437x ARM® Cortex™-A9 Microprocessors (MPUs) Technical Reference Manual (literature Number: SPRUHL7) RoHS compliance VAR-SOM-AM43 System-on-Module complies with the European Union Restriction on Use of Hazardous Substance Directive 2002/95/EC (“RoHS 1”), Directive 2011/65/EU (“RoHS 2”) as well as the China Management Methods for controlling Pollution by Electronic information Products (“China RoHS”) as defined and detailed inVariscite’s website: http://www.variscite.com/company/product-compliance-policy 85 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E Ordering Information Please refer to www.variscite.com Warranty Terms Variscite guarantees hardware products against defects in workmanship and material for a period of one (1) year from the date of shipment. Your sole remedy and Variscite’s sole liability shall be for Variscite, at its sole discretion, to either repair or replace the defective hardware product at no charge or to refund the purchase price. Shipment costs in both directions are the responsibility of the customer. This warranty is void if the hardware product has been altered or damaged by accident, misuse or abuse. Disclaimer of Warranty THIS WARRANTY IS MADE IN LIEU OF ANY OTHER WARRANTY, WHETHER EXPRESSED, OR IMPLIED, OF MERCHANTABILITY, FITNESS FOR A SPECIFIC PURPOSE, NON-INFRINGEMENT OR THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION, EXCEPT THE WARRANTY EXPRESSLY STATED HEREIN. THE REMEDIES SET FORTH HEREIN SHALL BE THE SOLE AND EXCLUSIVE REMEDIES OF ANY PURCHASER WITH RESPECT TO ANY DEFECTIVE PRODUCT. Limitation on Liability UNDER NO CIRCUMSTANCES SHALL VARISCITE BE LIABLE FOR ANY LOSS, DAMAGE OR EXPENSE SUFFERED OR INCURRED WITH RESPECT TO ANY DEFECTIVE PRODUCT. IN NO EVENT SHALL VARISCITE BE LIABLE FOR ANY INCIDENTAL OR CONSEQUENTIAL DAMAGES THAT YOU MAY SUFFER DIRECTLY OR INDIRECTLY FROM USE OF ANY PRODUCT. 86 V A R - S O M - A M 4 3 S Y S T E M O N M O D U L E About Variscite For over a decade Variscite has developed, produced and manufactured a powerful range of System on Modules, consistently setting market benchmarks in terms of speed and innovation. The company's portfolio is based on leading SoC vendors including Texas Instruments, Freescale, and Marvell. All Variscite production is performed at fully ISO 13485 compliant facilities, satisfying international customer and regulatory requirements for a broad range of industries including medical devices and related services. The company's production facilities are equipped with the most advanced SMT machines that ensure punctual deliveries and high quality products. Having first entered the embedded market in 2003 with specialized designs for a variety of industrial applications, Variscite has continued to innovate and be first-to-market. Just some System on Module launch highlights include the release of the first Cortex-A8 SOM back in 2009 and on 2011, Breaking the speed record again with the first TI OMAP4460-based, 1.5GHz CortexA9 System on Module. It's no surprise that within a decade Variscite has taken a leading position in the design and manufacture of system on modules. Variscite serves more than 1,500 customers in over 50 countries worldwide, delivering a cost effective, high performance portfolio that combines interface flexibility with advanced power management. A trusted provider of development and consulting services for a variety of embedded platforms, Variscite transforms clients' visions into successful products. Our Mission To innovate with future-proof solutions, well ahead of the market To provide comprehensive, rapid and premier technical support throughout the design cycle To deliver a one-stop-shop for total System on Module solutions and design services Contact Information Headquarters: Variscite Ltd. 4, Hamelacha St. Lod. P.O.B 1121 Airport City, 70100 ISRAEL phone +972 (9) 9562910 fax +972 (9) 9589477 email [email protected] sales [email protected] technical support [email protected] 87