ILI9341 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Specification Version: V1.10 Document No.: ILI9341_DS_V1.10.pdf ILI TECHNOLOGY CORP. 8F, No. 38, Taiyuan St., Jhubei City, Hsinchu Country 302 Taiwan R.O.C. Tel.886-3-5600099; Fax.886-3-5670585 http://www.ilitek.com a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 Table of Contents Section Page 1. Introduction.................................................................................................................................................... 7 2. Features ........................................................................................................................................................ 7 3. Block Diagram ............................................................................................................................................... 9 4. Pin Descriptions .......................................................................................................................................... 10 5. Pad Arrangement and Coordination............................................................................................................ 15 6. Block Function Description.......................................................................................................................... 24 7. Function Description ................................................................................................................................... 26 7.1. MCU interfaces .............................................................................................................................. 26 7.1.1. MCU interface selection ...................................................................................................... 26 7.1.2. 8080- 7.1.3. Write Cycle Sequence ......................................................................................................... 28 7.1.4. Read Cycle Sequence......................................................................................................... 29 7.1.5. 8080- 7.1.6. Write Cycle Sequence ......................................................................................................... 31 7.1.7. Read Cycle Sequence......................................................................................................... 32 7.1.8. Serial Interface .................................................................................................................... 33 7.1.9. Write Cycle Sequence ......................................................................................................... 33 Ⅰ Series Parallel Interface........................................................................................ 27 Ⅱ Series Parallel Interface........................................................................................ 30 7.1.10. Read Cycle Sequence......................................................................................................... 36 7.1.11. Data Transfer Break and Recovery ..................................................................................... 40 7.1.12. Data Transfer Pause............................................................................................................ 42 7.1.13. Serial Interface Pause (3_wire) ........................................................................................... 43 7.1.14. Parallel Interface Pause ...................................................................................................... 43 7.1.15. Data Transfer Mode............................................................................................................. 44 7.1.16. Data Transfer Method 1....................................................................................................... 44 7.1.17. Data Transfer Method 2....................................................................................................... 44 7.2. RGB Interface ................................................................................................................................ 45 7.2.1. RGB Interface Selection ...................................................................................................... 45 7.2.2. RGB Interface Timing .......................................................................................................... 49 7.3. VSYNC Interface............................................................................................................................ 52 7.4. Color Depth Conversion Look Up Table......................................................................................... 55 7.5. Display Data RAM (DDRAM) ......................................................................................................... 59 7.6. Display Data Format ...................................................................................................................... 60 7.6.1. 3-line Serial Interface........................................................................................................... 60 7.6.2. 4-line Serial Interface........................................................................................................... 63 7.6.3. 8-bit Parallel MCU Interface ................................................................................................ 65 7.6.4. 9-bit Parallel MCU Interface ................................................................................................ 67 7.6.5. 16-bit Parallel MCU Interface .............................................................................................. 70 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 2 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.6.6. 18-bit Parallel MCU Interface .............................................................................................. 76 7.6.7. 6-bit Parallel RGB Interface................................................................................................. 80 7.6.8. 16-bit Parallel RGB Interface............................................................................................... 82 7.6.9. 18-bit Parallel RGB Interface............................................................................................... 82 8. Command.................................................................................................................................................... 83 8.1. Command List ................................................................................................................................ 83 8.2. Description of Level 1 Command................................................................................................... 89 8.2.1. NOP (00h)............................................................................................................................ 89 8.2.2. Software Reset (01h)........................................................................................................... 90 8.2.3. Read display identification information (04h) ...................................................................... 91 8.2.4. Read Display Status (09h)................................................................................................... 92 8.2.5. Read Display Power Mode (0Ah) ........................................................................................ 94 8.2.6. Read Display MADCTL (0Bh).............................................................................................. 95 8.2.7. Read Display Pixel Format (0Ch) ........................................................................................ 96 8.2.8. Read Display Image Format (0Dh)...................................................................................... 97 8.2.9. Read Display Signal Mode (0Eh) ........................................................................................ 98 8.2.10. Read Display Self-Diagnostic Result (0Fh) ......................................................................... 99 8.2.11. Enter Sleep Mode (10h) .................................................................................................... 100 8.2.12. Sleep Out (11h).................................................................................................................. 101 8.2.13. Partial Mode ON (12h)....................................................................................................... 103 8.2.14. Normal Display Mode ON (13h) ........................................................................................ 104 8.2.15. Display Inversion OFF (20h).............................................................................................. 105 8.2.16. Display Inversion ON (21h) ............................................................................................... 106 8.2.17. Gamma Set (26h) .............................................................................................................. 107 8.2.18. Display OFF (28h) ............................................................................................................. 108 8.2.19. Display ON (29h) ............................................................................................................... 109 8.2.20. Column Address Set (2Ah) ................................................................................................ 110 8.2.21. Page Address Set (2Bh) .................................................................................................... 112 8.2.22. Memory Write (2Ch) .......................................................................................................... 114 8.2.23. Color Set (2Dh).................................................................................................................. 115 8.2.24. Memory Read (2Eh) .......................................................................................................... 116 8.2.25. Partial Area (30h)............................................................................................................... 118 8.2.26. Vertical Scrolling Definition (33h) ...................................................................................... 120 8.2.27. Tearing Effect Line OFF (34h) ........................................................................................... 124 8.2.28. Tearing Effect Line ON (35h) ............................................................................................. 125 8.2.29. Memory Access Control (36h) ........................................................................................... 127 8.2.30. Vertical Scrolling Start Address (37h) ................................................................................ 129 8.2.31. Idle Mode OFF (38h) ......................................................................................................... 131 8.2.32. Idle Mode ON (39h) ........................................................................................................... 132 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 3 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.33. COLMOD: Pixel Format Set (3Ah) .................................................................................... 134 8.2.34. Write_Memory_Continue (3Ch)......................................................................................... 135 8.2.35. Read_Memory_Continue (3Eh)......................................................................................... 137 8.2.36. Set_Tear_Scanline (44h) ................................................................................................... 139 8.2.37. Get_Scanline (45h)............................................................................................................ 140 8.2.38. Write Display Brightness (51h) .......................................................................................... 141 8.2.39. Read Display Brightness (52h).......................................................................................... 142 8.2.40. Write CTRL Display (53h).................................................................................................. 143 8.2.41. Read CTRL Display (54h) ................................................................................................. 145 8.2.42. Write Content Adaptive Brightness Control (55h).............................................................. 147 8.2.43. Read Content Adaptive Brightness Control (56h) ............................................................. 148 8.2.44. Write CABC Minimum Brightness (5Eh)............................................................................ 149 8.2.45. Read CABC Minimum Brightness (5Fh)............................................................................ 150 8.2.46. Read ID1 (DAh) ................................................................................................................. 151 8.2.47. Read ID2 (DBh) ................................................................................................................. 152 8.2.48. Read ID3 (DCh) ................................................................................................................. 153 8.3. Description of Level 2 Command................................................................................................. 154 8.3.1. RGB Interface Signal Control (B0h) .................................................................................. 154 8.3.2. Frame Rate Control (In Normal Mode/Full Colors) (B1h).................................................. 155 8.3.3. Frame Rate Control (In Idle Mode/8 colors) (B2h) ............................................................ 157 8.3.4. Frame Rate control (In Partial Mode/Full Colors) (B3h) .................................................... 159 8.3.5. Display Inversion Control (B4h)......................................................................................... 161 8.3.6. Blanking Porch Control (B5h) ............................................................................................ 162 8.3.7. Display Function Control (B6h).......................................................................................... 164 8.3.8. Entry Mode Set (B7h) ........................................................................................................ 168 8.3.9. Backlight Control 1 (B8h)................................................................................................... 169 8.3.10. Backlight Control 2 (B9h)................................................................................................... 170 8.3.11. Backlight Control 3 (BAh) .................................................................................................. 172 8.3.12. Backlight Control 4 (BBh) .................................................................................................. 173 8.3.13. Backlight Control 5 (BCh) .................................................................................................. 175 8.3.14. Backlight Control 7 (BEh) .................................................................................................. 176 8.3.15. Backlight Control 8 (BFh) .................................................................................................. 177 8.3.16. Power Control 1 (C0h)....................................................................................................... 178 8.3.17. Power Control 2 (C1h)....................................................................................................... 179 8.3.18. VCOM Control 1(C5h) ....................................................................................................... 180 8.3.19. VCOM Control 2(C7h) ....................................................................................................... 182 8.3.20. NV Memory Write (D0h) .................................................................................................... 184 8.3.21. NV Memory Protection Key (D1h) ..................................................................................... 185 8.3.22. NV Memory Status Read (D2h) ......................................................................................... 186 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 4 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.23. Read ID4 (D3h) ................................................................................................................. 187 8.3.24. Positive Gamma Correction (E0h)..................................................................................... 188 8.3.25. Negative Gamma Correction (E1h) ................................................................................... 189 8.3.26. Digital Gamma Control 1 (E2h) ......................................................................................... 190 8.3.27. Digital Gamma Control 2(E3h) .......................................................................................... 191 8.3.28. Interface Control (F6h) ...................................................................................................... 192 8.4 Description of extend register command……………………………………………………………….195 8.4.1. Power control A (CBh)…………………………………………………………………………..195 8.4.2. Power control B (CFh)…………………………………………………………………………..196 8.4.3. Driver timing control A (E8h)……………………………………….…………………………...197 8.4.4. Driver timing control B (EAh)…………...............................................................................198 8.4.5. Power on sequence control (EDh)……………………………………………………………..199 8.4.6. Enable 3 gamma (F2h)…………………………………………………………………………..200 8.4.7. Pump ratio control (F7h)………………………………………………………………………...201 9. Display Data RAM ..................................................................................................................................... 202 9.1. Configuration ................................................................................................................................ 202 9.2. Memory to Display Address Mapping .......................................................................................... 203 9.3. 9.2.1. Normal Display ON or Partial Mode ON, Vertical Scroll Mode OFF.................................. 203 9.2.2. Vertical Scroll Mode........................................................................................................... 204 9.2.3. Vertical Scroll Example...................................................................................................... 205 9.2.4. Case1: TFA+VSA+BFA < 320 ........................................................................................... 205 9.2.5. Case2: TFA+VSA+BFA = 320 (Rolling Scrolling) .............................................................. 206 MCU to memory write/read direction ........................................................................................... 207 10. Tearing Effect Output................................................................................................................................. 209 10.1. Tearing Effect Line Modes............................................................................................................ 209 10.2. Tearing Effect Line Timings .......................................................................................................... 210 11. Sleep Out – Command and Self-Diagnostic Functions of the Display Module......................................... 211 11.1. Register loading Detection ........................................................................................................... 211 11.2. Functionality Detection................................................................................................................. 212 12. Power ON/OFF Sequence ........................................................................................................................ 213 12.1. Case 1 – RESX line is held High or Unstable by Host at Power ON ........................................... 213 12.2. Case 2 – RESX line is held Low by Host at Power ON ............................................................... 214 12.3. Uncontrolled Power Off ................................................................................................................ 215 13. Power Level Definition .............................................................................................................................. 216 13.1. Power Levels................................................................................................................................ 216 13.2. Power Flow Chart......................................................................................................................... 217 14. Gamma Curves Selection ......................................................................................................................... 218 14.1. Gamma Default Values (for NW type LC) .................................................................................... 218 14.2. Gamma Curves ............................................................................................................................ 219 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 5 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 14.2.1. Gamma Curve 1 (GC0), applies the function y=x 2.2 ILI9341 .......................................................... 219 14.3. Gamma Curves ............................................................................................................................ 220 14.3.1. Grayscale Voltage Generation........................................................................................... 220 14.3.2. Positive Gamma Correction............................................................................................... 221 14.3.3. Negative Gamma Correction ............................................................................................. 222 15. Reset ......................................................................................................................................................... 223 15.1. Registers ...................................................................................................................................... 223 15.2. Output Pins, I/O Pins.................................................................................................................... 224 15.3. Input Pins ..................................................................................................................................... 224 15.4. Reset Timing ................................................................................................................................ 225 16. Configuration of Power Supply Circuit ...................................................................................................... 226 17. NV Memory Programming Flow ................................................................................................................ 227 18. Electrical Characteristics........................................................................................................................... 229 18.1. Absolute Maximum Ratings ......................................................................................................... 229 18.2. DC Characteristics ....................................................................................................................... 230 19.2.1. General DC Characteristics............................................................................................... 230 18.3. AC Characteristics ....................................................................................................................... 232 Ⅰ system) ........... 232 19.3.2. Display Parallel 18/16/9/8-bit Interface Timing Characteristics(8080-Ⅱ system) ............ 234 19.3.1. Display Parallel 18/16/9/8-bit Interface Timing Characteristics (8080- 19.3.3. Display Serial Interface Timing Characteristics (3-line SPI system) ................................. 236 19.3.4. Display Serial Interface Timing Characteristics (4-line SPI system) ................................. 237 19.3.5. Parallel 18/16/6-bit RGB Interface Timing Characteristics ................................................ 238 19. Revision History ........................................................................................................................................ 239 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 6 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 1. Introduction ILI9341 is a 262,144-color single-chip SOC driver for a-TFT liquid crystal display with resolution of 240RGBx320 dots, comprising a 720-channel source driver, a 320-channel gate driver, 172,800 bytes GRAM for graphic display data of 240RGBx320 dots, and power supply circuit. ILI9341 supports parallel 8-/9-/16-/18-bit data bus MCU interface, 6-/16-/18-bit data bus RGB interface and 3-/4-line serial peripheral interface (SPI). The moving picture area can be specified in internal GRAM by window address function. The specified window area can be updated selectively, so that moving picture can be displayed simultaneously independent of still picture area. ILI9341 can operate with 1.65V ~ 3.3V I/O interface voltage and an incorporated voltage follower circuit to generate voltage levels for driving an LCD. ILI9341 supports full color, 8-color display mode and sleep mode for precise power control by software and these features make the ILI9341 an ideal LCD driver for medium or small size portable products such as digital cellular phones, smart phone, MP3 and PMP where long battery life is a major concern. 2. Features Display resolution: [240xRGB](H) x 320(V) Output: 720 source outputs 320 gate outputs Common electrode output (VCOM) a-TFT LCD driver with on-chip full display RAM: 172,800 bytes System Interface 8-bits, 9-bits, 16-bits, 18-bits interface with 8080- /8080- series MCU 6-bits, 16-bits, 18-bits RGB interface with graphic controller 3-line / 4-line serial interface Display mode: Full color mode (Idle mode OFF): 262K-color (selectable color depth mode by software) Reduce color mode (Idle mode ON): 8-color Power saving mode: Sleep mode On chip functions: VCOM generator and adjustment Timing generator Oscillator DC/DC converter Line/frame inversion 1 preset Gamma curve with separate RGB Gamma correction Content Adaptive Brightness Control MTP (3 times): 8-bits for ID1, ID2, ID3 7-bits for VCOM adjustment Ⅰ Ⅱ The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 7 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 Low -power consumption architecture Low operating power supplies: VDDI = 1.65V ~ 3.3V (logic) VCI = 2.5V ~ 3.3V (analog) LCD Voltage drive: Source/VCOM power supply voltage DDVDH - GND = 4.5V ~ 5.8V VCL - GND = -1.5V ~ -2.5V Gate driver output voltage VGH - GND = 10.0V ~ 16.0V VGL - GND = -5.0V ~ -10.0V VGH - VGL 28V VCOM driver output voltage VCOMH = 3.0V ~ (DDVDH – 0.2)V VCOML = (VCL+0.2)V ~ 0V VCOMH - VCOML 6.0V Operate temperature range: -40 to 85 a-Si TFT LCD storage capacitor : Cst on Common structure only ≦ ≦ ℃ ℃ The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 8 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 3. Block Diagram VDDI IM[3:0] 4 Index Register (IR) 8/9/16/18-bit MCU I/F RESX CSX 7 WRX RDX D/CX D[17:0] Control Register (CR) 18 18 3/4 Serial I/F Address Counter (AC) LCD Source Driver S720 ~ S1 TE SDA SDO HSYNC VSYNC 18 6/16/18-bit RGB I/F 18 Graphics Operation V63 ~ V0 DOTCLK DE 18 Read Latch EXTC Write Latch 18 BC BC_CTRL VDDI_LED LED Controller 18 Grayscale Reference Voltage GVDD Graphics RAM (GRAM) TREGB CABC Block DUMMYR1,2 DUMMY VCORE VSS Regulator LCD Gate Driver Timing Controller RC-OSC. G320 ~ G1 VCI VSSA VCOM Generator Charge-pump Power Circuit VCOM VGL VGH C22P C22M C21M VCL C21P C31P C31M C12P C12M DDVDH C11P C11M VSSC The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 9 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 4. Pin Descriptions Power Supply Pins Pin Name VDDI I/O I VDDI_LED I VCI I Type P Descriptions Low voltage power supply for interface logic circuits (1.65 ~ 3.3 V) Power supply for LED driver interface. (1.65 ~ 3.3 V) If LED driver is not used, fix this pin at VDDI. Analog Power High voltage power supply for analog circuit blocks (2.5 ~ 3.3 V) Regulated Low voltage level for interface circuits Vcore O Digital Power VSS3 I I/O Ground System ground level for I/O circuits. VSS I Digital Ground System ground level for logic blocks VSSA I Analog Ground System ground level for analog circuit blocks Connect to VSS on the FPC to prevent noise. VSSC I Analog Ground System ground level for analog circuit blocks Connect to VSS on the FPC to prevent noise Pin Name I/O Type Connect a capacitor for stabilization. Don’t apply any external power to this pad Interface Logic Signals Descriptions - Select the MCU interface mode IM3 IM[3:0] I (VDDI/VSS) IM2 IM1 IM0 MCU-Interface Mode DB Pin in use Register/Content GRAM D[7:0] D[7:0] 0 0 0 0 80 MCU 8-bit bus interface 0 0 0 1 80 MCU 16-bit bus interface D[7:0] D[15:0] 0 0 1 0 80 MCU 9-bit bus interface D[7:0] D[8:0] 0 0 1 1 80 MCU 18-bit bus interface D[7:0] D[17:0] 0 1 0 1 3-wire 9-bit data serial interface SDA: In/OUT 0 1 1 0 4-wire 8-bit data serial interface SDA: In/OUT 1 0 0 0 80 MCU 16-bit bus interface D[8:1] D[17:10], D[8:1] 1 0 0 1 80 MCU 8-bit bus interface D[17:10] D[17:10] 1 0 1 0 80 MCU 18-bit bus interface D[8:1] D[17:0] 1 0 1 1 80 MCU 9-bit bus interface D[17:10] D[17:9] 1 1 0 1 3-wire 9-bit data serial interface SDI: In SDO: Out 1 1 1 0 4-wire 8-bit data serial interface SDI: In SDO: Out Ⅰ Ⅰ Ⅰ Ⅰ Ⅰ Ⅰ Ⅱ Ⅱ Ⅱ Ⅱ Ⅱ Ⅱ MPU Parallel interface bus and serial interface select If use RGB Interface must select serial interface. * : Fix this pin at VDDI or VSS. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 10 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color RESX EXTC CSX I I I MCU (VDDI/VSS) MCU (VDDI/VSS) MCU (VDDI/VSS) ILI9341 This signal will reset the device and must be applied to properly initialize the chip. Signal is active low. Extended command set enable. Low: extended command set is discarded. High: extended command set is accepted. Please connect EXTC to VDDI to read/write extended registers (RB0h~RCFh, RE0h~RFFh) Chip select input pin (“Low” enable). This pin can be permanently fixed “Low” in MPU interface mode only. * note1,2 This pin is used to select “Data or Command” in the parallel interface or 4-wire 8-bit serial data interface. D/CX (SCL) I MCU (VDDI/VSS) When DCX = ’1’, data is selected. When DCX = ’0’, command is selected. This pin is used serial interface clock in 3-wire 9-bit / 4-wire 8-bit serial data interface. I MCU (VDDI/VSS) WRX (D/CX) I MCU (VDDI/VSS) D[17:0] I/O MCU (VDDI/VSS) RDX If not used, this pin should be connected to VDDI or VSS. 8080- /8080- system (RDX): Serves as a read signal and MCU read data at the rising edge. Fix to VDDI level when not in use. - 8080- /8080- system (WRX): Serves as a write signal and writes data at the rising edge. - 4-line system (D/CX): Serves as command or parameter select. Fix to VDDI level when not in use. 18-bit parallel bi-directional data bus for MCU system and RGB interface mode Fix to VSS level when not in use Ⅰ Ⅱ Ⅰ Ⅱ When IM[3] : Low, Serial in/out signal. SDI/SDA I/O MCU (VDDI/VSS) When IM[3] : High, Serial input signal. The data is applied on the rising edge of the SCL signal. If not used, fix this pin at VDDI or VSS. SDO O MCU (VDDI/VSS) Serial output signal. The data is outputted on the falling edge of the SCL signal. If not used, open this pin Tearing effect output pin to synchronize MPU to frame writing, TE O MCU (VDDI/VSS) activated by S/W command. When this pin is not activated, this pin is low. DOTCLK I MCU (VDDI/VSS) VSYNC I MCU (VDDI/VSS) If not used, open this pin. Dot clock signal for RGB interface operation. Fix to VDDI or VSS level when not in use. Frame synchronizing signal for RGB interface operation. Fix to VDDI or VSS level when not in use. HSYNC I DE I MCU (VDDI/VSS) MCU (VDDI/VSS) Line synchronizing signal for RGB interface operation. Fix to VDDI or VSS level when not in use. Data enable signal for RGB interface operation. Fix to VDDI or VSS level when not in use. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 11 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 Note. 1. If CSX is connected to VSS in Parallel interface mode, there will be no abnormal visible effect to the display module. Also there will be no restriction on using the Parallel Read/Write protocols, Power On/Off Sequences or other functions. Furthermore there will be no influence to the Power Consumption of the display module. 2. When CSX=’1’, there is no influence to the parallel and serial interface. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 12 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color LCD Driver Input/Output Pins Descriptions Pin Name I/O Type S720~S1 O Source Source output signals.. Leave the pin to open when not in use. G320~G1 O Gate Gate output signals. Leave the pin to open when not in use. O Power Stabilizing capacitor DDVDH ILI9341 Output voltage of 1st step up circuit (2 x VCI). Input voltage to 2nd step up circuit. Generated power output pad for source driver block. Connect this pad to the capacitor for stabilization. VGH O Power Stabilizing capacitor Power supply for the gate driver. Adjust the VGH level with the BT[2:0] bits. Connect this pad with a stabilizing capacitor. VGL O Power Stabilizing capacitor Power supply for the gate driver. Adjust the VGL level with the BT[2:0] bits. Connect this pad with a stabilizing capacitor. VCL 0 Power Stabilizing capacitor Power supply for VCOML. VCL = 0~ - VCI Connect this pad with a stabilizing capacitor. P Stabilizing capacitor Connect the charge-pumping capacitor for generating DDVDH level. P Stabilizing capacitor Connect the charge-pumping capacitor for generating VGH, VGL level. C11P, C11M C12P, C12M C21P, C21M C22P, C22M GVDD High reference voltage for grayscale voltage generator. O Internal register can be used to adjust the voltage. Power supply pad for the TFT- display counter electrode. VCOM O Charge recycling method is used with VCI and VSSA voltage. Connect this pad to the TFT-display counter electrode. Output pin for PWM (Pulse Width Modulation) signal of LED driving. LEDPWM O LEDON O Pin Name I/O Type DUMMY - Open If not used, open this pad. Output pin for enabling LED driving. If not used, open this pad. Test Pins Descriptions Input pads used only for test purpose at IC-side. During normal operation, leave these pads open. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 13 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 Liquid crystal power supply specifications Table No. 1 2 3 Item TFT Source Driver TFT Gate Driver TFT Display’s Capacitor Structure 4 Liquid Crystal Drive Output 5 Input Voltage 6 Liquid Crystal Drive Voltages 7 Internal Step-up Circuits S1 ~ S720 G1 ~ G320 VCOM VDDI VCI DDVDH VGH VGL VCL VGH - VGL DDVDH VGH VGL VCL Description 720 pins (240 x RGB) 320 pins Cst structure only (Cs on Common) V0 ~ V63 grayscales VGH - VGL VCOMH - VCOML: Amplitude = electronic volumes 1.65V ~ 3.30V 2.50V ~ 3.30V 4.5V ~ 5.8V 10.0V ~ 16.0V -5.0V ~ -10.0V -1.5V ~ -2.5V Max. 28.0V VCI x2, VCI x6, x7 VCI x-3, x-4, VCI x-1 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 14 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 5. Pad Arrangement and Coordination 1 2 0 ………………… 1 0 3 0 4 0 5 0 7 0 ……………………. 6 0 8 0 1 0 0 Face Up (Bump View) 9 0 1 1 0 y 1 2 0 1 4 0 1 5 0 1 6 0 ……………………. x 1 3 0 1 7 0 1 8 0 2 0 0 2 1 0 2 2 0 ………………… 1 9 0 2 3 0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 15 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color No. Pad name X Y No. Pad name X Y No. Pad name X Y ILI9341 No. Pad name X Y 1 DUMMY -7292.5 -248 51 C12M -4292.5 -248 101 VSSA -1292.5 -248 151 LEDPWM 2 DUMMY -7232.5 -248 52 C12M -4232.5 -248 102 VSSA -1232.5 -248 3 VCOM -7172.5 -248 53 C11P -4172.5 -248 103 VSSA -1172.5 -248 4 VCOM -7112.5 -248 54 C11P -4112.5 -248 104 VSSA -1112.5 5 VCOM -7052.5 -248 55 C11P -4052.5 -248 105 VSSA -1052.5 -248 155 DB[18]_Dummy 2535 -248 6 VCOM -6992.5 -248 56 C11P -3992.5 -248 106 DUMMY -992.5 -248 156 DB[19]_Dummy 2620 -248 7 VCOM -6932.5 -248 57 C11P -3932.5 -248 107 VGS -932.5 -248 157 DB[20]_Dummy 2705 -248 8 VCOM -6872.5 -248 58 C11P -3872.5 -248 108 VGS -872.5 -248 158 DB[21]_Dummy 2790 -248 9 VCOM -6812.5 -248 59 C11P -3812.5 -248 109 EXTC -812.5 -248 159 DB[22]_Dummy 2875 -248 -248 -248 2245 -248 152 LEDON 2330 -248 153 VDDI_LED 2402.5 -248 154 VDDI_LED 2462.5 -248 10 VCOM -6752.5 -248 60 C11M -3752.5 -248 110 IM<3> -752.5 -248 160 DB[23]_Dummy 2960 11 DUMMY -6692.5 -248 61 C11M -3692.5 -248 111 IM<2> -692.5 -248 161 DUMMY 3032.5 -248 12 C22P -6632.5 -248 62 C11M -3632.5 -248 112 IM<1> -632.5 -248 162 VDDI 3092.5 -248 13 C22P -6572.5 -248 63 C11M -3572.5 -248 113 IM<0> -572.5 -248 163 VDDI 3152.5 -248 14 C22M -6512.5 -248 64 C11M -3512.5 -248 114 RESX -512.5 -248 164 VDDI 3212.5 -248 15 C22M -6452.5 -248 65 C11M -3452.5 -248 115 CSX -452.5 -248 165 VDDI 3272.5 -248 16 C21P -6392.5 -248 66 C11M -3392.5 -248 116 DCX -392.5 -248 166 VDDI 3332.5 -248 17 C21P -6332.5 -248 67 (GND) -3332.5 -248 117 WRX -332.5 -248 167 VDDI 3392.5 -248 18 C21M -6272.5 -248 68 (GND) -3272.5 -248 118 RDX -272.5 -248 168 VDDI 3452.5 -248 19 C21M -6212.5 -248 69 (GND) -3212.5 -248 119 DUMMY -212.5 -248 169 Vcore 3512.5 -248 20 VGH -6152.5 -248 70 (GND) -3152.5 -248 120 VSYNC -152.5 -248 170 Vcore 3572.5 -248 21 VGH -6092.5 -248 71 (GND) -3092.5 -248 121 HSYNC -92.5 -248 171 Vcore 3632.5 -248 22 VGH -6032.5 -248 72 (GND) -3032.5 -248 122 ENABL -32.5 -248 172 Vcore 3692.5 -248 23 VGH -5972.5 -248 73 (GND) -2972.5 -248 123 DOTCLK 27.5 -248 173 Vcore 3752.5 -248 24 VGH -5912.5 -248 74 VCI -2912.5 -248 124 DUMMY 87.5 -248 174 Vcore 3812.5 -248 25 DUMMY -5852.5 -248 75 VCI -2852.5 -248 125 SDA 160 -248 175 Vcore 3872.5 -248 26 VGL -5792.5 -248 76 VCI -2792.5 -248 126 DB[0] 245 -248 176 Vcore 3932.5 -248 27 VGL -5732.5 -248 77 VCI -2732.5 -248 127 DB[1] 330 -248 177 Vcore 3992.5 -248 28 VGL -5672.5 -248 78 VCI -2672.5 -248 128 DB[2] 415 -248 178 Vcore 4052.5 -248 29 VGL -5612.5 -248 79 VCI -2612.5 -248 129 DB[3] 500 -248 179 Vcore 4112.5 -248 30 VGL -5552.5 -248 80 VCI -2552.5 -248 130 DUMMY 572.5 -248 180 Vcore 4172.5 -248 31 VGL -5492.5 -248 81 VCI -2492.5 -248 131 DB[4] 645 -248 181 Vcore 4232.5 -248 32 DDVDH -5432.5 -248 82 VSS3 -2432.5 -248 132 DB[5] 730 -248 182 Vcore 4292.5 -248 33 DDVDH -5372.5 -248 83 VSS3 -2372.5 -248 133 DB[6] 815 -248 183 DUMMY 4352.5 -248 34 DDVDH -5312.5 -248 84 VSS3 -2312.5 -248 134 DB[7] 900 -248 184 GVDD 4412.5 -248 35 DDVDH -5252.5 -248 85 VSS -2252.5 -248 135 DUMMY 972.5 -248 185 GVDD 4472.5 -248 36 DDVDH -5192.5 -248 86 VSS -2192.5 -248 136 DB[8] 1045 -248 186 GVDD 4532.5 -248 37 DDVDH -5132.5 -248 87 VSS -2132.5 -248 137 DB[9] 1130 -248 187 GVDD 4592.5 -248 38 DDVDH -5072.5 -248 88 VSS -2072.5 -248 138 DB[10] 1215 -248 188 DUMMY 4652.5 -248 39 C12P -5012.5 -248 89 VSS -2012.5 -248 139 DB[11] 1300 -248 189 DUMMY 4712.5 -248 40 C12P -4952.5 -248 90 VSS -1952.5 -248 140 DUMMY 1372.5 -248 190 VCL 4772.5 -248 41 C12P -4892.5 -248 91 VSSC -1892.5 -248 141 DB[12] 1445 -248 191 VCL 4832.5 -248 42 C12P -4832.5 -248 92 VSSC -1832.5 -248 142 DB[13] 1530 -248 192 VCL 4892.5 -248 43 C12P -4772.5 -248 93 VSSC -1772.5 -248 143 DB[14] 1615 -248 193 VCL 4952.5 -248 44 C12P -4712.5 -248 94 VSSC -1712.5 -248 144 DB[15] 1700 -248 194 VCL 5012.5 -248 45 C12P -4652.5 -248 95 VSSC -1652.5 -248 145 DUMMY 1772.5 -248 195 VCL 5072.5 -248 46 C12M -4592.5 -248 96 VSSC -1592.5 -248 146 DB[16] 1845 -248 196 VCL 5132.5 -248 47 C12M -4532.5 -248 97 VSSC -1532.5 -248 147 DB[17] 1930 -248 197 VCL 5192.5 -248 48 C12M -4472.5 -248 98 VSSA -1472.5 -248 148 DUMMY 2002.5 -248 198 DUMMY 5252.5 -248 49 C12M -4412.5 -248 99 VSSA -1412.5 -248 149 TE 2075 -248 199 DUMMY 5312.5 -248 50 C12M -4352.5 -248 100 VSSA -1352.5 -248 150 SDO 2160 -248 200 DUMMY 5372.5 -248 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 16 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color X Y X X ILI9341 No. Pad name No. Pad name Y No. Pad name Y No. Pad name 201 DUMMY 5432.5 -248 251 G32 7147 224 301 G132 6447 224 351 G232 5747 X 224 Y 202 DUMMY 5492.5 -248 252 G34 7133 93 302 G134 6433 93 352 G234 5733 93 203 DUMMY 5552.5 -248 253 G36 7119 224 303 G136 6419 224 353 G236 5719 224 204 DUMMY 5612.5 -248 254 G38 7105 93 304 G138 6405 93 354 G238 5705 93 205 DUMMY 5672.5 -248 255 G40 7091 224 305 G140 6391 224 355 G240 5691 224 206 (GND) 5732.5 -248 256 G42 7077 93 306 G142 6377 93 356 G242 5677 93 207 (GND) 5792.5 -248 257 G44 7063 224 307 G144 6363 224 357 G244 5663 224 208 (GND) 5852.5 -248 258 G46 7049 93 308 G146 6349 93 358 G246 5649 93 209 (GND) 5912.5 -248 259 G48 7035 224 309 G148 6335 224 359 G248 5635 224 210 (GND) 5972.5 -248 260 G50 7021 93 310 G150 6321 93 360 G250 5621 93 211 (GND) 6032.5 -248 261 G52 7007 224 311 G152 6307 224 361 G252 5607 224 212 (GND) 6092.5 -248 262 G54 6993 93 312 G154 6293 93 362 G254 5593 93 213 (GND) 6152.5 -248 263 G56 6979 224 313 G156 6279 224 363 G256 5579 224 214 DUMMY 6212.5 -248 264 G58 6965 93 314 G158 6265 93 364 G258 5565 93 215 DUMMY 6272.5 -248 265 G60 6951 224 315 G160 6251 224 365 G260 5551 224 216 DUMMY 6332.5 -248 266 G62 6937 93 316 G162 6237 93 366 G262 5537 93 217 DUMMY 6392.5 -248 267 G64 6923 224 317 G164 6223 224 367 G264 5523 224 218 DUMMY 6452.5 -248 268 G66 6909 93 318 G166 6209 93 368 G266 5509 93 219 DUMMY 6512.5 -248 269 G68 6895 224 319 G168 6195 224 369 G268 5495 224 220 DUMMY 6572.5 -248 270 G70 6881 93 320 G170 6181 93 370 G270 5481 93 221 DUMMY 6632.5 -248 271 G72 6867 224 321 G172 6167 224 371 G272 5467 224 222 DUMMY 6692.5 -248 272 G74 6853 93 322 G174 6153 93 372 G274 5453 93 223 VCOM 6752.5 -248 273 G76 6839 224 323 G176 6139 224 373 G276 5439 224 224 VCOM 6812.5 -248 274 G78 6825 93 324 G178 6125 93 374 G278 5425 93 225 VCOM 6872.5 -248 275 G80 6811 224 325 G180 6111 224 375 G280 5411 224 226 VCOM 6932.5 -248 276 G82 6797 93 326 G182 6097 93 376 G282 5397 93 227 VCOM 6992.5 -248 277 G84 6783 224 327 G184 6083 224 377 G284 5383 224 228 VCOM 7052.5 -248 278 G86 6769 93 328 G186 6069 93 378 G286 5369 93 229 VCOM 7112.5 -248 279 G88 6755 224 329 G188 6055 224 379 G288 5355 224 230 VCOM 7172.5 -248 280 G90 6741 93 330 G190 6041 93 380 G290 5341 93 231 DUMMY 7232.5 -248 281 G92 6727 224 331 G192 6027 224 381 G292 5327 224 232 DUMMY 7292.5 -248 282 G94 6713 93 332 G194 6013 93 382 G294 5313 93 233 DUMMY 7399 224 283 G96 6699 224 333 G196 5999 224 383 G296 5299 224 234 DUMMY 7385 93 284 G98 6685 93 334 G198 5985 93 384 G298 5285 93 235 DUMMY 7371 224 285 G100 6671 224 335 G200 5971 224 385 G300 5271 224 236 G2 7357 93 286 G102 6657 93 336 G202 5957 93 386 G302 5257 93 237 G4 7343 224 287 G104 6643 224 337 G204 5943 224 387 G304 5243 224 238 G6 7329 93 288 G106 6629 93 338 G206 5929 93 388 G306 5229 93 239 G8 7315 224 289 G108 6615 224 339 G208 5915 224 389 G308 5215 224 240 G10 7301 93 290 G110 6601 93 340 G210 5901 93 390 G310 5201 93 241 G12 7287 224 291 G112 6587 224 341 G212 5887 224 391 G312 5187 224 242 G14 7273 93 292 G114 6573 93 342 G214 5873 93 392 G314 5173 93 243 G16 7259 224 293 G116 6559 224 343 G216 5859 224 393 G316 5159 224 244 G18 7245 93 294 G118 6545 93 344 G218 5845 93 394 G318 5145 93 245 G20 7231 224 295 G120 6531 224 345 G220 5831 224 395 G320 5131 224 246 G22 7217 93 296 G122 6517 93 346 G222 5817 93 396 S720 5075 93 247 G24 7203 224 297 G124 6503 224 347 G224 5803 224 397 S719 5061 224 248 G26 7189 93 298 G126 6489 93 348 G226 5789 93 398 S718 5047 93 249 G28 7175 224 299 G128 6475 224 349 G228 5775 224 399 S717 5033 224 250 G30 7161 93 300 G130 6461 93 350 G230 5761 93 400 S716 5019 93 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 17 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color No. Pad name X Y No. Pad name X Y No. Pad name X Y ILI9341 No. Pad name X Y 401 S715 5005 224 451 S665 4305 224 501 S615 3605 224 551 S565 2905 224 402 S714 4991 93 452 S664 4291 93 502 S614 3591 93 552 S564 2891 93 403 S713 4977 224 453 S663 4277 224 503 S613 3577 224 553 S563 2877 224 404 S712 4963 93 454 S662 4263 93 504 S612 3563 93 554 S562 2863 93 405 S711 4949 224 455 S661 4249 224 505 S611 3549 224 555 S561 2849 224 406 S710 4935 93 456 S660 4235 93 506 S610 3535 93 556 S560 2835 93 407 S709 4921 224 457 S659 4221 224 507 S609 3521 224 557 S559 2821 224 408 S708 4907 93 458 S658 4207 93 508 S608 3507 93 558 S558 2807 93 409 S707 4893 224 459 S657 4193 224 509 S607 3493 224 559 S557 2793 224 410 S706 4879 93 460 S656 4179 93 510 S606 3479 93 560 S556 2779 93 411 S705 4865 224 461 S655 4165 224 511 S605 3465 224 561 S555 2765 224 412 S704 4851 93 462 S654 4151 93 512 S604 3451 93 562 S554 2751 93 413 S703 4837 224 463 S653 4137 224 513 S603 3437 224 563 S553 2737 224 414 S702 4823 93 464 S652 4123 93 514 S602 3423 93 564 S552 2723 93 415 S701 4809 224 465 S651 4109 224 515 S601 3409 224 565 S551 2709 224 416 S700 4795 93 466 S650 4095 93 516 S600 3395 93 566 S550 2695 93 417 S699 4781 224 467 S649 4081 224 517 S599 3381 224 567 S549 2681 224 418 S698 4767 93 468 S648 4067 93 518 S598 3367 93 568 S548 2667 93 419 S697 4753 224 469 S647 4053 224 519 S597 3353 224 569 S547 2653 224 420 S696 4739 93 470 S646 4039 93 520 S596 3339 93 570 S546 2639 93 421 S695 4725 224 471 S645 4025 224 521 S595 3325 224 571 S545 2625 224 422 S694 4711 93 472 S644 4011 93 522 S594 3311 93 572 S544 2611 93 423 S693 4697 224 473 S643 3997 224 523 S593 3297 224 573 S543 2597 224 424 S692 4683 93 474 S642 3983 93 524 S592 3283 93 574 S542 2583 93 425 S691 4669 224 475 S641 3969 224 525 S591 3269 224 575 S541 2569 224 426 S690 4655 93 476 S640 3955 93 526 S590 3255 93 576 S540 2555 93 427 S689 4641 224 477 S639 3941 224 527 S589 3241 224 577 S539 2541 224 428 S688 4627 93 478 S638 3927 93 528 S588 3227 93 578 S538 2527 93 429 S687 4613 224 479 S637 3913 224 529 S587 3213 224 579 S537 2513 224 430 S686 4599 93 480 S636 3899 93 530 S586 3199 93 580 S536 2499 93 431 S685 4585 224 481 S635 3885 224 531 S585 3185 224 581 S535 2485 224 432 S684 4571 93 482 S634 3871 93 532 S584 3171 93 582 S534 2471 93 433 S683 4557 224 483 S633 3857 224 533 S583 3157 224 583 S533 2457 224 434 S682 4543 93 484 S632 3843 93 534 S582 3143 93 584 S532 2443 93 435 S681 4529 224 485 S631 3829 224 535 S581 3129 224 585 S531 2429 224 436 S680 4515 93 486 S630 3815 93 536 S580 3115 93 586 S530 2415 93 437 S679 4501 224 487 S629 3801 224 537 S579 3101 224 587 S529 2401 224 438 S678 4487 93 488 S628 3787 93 538 S578 3087 93 588 S528 2387 93 439 S677 4473 224 489 S627 3773 224 539 S577 3073 224 589 S527 2373 224 440 S676 4459 93 490 S626 3759 93 540 S576 3059 93 590 S526 2359 93 441 S675 4445 224 491 S625 3745 224 541 S575 3045 224 591 S525 2345 224 442 S674 4431 93 492 S624 3731 93 542 S574 3031 93 592 S524 2331 93 443 S673 4417 224 493 S623 3717 224 543 S573 3017 224 593 S523 2317 224 444 S672 4403 93 494 S622 3703 93 544 S572 3003 93 594 S522 2303 93 445 S671 4389 224 495 S621 3689 224 545 S571 2989 224 595 S521 2289 224 446 S670 4375 93 496 S620 3675 93 546 S570 2975 93 596 S520 2275 93 447 S669 4361 224 497 S619 3661 224 547 S569 2961 224 597 S519 2261 224 448 S668 4347 93 498 S618 3647 93 548 S568 2947 93 598 S518 2247 93 449 S667 4333 224 499 S617 3633 224 549 S567 2933 224 599 S517 2233 224 450 S666 4319 93 500 S616 3619 93 550 S566 2919 93 600 S516 2219 93 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 18 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color No. Pad name X Y 601 S515 2205 224 651 S465 1505 224 701 S415 805 224 751 S365 105 224 602 S514 2191 93 652 S464 1491 93 702 S414 791 93 752 S364 91 93 603 S513 2177 224 653 S463 1477 224 703 S413 777 224 753 S363 77 224 604 S512 2163 93 654 S462 1463 93 704 S412 763 93 754 S362 63 93 605 S511 2149 224 655 S461 1449 224 705 S411 749 224 755 S361 49 224 606 S510 2135 93 656 S460 1435 93 706 S410 735 93 756 S360 -49 93 607 S509 2121 224 657 S459 1421 224 707 S409 721 224 757 S359 -63 224 608 S508 2107 93 658 S458 1407 93 708 S408 707 93 758 S358 -77 93 609 S507 2093 224 659 S457 1393 224 709 S407 693 224 759 S357 -91 224 610 S506 2079 93 660 S456 1379 93 710 S406 679 93 760 S356 -105 93 611 S505 X Y No. Pad name No. Pad name X Y ILI9341 No. Pad name X Y 2065 224 661 S455 1365 224 711 S405 665 224 761 S355 -119 224 612 S504 2051 93 662 S454 1351 93 712 S404 651 93 762 S354 -133 93 613 S503 2037 224 663 S453 1337 224 713 S403 637 224 763 S353 -147 224 614 S502 2023 93 664 S452 1323 93 714 S402 623 93 764 S352 -161 93 615 S501 2009 224 665 S451 1309 224 715 S401 609 224 765 S351 -175 224 616 S500 1995 93 666 S450 1295 93 716 S400 595 93 766 S350 -189 93 617 S499 1981 224 667 S449 1281 224 717 S399 581 224 767 S349 -203 224 618 S498 1967 93 668 S448 1267 93 718 S398 567 93 768 S348 -217 93 619 S497 1953 224 669 S447 1253 224 719 S397 553 224 769 S347 -231 224 620 S496 1939 93 670 S446 1239 93 720 S396 539 93 770 S346 -245 93 621 S495 1925 224 671 S445 1225 224 721 S395 525 224 771 S345 -259 224 622 S494 1911 93 672 S444 1211 93 722 S394 511 93 772 S344 -273 93 623 S493 1897 224 673 S443 1197 224 723 S393 497 224 773 S343 -287 224 624 S492 1883 93 674 S442 1183 93 724 S392 483 93 774 S342 -301 93 625 S491 1869 224 675 S441 1169 224 725 S391 469 224 775 S341 -315 224 626 S490 1855 93 676 S440 1155 93 726 S390 455 93 776 S340 -329 93 627 S489 1841 224 677 S439 1141 224 727 S389 441 224 777 S339 -343 224 628 S488 1827 93 678 S438 1127 93 728 S388 427 93 778 S338 -357 93 629 S487 1813 224 679 S437 1113 224 729 S387 413 224 779 S337 -371 224 630 S486 1799 93 680 S436 1099 93 730 S386 399 93 780 S336 -385 93 631 S485 1785 224 681 S435 1085 224 731 S385 385 224 781 S335 -399 224 632 S484 1771 93 682 S434 1071 93 732 S384 371 93 782 S334 -413 93 633 S483 1757 224 683 S433 1057 224 733 S383 357 224 783 S333 -427 224 634 S482 1743 93 684 S432 1043 93 734 S382 343 93 784 S332 -441 93 635 S481 1729 224 685 S431 1029 224 735 S381 329 224 785 S331 -455 224 636 S480 1715 93 686 S430 1015 93 736 S380 315 93 786 S330 -469 93 637 S479 1701 224 687 S429 1001 224 737 S379 301 224 787 S329 -483 224 638 S478 1687 93 688 S428 987 93 738 S378 287 93 788 S328 -497 93 639 S477 1673 224 689 S427 973 224 739 S377 273 224 789 S327 -511 224 640 S476 1659 93 690 S426 959 93 740 S376 259 93 790 S326 -525 93 641 S475 1645 224 691 S425 945 224 741 S375 245 224 791 S325 -539 224 642 S474 1631 93 692 S424 931 93 742 S374 231 93 792 S324 -553 93 643 S473 1617 224 693 S423 917 224 743 S373 217 224 793 S323 -567 224 644 S472 1603 93 694 S422 903 93 744 S372 203 93 794 S322 -581 93 645 S471 1589 224 695 S421 889 224 745 S371 189 224 795 S321 -595 224 646 S470 1575 93 696 S420 875 93 746 S370 175 93 796 S320 -609 93 647 S469 1561 224 697 S419 861 224 747 S369 161 224 797 S319 -623 224 648 S468 1547 93 698 S418 847 93 748 S368 147 93 798 S318 -637 93 649 S467 1533 224 699 S417 833 224 749 S367 133 224 799 S317 -651 224 650 S466 1519 93 700 S416 819 93 750 S366 119 93 800 S316 -665 93 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 19 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color No. Pad name No. Pad name X Y X Y 801 S315 -679 224 851 S265 -1379 224 901 S215 -2079 224 951 S165 -2779 224 802 S314 -693 93 852 S264 -1393 93 902 S214 -2093 93 952 S164 -2793 93 803 S313 -707 224 853 S263 -1407 224 903 S213 -2107 224 953 S163 -2807 224 804 S312 -721 93 854 S262 -1421 93 904 S212 -2121 93 954 S162 -2821 93 805 S311 -735 224 855 S261 -1435 224 905 S211 -2135 224 955 S161 -2835 224 806 S310 -749 93 856 S260 -1449 93 906 S210 -2149 93 956 S160 -2849 93 807 S309 -763 224 857 S259 -1463 224 907 S209 -2163 224 957 S159 -2863 224 808 S308 -777 93 858 S258 -1477 93 908 S208 -2177 93 958 S158 -2877 93 809 S307 -791 224 859 S257 -1491 224 909 S207 -2191 224 959 S157 -2891 224 810 S306 -805 93 860 S256 -1505 93 910 S206 -2205 93 960 S156 -2905 93 811 S305 -819 224 861 S255 -1519 224 911 S205 -2219 224 961 S155 -2919 224 812 S304 -833 93 862 S254 -1533 93 912 S204 -2233 93 962 S154 -2933 93 813 S303 -847 224 863 S253 -1547 224 913 S203 -2247 224 963 S153 -2947 224 814 S302 -861 93 864 S252 -1561 93 914 S202 -2261 93 964 S152 -2961 93 815 S301 -875 224 865 S251 -1575 224 915 S201 -2275 224 965 S151 -2975 224 816 S300 -889 93 866 S250 -1589 93 916 S200 -2289 93 966 S150 -2989 93 817 S299 -903 224 867 S249 -1603 224 917 S199 -2303 224 967 S149 -3003 224 818 S298 -917 93 868 S248 -1617 93 918 S198 -2317 93 968 S148 -3017 93 819 S297 -931 224 869 S247 -1631 224 919 S197 -2331 224 969 S147 -3031 224 820 S296 -945 93 870 S246 -1645 93 920 S196 -2345 93 970 S146 -3045 93 821 S295 -959 224 871 S245 -1659 224 921 S195 -2359 224 971 S145 -3059 224 822 S294 -973 93 872 S244 -1673 93 922 S194 -2373 93 972 S144 -3073 93 823 S293 -987 224 873 S243 -1687 224 923 S193 -2387 224 973 S143 -3087 224 824 S292 -1001 93 874 S242 -1701 93 924 S192 -2401 93 974 S142 -3101 93 825 S291 -1015 224 875 S241 -1715 224 925 S191 -2415 224 975 S141 -3115 826 S290 -1029 93 876 S240 -1729 93 926 S190 -2429 93 976 S140 -3129 93 827 S289 -1043 224 877 S239 -1743 224 927 S189 -2443 224 977 S139 -3143 224 828 S288 -1057 93 878 S238 -1757 93 928 S188 -2457 93 978 S138 -3157 93 829 S287 -1071 224 879 S237 -1771 224 929 S187 -2471 224 979 S137 -3171 224 830 S286 -1085 93 880 S236 -1785 93 930 S186 -2485 93 980 S136 -3185 93 831 S285 -1099 224 881 S235 -1799 224 931 S185 -2499 224 981 S135 -3199 224 832 S284 -1113 93 882 S234 -1813 93 932 S184 -2513 93 982 S134 -3213 93 833 S283 -1127 224 883 S233 -1827 224 933 S183 -2527 224 983 S133 -3227 224 834 S282 -1141 93 884 S232 -1841 93 934 S182 -2541 93 984 S132 -3241 93 835 S281 -1155 224 885 S231 -1855 224 935 S181 -2555 224 985 S131 -3255 224 836 S280 -1169 93 886 S230 -1869 93 936 S180 -2569 93 986 S130 -3269 93 837 S279 -1183 224 887 S229 -1883 224 937 S179 -2583 224 987 S129 -3283 224 838 S278 -1197 93 888 S228 -1897 93 938 S178 -2597 93 988 S128 -3297 93 839 S277 -1211 224 889 S227 -1911 939 S177 -2611 989 S127 -3311 840 S276 -1225 93 890 S226 -1925 93 940 S176 -2625 93 990 S126 -3325 93 841 S275 -1239 224 891 S225 -1939 224 941 S175 -2639 224 991 S125 -3339 224 842 S274 -1253 93 892 S224 -1953 93 942 S174 -2653 93 992 S124 -3353 93 843 S273 -1267 224 893 S223 -1967 224 943 S173 -2667 224 993 S123 -3367 224 844 S272 -1281 93 894 S222 -1981 93 944 S172 -2681 93 994 S122 -3381 93 845 S271 -1295 224 895 S221 -1995 224 945 S171 -2695 224 995 S121 -3395 224 846 S270 -1309 93 896 S220 -2009 93 946 S170 -2709 93 996 S120 -3409 93 847 S269 -1323 224 897 S219 -2023 224 947 S169 -2723 224 997 S119 -3423 224 848 S268 -1337 93 898 S218 -2037 93 948 S168 -2737 93 998 S118 -3437 93 849 S267 -1351 224 899 S217 -2051 224 949 S167 -2751 224 999 S117 -3451 224 850 S266 -1365 93 900 S216 -2065 93 950 S166 -2765 93 1000 S116 224 No. Pad name X Y ILI9341 224 No. Pad name X Y 224 224 -3465 93 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 20 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color No. Pad name X Y No. Pad name X Y No. Pad name X Y ILI9341 No. Pad name X Y 1001 S115 -3479 224 1051 S65 -4179 224 1101 S15 -4879 224 1151 G249 -5621 224 1002 S114 -3493 93 1052 S64 -4193 93 1102 S14 -4893 93 1152 G247 -5635 93 1003 S113 -3507 224 1053 S63 -4207 224 1103 S13 -4907 224 1153 G245 -5649 224 1004 S112 -3521 93 1054 S62 -4221 93 1104 S12 -4921 93 1154 G243 -5663 93 1005 S111 -3535 224 1055 S61 -4235 224 1105 S11 -4935 224 1155 G241 -5677 224 1006 S110 -3549 93 1056 S60 -4249 93 1106 S10 -4949 93 1156 G239 -5691 93 1007 S109 -3563 224 1057 S59 -4263 224 1107 S9 -4963 224 1157 G237 -5705 224 1008 S108 -3577 93 1058 S58 -4277 93 1108 S8 -4977 93 1158 G235 -5719 93 1009 S107 -3591 224 1059 S57 -4291 224 1109 S7 -4991 224 1159 G233 -5733 224 1010 S106 -3605 93 1060 S56 -4305 93 1110 S6 -5005 93 1160 G231 -5747 93 1011 S105 -3619 224 1061 S55 -4319 224 1111 S5 -5019 224 1161 G229 -5761 224 1012 S104 -3633 93 1062 S54 -4333 93 1112 S4 -5033 93 1162 G227 -5775 93 1013 S103 -3647 224 1063 S53 -4347 224 1113 S3 -5047 224 1163 G225 -5789 224 1014 S102 -3661 93 1064 S52 -4361 93 1114 S2 -5061 93 1164 G223 -5803 93 1015 S101 -3675 224 1065 S51 -4375 224 1115 S1 -5075 224 1165 G221 -5817 224 1016 S100 -3689 93 1066 S50 -4389 93 1116 G319 -5131 93 1166 G219 -5831 93 1017 S99 -3703 224 1067 S49 -4403 224 1117 G317 -5145 224 1167 G217 -5845 224 1018 S98 -3717 93 1068 S48 -4417 93 1118 G315 -5159 93 1168 G215 -5859 93 1019 S97 -3731 224 1069 S47 -4431 224 1119 G313 -5173 224 1169 G213 -5873 224 1020 S96 -3745 93 1070 S46 -4445 93 1120 G311 -5187 93 1170 G211 -5887 93 1021 S95 -3759 224 1071 S45 -4459 224 1121 G309 -5201 224 1171 G209 -5901 224 1022 S94 -3773 93 1072 S44 -4473 93 1122 G307 -5215 93 1172 G207 -5915 93 1023 S93 -3787 224 1073 S43 -4487 224 1123 G305 -5229 224 1173 G205 -5929 224 1024 S92 -3801 93 1074 S42 -4501 93 1124 G303 -5243 93 1174 G203 -5943 93 1025 S91 -3815 224 1075 S41 -4515 224 1125 G301 -5257 224 1175 G201 -5957 224 1026 S90 -3829 93 1076 S40 -4529 93 1126 G299 -5271 93 1176 G199 -5971 93 1027 S89 -3843 224 1077 S39 -4543 224 1127 G297 -5285 224 1177 G197 -5985 224 1028 S88 -3857 93 1078 S38 -4557 93 1128 G295 -5299 93 1178 G195 -5999 93 1029 S87 -3871 224 1079 S37 -4571 224 1129 G293 -5313 224 1179 G193 -6013 224 1030 S86 -3885 93 1080 S36 -4585 93 1130 G291 -5327 93 1180 G191 -6027 93 1031 S85 -3899 224 1081 S35 -4599 224 1131 G289 -5341 224 1181 G189 -6041 224 1032 S84 -3913 93 1082 S34 -4613 93 1132 G287 -5355 93 1182 G187 -6055 93 1033 S83 -3927 224 1083 S33 -4627 224 1133 G285 -5369 224 1183 G185 -6069 224 1034 S82 -3941 93 1084 S32 -4641 93 1134 G283 -5383 93 1184 G183 -6083 93 1035 S81 -3955 224 1085 S31 -4655 224 1135 G281 -5397 224 1185 G181 -6097 224 1036 S80 -3969 93 1086 S30 -4669 93 1136 G279 -5411 1186 G179 -6111 1037 S79 -3983 224 1087 S29 -4683 224 1137 G277 -5425 224 1187 G177 -6125 224 1038 S78 -3997 93 1088 S28 -4697 93 1138 G275 -5439 93 1188 G175 -6139 93 1039 S77 -4011 1089 S27 -4711 1139 G273 -5453 224 1189 G173 -6153 224 1040 S76 -4025 93 1090 S26 -4725 93 1140 G271 -5467 93 1190 G171 -6167 93 1041 S75 -4039 224 1091 S25 -4739 224 1141 G269 -5481 224 1191 G169 -6181 224 1042 S74 -4053 93 1092 S24 -4753 93 1142 G267 -5495 93 1192 G167 -6195 93 1043 S73 -4067 224 1093 S23 -4767 224 1143 G265 -5509 224 1193 G165 -6209 224 1044 S72 -4081 93 1094 S22 -4781 93 1144 G263 -5523 93 1194 G163 -6223 93 1045 S71 -4095 224 1095 S21 -4795 224 1145 G261 -5537 224 1195 G161 -6237 224 1046 S70 -4109 93 1096 S20 -4809 93 1146 G259 -5551 93 1196 G159 -6251 93 1047 S69 -4123 224 1097 S19 -4823 224 1147 G257 -5565 224 1197 G157 -6265 224 1048 S68 -4137 93 1098 S18 -4837 93 1148 G255 -5579 93 1198 G155 -6279 93 1049 S67 -4151 224 1099 S17 -4851 224 1149 G253 -5593 224 1199 G153 -6293 224 1050 S66 -4165 93 1100 S16 -4865 93 1150 G251 -5607 93 1200 G151 -6307 93 224 224 93 93 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 21 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color No. Pad name X Y No. Pad name X Y 1201 G149 -6321 224 1251 G49 -7021 224 1202 G147 -6335 93 1252 G47 -7035 93 1203 G145 -6349 224 1253 G45 -7049 224 1204 G143 -6363 93 1254 G43 -7063 93 1205 G141 -6377 224 1255 G41 -7077 224 1206 G139 -6391 93 1256 G39 -7091 93 1207 G137 -6405 224 1257 G37 -7105 224 1208 G135 -6419 93 1258 G35 -7119 93 1209 G133 -6433 224 1259 G33 -7133 224 1210 G131 -6447 93 1260 G31 -7147 93 1211 G129 -6461 224 1261 G29 -7161 224 1212 G127 -6475 93 1262 G27 -7175 93 1213 G125 -6489 224 1263 G25 -7189 224 1214 G123 -6503 93 1264 G23 -7203 93 1215 G121 -6517 224 1265 G21 -7217 224 1216 G119 -6531 93 1266 G19 -7231 93 1217 G117 -6545 224 1267 G17 -7245 224 1218 G115 -6559 93 1268 G15 -7259 93 1219 G113 -6573 224 1269 G13 -7273 224 1220 G111 -6587 93 1270 G11 -7287 93 1221 G109 -6601 224 1271 G9 -7301 224 1222 G107 -6615 93 1272 G7 -7315 93 1223 G105 -6629 224 1273 G5 -7329 224 1224 G103 -6643 93 1274 G3 -7343 93 1225 G101 -6657 224 1275 G1 -7357 224 1226 G99 -6671 93 1276 DUMMY -7371 93 1227 G97 -6685 224 1277 DUMMY -7385 224 1228 G95 -6699 93 1278 DUMMY -7399 93 1229 G93 -6713 224 1230 G91 -6727 93 1231 G89 -6741 224 1232 -6755 93 G87 1233 G85 -6769 224 1234 G83 -6783 93 1235 G81 -6797 224 1236 G79 -6811 93 1237 G77 -6825 224 1238 G75 -6839 93 1239 G73 -6853 224 1240 G71 -6867 93 1241 G69 -6881 224 1242 G67 -6895 93 1243 G65 1244 G63 1245 G61 -6937 224 1246 G59 -6951 93 1247 G57 -6965 224 1248 G55 -6979 93 1249 G53 -6993 224 1250 G51 -7007 93 ILI9341 Alignment mark X Y -6909 224 Left COG Align -7480 225 -6923 93 Right COG Align 7480 225 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 22 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 BUMP Size Input Pad (1 ~ 232) x x 2 5 1 0 0 3 1 Output Pad (233 ~ 1278) 1 0 0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 23 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 6. Block Function Description MCU System Interface ILI9341 provides four kinds of MCU system interface with 8080- Ⅰ/8080-Ⅱ series parallel interface and 3-/4-line serial interface. The selection of the given interfaces are done by external IM [3:0] pins and shown as below: IM3 IM2 IM1 IM0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 1 1 1 1 0 In 8080- Pins in use MCU-Interface Mode Ⅰ 8080 MCU 16-bit bus interface Ⅰ 8080 MCU 9-bit bus interface Ⅰ 8080 MCU 18-bit bus interface Ⅰ 3-wire 9-bit data serial interface Ⅰ 4-wire 8-bit data serial interface Ⅰ 8080 MCU 16-bit bus interface Ⅱ 8080 MCU 8-bit bus interface Ⅱ 8080 MCU 18-bit bus interface Ⅱ 8080 MCU 9-bit bus interface Ⅱ 3-wire 9-bit data serial interface Ⅱ 4-wire 8-bit data serial interface Ⅱ Register/Content GRAM D[7:0] D[7:0],WRX,RDX,CSX,D/CX D[7:0] D[15:0],WRX,RDX,CSX,D/CX D[7:0] D[8:0],WRX,RDX,CSX,D/CX D[7:0] D[17:0],WRX,RDX,CSX,D/CX 8080 MCU 8-bit bus interface SCL,SDA,CSX SCL,SDA,D/CX,CSX D[8:1] D[17:10],D[8:1],WRX,RDX,CSX,D/CX D[17:10] D[17:10],WRX,RDX,CSX,D/CX D[8:1] D[17:0],WRX,RDX,CSX,D/CX D[17:10] D[17:9],WRX,RDX,CSX,D/CX SCL,SDI,SDO, CSX SCL,SDI,D/CX,SDO, CSX Ⅰ/8080-Ⅱ series parallel interface, the registers are accessed by the D[17:0] data pins. Ⅰ Series Ⅱ Series 8080CSX D/CX RDX “L” “L” “H” “L” “H” “L” “H” 8080WRX “H” “H” CSX D/CX RDX “L” “L” “H” “L” “H” “L” “H” Operation WRX Write command “H” “H” Read parameter Write parameter Parallel RGB Interface ILI9341 also supports the RGB interface for displaying a moving picture. When the RGB interface is selected, display operation is synchronized with externally signals, VSYNC, HSYNC, and DOTCLK and input display data is written in synchronization with these signals according to the polarity of enable signal (DE). Graphic RAM (GRAM) GRAM is a graphic RAM to store display data. GRAM size is 172,800 bytes with 18 bits per pixel for a maximum 240(RGB) x320 dot graphic display. Grayscale Voltage Generating Circuit Grayscale voltage generating circuit generates a liquid crystal drive voltage, which corresponds to grayscale level set in the gamma correction register. ILI9341 can display maximum 262,144 colors. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 24 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 Power Supply Circuit The LCD drive power supply circuit generates the voltage levels as GVDD, VGH, VGL and VCOM for driving TFT LCD panel. Timing controller The timing controller generates all the timing signals for display and GRAM access. Oscillator ILI9341 incorporates RC oscillator circuit and output a stable output frequency for operation. Panel Driver Circuit Liquid crystal display driver circuit consists of 720-output source driver (S1~S720), 320-output gate driver (G1~G320), and VCOM signal. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 25 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7. Function Description 7.1. MCU interfaces ILI9341 provides the 8-/9-/16-/18-bit parallel system interface for 8080- Ⅰ/8080-Ⅱ series, and 3-/4-line serial system interface for serial data input. The input system interface is selected by external pins IM [3:0] and the bit formal per pixel color order is selected by DBI [2:0] bits of 3Ah register. 7.1.1. MCU interface selection The selection of interface is done by setting external pins IM [3:0] as shown in the following table. IM2 IM1 IM0 0 0 0 0 8080 MCU 8-bit bus interface D[7:0] D[7:0],WRX,RDX,CSX,D/CX 0 0 0 1 8080 MCU 16-bit bus interface D[7:0] D[15:0] ,WRX,RDX,CSX,D/CX 0 0 1 0 D[7:0] D[8:0] ,WRX,RDX,CSX,D/CX 0 0 1 1 D[7:0] D[17:0] ,WRX,RDX,CSX,D/CX 0 1 0 1 0 1 1 0 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 1 1 1 1 0 MCU-Interface Mode Pins in use IM3 Ⅰ Ⅰ 8080 MCU 9-bit bus interface Ⅰ 8080 MCU 18-bit bus interface Ⅰ 3-wire 9-bit data serial interface Ⅰ 4-wire 8-bit data serial interface Ⅰ 8080 MCU 16-bit bus interface Ⅱ 8080 MCU 8-bit bus interface Ⅱ 8080 MCU 18-bit bus interface Ⅱ 8080 MCU 9-bit bus interface Ⅱ 3-wire 9-bit data serial interface Ⅱ 4-wire 8-bit data serial interface Ⅱ Register/Content GRAM SCL,SDA,CSX SCL,SDA,D/CX,CSX D[8:1] D[17:10],D[8:1],WRX,RDX,CSX,D/CX D[17:10] D[17:10],WRX,RDX,CSX,D/CX D[8:1] D[17:0],WRX,RDX,CSX,D/CX D[17:10] D[17:9],WRX,RDX,CSX,D/CX SCL,SDI,SDO, CSX SCL,SDI,D/CX,SDO, CSX The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 26 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.1.2. 8080-Ⅰ Ⅰ Series Parallel Interface ILI9341 can be accessed via 8-/9-/16-/18-bit MCU 8080- Ⅰ series parallel interface. The chip-select CSX (active low) is used to enable or disable ILI9341 chip. The RESX (active low) is an external reset signal. WRX is the parallel data write strobe, RDX is the parallel data read strobe and D[17:0] is parallel data bus. ILI9341 latches the input data at the rising edge of WRX signal. The D/CX is the signal of data/command selection. When D/CX=’1’, D [17:0] bits are display RAM data or command’s parameters. When D/CX=’0’, D [17:0] bits are commands. Ⅰ series bi-directional interface can be used for communication between the MCU controller and LCD driver chip. The 8080-Ⅰ Interface selection is done when IM3 pin is low state (VSS level). Interface bus width The 8080- can be selected by IM [2:0] bits. The selection of 8080- IM3 IM2 IM1 IM0 Ⅰ series parallel interface is shown as the table in the following. MCU-Interface Mode CSX WRX “L” 0 0 0 0 8080 MCU 8-bit bus interface Ⅰ “L” 0 0 1 8080 MCU 16-bit bus interface Ⅰ “L” 0 1 0 8080 MCU 9-bit bus interface Ⅰ “L” 0 1 1 8080 MCU 18-bit bus interface Ⅰ “L” “H” Write parameter or display data. “H” Reads parameter or display data. “L” Write command code. “H” Read internal status. “H” Write parameter or display data. “H” Reads parameter or display data. “L” Write command code. “H” Read internal status. “H” Write parameter or display data. “H” Reads parameter or display data. “L” Write command code. “H” Read internal status. “H” Write parameter or display data. “H” Reads parameter or display data. “H” “H” “H” “H” “H” “H” “H” “L” “L” Read internal status. “H” “L” 0 “H” “H” “L” “L” Write command code. “H” “L” 0 “L” “H” “L” “L” “H” “H” “L” 0 D/CX “H” “L” “L” RDX “H” “H” Function The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 27 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.1.3. Write Cycle Sequence The WRX signal is driven from high to low and then be pulled back to high during the write cycle. The host processor provides information during the write cycle when the display module captures the information from host processor on the rising edge of WRX. When the D/CX signal is driven to low level, then input data on the interface is interpreted as command information. The D/CX signal also can be pulled high level when the data on the interface is RAM data or command’s parameter. The following figure shows a write cycle for the 8080- Ⅰ MCU interface. Host ILI9341 Interface Note: WRX is an unsynchronized signal (It can be stopped) The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 28 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.1.4. Read Cycle Sequence The RDX signal is driven from high to low and then allowed to be pulled back to high during the read cycle. The display module provides information to the host processor during the read cycle while the host processor reads the display module information on the rising edge of RDX signal. When the D/CX signal is driven to low level, then input data on the interface is interpreted as command. The D/CX signal also can be pulled high level when the data on the interface is RAM data or command parameter. The following figure shows the read cycle for the 8080- Ⅰ MCU interface. ` ILI9341 Host Interface Note: RDX is an unsynchronized signal (It can be stopped). Note: Read data is only valid when the D/CX input is pulled high. If D/CX is driven low during read then the display information outputs will be High-Z. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 29 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.1.5. 8080-Ⅱ Ⅱ Series Parallel Interface ILI9341 can be accessed via 8-/9-/16-/18-bit MCU 8080- Ⅱ series parallel interface. The chip-select CSX (active low) is used to enable or disable ILI9341 chip. The RESX (active low) is an external reset signal. WRX is the parallel data write strobe, RDX is the parallel data read strobe and D[17:0] is parallel data bus. ILI9341 latches the input data at the rising edge of WRX signal. The D/CX is the signal of data/command selection. When D/CX=’1’, D [17:0] bits are display RAM data or command’s parameters. When D/CX=’0’, D [17:0] bits are commands. Ⅱ series bi-directional interface can be used for communication between the MCU controller and LCD driver chip. The 8080-Ⅱ Interface selection is done when IM3 pin is high state (VDDI level). Interface bus width The 8080- can be selected by IM [2:0] bits. The selection of 8080- IM3 IM2 IM1 Ⅱ series parallel interface is shown as the table in the following. IM0 MCU-Interface Mode CSX WRX “L” 1 0 0 0 8080 MCU 16-bit bus interface Ⅱ “L” 0 0 1 8080 MCU 8-bit bus interface Ⅱ “L” 0 1 0 8080 MCU 18-bit bus interface Ⅱ “L” 0 1 1 8080 MCU 9-bit bus interface Ⅱ “L” “H” Write parameter or display data. “H” Reads parameter or display data. “L” Write command code. “H” Read internal status. “H” Write parameter or display data. “H” Reads parameter or display data. “L” Write command code. “H” Read internal status. “H” Write parameter or display data. “H” Reads parameter or display data. “L” Write command code. “H” Read internal status. “H” Write parameter or display data. “H” Reads parameter or display data. “H” “H” “H” “H” “H” “H” “H” “L” “L” Read internal status. “H” “L” 1 “H” “H” “L” “L” Write command code. “H” “L” 1 “L” “H” “L” “L” “H” “H” “L” 1 D/CX “H” “L” “L” RDX “H” “H” Function The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 30 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.1.6. Write Cycle Sequence The WRX signal is driven from high to low and then be pulled back to high during the write cycle. The host processor provides information during the write cycle when the display module captures the information from host processor on the rising edge of WRX. When the D/CX signal is driven to low level, then input data on the interface is interpreted as command information. The D/CX signal also can be pulled high level when the data on the interface is RAM data or command’s parameter. The following figure shows a write cycle for the 8080- Ⅱ MCU interface. Host ILI9341 Interface Note: WRX is an unsynchronized signal (It can be stopped) The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 31 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.1.7. Read Cycle Sequence The RDX signal is driven from high to low and then allowed to be pulled back to high during the read cycle. The display module provides information to the host processor during the read cycle while the host processor reads the display module information on the rising edge of RDX signal. When the D/CX signal is driven to low level, then input data on the interface is interpreted as command. The D/CX signal also can be pulled high level when the data on the interface is RAM data or command parameter. The following figure shows the read cycle for the 8080- Ⅱ MCU interface. ILI9341 Host Interface Note: RDX is an unsynchronized signal (It can be stopped). Note: Read data is only valid when the D/CX input is pulled high. If D/CX is driven low during read then the display information outputs will be High-Z. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 32 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.1.8. Serial Interface The selection of interface is done by IM [3:0] bits. Please refer to the Table in the following. IM3 IM2 IM1 IM0 MCU-Interface Mode CSX D/CX 0 1 0 1 3-line serial interface “L” - Read/Write command, parameter or display data. 0 1 1 0 4-line serial interface “L” ‘H/L” Read/Write command, parameter or display data. 1 1 0 1 3-line serial interface “L” - Read/Write command, parameter or display data. 1 1 1 0 4-line serial interface “L” ‘H/L” Read/Write command, parameter or display data. SCL Function ILI9341 supplies 3-lines/ 9-bit and 4-line/8-bit bi-directional serial interfaces for communication between host and ILI9341. The 3-line serial mode consists of the chip enable input (CSX), the serial clock input (SCL) and serial data Input/Output (SDA or SDI/SDO). The 4-line serial mode consists of the Data/Command selection input (D/CX), chip enable input (CSX), the serial clock input (SCL) and serial data Input/Output (SDA or SDI/SDO) for data transmission. The data bus (D [17:0]), which are not used, must be connected to GND. Serial clock (SCL) is used for interface with MCU only, so it can be stopped when no communication is necessary. 7.1.9. Write Cycle Sequence The write mode of the interface means that host writes commands or data to ILI9341. The 3-lines serial data packet contains a data/command select bit (D/CX) and a transmission byte. If the D/CX bit is “low”, the transmission byte is interpreted as a command byte. If the D/CX bit is “high”, the transmission byte is stored as the display data RAM (Memory write command), or command register as parameter. Any instruction can be sent in any order to ILI9341 and the MSB is transmitted first. The serial interface is initialized when CSX is high status. In this state, SCL clock pulse and SDA data are no effect. A falling edge on CSX enables the serial interface and indicates the start of data transmission. See the detailed data format for 3-/4-line serial interface. Data Format for 3-line Serial Interface Transmission byte may be Command or Data MSB D/CX D/CX D7 8-bit Transmission Byte LSB D6 D/CX D5 D4 D3 D2 D1 D0 8-bit Transmission Byte Data/Command select bit The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 33 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 Data Format for 4-line Serial Interface Transmission byte may be Command or Data MSB D7 8-bit Transmission Byte LSB D6 D5 D4 8-bit Transmission Byte D3 D2 D1 D0 8-bit Transmission Byte The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 34 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 Host processor drives the CSX pin to low and starts by setting the D/CX bit on SDA. The bit is read by ILI9341 on the first rising edge of SCL signal. On the next falling edge of SCL, the MSB data bit (D7) is set on SDA by the host. On the next falling edge of SCL, the next bit (D6) is set on SDA. If the optional D/CX signal is used, a byte is eight read cycle width. The 3/4-line serial interface writes sequence described in the figure as below. 3-line Serial Interface Protocol S TB TB P CSX Host (MCU to Driver) 0 SDA D7 D6 D5 D4 D3 D2 D1 D0 D/C D7 D6 D5 D4 D3 D2 D1 D0 SCL Command Data / Command / Parameter The CSX can be high level between the data and next command.The SDA and SCL are invalid during CSX is high level 4 -lin e S e ria l In te rfa c e P ro to c o l S TB TB P CSX 0 D /C X TB D /C SCL SDA D7 D6 D5 D4 D3 D2 D1 D0 C om m and D7 D6 D5 D4 D3 D2 D1 D0 D a ta / C o m m a n d / P a ra m e te r C S X c a n b e "H " b e tw e e n c o m m a n d / c o m m a n d a n d p a ra m e te r / c o m m a n d . S C L a n d S D A d u rin g C S X = "H " is in v a lid . The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 35 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.1.10. Read Cycle Sequence The read mode of interface means that the host reads register’s parameter or display data from ILI9341. The host has to send a command (Read ID or register command) and then the following byte is transmitted in the opposite direction. ILI9341 latches the SDA (input data) at the rising edges of SCL (serial clock), and then shifts SDA (output data) at falling edges of SCL (serial clock). After the read status command has been sent, the SDA line must be set to tri-state and no later than at the falling edge of SCL of the last bit. The read mode has three types of transmitted command data (8-/24-/32-bit) according command code. 3-wire Serial Interface Protocol 3-wire Serial Protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read) S TB TB P S CSX SCL Interface I SDA D/C D7 D6 D5 D4 D3 D2 D1 D0 D/C D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D/C D/C SDA Interface II D7 SDO D6 D5 Command D4 D3 D2 D1 D0 Read Data Output 3-wire Serial Protocol (for RDDID command: 24-bit read) S TB TB P S CSX SCL Interface I SDA D/C D7 D6 D5 D4 D3 D2 D1 D0 SDA D/C D7 D6 D5 D4 D3 D2 D1 D0 D23 D22 D21 D2 D1 D0 D/C D/C Interface II D23 SDO D22 D21 D2 D1 D0 Multi-byte Read Data Output Command Dummy Clock Cycle The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 36 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 3-wire Serial Protocol (for RDDST command: 32-bit read) S TB TB P S CSX SCL Interface I SDA D/C D7 D6 D5 D4 D3 D2 D1 D0 SDA D/C D7 D6 D5 D4 D3 D2 D1 D0 D31 D30 D29 D2 D1 D0 D/C D/C Interface II D31 SDO D30 D29 D2 D1 D0 Multi-byte Read Data Output Command Dummy Clock Cycle The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 37 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 4-wire Serial Interface Protocol 4-wire Serial Protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read) S TB TB P S CSX SCL 0 D/CX Interface I SDA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SDI Interface II SDO Command Read Data Output 4-wire Serial Protocol (for RDDID command: 24-bit read) S TB TB P S CSX SCL 0 D/CX Interface I SDA D7 D6 D5 D4 D3 D2 D1 D0 SDI D7 D6 D5 D4 D3 D2 D1 D0 D23 D22 D21 D2 D1 D0 D23 D22 D21 D2 D1 D0 Interface II SDO Multi-byte Read Data Output Command Dummy Clock Cycle The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 38 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 4-wire Serial Protocol (for RDDST command: 32-bit read) S TB TB P S CSX SCL 0 D/CX Interface I SDA D7 D6 D5 D4 D3 D2 D1 D0 SDI D7 D6 D5 D4 D3 D2 D1 D0 D31 D30 D29 D2 D1 D0 D31 D30 D29 D2 D1 D0 Interface II SDO Multi-byte Read Data Output Command Dummy Clock Cycle The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 39 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.1.11. Data Transfer Break and Recovery If there is a break in data transmission by RESX pulse, while transferring a command or frame memory data or multiple parameter command data, before Bit D0 of the byte has been completed, then the driver will reject the previous bits and have reset the interface such that it will be ready to receive command data again when the chip select pin (CSX) is activated after RESX have been high state. S TB TB P CSX RESX Wait for more than 10us Driver (MPU to Driver) SCL SDA D/C D7 D6 D5 D4 D3 D2 D/C D7 D6 D5 Command / Parameter / Data D4 D3 D2 D1 D0 Command ”” The SCL and SDA during RESX= L is invalid and next byte becomes command . If there is a break in data transmission by CSX pulse, while transferring a command or frame memory data or multiple parameter command data, before Bit D0 of the byte has been completed, then the driver will reject the previous bits and have reset the interface such that it will be ready to receive the same byte re-transmitted when the chip select pin (CSX) is next activated. S TB TB P CSX Driver (MPU to Driver) SCL SDA D/C D7 D6 D5 D4 Data / Command / Parameter D/C Break D7 D6 D5 D4 D3 D2 D1 D0 Data / Command / Parameter If a two or more parameter command is being sent and a break occurs while sending any parameter before the last one and if the host then sends a new command rather than continue to send the remained parameters that was interrupted, then the parameters which had been successfully sent are stored and the parameter where the break occurred is rejected. The interface is ready to receive next byte as shown below. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 40 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Break Command 1 Parameter 11 Parameter 12 ILI9341 Parameter11 is successfully sent, but Parameter12 is breaked and needed to be transfer again. Command 2 Command 1 Parameter 11 Parameter 12 Parameter 13 Command1 with first parameter (Parameter11) sould be excuted again to write remained parameter(Parameter12 and Parameter13) If a two or more parameter command is being sent and a break occurs by the other command before the last one is sent, then the parameters which had been successfully sent are stored and the other parameter of that command remains previous value. Break Command 1 Parameter 11 Parameter11 is successfully sent, but other parameters are not sent and broken by the other command. Command 2 Command 1 Parameter 11 Parameter 12 Parameter 13 Command1 with first parameter (Parameter11) sould be excuted again to write remained parameter(Parameter12 and Parameter13) The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 41 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.1.12. Data Transfer Pause It will be possible when transferring a command, frame memory data or multiple parameter data to invoke a pause in the data transmission. If the chip select pin (CSX) is released to high state after a whole byte of a frame memory data or multiple parameter data has been completed, then ILI9341 will wait and continue the frame memory data or parameter data transmission from the point where it was paused. If the chip select pin is released after a whole byte of a command has been completed, then the display module will receive either the command’s parameters (if appropriate) or a new command when the chip select pin is next enabled as shown below. This applies to the following 4 conditions: 1) Command-Pause-Command 2) Command-Pause-Parameter 3) Parameter-Pause-Command 4) Parameter-Pause-Parameter Condition 1: The host transmits a new Command (Command 2) when a pause occurs after Command 1. Condition 4: The host continues to transmit the remain parameter (Parameter 22) when a pause occurs after Parameter 21. Command 2 Parameter 21 Parameter 22 Pause Command 1 Pause Parameter 11 Pause Condition 3: The host transmits a new command (Command 3) when a pause occurs after Parameter 11. Command 3 Condition 2: The host continues to transmit the remain parameter (Parameter 11) when a pause occurs after Command 1. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 42 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.1.13. Serial Interface Pause (3_wire) S TB TB P CSX Host (MCU to Driver) SDA 0 D7 D6 D5 D4 D3 D2 D1 D0 D/C D7 D6 D5 D4 D3 D2 D1 D0 SCL Command Data / Command / Parameter The CSX can be high level between the data and next command.The SDA and SCL are invalid during CSX is high level 7.1.14. Parallel Interface Pause CSX Pause D/CX RDX WRX D[17:0] D17 to D0 Command / Parameter D17 t o D0 Pause Command / Parameter The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 43 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.1.15. Data Transfer Mode ILI9341 can provide two different kinds of color depth (16-bit/pixel and 18-bit/pixel) display data to the graphic RAM. The data format is described for each interface. Data can be downloaded to the frame memory by 2 methods. 7.1.16. Data Transfer Method 1 The image data is sent to the frame memory in the successive frame writing, each time the frame memory is filled by image data, the frame memory pointer is reset to the start point and the next frame is written. Start Start Frame Memory Write Stop Image Data Frame 1 Image Data Frame 2 Image Data Frame 3 Any Command 7.1.17. Data Transfer Method 2 Image data is sent and at the end of each frame memory download, a command is sent to stop frame memory writing. Then start memory write command is sent, and a new frame is downloaded. Start Start Frame Image Data Memory Frame 1 Write Stop Any Command Start Frame Image Data Memory Frame 2 Write Any Command Any Command Note 1: These methods are applied to all data transfer color modes on both serial and parallel interfaces. Note 2: The frame memory can contain both odd and even number of pixels for both methods. Only complete pixel data will be stored in the frame memory. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 44 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.2. RGB Interface 7.2.1. RGB Interface Selection ILI9341 has two kinds of RGB interface and these interfaces can be selected by RCM [1:0] bits. When RCM [1:0] bits are set to “10”, the DE mode is selected which utilizes VSYNC, HSYNC, DOTCLK, DE, D [17:0] pins; when RCM [1:0] bits are set to “11”, the SYNC mode is selected which utilizes which utilizes VSYNC, HSYNC, DOTCLK, D [17:0] pins. Using RGB interface must selection serial interface. ILI9341 supports several pixel formats that can be selected by DPI [2:0] bits of “Pixel Format Set (3Ah)” and RIM bit of RF6h command. The selection of a given interfaces is done by setting RCM [1:0] and DPI [2:0] as show in the following table. RCM[1:0] RIM RGB Interface Mode DPI[2:0] 1 0 0 1 1 0 18-bit RGB interface (262K colors) 1 0 0 1 0 1 16-bit RGB interface (65K colors) RGB Mode Used Pins VSYNC, HSYNC, DE, DOTCLK,D[17:0] VSYNC, HSYNC, DE, DOTCLK, D[17:13] & D[11:1] DE Mode Valid data is determined by the DE signal 1 0 1 1 1 0 6-bit RGB interface (262K colors) 1 0 1 1 0 1 6-bit RGB interface (65K colors) VSYNC, HSYNC, DE, DOTCLK, D[5:0] 1 1 0 1 1 0 18-bit RGB interface (262K colors) VSYNC, HSYNC, DOTCLK, D[17:0] 1 1 0 1 0 1 16-bit RGB interface (65K colors) 1 1 1 1 1 0 6-bit RGB interface (262K colors) 1 1 1 1 0 1 6-bit RGB interface (65K colors) VSYNC, HSYNC, DE, DOTCLK, D[5:0] SYNC Mode VSYNC, HSYNC, DOTCLK, D[17:13] & D[11:1] In SYNC mode, DE signal is ignored; blanking porch is determined by B5h command. VSYNC, HSYNC, DOTCLK, D[5:0] VSYNC, HSYNC, DOTCLK, D[5:0] 18-bit data bus interface (D[17:0] is used) , DPI[2:0] = 110, and RIM=0 D17 18bpp Frame Memory Write R[5] D16 R[4] D15 R[3] D14 R[2] D13 R[1] D12 R[0] D11 G[5] D10 G[4] D9 G[3] D8 G[2] D7 G[1] D6 G[0] D5 B[5] D4 B[4] D3 B[3] D2 B[2] D1 B[1] D0 B[0] 16-bit data bus interface (D[17:13] & D[11:1] is used) , DPI[2:0] = 101, and RIM=0 D17 16bpp Frame Memory Write R[4] D16 R[3] D15 R[2] D14 R[1] D13 R[0] D12 D11 G[5] D10 G[4] D9 G[3] D8 G[2] D7 G[1] D6 G[0] D5 B[4] D4 B[3] D3 B[2] D2 B[1] D1 B[0] D0 D2 G[2] D1 G[1] D0 G[0] D5 B[5] D4 B[4] D3 B[3] D2 B[2] D1 B[1] D0 B[0] D2 G[2] D1 G[1] D0 G[0] D5 B[4] D4 B[3] D3 B[2] D2 B[1] D1 B[0] D0 The LSB data of red/blue color depends on the EPF[1:0] setting. 6-bit data bus interface (D[5:0] is used) , DPI[2:0] = 110, and RIM=1 D17 D5 18bpp Frame Memory Write R[5] D4 R[4] D3 R[3] D2 R[2] D1 R[1] D0 R[0] D5 G[5] D4 G[4] D3 G[3] 6-bit data bus interface (D[5:0] is used) , DPI[2:0] = 101, and RIM=1 D17 D5 16bpp Frame Memory Write R[4] D4 R[3] D3 R[2] D2 R[1] D1 R[0] D0 D5 G[5] D4 G[4] D3 G[3] The LSB data of red/blue color depends on the EPF[1:0] setting. Pixel clock (DOTCLK) is running all the time without stopping and used to enter VSYNC, HSYNC, DE and D [17:0] states when there is a rising edge of the DOTCLK. Vertical synchronization (VSYNC) is used to tell when The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 45 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 there is received a new frame of the display. This is low enable and its state is read to the display module by a rising edge of the DOTCLK signal. Horizontal synchronization (HSYNC) is used to tell when there is received a new line of the frame. This is low enable and its state is read to the display module by a rising edge of the DOTCLK signal. In DE mode, Data Enable (DE) is used to tell when there is received RGB information that should be transferred on the display. This is a high enable and its state is read to the display module by a rising edge of the DOTCLK signal. D [17:0] are used to tell what is the information of the image that is transferred on the display (When DE= ’0’ (low) and there is a rising edge of DOTCLK). D [17:0] can be ‘0’ (low) or ‘1’ (high). These lines are read by a rising edge of the DOTCLK signal. In SYNC mode, the valid display data in inputted in pixel unit via D [17:0] according to HFP/HBP settings of HSYNC signal and VFP/VBP setting of VSYNC. In both RGB interface modes, the input display data is written to GRAM first then outputs corresponding source voltage according the gray data from GRAM. VBP VAdr HAdr HFP (Hsync + HBP) – Horizontal interval when no valid display data is sent from host to display (Vsync + VBP) - Vertical interval when no valid display data is transferred from host to display VFP HBP HFP - Horizontal interval when no valid display data is sent from host to display Vsync Hsync (VAdr + HAdr) - Period when valid display data are transferred from host to display module VFP -- Vertic al interval when no valid display data is transferred from host to display Parameters Horizontal Synchronization Horizontal Back Porch Horizontal Address Horizontal Front Porch Vertical Synchronization Vertical Back Porch Vertical Address Vertical Front Porch Symbols Hsync HBP HAdr HFP Vsync VBP VAdr VFP Condition Min. 2 2 2 1 1 3 Typ. 10 20 240 10 2 2 320 4 Max. 16 24 16 4 - Units DOTCLK DOTCLK DOTCLK DOTCLK Line Line Line Line Typical values are setting example when used with panel resolution 240 x 320 (QVGA), clock frequency 6.35MHz and frame The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 46 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 frequency about 70Hz. Notes: 1. Vertical period (one frame) shall be equal to the sum of Vsync + VBP + VAdr + VFP. 2. Horizontal period (one line) shall be equal to the sum of Hsync + HBP + HAdr + HFP. 3. Control signals PCLK and Hsync shall be transmitted as specified at all times while valid pixels are transferred between the host processor and the display module. Also make sure that (Number of PCLK per 1 line) ≥ (Number of RTN clock) x Division ratio (DIV) x PCDIV Setting Example for Display Control Clock in RGB Interface Operation Register Display operation using DPI is in synchronization with internal clock PCLKD which is generated by dividing DOTCLK. PCDIV [5:0]: Number of DOTCLK during internal clock PCLKD’s high / low period. In units of 1 clock. PCDIV specifying DOTCLK’s division ratio, are determined so that difference between PCLKD’s frequency and internal oscillation clock 615KHz is the smallest. Set PCDIV follow the restriction (Number of PCLK in 1H) ≥ (Number of RTN clock) x Division ratio (DIV) x PCDIV. Setting Example: To set frame frequency to 70Hz: Internal Clock Internal Oscillation Clock: 615KHz DIV[1:0] = 2’b0 (x 1/1) RTN[4:0] = 5’h1b (27 clocks) FP = 7'h2 (2 lines), BP = 7'h2 (2 lines), NL = 6’h27 (320 lines) Frame Rate 70.30Hz DOTCLK HSYNC = 10 CLK HBP = 20 CLK HFP=10 CLK 70Hz x (2 + 320 + 2) lines x (10 + 20 + 240 + 10) clocks = 6.35MHz DOTCLK frequency = 6.35MHz 6.35 MHz / 615KHz = 10.32 Set PCDIV so that PCLK is divided by 10. external fosc = 6.35 MHz / 10 = 635KHz PCDIV = [ 6.35MHz / 635KHz) / 2 ] - 1 = 4 PCDIV[5:0] = 6’h04 (10 DOTCLK) The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 47 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 48 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.2.2. RGB Interface Timing The timing chart of 18-/16-bit RGB interface mode is shown as below. 1 frame Front porch Back porch VSYNC VLW>=1H HSYNC DOTCLK ENABLE D[17:0] HLW>=2DOTCLKs HSYNC 1H DOTCLK ENABLE DTST>=HLW D[5:0] RG B RG B B R G B Valid data VLW : VSYNC Low Width HLW : HSYNC Low Width DTST : Data Transfer Startup Time DOTCLK PCDIVH[3:0] PCDIVL[3:0] PCLKD Note 1: The DE signal is not needed when RGB interface SYNC mode is selected. Note 2: VSPL=’0’, HSPL=’0’, DPL=’0’ and EPL=’0’ of “Interface Mode Control (B0h)” command. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 49 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 The timing chart of 6-bit RGB interface mode is shown as below: 1 frame Front porch Back porch VSYNC VLW>=1H HSYNC DOTCLK ENABLE D[5:0] HLW>=2DOTCLKs HSYNC 1H DOTCLK ENABLE DTST>=HLW D[5:0] RG B RG B B R G B Valid data VLW : VSYNC Low Width HLW : HSYNC Low Width DTST : Data Transfer Startup Time DOTCLK PCDIVH[3:0] PCDIVL[3:0] PCLKD Note 1: The DE signal is not needed when RGB interface SYNC mode is selected. Note 2: VSPL=’0’, HSPL=’0’, DPL=’0’ and EPL=’0’ of “Interface Mode Control (B0h)” command. Note 3: In 6-bit RGB interface mode, each dot of one pixel (R, G and B) is transferred in synchronization with DOTCLK. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 50 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 Note 4: In 6-bit RGB interface mode, set the cycles of VSYNC, HSYNC and DE to 3 multiples of DOTCLK. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 51 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.3. VSYNC Interface ILI9341 supports the VSYNC interface in synchronization with the frame-synchronizing signal VSYNC to display the moving picture with the 8080- Ⅰ/8080-Ⅱ system interface. When the VSYNC interface is selected to display a moving picture, the minimum GRAM update speed is limited and the VSYNC interface is enabled by setting DM[1:0] = “10” and RM = “0”. VSYNC MPU nCS RS nWR DB[17:0] In the VSYNC mode, the display operation is synchronized with the internal clock and VSYNC input and the frame rate is determined by the pulse rate of VSYNC signal. All display data are stored in GRAM to minimize total data transfer required for moving picture display. VSYNC Write data to RAM through system interface Rewriting screen data Rewriting screen data Display operation synchronized with internal clocks The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 52 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 The VSYNC interface has the minimum speed limitation of writing data to the internal GRAM via the system interface, which are calculated from the following formula. Internal clock frequency (fosc.) [Hz] = FrameFrequency x (DisplayLine (NL) + FrontPorch (VFP) + BackPorch (VBP)) x ClockCyclePerLines (RTN) x FrequencyFluctuation. Minimum RAM write speed [Hz] > 240 × DisplayLin es(NL) [BackPorch (VBP) + DisplayLin es(NL) − margins] × Clocks per line × (1/fosc) Note: When the RAM write operation does not start from the falling edge of VSYNC, the time from the falling edge of VSYNC until the start of RAM write operation must also be taken into account. An example of minimum GRAM writing speed and internal clock frequency in VSYNC interface mode is as below. [Example] Display size: 240 RGB × 320 lines Lines: 320 lines (NL = 100111) Back porch: 2 lines (VBP = 0000010) Front porch: 2 lines (VFP = 0000010) Frame frequency: 70 Hz Frequency fluctuation: 10% Internal oscillator clock (fosc.) [Hz] = 70 x [320+ 2 + 2] x 27 clocks x (1.1/0.9) ≒ 748KHz The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 53 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 When calculate the internal clock frequency, the oscillator variation is needed to be taken into consideration. In the above example, the calculated internal clock frequency with ±10% margin variation is considered and ensures to complete the display operation within one VSYNC cycle. The causes of frequency variation come from fabrication process of LSI, room temperature, external resistors and VCI voltage variation. Minimum speed for RAM writing [Hz] > 240 x 320 x 748K / [ (2 + 320 – 2)lines x 27clocks] ≒ 6.65 MHz The above theoretical value is calculated based on the premise that the ILI9341 starts to write data into the internal GRAM on the falling edge of VSYNC. There must at least be a margin of 2 lines between the physical display line and the GRAM line address where data writing operation is performed. The GRAM write speed of 6.65MHz or more will guarantee the completion of GRAM write operation before the ILI9341 starts to display the GRAM data on the screen and enable to rewrite the entire screen without flicker. Notes in using the VSYNC interface 1. The minimum GRAM write speed must be satisfied and the frequency variation must be taken into consideration. 2. The display frame rate is determined by the VSYNC signal and the period of VSYNC must be longer than the scan period of an entire display. 3. When switching from the internal clock operation mode (DM[1:0] = “00”) to the VSYNC interface mode or inversely, the switching starts from the next VSYNC cycle, i.e. after completing the display of the frame. 4. The partial display, vertical scroll, and interlaced scan functions are not available in VSYNC interface mode. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 54 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.4. Color Depth Conversion Look Up Table When ILI9341 operates in parallel 16-bit interface, the color depth conversion is done by look-up table and extend input data format to 18-bit. See the detailed for look-up table of color depth conversion. R input (5-bit) R output (6-bit) 16-bit/pixel –mode 18-bit/pixel –mode 65,536 colors 262,144 colors 00000 R005 R004 R003 R002 R001 R000 1 00001 R015 R014 R013 R012 R011 R010 2 00010 R025 R024 R023 R022 R021 R020 3 00011 R035 R034 R033 R032 R031 R030 4 00100 R045 R044 R043 R042 R041 R040 5 00101 R055 R054 R053 R052 R051 R050 6 00110 R065 R064 R063 R062 R061 R060 7 00111 R075 R074 R073 R072 R071 R070 8 01000 R085 R084 R083 R082 R081 R080 9 01001 R095 R094 R093 R092 R091 R090 10 01010 R105 R104 R103 R102 R101 R100 11 01011 R115 R114 R113 R112 R111 R110 12 01100 R125 R124 R123 R122 R121 R120 13 01101 R135 R134 R133 R132 R131 R130 14 01110 R145 R144 R143 R142 R141 R140 15 01111 R155 R154 R153 R152 R151 R150 16 10000 R165 R164 R163 R162 R161 R160 17 10001 R175 R174 R173 R172 R171 R170 18 10010 R185 R184 R183 R182 R181 R180 19 10011 R195 R194 R193 R192 R191 R190 20 10100 R205 R204 R203 R202 R201 R200 21 10101 R215 R214 R213 R212 R211 R210 22 10110 R225 R224 R223 R222 R221 R220 23 10111 R235 R234 R233 R232 R231 R230 24 11000 R245 R244 R243 R242 R241 R240 25 11001 R255 R254 R253 R252 R251 R250 26 11010 R265 R264 R263 R262 R261 R260 27 11011 R275 R274 R273 R272 R271 R270 28 11100 R285 R284 R283 R282 R281 R280 29 11101 R295 R294 R293 R292 R291 R290 30 11110 R305 R304 R303 R302 R301 R300 31 11111 R315 R314 R313 R312 R311 R310 32 Command Code (0x2Dh) RGBSET Parameter The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 55 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 G input (6-bit) G output (6-bit) 16-bit/pixel –mode 18-bit/pixel –mode 65,536 colors 262,144 colors 000000 G005 G004 G003 G002 G001 G000 33 000001 G015 G014 G013 G012 G011 G010 34 000010 G025 G024 G023 G022 G021 G020 35 000011 G035 G034 G033 G032 G031 G030 36 000100 G045 G044 G043 G042 G041 G040 37 000101 G055 G054 G053 G052 G051 G050 38 000110 G065 G064 G063 G062 G061 G060 39 000111 G075 G074 G073 G072 G071 G070 40 001000 G085 G084 G083 G082 G081 G080 41 001001 G095 G094 G093 G092 G091 G090 42 001010 G105 G104 G103 G102 G101 G100 43 001011 G115 G114 G113 G112 G111 G110 44 001100 G125 G124 G123 G122 G121 G120 45 001101 G135 G134 G133 G132 G131 G130 46 001110 G145 G144 G143 G142 G141 G140 47 001111 G155 G154 G153 G152 G151 G150 48 010000 G165 G164 G163 G162 G161 G160 49 010001 G175 G174 G173 G172 G171 G170 50 010010 G185 G184 G183 G182 G181 G180 51 010011 G195 G194 G193 G192 G191 G190 52 010100 G205 G204 G203 G202 G201 G200 53 010101 G215 G214 G213 G212 G211 G210 54 010110 G225 G224 G223 G222 G221 G220 55 010111 G235 G234 G233 G232 G231 G230 56 011000 G245 G244 G243 G242 G241 G240 57 011001 G255 G254 G253 G252 G251 G250 58 011010 G265 G264 G263 G262 G261 G260 59 011011 G275 G274 G273 G272 G271 G270 60 011100 G285 G284 G283 G282 G281 G280 61 011101 G295 G294 G293 G292 G291 G290 62 011110 G305 G304 G303 G302 G301 G300 63 011111 G315 G314 G313 G312 G311 G310 64 100000 G325 G324 G323 G322 G321 G320 65 100001 G335 G334 G333 G332 G331 G330 66 Command Code (0x2Dh) RGBSET Parameter The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 56 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 G input (6-bit) G output (6-bit) 16-bit/pixel –mode 18-bit/pixel –mode 65,536 colors 262,144 colors 100010 G345 G344 G343 G342 G341 G340 67 100011 G355 G354 G353 G352 G351 G350 68 100100 G365 G364 G363 G362 G361 G360 69 100101 G375 G374 G373 G372 G371 G370 70 100110 G385 G384 G383 G382 G381 G380 71 100111 G395 G394 G393 G392 G391 G390 72 101000 G405 G404 G403 G402 G401 G400 73 101001 G415 G414 G413 G412 G411 G410 74 101010 G425 G424 G423 G422 G421 G420 75 101011 G435 G434 G433 G432 G431 G430 76 101100 G445 G444 G443 G442 G441 G440 77 101101 G455 G454 G453 G452 G451 G450 78 101110 G465 G464 G463 G462 G461 G460 79 101111 G475 G474 G473 G472 G471 G470 80 110000 G485 G484 G483 G482 G481 G480 81 110001 G495 G494 G493 G492 G491 G490 82 110010 G505 G504 G503 G502 G501 G500 83 110011 G515 G514 G513 G512 G511 G510 84 110100 G525 G524 G523 G522 G521 G520 85 110101 G535 G534 G533 G532 G531 G530 86 110110 G545 G544 G543 G542 G541 G540 87 110111 G555 G554 G553 G552 G551 G550 88 111000 G565 G564 G563 G562 G561 G560 89 111001 G575 G574 G573 G572 G571 G570 90 111010 G585 G584 G583 G582 G581 G580 91 111011 G595 G594 G593 G592 G591 G590 92 111100 G605 G604 G603 G602 G601 G600 93 111101 G615 G614 G613 G612 G611 G610 94 111110 G625 G624 G623 G622 G621 G620 95 111111 G635 G634 G633 G632 G631 G630 96 Command Code (0x2Dh) RGBSET Parameter The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 57 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 B input (5-bit) B output (6-bit) 16-bit/pixel –mode 18-bit/pixel –mode 65,536 colors 262,144 colors 00000 B005 B004 B003 B002 B001 B000 97 00001 B015 B014 B013 B012 B011 B010 98 00010 B025 B024 B023 B022 B021 B020 99 00011 B035 B034 B033 B032 B031 B030 100 00100 B045 B044 B043 B042 B041 B040 101 00101 B055 B054 B053 B052 B051 B050 102 00110 B065 B064 B063 B062 B061 B060 103 00111 B075 B074 B073 B072 B071 B070 104 01000 B085 B084 B083 B082 B081 B080 105 01001 B095 B094 B093 B092 B091 B090 106 01010 B105 B104 B103 B102 B101 B100 107 01011 B115 B114 B113 B112 B111 B110 108 01100 B125 B124 B123 B122 B121 B120 109 01101 B135 B134 B133 B132 B131 B130 110 01110 B145 B144 B143 B142 B141 B140 111 01111 B155 B154 B153 B152 B151 B150 112 10000 B165 B164 B163 B162 B161 B160 113 10001 B175 B174 B173 B172 B171 B170 114 10010 B185 B184 B183 B182 B181 B180 115 10011 B195 B194 B193 B192 B191 B190 116 10100 B205 B204 B203 B202 B201 B200 117 10101 B215 B214 B213 B212 B211 B210 118 10110 B225 B224 B223 B222 B221 B220 119 10111 B235 B234 B233 B232 B231 B230 120 11000 B245 B244 B243 B242 B241 B240 121 11001 B255 B254 B253 B252 B251 B250 122 11010 B265 B264 B263 B262 B261 B260 123 11011 B275 B274 B273 B272 B271 B270 124 11100 B285 B284 B283 B282 B281 B280 125 11101 B295 B294 B293 B292 B291 B290 126 11110 B305 B304 B303 B302 B301 B300 127 11111 B315 B314 B313 B312 B311 B310 128 Command Code (0x2Dh) RGBSET Parameter The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 58 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.5. Display Data RAM (DDRAM) ILI9341 has an integrated 240x320x18-bit graphic type static RAM. This 172,800-byte memory allows storing a 240xRGBx320 image with an 18-bit resolution (262K-color). There is no abnormal visible effect on the display when there are simultaneous panel display read and interface read/write to the same location of the frame memory. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 59 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 7.6. Display Data Format ILI9341 supplies 18-/16-/9-/8-bit parallel MCU interface with 8080- ILI9341 Ⅰ/8080-Ⅱ series, 3-/4-line serial interface and 6-/16-18-bit parallel RGB interface. The parallel MCU interface and serial interface mode can be selected by external pins IM [3:0] and RGB interface mode can be selected by software command parameters RCM[1:0]. 7.6.1. 3-line Serial Interface The 3-line/9-bit serial bus interface of ILI9341 can be used by setting external pin as IM [3:0] to “0101” for serial interface I or IM [3:0] to “1101” for serial interface II. The shown figure is the example of 3-line SPI interface. 3-line Serial Interface I MPU SCL CSX SDA Driver D[17:0] 3-line Serial Interface II MPU SCL CSX SDI SD0 Driver D[17:0] In 3-line serial interface, different display data format is available for two color depths supported by the LCM listed below. -65k colors, RGB 5, 6, 5 -bits input -262k colors, RGB 6, 6, 6 -bits input. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 60 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 16 bit/pixel color order (R:5-bit, G:6-bit, B:5-bit), 65,536 colors ‘ 1’ RESX IM[3:0]=0101 or 1101 IM[3:0] CSX Pixel n D8 SDA 1 D7 R1 4 D6 R1 3 D5 D4 R1 2 R1 1 D3 R1 0 Pixel n+1 D2 D1 D0 G1 5 G1 4 G1 3 D8 D7 G1 2 1 D6 D5 D4 G1 1 G1 0 B1 4 D3 D2 B1 3 B1 2 D1 B1 1 D0 B1 0 D8 D7 R2 4 1 D6 R2 3 D5 R2 2 D4 R2 1 D3 R2 0 D2 G2 5 D1 D0 G2 4 G2 3 SCL 16-bit Look-Up Table for 65k Colors mapping (16-bit to 18-bit) 18-bit Frame memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note 1: The pixel data with 16-bit color depth information. Note 2: The most significant bits are: Rx4, Gx5 and Bx4. Note 3: The least significant bits are: Rx0, Gx0 and Bx0. Note 4: ‘-‘= Don’t care –Can be set “0” or “1”. 18 bit/pixel color order (R:6-bit, G:6-bit, B:6-bit), 262,144 colors RESX ‘ 1’ IM[3:0]=0101 or 1101 IM[3:0] CSX Pixel n D8 SDA 1 D7 R1 5 D6 R1 4 D5 R1 3 D4 R1 2 D3 R1 1 D2 R1 0 D1 - D0 - D8 1 D7 G1 5 D6 D5 D4 G1 4 G1 3 G1 2 D3 G1 1 D2 G1 0 D1 D0 D8 - - 1 D7 B1 5 D6 B1 4 D5 B1 3 D4 B1 2 D3 B1 1 D2 B1 0 D1 - D0 - SCL 18-bit Frame memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note 1: The pixel data with 18-bit color depth information. Note 2: The most significant bits are: Rx5, Gx5 and Bx5. Note 3: The least significant bits are : Rx0, Gx0 and Bx0. Note 4: ‘-‘= Don’t care - Can be set “0” or “1”. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 61 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 Read data through 3-line SPI mode RESX ‘ 1’ IM[3:0]=0101 or 1101 IM[3:0] CSX SCL SDA (I/F I) SDI (I/F II) SDA (I/F I) SDO (I/F II) 0 High-Z R2Eh High-Z D23 D22 D21 9 Dummy Clock D20 D19 D18 D17 D16 D2 D1 D0 D23 D22 D21 D20 D19 1-Pixel data Note 1: ‘-‘= Don’t care –Can be set “0” or “1”. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 62 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.6.2. 4-line Serial Interface The 4-line/8-bit serial bus interface of ILI9341 can be used by setting external pin as IM [3:0] to “0110” for serial interface I or IM [3:0] to “1110” for serial interface II. The shown figure is the example of 4-line SPI interface. In 4-line serial interface, different display data format is available for two color depths supported by the LCM listed below. -65k colors, RGB 5, 6, 5 -bits input. -262k colors, RGB 6, 6, 6 -bits input. 16 bit/pixel color order (R:5-bit, G:6-bit, B:5-bit), 65,536 colors RESX ‘ 1’ IM[3:0]=0110 or 1110 IM[3:0] CSX 1 D/CX 1 Pixel n SDA/ SDI 1 Pixel n+1 D7 D6 D5 R1 4 R1 3 R1 2 D4 R1 1 D3 D2 D1 D0 R1 0 G1 5 G1 4 G1 3 D7 G1 2 D6 D5 G1 1 G1 0 D4 B1 4 D3 B1 3 D2 D1 D0 B1 2 B1 1 B1 0 D7 R2 4 D6 R2 3 D5 R2 2 D4 R2 1 D3 R2 0 D2 G2 5 D1 D0 D7 G2 4 G2 3 G2 2 D6 D5 G2 1 G2 0 SCL 16-bit Look-Up Table for 65k Colors mapping (16-bit to 18-bit) 18-bit Frame memory R1 G1 B1 R2 G2 B2 R3 G3 B3 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 63 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 Note 1: The pixel data with 16-bit color depth information. Note 2: The most significant bits are: Rx4, Gx5 and Bx4. Note 3: The least significant bits are: Rx0, Gx0 and Bx0. Note 4: ‘-‘= Don’t care –Can be set “0” or “1”. 18 bit/pixel color order (R:6-bit, G:6-bit, B:6-bit), 262,144 colors ‘ 1’ RESX IM[3:0]=0110 or 1110 IM[3:0] CSX D/CX 1 1 1 Pixel n SDA/ SDI D7 D6 D5 D4 D3 D2 R1 5 R1 4 R1 3 R1 2 R1 1 R1 0 D1 D0 D7 G1 5 D6 D5 G1 4 G1 3 D4 D3 G1 1 G1 2 D2 D1 D0 G1 0 D7 D6 D5 D4 B1 5 B1 4 B1 3 B1 2 D3 B1 1 D2 D1 D0 B1 0 SCL 18-bit Frame memory R1 G1 R2 B1 G2 B2 R3 G3 B3 Note 1: The pixel data with 18-bit color depth information. Note 2: The most significant bits are: Rx5, Gx5 and Bx5. Note 3: The least significant bits are: Rx0, Gx0 and Bx0. Note 4: ‘-‘= Don’t care –Can be set “0” or “1”. Read data through 4-line SPI mode ‘1 ’ RESX' IM[3:0] CSX IM[3:0]=0110 or 1110 Host SCL 0 D/CX SDA (I/F I) SDI (I/F II) Driver - High-Z R2Eh SDA (I/F I) SDO (I/F II) High-Z D23 D22 D21 D20 D19 D18 D17 D16 D2 D1 D0 D23 D22 D21 D20 D19 1-Pixel data 8 Dummy Clock Read Data format as below D23 R1 5 D22 D21 D20 R1 4 R1 3 R1 2 D19 D18 R1 1 R1 0 D17 - D16 D15 D14 - G1 5 G1 4 D13 D12 D11 R1 3 R1 2 R1 R1 13 D10 D9 R1 0 - D8 - D7 D6 B1 5 B1 4 D5 D4 D3 D2 D1 D0 B1 3 B1 2 B1 1 B1 0 - - Note 1: ‘-‘= Don’t care – Can be set “0” or “1”. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 64 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.6.3. 8-bit Parallel MCU Interface Ⅰ system 8-bit parallel bus interface of ILI9341 can be used by setting external pin as IM [3:0] to “0000”.The following shown figure is the example of interface with 8080-Ⅰ MCU system interface. The 8080- Different display data formats are available for two color depths supported by listed below. - 65K-Colors, RGB 5, 6, 5 -bits input data. - 262K-Colors, RGB 6, 6, 6 -bits input data. 65K color: 16-bit/pixel (RGB 5-6-5 bits input) One pixel (3 sub-pixels) display data is sent by 2 byte transfers when DBI [2:0] bits of 3Ah register are set to “101”. Count D/CX D7 D6 D5 D4 D3 D2 D1 D0 0 0 C7 C6 C5 C4 C3 C2 C1 C0 1 1 0R4 0R3 0R2 0R1 0R0 0G5 0G4 0G3 2 1 0G2 0G1 0G0 0B4 0B3 0B2 0B1 0B0 3 1 1R4 1R3 1R2 1R1 1R0 1G5 1G4 1G3 4 1 1G2 1G1 1G0 1B4 1B3 1B2 1B1 1B0 … … … … … … … … … … 477 1 238R4 238R3 238R2 238R1 238R0 238G5 238G4 238G3 478 1 238G2 238G1 238G0 238B4 238B3 238B2 238B1 238B0 479 1 239R4 239R3 239R2 239R1 239R0 239G5 239G4 239G3 480 1 239G2 239G1 239G0 239B4 239B3 239B2 239B1 239B0 262K color: 18-bit/pixel (RGB 6-6-6 bits input) One pixel (3 sub-pixels) display data is sent by 3 bytes transfer when DBI [2:0] bits of 3Ah register are set to “110”. Count D/CX D7 D6 D5 D4 D3 D2 D1 D0 0 0 C7 C6 C5 C4 C3 C2 C1 C0 1 1 0R5 0R4 0R3 0R2 0R1 0R0 2 1 0G5 0G4 0G3 0G2 0G1 0G0 3 1 0B5 0B4 0B3 0B2 0B1 0B0 … … … … … … … … … … 718 1 239R5 239R4 239R3 239R2 239R1 239R0 719 1 239G5 239G4 239G3 239G2 239G1 239G0 720 1 239B5 239B4 239B3 239B2 239B1 239B0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 65 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 Ⅱsystem 8-bit parallel bus interface of ILI9341 can be used by settings as IM [3:0] =”1001”. The following shown figure is the example of interface with 8080-Ⅱ MCU system interface. The 8080- Different display data formats are available for two color depths supported by listed below. - 65K-Colors, RGB 5, 6, 5 -bits input data. - 262K-Colors, RGB 6, 6, 6 -bits input data. 65K color: 16-bit/pixel (RGB 5-6-5 bits input) One pixel (3 sub-pixels) display data is sent by 2 byte transfers when DBI [2:0] bits of 3Ah register are set to “101”. Count D/CX D17 D16 D15 D14 D13 D12 D11 D10 0 0 C7 C6 C5 C4 C3 C2 C1 C0 1 1 0R4 0R3 0R2 0R1 0R0 0G5 0G4 0G3 2 1 0G2 0G1 0G0 0B4 0B3 0B2 0B1 0B0 3 1 1R4 1R3 1R2 1R1 1R0 1G5 1G4 1G3 4 1 1G2 1G1 1G0 1B4 1B3 1B2 1B1 1B0 … … … … … … … … … … 477 1 238R4 238R3 238R2 238R1 238R0 238G5 238G4 238G3 478 1 238G2 238G1 238G0 238B4 238B3 238B2 238B1 238B0 479 1 239R4 239R3 239R2 239R1 239R0 239G5 239G4 239G3 480 1 239G2 239G1 239G0 239B4 239B3 239B2 239B1 239B0 262K color: 18-bit/pixel (RGB 6-6-6 bits input) One pixel (3 sub-pixels) display data is sent by 3 bytes transfer when DBI [2:0] bits of 3Ah register are set to “110”. Count D/CX D17 D16 D15 D14 D13 D12 D11 D10 0 0 C7 C6 C5 C4 C3 C2 C1 C0 1 1 0R5 0R4 0R3 0R2 0R1 0R0 2 1 0G5 0G4 0G3 0G2 0G1 0G0 3 1 0B5 0B4 0B3 0B2 0B1 0B0 … … … … … … … … … … 718 1 239R5 239R4 239R3 239R2 239R1 239R0 719 1 239G5 239G4 239G3 239G2 239G1 239G0 720 1 239B5 239B4 239B3 239B2 239B1 239B0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 66 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.6.4. 9-bit Parallel MCU Interface Ⅰ system 9-bit parallel bus interface of ILI9341 can be selected by setting hardware pin IM [3:0] to “0010”. The following shown figure is the example of interface with 8080-Ⅰ MCU system interface. The 8080- 65K color: 16-bit/pixel (RGB 5-6-5 bits input) One pixel (3 sub-pixels) display data is sent by 2 transfers when DBI [2:0] bits of 3Ah register are set to “101”. Count D/CX D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 2 1 3 1 4 1 … … 477 1 478 1 479 1 480 1 C7 C6 C5 C4 C3 C2 C1 C0 0R4 0R3 0R2 0R1 0R0 0G5 0G4 0G3 0G2 0G1 0G0 0B4 0B3 0B2 0B1 0B0 1R4 1R3 1R2 1R1 1R0 1G5 1G4 1G3 1G2 1G1 1G0 1B4 1B3 1B2 1B1 1B0 … … … … … … … … 238R4 238R3 238R2 238R1 238R0 238G5 238G4 238G3 238G2 238G1 238G0 238B4 238B3 238B2 238B1 238B0 239R4 239R3 239R2 239R1 239R0 239G5 239G4 239G3 239G2 239G1 239G0 239B4 239B3 239B2 239B1 239B0 262K color: 18-bit/pixel (RGB 6-6-6 bits input) There are 2 pixels (6 sub-pixels) display data is sent by 4 transfers, when DBI [2:0] bits of 3Ah register are set to “110”. MDT[1:0]=”00” Count D/CX D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 C7 C6 C5 C4 C3 C2 C1 C0 1 1 0R5 0R4 0R3 0R2 0R1 0R0 0G5 0G4 0G3 2 1 0G2 0G1 0G0 0B5 0B4 0B3 0B2 0B1 0B0 3 1 1R5 1R4 1R3 1R2 1R1 1R0 1G5 1G4 1G3 4 1 1G2 1G1 1G0 1B5 1B4 1B3 1B2 1B1 1B0 … … … … … … … … … … 478 1 238R5 238R4 238R3 238R2 238R1 238R0 238G5 238G4 238G3 478 1 238G2 238G1 238G0 238B5 238B4 238B3 238B2 238B1 238B0 479 1 239R5 239R4 239R3 239R2 239R1 239R0 239G5 239G4 239G3 480 1 239G2 239G1 239G0 239B5 239B4 239B3 239B2 239B1 239B0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 67 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 MDT[1:0]=”01” Count D/CX D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 2 1 3 1 … … 718 1 719 1 720 1 C7 C6 C5 C4 C3 C2 C1 C0 0R5 0R4 0R3 0R2 0R1 0R0 0G5 0G4 0G3 0G2 0G1 0G0 0B5 0B4 0B3 0B2 0B1 0B0 … … … … … … … … 239R5 239R4 239R3 239R2 239R1 239R0 239G5 239G4 239G3 239G2 239G1 239G0 239B5 239B4 239B3 239B2 239B1 239B0 Ⅱ system 9-bit parallel bus interface of ILI9341 can be selected by setting hardware pin IM [3:0] to “1011”. The following shown figure is the example of interface with 8080-Ⅱ MCU system interface. The 8080- 65K color: 16-bit/pixel (RGB 5-6-5 bits input) One pixel (3 sub-pixels) display data is sent by 2 transfers when DBI [2:0] bits of 3Ah register are set to “101”. Count D/CX D17 D16 D15 D14 D13 D12 D11 D10 D9 0 0 C7 C6 C5 C4 C3 C2 C1 C0 1 1 2 1 3 1 4 1 … … 477 1 478 1 479 1 480 1 0R4 0R3 0R2 0R1 0R0 0G5 0G4 0G3 0G2 0G1 0G0 0B4 0B3 0B2 0B1 0B0 1R4 1R3 1R2 1R1 1R0 1G5 1G4 1G3 1G2 1G1 1G0 1B4 1B3 1B2 1B1 1B0 … … … … … … … … 238R4 238R3 238R2 238R1 238R0 238G5 238G4 238G3 238G2 238G1 238G0 238B4 238B3 238B2 238B1 238B0 239R4 239R3 239R2 239R1 239R0 239G5 239G4 239G3 239G2 239G1 239G0 239B4 239B3 239B2 239B1 239B0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 68 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 262K color: 18-bit/pixel (RGB 6-6-6 bits input) There are 2 pixels (6 sub-pixels) display data is sent by 4 transfers, when DBI [2:0] bits of 3Ah register are set to “110”. MDT[1:0]=”00” Count D/CX D17 D16 D15 D14 D13 D12 D11 D10 D9 0 0 C7 C6 C5 C4 C3 C2 C1 C0 1 1 0R5 0R4 0R3 0R2 0R1 0R0 0G5 0G4 0G3 2 1 0G2 0G1 0G0 0B5 0B4 0B3 0B2 0B1 0B0 3 1 1R5 1R4 1R3 1R2 1R1 1R0 1G5 1G4 1G3 4 1 1G2 1G1 1G0 1B5 1B4 1B3 1B2 1B1 1B0 … … 478 1 238R5 238R4 238R3 238R2 238R1 238R0 238G5 238G4 238G3 … … … … … … … … 478 1 238G2 238G1 238G0 238B5 238B4 238B3 238B2 238B1 238B0 479 1 239R5 239R4 239R3 239R2 239R1 239R0 239G5 239G4 239G3 480 1 239G2 239G1 239G0 239B5 239B4 239B3 239B2 239B1 239B0 MDT[1:0]=”01” Count D/CX D17 D16 D15 D14 D13 D12 D11 D10 D9 0 0 C7 C6 C5 C4 C3 C2 C1 C0 1 1 2 1 3 1 … … 718 1 719 1 720 1 0R5 0R4 0R3 0R2 0R1 0R0 0G5 0G4 0G3 0G2 0G1 0G0 0B5 0B4 0B3 0B2 0B1 0B0 … … … … … … … … 239R5 239R4 239R3 239R2 239R1 239R0 239G5 239G4 239G3 239G2 239G1 239G0 239B5 239B4 239B3 239B2 239B1 239B0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 69 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.6.5. 16-bit Parallel MCU Interface Ⅰ system 16-bit parallel bus interface of ILI9341 can be selected by setting hardware pin IM[3:0] to “0001”.The following shown figure is the example of interface with 8080-Ⅰ MCU system interface. The 8080- Different display data format is available for two colors depth supported by listed below. - 65K-Colors, RGB 5, 6, 5 -bits input data. - 262K-Colors, RGB 6, 6, 6 -bits input data. 65K color: 16-bit/pixel (RGB 5-6-5 bits input) One pixel (3 sub-pixels) display data is sent by 1 transfer when DBI [2:0] bits of 3Ah register are set to “101”. Count D/CX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 C7 C6 C5 C4 C3 C2 C1 C0 1 1 0R4 0R3 0R2 0R1 0R0 0G5 0G4 0G3 0G2 0G1 0G0 0B4 0B3 0B2 0B1 0B0 2 1 1R4 1R3 1R2 1R1 1R0 1G5 1G4 1G3 1G2 1G1 1G0 1B4 1B3 1B2 1B1 1B0 3 1 2R4 2R3 2R2 2R1 2R0 2G5 2G4 2G3 2G2 2G1 2G0 2B4 2B3 2B2 2B1 2B0 … … … … … … … … … … … … … … … … … … 238 1 237R4 237R3 237R2 237R1 237R0 237G5 237G4 237G3 237G2 237G1 237G0 237B4 237B3 237B2 237B1 237B0 239 1 238R4 238R3 238R2 238R1 238R0 238G5 238G4 238G3 238G2 238G1 238G0 238B4 238B3 238B2 238B1 238B0 240 1 239R4 239R3 239R2 239R1 239R0 239G5 239G4 239G3 239G2 239G1 239G0 239B4 239B3 239B2 239B1 239B0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 70 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 262K color: 18-bit/pixel (RGB 6-6-6 bits input) One pixel (3 sub-pixels) display data is sent by 2 transfers when DBI [2:0] bits of 3Ah register are set to “110”. MDT[1:0]=”00” Count D/CX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 0R5 0R4 0R3 0R2 0R1 0R0 2 1 0B5 0B4 0B3 0B2 0B1 0B0 3 1 1G5 1G4 1G3 1G2 1G1 1G0 C7 C6 C5 C4 C3 C2 C1 C0 0G5 0G4 0G3 0G2 0G1 0G0 1R5 1R4 1R3 1R2 1R1 1R0 1B5 1B4 1B3 1B2 1B1 1B0 … … … … … … … … … … … … … … … … … … 358 1 238R5 238R4 238R3 238R2 238R1 238R0 359 1 238B5 238B4 238B3 238B2 238B1 238B0 360 1 239G5 239G4 239G3 239G2 239G1 239G0 238G5 238G4 238G3 238G2 238G1 238G0 239R5 239R4 239R3 239R2 239R1 239R0 239B5 239B4 239B3 239B2 239B1 239B0 MDT[1:0]=”01” Count D/CX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 C7 C6 C5 C4 C3 C2 C1 C0 1 1 0R5 0R4 0R3 0R2 0R1 0R0 0G5 0G4 0G3 0G2 0G1 0G0 2 1 0B5 0B4 0B3 0B2 0B1 0B0 3 1 1R5 1R4 1R3 1R2 1R1 1R0 1G5 1G4 1G3 1G2 1G1 1G0 1B5 1B4 1B3 1B2 1B1 1B0 … … … … … … … … … … … … … … … … … … 357 238R5 238R4 238R3 238R2 238R1 238R0 238G5 238G4 238G3 238G2 238G1 238G0 358 1 238B5 238B4 238B3 238B2 238B1 238B0 479 1 239R5 239R4 239R3 239R2 239R1 239R0 480 1 239B5 239B4 239B3 239B2 239B1 239B0 239G5 239G4 239G3 239G2 239G1 239G0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 71 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 MDT[1:0]=”10” Count D/CX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 C7 C6 C5 C4 C3 C2 C1 C0 1 1 0R5 0R4 0R3 0R2 0R1 0R0 0G5 0G4 0G3 0G2 0G1 0G0 0B5 0B4 0B3 0B2 2 1 0B1 0B0 3 1 1R5 1R4 1R3 1R2 1R1 1R0 1G5 1G4 1G3 1G2 1G1 1G0 1B5 1B4 1B3 1B2 1 1 2 1 0R3 0R2 0R1 0R0 0G5 0G4 0G3 0G2 0G1 0G0 0B5 0B4 0B3 0B2 0B1 0B0 3 1 1B1 1B0 … … … … … … … … … … … … … … … … … … 357 238R5 238R4 238R3 238R2 238R1 238R0 238G5 238G4 238G3 238G2 238G1 238G0 238B5 238B4 238B3 238B2 358 1 238B1 238B0 479 1 239R5 239R4 239R3 239R2 239R1 239R0 239G5 239G4 239G3 239G2 239G1 239G0 239B5 239B4 239B3 239B2 480 1 239B1 239B0 358 1 238R3 238R2 238R1 238R0 238G5 238G4 238G3 238G2 238G1 238G0 238B5 238B4 238B3 238B2 238B1 238B0 479 1 480 1 239R3 239R2 239R1 239R0 239G5 239G4 239G3 239G2 239G1 239G0 239B5 239B4 239B3 239B2 239B1 239B0 MDT[1:0]=”11” Count D/CX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 C7 C6 C5 C4 C3 C2 C1 C0 0R5 0R4 1R5 1R4 1R3 1R2 1R1 1R0 1G5 1G4 1G3 1G2 1G1 1G0 1B5 1B4 1B3 1B2 1B1 1B0 … … … … … … … … … … … … … … … … … … 357 238R5 238R4 239R5 239R4 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 72 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 Ⅱ system 16-bit parallel bus interface of ILI9341 can be selected by settings IM [3:0] =”1000”. The following shown figure is the example of interface with 8080-Ⅱ MCU system interface. The 8080- Different display data format is available for two colors depth supported by listed below. - 65K-Colors, RGB 5, 6, 5 -bits input data. - 262K-Colors, RGB 6, 6, 6 -bits input data. 65K color: 16-bit/pixel (RGB 5-6-5 bits input) One pixel (3 sub-pixels) display data is sent by 1 transfer when DBI [2:0] bits of 3Ah register are set to “101”. Count D/CX D17 D16 D15 D14 D13 D12 D11 D10 D8 D7 D6 D5 D4 D3 D2 D1 0 0 C7 C6 C5 C4 C3 C2 C1 C0 1 1 0R4 0R3 0R2 0R1 0R0 0G5 0G4 0G3 0G2 0G1 0G0 0B4 0B3 0B2 0B1 0B0 2 1 1R4 1R3 1R2 1R1 1R0 1G5 1G4 1G3 1G2 1G1 1G0 1B4 1B3 1B2 1B1 1B0 3 1 2R4 2R3 2R2 2R1 2R0 2G5 2G4 2G3 2G2 2G1 2G0 2B4 2B3 2B2 2B1 2B0 … … … … … … … … … … … … … … … … … … 238 1 237R4 237R3 237R2 237R1 237R0 237G5 237G4 237G3 237G2 237G1 237G0 237B4 237B3 237B2 237B1 237B0 239 1 238R4 238R3 238R2 238R1 238R0 238G5 238G4 238G3 238G2 238G1 238G0 238B4 238B3 238B2 238B1 238B0 240 1 239R4 239R3 239R2 239R1 239R0 239G5 239G4 239G3 239G2 239G1 239G0 239B4 239B3 239B2 239B1 239B0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 73 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 262K color: 18-bit/pixel (RGB 6-6-6 bits input) One pixel (3 sub-pixels) display data is sent by 2 transfers when DBI [2:0] bits of 3Ah register are set to “110”. MDT[1:0]=”00” Count D/CX D17 D16 D15 D14 D13 D12 D11 D10 D8 D7 D6 D5 D4 D3 D2 D1 0 0 1 1 0R5 0R4 0R3 0R2 0R1 0R0 2 1 0B5 0B4 0B3 0B2 0B1 0B0 3 1 1G5 1G4 1G3 1G2 1G1 1G0 C7 C6 C5 C4 C3 C2 C1 C0 0G5 0G4 0G3 0G2 0G1 0G0 1R5 1R4 1R3 1R2 1R1 1R0 1B5 1B4 1B3 1B2 1B1 1B0 … … … … … … … … … … … … … … … … … … 358 1 238R5 238R4 238R3 238R2 238R1 238R0 359 1 238B5 238B4 238B3 238B2 238B1 238B0 360 1 239G5 239G4 239G3 239G2 239G1 239G0 238G5 238G4 238G3 238G2 238G1 238G0 239R5 239R4 239R3 239R2 239R1 239R0 239B5 239B4 239B3 239B2 239B1 239B0 MDT[1:0]=”01” Count D/CX D17 D16 D15 D14 D13 D12 D11 D10 D8 D7 D6 D5 D4 D3 D2 D1 0 0 C7 C6 C5 C4 C3 C2 C1 C0 1 1 0R5 0R4 0R3 0R2 0R1 0R0 0G5 0G4 0G3 0G2 0G1 0G0 2 1 0B5 0B4 0B3 0B2 0B1 0B0 3 1 1R5 1R4 1R3 1R2 1R1 1R0 1G5 1G4 1G3 1G2 1G1 1G0 1B5 1B4 1B3 1B2 1B1 1B0 … … … … … … … … … … … … … … … … … … 357 238R5 238R4 238R3 238R2 238R1 238R0 238G5 238G4 238G3 238G2 238G1 238G0 358 1 238B5 238B4 238B3 238B2 238B1 238B0 479 1 239R5 239R4 239R3 239R2 239R1 239R0 480 1 239B5 239B4 239B3 239B2 239B1 239B0 239G5 239G4 239G3 239G2 239G1 239G0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 74 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 MDT[1:0]=”10” Count D/CX D17 D16 D15 D14 D13 D12 D11 D10 D8 D7 D6 D5 D4 D3 D2 D1 0 0 C7 C6 C5 C4 C3 C2 C1 C0 1 1 0R5 0R4 0R3 0R2 0R1 0R0 0G5 0G4 0G3 0G2 0G1 0G0 0B5 0B4 0B3 0B2 2 1 0B1 0B0 3 1 1R5 1R4 1R3 1R2 1R1 1R0 1G5 1G4 1G3 1G2 1G1 1G0 1B5 1B4 1B3 1B2 1 1 2 1 0R3 0R2 0R1 0R0 0G5 0G4 0G3 0G2 0G1 0G0 0B5 0B4 0B3 0B2 0B1 0B0 3 1 1B1 1B0 … … … … … … … … … … … … … … … … … … 357 238R5 238R4 238R3 238R2 238R1 238R0 238G5 238G4 238G3 238G2 238G1 238G0 238B5 238B4 238B3 238B2 358 1 238B1 238B0 479 1 239R5 239R4 239R3 239R2 239R1 239R0 239G5 239G4 239G3 239G2 239G1 239G0 239B5 239B4 239B3 239B2 480 1 239B1 239B0 358 1 238R3 238R2 238R1 238R0 238G5 238G4 238G3 238G2 238G1 238G0 238B5 238B4 238B3 238B2 238B1 238B0 479 1 480 1 239R3 239R2 239R1 239R0 239G5 239G4 239G3 239G2 239G1 239G0 239B5 239B4 239B3 239B2 239B1 239B0 MDT[1:0]=”11” Count D/CX D17 D16 D15 D14 D13 D12 D11 D10 D8 D7 D6 D5 D4 D3 D2 D1 0 0 C7 C6 C5 C4 C3 C2 C1 C0 0R5 0R4 1R5 1R4 1R3 1R2 1R1 1R0 1G5 1G4 1G3 1G2 1G1 1G0 1B5 1B4 1B3 1B2 1B1 1B0 … … … … … … … … … … … … … … … … … … 357 238R5 238R4 239R5 239R4 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 75 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.6.6. 18-bit Parallel MCU Interface Ⅰ system 18-bit parallel bus interface of ILI9341 can be selected by setting hardware pin IM[3:0] to “0011”.The following shown figure is the example of interface with 8080-Ⅰ MCU system interface. The 8080- Different display data format is available for one color depth only supported by listed below. - 65K-Colors, RGB 5, 6, 5 -bits input data. - 262K-Colors, RGB 6, 6, 6 -bits input data. 65K color: 16-bit/pixel (RGB 5-6-5 bits input) One pixel (3 sub-pixels) display data is sent by 1 transfer when DBI [2:0] bits of 3Ah register are set to “101”. Count D/CX D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 2 1 3 1 … … 238 1 239 1 240 1 C7 C6 C5 C4 C3 C2 C1 C0 0R4 0R3 0R2 0R1 0R0 0G5 0G4 0G3 0G2 0G1 0G0 0B4 0B3 0B2 0B1 0B0 1R4 1R3 1R2 1R1 1R0 1G5 1G4 1G3 1G2 1G1 1G0 1B4 1B3 1B2 1B1 1B0 2R4 2R3 2R2 2R1 2R0 2G5 2G4 2G3 2G2 2G1 2G0 2B4 2B3 2B2 2B1 2B0 … … … … … … … … … … … … … … … … 237R4 237R3 237R2 237R1 237R0 237G5 237G4 237G3 237G2 237G1 237G0 237B4 237B3 237B2 237B1 237B0 238R4 238R3 238R2 238R1 238R0 238G5 238G4 238G3 238G2 238G1 238G0 238B4 238B3 238B2 238B1 238B0 239R4 239R3 239R2 239R1 239R0 239G5 239G4 239G3 239G2 239G1 239G0 239B4 239B3 239B2 239B1 239B0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 76 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 262K color: 18-bit/pixel (RGB 6-6-6 bits input) One pixel (3 sub-pixels) display data is sent by 1 transfer when DBI [2:0] bits of 3Ah register are set to “110”. Count D/CX D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 C7 C6 C5 C4 C3 C2 C1 C0 1 1 0R5 0R4 0R3 0R2 0R1 0R0 0G5 0G4 0G3 0G2 0G1 0G0 0B5 0B4 0B3 0B2 0B1 0B0 2 1 1R5 1R4 1R3 1R2 1R1 1R0 1G5 1G4 1G3 1G2 1G1 1G0 1B5 1B4 1B3 1B2 1B1 1B0 3 1 2R5 2R4 2R3 2R2 2R1 2R0 2G5 2G4 2G3 2G2 2G1 2G0 2B5 2B4 2B3 2B2 2B1 2B0 … … … … … … … … … … … … … … … … … … … … 238 1 237R5 237R4 237R3 237R2 237R1 237R0 237G5 237G4 237G3 237G2 237G1 237G0 237B5 237B4 237B3 237B2 237B1 237B0 239 1 238R5 238R4 238R3 238R2 238R1 238R0 238G5 238G4 238G3 238G2 238G1 238G0 238B5 238B4 238B3 238B2 238B1 238B0 240 1 239R5 239R4 239R3 239R2 239R1 239R0 239G5 239G4 239G3 239G2 239G1 239G0 239B5 239B4 239B3 239B2 239B1 239B0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 77 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 Ⅱ system 18-bit parallel bus interface mode can be selected by settings IM [3:0] =”1010”. The following shown figure is the example of interface with 8080-Ⅱ MCU system interface. The 8080- Different display data format is available for one color depth only supported by listed below. - 65K-Colors, RGB 5, 6, 5 -bits input data. - 262K-Colors, RGB 6, 6, 6 -bits input data. 65K color: 16-bit/pixel (RGB 5-6-5 bits input) One pixel (3 sub-pixels) display data is sent by 1 transfer when DBI [2:0] bits of 3Ah register are set to “101”. Count D/CX D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 C7 C6 C5 C4 C3 C2 C1 C0 1 1 2 1 3 1 … … 238 1 239 1 240 1 0R4 0R3 0R2 0R1 0R0 0G5 0G4 0G3 0G2 0G1 0G0 0B4 0B3 0B2 0B1 0B0 1R4 1R3 1R2 1R1 1R0 1G5 1G4 1G3 1G2 1G1 1G0 1B4 1B3 1B2 1B1 1B0 2R4 2R3 2R2 2R1 2R0 2G5 2G4 2G3 2G2 2G1 2G0 2B4 2B3 2B2 2B1 2B0 … … … … … … … … … … … … … … … … 237R4 237R3 237R2 237R1 237R0 237G5 237G4 237G3 237G2 237G1 237G0 237B4 237B3 237B2 237B1 237B0 238R4 238R3 238R2 238R1 238R0 238G5 238G4 238G3 238G2 238G1 238G0 238B4 238B3 238B2 238B1 238B0 239R4 239R3 239R2 239R1 239R0 239G5 239G4 239G3 239G2 239G1 239G0 239B4 239B3 239B2 239B1 239B0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 78 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 262K color: 18-bit/pixel (RGB 6-6-6 bits input) One pixel (3 sub-pixels) display data is sent by 1 transfer when DBI [2:0] bits of 3Ah register are set to “110”. Count D/CX D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 C7 C6 C5 C4 C3 C2 C1 C0 1 1 0R5 0R4 0R3 0R2 0R1 0R0 0G5 0G4 0G3 0G2 0G1 0G0 0B5 0B4 0B3 0B2 0B1 0B0 2 1 1R5 1R4 1R3 1R2 1R1 1R0 1G5 1G4 1G3 1G2 1G1 1G0 1B5 1B4 1B3 1B2 1B1 1B0 3 1 2R5 2R4 2R3 2R2 2R1 2R0 2G5 2G4 2G3 2G2 2G1 2G0 2B5 2B4 2B3 2B2 2B1 2B0 … … … … … … … … … … … … … … … … … … … … 238 1 237R5 237R4 237R3 237R2 237R1 237R0 237G5 237G4 237G3 237G2 237G1 237G0 237B5 237B4 237B3 237B2 237B1 237B0 239 1 238R5 238R4 238R3 238R2 238R1 238R0 238G5 238G4 238G3 238G2 238G1 238G0 238B5 238B4 238B3 238B2 238B1 238B0 240 1 239R5 239R4 239R3 239R2 239R1 239R0 239G5 239G4 239G3 239G2 239G1 239G0 239B5 239B4 239B3 239B2 239B1 239B0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 79 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.6.7. 6-bit Parallel RGB Interface The 6-bit RGB interface is selected by setting the DPI [2:0] bit to “110”. When RCM [1:0] are set to “10” and DE mode is selected, the display operation is synchronized with VSYNC, HSYNC and DOTCLK signals. The display data are transferred to the internal GRAM in synchronization with the display operation via 6-bit RGB data bus (D [5:0]) according to the data enable signal (DE) when RCM [1:0] are set to “10”. The RGB interface SYNC mode is selected by setting the RCM [1:0] to “11”, the valid display data is inputted in pixel unit via D [5:0] according to the VFP/VBP and HFP/HBP settings. Unused pins must be connected to GND to ensure normally operation. Registers can be set by the SPI system interface. 65K color: 16-bit/pixel (RGB 5-6-5 bits input) 262K color: 18-bit/pixel (RGB 6-6-6 bits input) ILI9341 has data transfer counters to count the first, second, third data transfer in 6-bit RGB interface mode. The transfer counter is always reset to the state of first data transfer on the falling edge of VSYNC. If a mismatch arises in the number of each data transfer, the counter is reset to the state of first data transfer at the start of the frame (i.e. on the falling edge of VSYNC) to restart data transfer in the correct order from the next frame. This function is expedient for moving picture display, which requires consecutive data transfer in light of minimizing effects from failed data transfer and enabling the system to return to a normal state. Note that internal display operation is performed in units of pixels (RGB: taking 3 inputs of DOTCLK). Accordingly, the number of DOTCLK inputs in one frame period must be a multiple of 3 to complete data transfer correctly. Otherwise it will affect the display of that frame as well as the next frame. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 80 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 DE Mode, RCM[1:0]=“10” VSYNC HSYNC ENABLE VBP Active Area VFP Totale Area HSYNC ENABLE DOTCLK D[5:0] HBP Active Area HFP Totale Area The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 81 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 7.6.8. 16-bit Parallel RGB Interface The 16-bit RGB interface is selected by setting the DPI [2:0] bits to “101”. When RCM [1:0] are set to “10” and DE mode is selected, the display operation is synchronized with VSYNC, HSYNC and DOTCLK signals. The display data is transferred to the internal GRAM in synchronization with the display operation via 16-bit RGB data bus (D [17:13] & D [11:1]) according to the data enable signal (DE). The RGB interface SYNC mode is selected by setting the RCM [1:0] to “11”, the valid display data is inputted in pixel unit via D [17:13] and D [11:1] according to the VFP/VBP and HFP/HBP settings. The unused D12 and D0 pins must be connected to GND for ensure normally operation. Registers can be set by the SPI system interface. Input Data D17 D16 D15 D14 D13 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 Write Data Register D17 D16 D15 D14 D13 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 B3 B2 B1 Look-Up Table for 65k Colors mapping (16-bit to 18-bit) GRAM Data & RGB Mapping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B0 7.6.9. 18-bit Parallel RGB Interface The 18-bit RGB interface is selected by setting the DPI [2:0] bits to “110”. When RCM [1:0] are set to “10” and DE mode is selected, the display operation is synchronized with VSYNC, HSYNC and DOTCLK signals. The display data are transferred to the internal GRAM in synchronization with the display operation via 18-bit RGB data bus (D [17:0]) according to the data enable signal (DE) when RCM [1:0] are set to “10”. The RGB interface SYNC mode is selected by setting the RCM [1:0] to “11”, the valid display data is inputted in pixel unit via D [17:0] according to the VFP/VBP and HFP/HBP settings. Registers can be set by the SPI system interface. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 82 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8. Command 8.1. Command List Regulative Command Set Command Function D17-8 D7 D6 D5 D4 D3 D2 D1 D0 Hex No Operation 0 1 ↑ XX 0 0 0 0 0 0 0 0 00h Software Reset 0 1 ↑ XX 0 0 0 0 0 0 0 1 01h 0 1 ↑ XX 0 0 0 0 0 1 0 0 04h 1 ↑ 1 XX X X X X X X X X 1 ↑ 1 XX ID1 [7:0] XX XX Read Display Identification Information Read Display Status Read Display Power Mode Read Display MADCTL Read Display Pixel Format Read Display Image Format Read Display Signal Mode Read Display Self-Diagnostic Result Enter Sleep Mode D/CX RDX WRX 1 ↑ 1 XX ID2 [7:0] 1 ↑ 1 XX ID3 [7:0] 0 1 ↑ XX 0 0 0 1 ↑ 1 XX X X X 1 ↑ 1 XX 1 ↑ 1 XX X 1 ↑ 1 XX X 1 ↑ 1 XX 0 1 ↑ XX 0 0 0 X X X XX 0 1 0 0 X X X X D [31:25] D [22:20] X 1 09h X XX X 00 D [19:16] X D [7:5] XX 61 X X D [10:8] 00 X X X X X 00 0 1 0 1 0 0Ah X X X X X XX 0 0 08 1 ↑ 1 XX 1 ↑ 1 XX 0 1 ↑ XX 0 0 0 0 1 0 1 1 0Bh 1 ↑ 1 XX X X X X X X X X XX 1 ↑ 1 XX 0 0 00 0 1 ↑ XX 0 0 0Ch X X XX 0 1 0Dh X X XX D [7:2] D [7:2] 0 0 X 0 0 1 1 X X X X 1 ↑ 1 XX X 1 ↑ 1 XX RIM 0 1 ↑ XX 0 0 0 0 1 1 X DPI [2:0] X DBI [2:0] 06 1 ↑ 1 XX X X X X X 1 ↑ 1 XX X X X X X 0 1 ↑ XX 0 0 0 0 1 1 1 0 0Eh 1 ↑ 1 XX X X X X X X X X XX 1 ↑ 1 XX 0 0 00 0 1 ↑ XX 0 1 1 0Fh X XX D [2:0] D [7:2] 1 ↑ 1 XX 1 ↑ 1 XX 0 1 ↑ XX 0 0 X 0 0 1 1 00 X X X X X X X X X X X X 00 0 0 1 0 0 0 0 10h D [7:6] Sleep OUT 0 1 ↑ XX 0 0 0 1 0 0 0 1 11h Partial Mode ON 0 1 ↑ XX 0 0 0 1 0 0 1 0 12h Normal Display Mode ON 0 1 ↑ XX 0 0 0 1 0 0 1 1 13h Display Inversion OFF 0 1 ↑ XX 0 0 1 0 0 0 0 0 20h Display Inversion ON 0 1 ↑ XX 0 0 1 0 0 0 0 1 21h 0 1 ↑ XX 0 0 1 0 0 1 1 0 26h 1 1 ↑ XX Display OFF 0 1 ↑ XX 0 0 1 0 1 0 0 0 28h Display ON 0 1 ↑ XX 0 0 1 0 1 0 0 1 29h 0 1 ↑ XX 0 0 1 0 1 0 1 0 2Ah 1 1 ↑ XX SC [15:8] XX 1 1 ↑ XX SC [7:0] XX Gamma Set Column Address Set Page Address Set GC [7:0] 01 1 1 ↑ XX EC [15:8] XX 1 1 ↑ XX EC [7:0] XX 0 1 ↑ XX 1 1 ↑ XX SP [15:8] XX 1 1 ↑ XX SP [7:0] XX 1 1 ↑ XX EP [15:8] XX 1 1 ↑ XX EP [7:0] XX 0 0 1 0 1 0 1 1 2Bh The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 83 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Memory Write Color SET Memory Read Partial Area Vertical Scrolling Definition Tearing Effect Line OFF Tearing Effect Line ON Memory Access Control Vertical Scrolling Start Address 0 1 ↑ 1 1 ↑ 0 1 1 1 0 ILI9341 XX 0 0 1 1 1 0 0 2Ch ↑ XX 0 0 1 1 1 0 1 2Dh ↑ 1 XX R00 [5:0] XX ↑ 1 XX Rnn [5:0] XX 1 ↑ 1 XX R31 [5:0] XX 1 ↑ 1 XX G00 [5:0] XX 1 ↑ 1 XX Gnn [5:0] XX 1 ↑ 1 XX G64 [5:0] XX 1 ↑ 1 XX B00 [5:0] XX 1 ↑ 1 XX Bnn [5:0] XX 1 ↑ 1 XX B31 [5:0] 0 1 ↑ XX 0 0 1 XX X X X D [17:0] 1 ↑ 1 1 ↑ 1 0 1 ↑ XX 1 1 ↑ XX 1 1 ↑ 1 1 ↑ 1 1 0 1 0 XX XX 0 1 1 1 0 X X X X X D [17:0] 0 0 1 1 2Eh XX XX 0 0 0 0 30h SR [15:8] 00 XX SR [7:0] 00 XX ER [15:8] 01 ↑ XX ER [7:0] 3F 1 ↑ XX 1 ↑ XX TFA [15:8] 1 1 ↑ XX TFA [7:0] 00 1 1 ↑ XX VSA [15:8] 01 1 1 ↑ XX VSA [7:0] 40 0 0 1 1 0 0 1 1 33h 00 1 1 ↑ XX BFA [15:8] 00 1 1 ↑ XX BFA [7:0] 00 0 1 ↑ XX 0 0 1 1 0 1 0 0 34h 0 1 ↑ XX 0 0 1 1 0 1 0 1 35h 1 1 ↑ XX X X X X X X X M 00 0 1 ↑ XX 0 0 1 1 0 1 1 0 36h 1 1 ↑ XX MY MX MV ML BGR MH X X 00 0 1 ↑ XX 0 0 1 1 0 1 1 1 37h 1 1 ↑ XX VSP [15:8] 00 1 1 ↑ XX VSP [7:0] 00 Idle Mode OFF 0 1 ↑ XX 0 0 1 1 1 0 0 0 Idle Mode ON 0 1 ↑ XX 0 0 1 1 1 0 0 1 39h 0 1 ↑ XX 0 0 1 1 1 0 1 0 3Ah 1 1 ↑ XX X 0 1 ↑ XX 0 0 3Ch 1 1 ↑ 0 1 ↑ XX 0 0 1 1 1 1 1 0 1 ↑ 1 XX X X X X X X X X 1 ↑ 1 0 1 ↑ XX 0 1 0 0 0 1 0 0 44h 1 1 ↑ XX X X X X X X X STS [8] 00 1 1 ↑ XX 0 1 ↑ XX 0 1 0 0 0 1 0 1 45h 1 ↑ 1 XX X X X X X X X X XX X X X X X X GTS [9:8] 00 Pixel Format Set Write Memory Continue Read Memory Continue Set Tear Scanline Get Scanline Write Display Brightness DPI [2:0] 0 1 X 1 1 DBI [2:0] 1 0 66 D [17:0] XX D [17:0] 1 ↑ 1 XX 1 ↑ 1 XX 0 1 ↑ XX 1 1 ↑ XX 0 1 XX 00 GTS [7:0] 1 3Eh XX STS [7:0] 0 38h 0 DBV [7:0] 00 0 0 1 51h 00 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 84 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Read Display Brightness Write CTRL Display Read CTRL Display Write Content Adaptive Brightness Control Read Content Adaptive Brightness Control Write CABC Minimum Brightness Read CABC Minimum Brightness Read ID1 Read ID2 Read ID3 0 1 1 ↑ ↑ 1 XX 0 X 1 X 0 X XX 1 ↑ 1 XX 0 1 ↑ XX 0 1 0 1 1 ↑ XX X X BCTRL 0 1 1 ↑ ↑ 1 XX XX 0 X 1 X 0 X 1 ↑ 1 XX X X BCTRL 0 1 ↑ XX 0 1 0 1 1 ↑ XX X X X 0 1 1 ↑ ↑ 1 XX XX 0 X 1 X 0 X 1 ↑ 1 XX X X X 0 1 ↑ XX 0 1 0 1 1 ↑ XX 0 1 1 ↑ ↑ 1 XX XX 0 X 1 X 0 X 1 ↑ 1 XX 0 1 1 ↑ ↑ 1 XX XX 1 X 1 X 0 X 1 ↑ 1 XX 0 1 ↑ XX 1 1 X X ILI9341 1 0 0 1 0 52h X X X X X XX 0 1 1 53h 00 DBV [7:0] 1 0 00 X 1 DD 0 BL 1 X 0 X 0 X X X X X XX X 1 DD 0 BL 1 X 0 X 1 00 55h X 1 X 0 X 1 1 0 00 56h X X X X X XX X 1 X 1 X 1 1 0 00 5Eh CMB [7:0] 1 0 1 1 1 00 5Fh X X X X X XX CMB [7:0] 1 1 0 1 0 00 DAh X X X X XX DBh X C [1:0] C [1:0] Module’s Manufacture [7:0] 1 ↑ 1 XX 1 ↑ 1 XX 0 1 ↑ XX 1 1 1 ↑ 1 XX X X 1 ↑ 1 XX 54h XX 0 1 1 0 1 1 X X X X X X LCD Module / Driver Version [7:0] XX XX 0 1 1 1 0 0 DCh X X X X X X XX LCD Module / Driver ID [7:0] XX Extended Command Set Command Function D17-8 D7 D6 D5 D4 D3 D2 D1 D0 Hex RGB Interface 0 1 ↑ XX 1 0 1 1 0 0 0 0 B0h Signal Control 1 1 ↑ XX ByPass_MODE X VSPL HSPL DPL EPL 40 0 1 ↑ XX 1 0 1 1 0 0 0 1 B1h X X X DIVA [1:0] Frame Control (In Normal Mode) Frame Control (In Idle Mode) Frame Control (In Partial Mode) Display Inversion Control Blanking Porch Control D/CX RDX WRX RCM [1:0] 1 1 ↑ XX X X X 1 1 ↑ XX X X X 0 1 ↑ XX 1 0 1 1 0 0 1 1 1 ↑ XX X X X X X X DIVB [1:0] 1 1 ↑ XX X X X 0 1 ↑ XX 1 0 1 1 0 0 1 1 ↑ XX X X X X X X 1 1 ↑ XX X X X RTNA [4:0] 00 1B 0 RTNB [4:0] B2h 00 1B 1 1 DIVC [1:0] RTNC [4:0] B3h 00 1B 0 1 ↑ XX 1 0 1 1 0 1 0 0 1 1 ↑ XX X X X X X NLA NLB NLC B4h 02 0 1 ↑ XX 1 0 1 1 0 1 0 1 B5h 1 1 ↑ XX 0 VFP [6:0] 1 1 ↑ XX 0 VBP [6:0] 1 1 ↑ XX 0 0 0 HFP [4:0] 0A 1 1 ↑ XX 0 0 0 HBP [4:0] 14 02 02 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 85 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Display Function Control Entry Mode Set Backlight Control 1 Backlight Control 2 Backlight Control 3 Backlight Control 4 Backlight Control 5 Backlight Control 7 Backlight Control 8 Power Control 1 Power Control 2 VCOM Control 1 VCOM Control 2 NV Memory Write NV Memory Protection Key NV Memory Status Read ILI9341 0 1 ↑ XX 1 0 1 1 0 1 1 ↑ XX X X X X PTG [1:0] 1 1 0 1 1 ↑ XX REV GS SS SM 1 1 ↑ XX X X NL [5:0] 27 1 1 ↑ XX X X PCDIV [5:0] XX PT [1:0] B6h 0A ISC [3:0] 82 0 1 ↑ XX 1 0 1 1 0 1 1 1 1 1 ↑ XX X X X X 0 GON DTE GAS 07 0 1 ↑ XX 1 0 1 1 1 0 0 0 B8h X X X X XX 0 1 B9h X X XX 1 1 ↑ XX X X X X 1 1 ↑ XX X X X X 0 1 ↑ XX 1 0 1 1 1 0 X X X X X X TH_UI [3:0] B7h 04 1 1 ↑ XX 1 1 ↑ XX 0 1 ↑ XX 1 0 1 1 1 0 1 0 BAh 1 1 ↑ XX X X X X X X X X XX 1 1 ↑ XX X X X X 0 1 ↑ XX 1 0 1 1 1 0 1 1 BBh X X X X X X X X XX TH_MV [3:0] TH_ST [3:0] B8 DTH_UI [3:0] 04 1 1 ↑ XX 1 1 ↑ XX 0 1 ↑ XX 1 0 1 1 1 1 0 0 BCh 1 1 ↑ XX X X X X X X X X XX 1 1 ↑ XX 0 1 ↑ XX 1 1 ↑ XX 0 1 ↑ 1 1 0 1 1 0 DTH_MV [3:0] DTH_ST [3:0] DIM2 [3:0] X 1 C9 DIM1 [2:0] 1 44 1 0 1 1 1 0 BEh XX 1 0 1 1 1 1 1 1 BFh ↑ XX X X X X X ↑ XX 1 1 0 0 0 1 ↑ XX X X 1 ↑ XX 1 1 0 0 0 1 1 ↑ XX X X X X 0 1 ↑ XX 1 1 0 0 1 1 ↑ XX X VMH [6:0] 31 1 1 ↑ XX X VML [6:0] 3C PWM_DIV [7:0] 1 0F LEDONR LEDONPOL LEDPWMOPL 0 0 C0h 0 1 C1h 1 C5h VRH [5:0] 0 0 0 X 0 0 26 BT [2:0] 1 1 00 0 0 00 0 1 ↑ XX 1 1 1 ↑ XX nVM 1 1 C7h 0 1 ↑ XX 1 1 0 1 0 0 0 D0h 1 1 ↑ XX X X X X X 1 1 ↑ XX 0 1 ↑ XX 1 1 0 1 1 ↑ XX KEY [23:16] 55 1 1 ↑ XX KEY [15:8] AA 1 1 ↑ XX 0 1 ↑ XX 1 1 0 1 0 0 1 ↑ 1 XX X X X X X X 1 ↑ 1 XX X ID2_CNT [2:0] X ID1_CNT [2:0] XX 1 ↑ 1 XX BUSY VMF_CNT [2:0] X ID3_CNT [2:0] XX VMF [6:0] 0 C0 PGM_ADR [2:0] 00 PGM_DATA [7:0] 1 0 0 XX 0 1 KEY [7:0] D1h 66 1 0 D2h X X XX The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 86 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 0 ↑ 1 XX 1 1 0 1 0 0 1 1 D3h 1 ↑ 1 XX X X X X X X X X XX 1 ↑ 1 XX 0 0 0 0 0 0 0 0 00 1 ↑ 1 XX 1 0 0 1 0 0 1 1 93 1 ↑ 1 XX 0 1 0 0 0 0 0 1 41 0 1 ↑ XX 1 1 1 0 0 0 0 0 E0h 1 1 ↑ XX X X X X 1 1 ↑ XX X X VP1 [5:0] 0E 1 1 ↑ XX X X VP2 [5:0] 12 1 1 ↑ XX X X X 1 1 ↑ XX X X X 1 1 ↑ XX X X X Positive Gamma 1 1 ↑ XX X Correction 1 1 ↑ XX 1 1 ↑ XX X 1 1 ↑ XX X X X 1 1 ↑ XX X X X 1 1 ↑ XX X X X 1 1 ↑ XX X X Read ID4 VP0 [3:0] X 08 VP4 [3:0] 05 VP6 [4:0] X 03 VP13 [3:0] 09 VP20 [6:0] 47 VP36 [3:0] VP27 [3:0] 86 VP43 [6:0] 2B X VP50 [3:0] 0B VP57 [4:0] X 04 VP59 [3:0] 00 VP61 [5:0] 00 VP62 [5:0] 00 1 1 ↑ XX X X 1 1 ↑ XX X X X X 0 1 ↑ XX 1 1 1 0 1 1 ↑ XX X X X X 1 1 ↑ XX X X VN1 [5:0] 1A 1 1 ↑ XX X X VN2 [5:0] 20 1 1 ↑ XX X X X 1 1 ↑ XX X X X X X 1 1 ↑ XX X Negative Gamma 1 1 ↑ XX X Correction 1 1 ↑ XX 1 1 ↑ XX X 1 1 ↑ XX X X X 1 1 ↑ XX X X X 1 1 ↑ XX X X X 1 1 ↑ XX X X VP63 [3:0] 0 0 0 00 1 VN0 [3:0] X 08 VN4 [3:0] 07 VN6 [4:0] X 0E VN13 [3:0] 05 VN20 [6:0] VN36 [3:0] 3A VN27 [3:0] 8A VN43 [6:0] X 40 VN50 [3:0] 04 VN57 [4:0] X E1h 18 VN59 [3:0] 0F VN61 [5:0] 3F VN62 [5:0] 3F 1 1 ↑ XX X X 1 1 ↑ XX X X X X Digital Gamma Control 1 0 1 ↑ XX 1 1 1 0 1st Parameter 1 1 ↑ XX RCA0 [3:0] BCA0 [3:0] XX : 1 1 ↑ XX RCAx [3:0] BCAx [3:0] XX 16th Parameter 1 1 ↑ XX RCA15 [3:0] BCA15 [3:0] XX Digital Gamma Control 2 0 1 ↑ XX 1st Parameter 1 1 ↑ XX RFA0 [3:0] BFA0 [3:0] XX : 1 1 ↑ XX RFAx [3:0] BFAx [3:0] XX 64th Parameter 1 1 ↑ XX 0 1 ↑ XX 1 1 1 1 0 1 1 0 1 1 ↑ XX MY_EOR MX_EOR MV_EOR X BGR_EOR X X WEMODE 1 1 ↑ XX X X X X 1 1 ↑ XX X X Interface Control 1 1 1 0 VN63 [3:0] 0 0 RFA63 [3:0] 0 1 1 0F 0 1 BFA63 [3:0] EPF [1:0] ENDIAN 0 X DM [1:0] E3h XX MDT [1:0] RM E2h RIM F6h 01 00 00 Note 1: Undefined commands are treated as NOP (00h) command. Note 2: B0 to D9 and DE to FF are for factory use of display supplier. USER can decide if these commands are available or they are treated as NOP (00h) commands before shipping to USER. Default value is NOP The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 87 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 (00h). Note 3: Commands 10h, 12h, 13h, 26h, 28h, 29h, 30h, 36h (Bit B4 only), 38h and 39h are updated during V-SYNC when ILI9341 is in Sleep OUT mode to avoid abnormal visual effects. During Sleep IN mode, these commands are updated immediately. Read status (09h), Read display power mode (0Ah), Read display MADCTL (0Bh), Read display pixel format (0Ch), Read display image mode (0Dh), Read display signal mode (0Eh) and Read display self diagnostic result (0Fh) of these commands are updated immediately both in Sleep IN mode and Sleep OUT mode. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 88 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2. Description of Level 1 Command 8.2.1. NOP (00h) 00h Command NOP (No Operation) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ XX 0 0 0 0 0 0 0 0 00h Parameter No Parameter. This command is an empty command; it does not have any effect on the display module. However it can be used to terminate Description Frame Memory Write or Read as described in RAMWR (Memory Write) and RAMRD (Memory Read) Commands. X = Don’t care. Restriction None Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Flow Chart Default Value Power On Sequence N/A SW Reset N/A HW Reset N/A None The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 89 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.2. Software Reset (01h) 01h Command SWRESET D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ XX 0 0 0 0 0 0 0 1 01h Parameter No Parameter. When the Software Reset command is written, it causes a software reset. It resets the commands and parameters to their S/W Reset default values. (See default tables in each command description.) Description Note: The Frame Memory contents are unaffected by this command X = Don’t care. It will be necessary to wait 5msec before sending new command following software reset. The display module loads all display supplier factory default values to the registers during this 5msec. If Software Reset is applied during Sleep Out mode, it will be Restriction necessary to wait 120msec before sending Sleep out command. Software Reset Command cannot be sent during Sleep Out sequence. Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value Power On Sequence N/A SW Reset N/A HW Reset N/A SWRESET(01h) Legend Command Display whole blank screen Parameter Display Flow Chart Action Mode Set Commands to S/W Default Values Sequential transfer Sleep In Mode The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 90 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.3. Read display identification information (04h) 04h RDDIDIF (Read Display Identification Information) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 0 0 0 0 1 0 0 04h 1st Parameter 1 ↑ 1 XX X X X X X X X X X 2 Parameter 1 ↑ 1 XX ID1 [7:0] XX 3rd Parameter 1 ↑ 1 XX ID2 [7:0] XX 4th Parameter 1 ↑ 1 XX ID3 [7:0] XX nd This read byte returns 24 bits display identification information. The 1st parameter is dummy data. Description The 2nd parameter (ID1 [7:0]): LCD module’s manufacturer ID. The 3rd parameter (ID2 [7:0]): LCD module/driver version ID. The 4th parameter (ID3 [7:0]): LCD module/driver ID. Restriction Register Availability Default Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Value Power On Sequence See description SW Reset See description HW Reset See description Legend RDDIDIF(04h) Command Host Parameter Driver Display Flow Chart 1st Parameter: Dummy Read 2nd Parameter: Send LCD module's manufacturer information 3rd Parameter: Send panel type and LCM/driver version information 4th Parameter: Send module/driver information Action Mode Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 91 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.4. Read Display Status (09h) 09h RDDST (Read Display Status) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 0 0 0 1 0 0 1 09h 1st Parameter 1 ↑ 1 XX X X X X X X X X X 2ndParameter 1 ↑ 1 XX 0 00 3rdParameter 1 ↑ 1 XX 0 4thParameter 1 ↑ 1 XX 0 5thParameter 1 ↑ 1 XX D [31:25] D [22:20] 0 D [7:5] 0 D [19:16] 0 0 0 0 61 D [10:8] 0 0 00 0 00 This command indicates the current status of the display as described in the table below: Bit D31 D30 Description Booster voltage status Row address order D29 Column address order D28 Row/column exchange D27 Vertical refresh D26 RGB/BGR order Status 0 Booster OFF 1 Booster ON 0 Top to Bottom (When MADCTL B7=’0’) 1 Bottom to Top (When MADCTL B7=’1’) 0 Left to Right (When MADCTL B6=’0’). 1 Right to Left (When MADCTL B6=’1’). 0 Normal Mode (When MADCTL B5=’0’). 1 Reverse Mode (When MADCTL B5=’1’). 0 LCD Refresh Top to Bottom (When MADCTL B4=’0’) 1 LCD Refresh Bottom to Top (When MADCTL B4=’1’). 0 RGB (When MADCTL B3=’0’) 1 BGR (When MADCTL B3=’1’) 0 LCD Refresh Left to Right (When MADCTL B2=’0’) D25 Horizontal refresh order 1 LCD Refresh Right to Left (When MADCTL B2=’1’) D24 Not used 0 --- D23 Not used 0 --- 101 16-bit/pixel 110 18-bit/pixel 0 Idle Mode OFF D22 D21 Description Value Interface color pixel format definition D20 D19 D18 Idle mode ON/OFF Partial mode ON/OFF 1 Idle Mode ON 0 Partial Mode OFF 1 Partial Mode ON. 0 Sleep IN Mode 1 Sleep OUT Mode. 0 Display Normal Mode OFF. D17 Sleep IN/OUT D16 Display normal mode ON/OFF 1 Display Normal Mode ON. D15 Vertical scrolling status 0 Scroll OFF D14 Not used 0 --- D13 Inversion status 0 Not defined D12 All pixel ON 0 Not defined D11 All pixel OFF 0 Not defined D10 Display ON/OFF D9 Tearing effect line ON/OFF D[8:6] Gamma curve selection 0 Display is OFF 1 Display is ON 0 Tearing Effect Line OFF 1 Tearing Effect ON 000 GC0 001 --- 010 --- 011 --- other Not defined The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 92 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 0 Mode 1, V-Blanking only 1 Mode 2, both H-Blanking and V-Blanking. Not used 0 --- Not used 0 --- D2 Not used 0 --- D1 Not used 0 --- D0 Not used 0 --- D5 Tearing effect line mode D4 D3 X = Don’t care Restriction Register Availability Default Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Value Power On Sequence 32’h00610000h SW Reset 32’h00610000h HW Reset 32’h00610000h Legend RDDST(09h) Flow Chart 1st Parameter: Dummy Read 2nd Parameter: Send D[31:25] display status 3rd Parameter: Send D[19:16] display status 4th Parameter: Send D[10:8] display status 5th Parameter: Send D[7:5] display status Command Host Parameter Driver Display Action Mode Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 93 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.5. Read Display Power Mode (0Ah) 0Ah RDDPM (Read Display Power Mode) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 0 0 0 1 0 1 0 0Ah 1st Parameter 1 ↑ 1 XX X X X X X X X X X 2ndParameter 1 ↑ 1 XX D7 D6 D5 D4 D3 D2 D1 D0 08 This command indicates the current status of the display as described in the table below:: Bit Value Description Comment 0 Booster Off or has a fault. --- 1 Booster On and working OK --- 0 Idle Mode Off. --- 1 Idle Mode On. --- 0 Partial Mode Off. --- 1 Partial Mode On. --- 0 Sleep In Mode --- 1 Sleep Out Mode --- 0 Display Normal Mode Off. --- 1 Display Normal Mode On --- 0 Display is Off. --- 1 Display is On --- D1 -- Not Defined Set to ‘0’ D0 -- Not Defined Set to ‘0’ D7 D6 D5 Description D4 D3 D2 X = Don’t care Restriction Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value Power On Sequence 8’h08h SW Reset 8’h08h HW Reset 8’h08h Legend RDDPM(0Ah) Command Host Parameter Driver Display Flow Chart 1st Parameter: Dummy Read 2nd Parameter: Send D[7:2] display power mode status Action Mode Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 94 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.6. Read Display MADCTL (0Bh) 0Bh RDDMADCTL (Read Display MADCTL) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 0 0 0 1 0 1 1 0Bh 1st Parameter 1 ↑ 1 XX X X X X X X X X X 2ndParameter 1 ↑ 1 XX D7 D6 D5 D4 D3 D2 D1 D0 00 This command indicates the current status of the display as described in the table below: Bit Value Description Comment 0 Top to Bottom (When MADCTL B7=’0’). --- 1 Bottom to Top (When MADCTL B7=’1’). --- 0 Left to Right (When MADCTL B6=’0’) --- 1 Right to Left (When MADCTL B6=’1’) --- 0 Normal Mode (When MADCTL B5=’0’). --- 1 Reverse Mode (When MADCTL B5=’1’) --- 0 LCD Refresh Top to Bottom (When MADCTL B4=’0’) --- 1 LCD Refresh Bottom to Top (When MADCTL B4=’1’). --- 0 RGB (When MADCTL B3=’0’) --- 1 BGR (When MADCTL B3=’1’). --- 0 LCD Refresh Left to Right (When MADCTL B2=’0’). --- 1 LCD Refresh Right to Left (When MADCTL B2=’1’). --- D1 -- Switching between Segment outputs and RAM Set to ‘0’ D0 -- Switching between Segment outputs and RAM Set to ‘0’ D7 D6 D5 Description D4 D3 D2 X = Don’t care Restriction Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value Power On Sequence 8’h00h SW Reset No Change HW Reset 8’h00h Legend RDDMADCTL(0Bh) Command Host Parameter Driver Display Flow Chart 1st Parameter: Dummy Read 2nd Parameter: Send D[7:2] display power mode status Action Mode Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 95 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.7. Read Display Pixel Format (0Ch) 0Ch RDDCOLMOD (Read Display Pixel Format) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 0 0 0 1 1 0 0 0Ch 1st Parameter 1 ↑ 1 XX X X X X X X X X 2ndParameter 1 ↑ 1 XX RIM DPI [2:0] 0 DBI [2:0] X 06 This command indicates the current status of the display as described in the table below: RIM Description DPI [2:0] RGB Interface Format DBI [2:0] MCU Interface Format 0 0 0 0 Reserved 0 0 0 Reserved 0 0 0 1 Reserved 0 0 1 Reserved 0 0 1 0 Reserved 0 1 0 Reserved 0 0 1 1 Reserved 0 1 1 Reserved 0 1 0 0 Reserved 1 0 0 Reserved 0 1 0 1 16 bits / pixel 1 0 1 16 bits / pixel 0 1 1 0 18 bits / pixel 1 1 0 18 bits / pixel 0 1 1 1 Reserved 1 1 1 Reserved 1 1 0 1 1 1 1 0 16 bits / pixel (6-bit 3 times data transfer) 18 bits / pixel (6-bit 3 times data transfer) X = Don’t care Restriction Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Value Status Default RIM DPI [2:0] Power On Sequence 1’b0 3’b000 DBI [2:0] 3’b110 SW Reset No Chang No Chang No Chang HW Reset 1’b0 3’b000 3’b110 Legend RDDCOLMOD(0Ch) Command Host Parameter Driver Display Flow Chart 1st Parameter: Dummy Read 2nd Parameter: Send D[7:2] display pixel format status Action Mode Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 96 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.8. Read Display Image Format (0Dh) 0Dh RDDIM (Read Display Image Mode) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 0 0 0 1 1 0 1 0Dh 1st Parameter 1 ↑ 1 XX X X X X X X X X 2ndParameter 1 ↑ 1 XX 0 0 0 0 0 D [2:0] X 00 This command indicates the current status of the display as described in the table below: D [2:0] 000 001 010 011 Other Description Description Gamma curve 1 (G2.2) ------Not defined X = Don’t care Restriction Register Availability Default Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Value Power On Sequence 3’b000 SW Reset 3’b000 HW Reset 3’b000 Legend RDDIM(0Dh) Command Host Parameter Driver Display Flow Chart 1st Parameter: Dummy Read 2nd Parameter: Send D[7:0] display image mode status Action Mode Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 97 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.9. Read Display Signal Mode (0Eh) 0Eh RDDSM (Read Display Signal Mode) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 0 0 0 1 1 1 0 0Eh 1stParameter 1 ↑ 1 XX X X X X X X X X X 2ndParameter 1 ↑ 1 XX D7 D6 D5 D4 D3 D2 D1 D0 00 This command indicates the current status of the display as described in the table below: Bit D7 D6 D5 Description D4 D3 D2 D1 D0 Value 0 1 0 1 0 1 0 1 0 1 0 1 0 0 Description Tearing effect line OFF Tearing effect line ON Tearing effect line mode 1 Tearing effect line mode 2 Horizontal sync. (RGB interface) OFF Horizontal sync. (RGB interface) ON Vertical sync. (RGB interface) OFF Vertical sync. (RGB interface) ON Pixel clock (DOTCLK, RGB interface) OFF Pixel clock (DOTCLK, RGB interface) ON Data enable (DE, RGB interface) OFF Data enable (DE, RGB interface) ON Reserved Reserved X = Don’t care Restriction Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value Power On Sequence 8’h00h SW Reset 8’h00h HW Reset 8’h00h Legend RDDSM(0Eh) Command Host Parameter Driver Display Flow Chart 1st Parameter: Dummy Read 2nd Parameter: Send D[7:0] display signal mode status Action Mode Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 98 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.10. Read Display Self-Diagnostic Result (0Fh) 0Fh RDDSDR (Read Display Self-Diagnostic Result) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 0 0 0 1 1 1 1 0Fh 1stParameter 1 ↑ 1 XX X X X X X X X X X 2ndParameter 1 ↑ 1 XX D7 D6 0 0 0 0 0 0 00 Description Bit Description D7 Register Loading Detection Action D6 Functionality Detection D5 Not Used ‘0’ D4 Not Used ‘0’ D3 Not Used ‘0’ D2 Not Used ‘0’ D1 Not Used ‘0’ D0 Not Used ‘0’ Invert the D7 bit if register values loading work properly. Invert the D6 bit if the display is functionality Restriction Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value Power On Sequence 8’h00h SW Reset 8’h00h HW Reset 8’h00h Legend RDDSDR(0Fh) Command Host Parameter Driver Display Flow Chart 1st Parameter: Dummy Read 2nd Parameter: Send D[7:6] display self-diagnostic status Action Mode Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 99 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.11. Enter Sleep Mode (10h) 10h Command SPLIN (Enter Sleep Mode) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ XX 0 0 0 1 0 0 0 0 10h Parameter No Parameter This command causes the LCD module to enter the minimum power consumption mode. In this mode e.g. the DC/DC converter is stopped, Internal oscillator is stopped, and panel scanning is stopped. Description MCU interface and memory are still working and the memory keeps its contents. X = Don’t care This command has no effect when module is already in sleep in mode. Sleep In Mode can only be left by the Sleep Out Command (11h). It will be necessary to wait 5msec before sending next to command, this is to allow time for the supply Restriction voltages and clock circuits to stabilize. It will be necessary to wait 120msec after sending Sleep Out command (when in Sleep In Mode) before Sleep In command can be sent. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value Power On Sequence Sleep IN Mode SW Reset Sleep IN Mode HW Reset Sleep IN Mode It takes 120msec to get into Sleep In mode after SLPIN command issued. Legend Command SPLIN (10h) Stop DC/DC Converter Parameter Display Action Flow Chart Display whole blank screen (Automatic No effect to DISP ON/OFF commands) Drain charge from LCD panel Mode Stop Internal Oscillator Sequential transfer Sleep In Mode The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 100 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.12. Sleep Out (11h) 11h Command SLPOUT (Sleep Out) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ XX 0 0 0 1 0 0 0 1 11h Parameter No Parameter This command turns off sleep mode. In this mode e.g. the DC/DC converter is enabled, Internal oscillator is started, and panel scanning is started. Description X = Don’t care This command has no effect when module is already in sleep out mode. Sleep Out Mode can only be left by the Sleep In Command (10h). It will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock circuits stabilize. The display module loads all display supplier’s factory default values to the registers during this Restriction 5msec and there cannot be any abnormal visual effect on the display image if factory default and register values are same when this load is done and when the display module is already Sleep Out –mode. The display module is doing self-diagnostic functions during this 5msec. It will be necessary to wait 120msec after sending Sleep In command (when in Sleep Out mode) before Sleep Out command can be sent. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Flow Chart Status Default Value Power On Sequence Sleep IN Mode SW Reset Sleep IN Mode HW Reset Sleep IN Mode It takes 120msec to become Sleep Out mode after SLPOUT command issued. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 101 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color SPLOUT (11h) Displa y whole blank screen for 2 frames (Automatic No effect to DISP ON/OFF Commands) ILI9341 Legend Command Parameter Start Internal Oscillator Display Displa y Memory contents in accordance with the current command table settings Action Mode Start up DC-DC Converter Sequential transfer Sleep Out Mode Charge Offset voltage for LCD Panel The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 102 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.13. Partial Mode ON (12h) 12h Command PTLON (Partial Mode On) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ XX 0 0 0 1 0 0 1 0 12h Parameter No Parameter This command turns on partial mode The partial mode window is described by the Partial Area command (30H). To leave Description Partial mode, the Normal Display Mode On command (13H) should be written. X = Don’t care Restriction This command has no effect when Partial mode is active. Register Availability Default Flow Chart Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Value Power On Sequence Normal Display Mode ON SW Reset Normal Display Mode ON HW Reset Normal Display Mode ON See Partial Area (30h) The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 103 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.14. Normal Display Mode ON (13h) 13h Command NORON (Normal Display Mode On) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ XX 0 0 0 1 0 0 1 1 13h Parameter No Parameter This command returns the display to normal mode. Normal display mode on means Partial mode off. Description Exit from NORON by the Partial mode On command (12h) X = Don’t care Restriction This command has no effect when Normal Display mode is active. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Flow Chart Status Default Value Power On Sequence Normal Display Mode ON SW Reset Normal Display Mode ON HW Reset Normal Display Mode ON See Partial Area (30h) The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 104 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.15. Display Inversion OFF (20h) 20h Command DINVOFF (Display Inversion OFF) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ XX 0 0 1 0 0 0 0 0 20h Parameter No Parameter This command is used to recover from display inversion mode. This command makes no change of the content of frame memory. This command doesn’t change any other status. Memory Display Panel Description X = Don’t care Restriction This command has no effect when module already is inversion OFF mode. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence Display Inversion OFF SW Reset Display Inversion OFF HW Reset Display Inversion OFF Legend Display Inversion On Mode Command Parameter Flow Chart INVOFF(20h) Display Action Mode Display Inversion Off Mode Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 105 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.16. Display Inversion ON (21h) 21h Command DINVON (Display Inversion ON) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ XX 0 0 1 0 0 0 0 1 21h Parameter No Parameter This command is used to enter into display inversion mode. This command makes no change of the content of frame memory. Every bit is inverted from the frame memory to the display. This command doesn’t change any other status. To exit Display inversion mode, the Display inversion OFF command (20h) should be written. Description X = Don’t care Restriction Register Availability Default This command has no effect when module already is inversion ON mode. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Value Power On Sequence Display Inversion OFF SW Reset Display Inversion OFF HW Reset Display Inversion OFF Legend Display Inversion On Mode Command Parameter Display Flow Chart INVON(21h) Action Mode Display Inversion Off Mode Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 106 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.17. Gamma Set (26h) 26h GAMSET (Gamma Set) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 0 1 0 0 1 1 0 26h Parameter 1 1 ↑ XX GC [7:0] 01 This command is used to select the desired Gamma curve for the current display. A maximum of 4 fixed gamma curves can be selected. The curve is selected by setting the appropriate bit in the parameter as described in the Table: Description GC [7:0] Curve Selected 01h Gamma curve 1 (G2.2) 02h --- 04h --- 08h --- Note: All other values are undefined. X = Don’t care Values of GC [7:0] not shown in table above are invalid and will not change the current selected Gamma curve until valid Restriction value is received. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value Power On Sequence 8’h01h SW Reset 8’h01h HW Reset 8’h01h Legend GAMSET (26h) Command Parameter Display Flow Chart 1st Parameter: GC[7:0] Action Mode New Gamma Curve Loaded Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 107 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.18. Display OFF (28h) 28h Command DISPOFF (Display OFF) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ XX 0 0 1 0 1 0 0 0 28h Parameter No Parameter This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory is disabled and blank page inserted. This command makes no change of contents of frame memory. This command does not change any other status. There will be no abnormal visible effect on the display. Memory Display Panel Description X = Don’t care. Restriction This command has no effect when module is already in display off mode. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence Display OFF SW Reset Display OFF HW Reset Display OFF Legend Display On Mode Command Parameter Display Flow Chart DISPOFF(28h) Action Mode Display Off Mode Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 108 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.19. Display ON (29h) 29h Command DISPON (Display ON) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ XX 0 0 1 0 1 0 0 1 29h Parameter No Parameter This command is used to recover from DISPLAY OFF mode. Output from the Frame Memory is enabled. This command makes no change of contents of frame memory. This command does not change any other status Memory Display Panel Description X = Don’t care. Restriction Register Availability This command has no effect when module is already in display on mode. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value Power On Sequence Display OFF SW Reset Display OFF HW Reset Display OFF Legend Display Off Mode Command Parameter Display Flow Chart DISPON(29h) Action Mode Display On Mode Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 109 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.20. Column Address Set (2Ah) 2Ah CASET (Column Address Set) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 0 1 0 1 0 1 0 2Ah 1st Parameter 1 1 ↑ XX SC15 SC14 SC13 SC12 SC11 SC10 SC9 SC8 2ndParameter 1 1 ↑ XX SC7 SC6 SC5 SC4 SC3 SC2 SC1 SC0 3rd Parameter 1 1 ↑ XX EC15 EC14 EC13 EC12 EC11 EC10 EC9 EC8 4th Parameter 1 1 ↑ XX EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0 Note1 Note1 This command is used to define area of frame memory where MCU can access. This command makes no change on the other driver status. The values of SC [15:0] and EC [15:0] are referred when RAMWR command comes. Each value represents one column line in the Frame Memory. SC[15:0] EC[15:0] Description X = Don’t care SC [15:0] always must be equal to or less than EC [15:0]. Restriction Note 1: When SC [15:0] or EC [15:0] is greater than 00EFh (When MADCTL’s B5 = 0) or 013Fh (When MADCTL’s B5 = 1), data of out of range will be ignored Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Power On Sequence Default Default Value SC [15:0]=0000h SW Reset SC [15:0]=0000h HW Reset SC [15:0]=0000h EC [15:0]=00EFh If MADCTL’s B5 = 0: EC [15:0]=00EFh If MADCTL’s B5 = 1: EC [15:0]=013Fh EC [15:0]=00EFh The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 110 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color CASET (2Ah) ILI9341 If Needed 1st Parameter: SC[15:8] 2nd Parameter: SC[7:0] 3rd Parameter: EC[15:8] 4th Parmeter EC[7:0] Legend Command Parameter PASET (2Bh) Display Flow Chart 1st Parameter: SP[15:8] 2nd Parameter: SP[7:0] 3rd Parameter: EP[15:8] 4th Parameter: EP[7:0] Action Mode Sequential transfer RAMWR(2Ch) If Needed Image Data D1[17:0],D2[17:0]..Dn[17:0] Any Commend The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 111 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.21. Page Address Set (2Bh) 2Bh PASET (Page Address Set) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 0 1 0 1 0 1 1 2Bh 1st Parameter 1 1 ↑ XX SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 2ndParameter 1 1 ↑ XX SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 3rdParameter 1 1 ↑ XX EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8 4th Parameter 1 1 ↑ XX EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 Note1 Note1 This command is used to define area of frame memory where MCU can access. This command makes no change on the other driver status. The values of SP [15:0] and EP [15:0] are referred when RAMWR command comes. Each value represents one Page line in the Frame Memory. SP[15:0] Description EP[15:0] X = Don’t care SP [15:0] always must be equal to or less than EP [15:0] Restriction Note 1: When SP [15:0] or EP [15:0] is greater than 013Fh (When MADCTL’s B5 = 0) or 00EFh (When MADCTL’s B5 = 1), data of out of range will be ignored. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value Power On Sequence SP [15:0]=0000h SW Reset SP [15:0]=0000h HW Reset SP [15:0]=0000h EP [15:0]=013Fh If MADCTL’s B5 = 0: EP [15:0]=013Fh If MADCTL’s B5 = 1: EP [15:0]=00EFh EP [15:0]=013Fh The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 112 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color CASET (2Ah) ILI9341 If Needed 1st Parameter: SC[15:8] 2nd Parameter: SC[7:0] 3rd Parameter: EC[15:8] 4th Parmeter EC[7:0] Legend Command Parameter PASET (2Bh) Display Flow Chart 1st Parameter: SP[15:8] 2nd Parameter: SP[7:0] 3rd Parameter: EP[15:8] 4th Parameter: EP[7:0] Action Mode Sequential transfer RAMWR(2Ch) If Needed Image Data D1[17:0],D2[17:0]..Dn[17:0] Any Commend The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 113 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.22. Memory Write (2Ch) 2Ch RAMWR (Memory Write) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 0 1 0 1 1 0 0 2Ch 1st Parameter 1 1 ↑ D1 [17:0] XX : 1 1 ↑ Dx [17:0] XX 1 1 ↑ Dn [17:0] XX Nth Parameter This command is used to transfer data from MCU to frame memory. This command makes no change to the other driver status. When this command is accepted, the column register and the page register are reset to the Start Column/Start Description Page positions. The Start Column/Start Page positions are different in accordance with MADCTL setting.) Then D [17:0] is stored in frame memory and the column register and the page register incremented. Sending any other command can stop frame Write. X = Don’t care. Restriction In all color modes, there is no restriction on length of parameters. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence Contents of memory is set randomly SW Reset Contents of memory is not cleared HW Reset Contents of memory is not cleared CASET (2Ah) If Needed 1st Parameter: SC[15:8] 2nd Parameter: SC[7:0] 3rd Parameter: EC[15:8] 4th Parmeter EC[7:0] Legend Command Parameter PASET (2Bh) Display Flow Chart 1st Parameter: SP[15:8] 2nd Parameter: SP[7:0] 3rd Parameter: EP[15:8] 4th Parameter: EP[7:0] Action Mode Sequential transfer RAMWR(2Ch) If Needed Image Data D1[17:0],D2[17:0]..Dn[17:0] Any Commend The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 114 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.23. Color Set (2Dh) 2Dh RGBSET (Color Set) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 0 1 0 1 1 0 1 2Dh 1st Parameter 1 1 ↑ XX 0 0 R00 [5:0] XX nth Parameter 1 1 ↑ XX 0 0 Rnn [5:0] XX 32 Parameter 1 1 ↑ XX 0 0 R31 [5:0] XX 33rdParameter 1 1 ↑ XX 0 0 G00 [5:0] XX nth Parameter 1 1 ↑ XX 0 0 Gnn [5:0] XX 96thParameter 1 1 ↑ XX 0 0 G64 [5:0] XX 97thParameter 1 1 ↑ XX 0 0 B00 [5:0] XX nth Parameter 1 1 ↑ XX 0 0 Bnn [5:0] XX 128thParameter 1 1 ↑ XX 0 0 B31 [5:0] XX nd This command is used to define the LUT for 16-bit to 18-bit color depth conversion. 128 bytes must be written to the LUT regardless of the color mode. Only the values in Section 7.4 are referred. Description This command has no effect on other commands, parameter and contents of frame memory. Visible change takes effect next time the frame memory is written to. Restriction Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence Random values SW Reset Contents of LUT protected HW Reset Random values Legend RGBSET (2Dh) Command Flow Chart 1st Parameter: R00[5:0] : 32nd Parameter: R31[5:0] 33rd Parameter: G00[5:0] : 96th Parameter: G63[5:0] 97th Parameter: B00[5:0] : 128th Parameter: B31[5:0] Parameter Display Action Mode Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 115 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.24. Memory Read (2Eh) 2Eh RAMRD (Memory Read) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 0 1 0 1 1 1 0 2Eh 1stParameter 1 1 ↑ XX X X X X X X X X 2ndParameter 1 1 ↑ D1 [17:0] XX : 1 1 ↑ Dx [17:0] XX 1 1 ↑ Dn [17:0] XX (N+1)th Parameter X This command transfers image data from ILI9341’s frame memory to the host processor starting at the pixel location specified by preceding set_column_address and set_page_address commands. If Memory Access control B5 = 0: The column and page registers are reset to the Start Column (SC) and Start Page (SP), respectively. Pixels are read from frame memory at (SC, SP). The column register is then incremented and pixels read from the frame memory until the column register equals the End Column (EC) value. The column register is then reset to SC and the page register is incremented. Pixels are read from the frame memory until the page register equals the End Page (EP) value or the host Description processor sends another command. If Memory Access Control B5 = 1: The column and page registers are reset to the Start Column (SC) and Start Page (SP), respectively. Pixels are read from frame memory at (SC, SP). The page register is then incremented and pixels read from the frame memory until the page register equals the End Page (EP) value. The page register is then reset to SP and the column register is incremented. Pixels are read from the frame memory until the column register equals the End Column (EC) value or the host processor sends another command. Restriction Register Availability There is no restriction on length of parameters. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value Power On Sequence Contents of memory is set randomly SW Reset Contents of memory is set randomly HW Reset Contents of memory is set randomly The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 116 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color RAMRD (2Eh) ILI9341 Legend Command Dummy Read Parameter Display Flow Chart Action Image Data D1[17:0],D2[17:0]..Dn[17:0] Mode Sequential transfer Any Command The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 117 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.25. Partial Area (30h) 30h PLTAR (Partial Area) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 0 1 1 0 0 0 0 30h 1st Parameter 1 1 ↑ XX SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 00 2ndParameter 1 1 ↑ XX SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 00 3 Parameter 1 1 ↑ XX ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8 01 4th Parameter 1 1 ↑ XX ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 3F rd This command defines the partial mode’s display area. There are 2 parameters associated with this command, the first defines the Start Row (SR) and the second the End Row (ER), as illustrated in the figures below. SR and ER refer to the Frame Memory Line Pointer. If End Row>Start Row when MADCTL B4=0:- Start Row SR[15:0] Partial Area End Row ER[15:0] If End Row>Start Row when MADCTL B4=1:- End Row ER[15:0] Description Partial Area Start Row SR[15:0] If End Row<Start Row when MADCTL B4=0:- Partial Area End Row ER[15:0] Start Row SR[15:0] Partial Area If End Row = Start Row then the Partial Area will be one row deep. X = Don’t care. Restriction SR [15…0] and ER [15…0] cannot be 0000h nor exceed 013Fh. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 118 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default ILI9341 Default Value SR [15:0] ER [15:0] Power On Sequence 16’h0000h 16’h013Fh SW Reset 16’h 0000h 16’h 013Fh HW Reset 16’h 0000h 16’h 013Fh 1. To Enter Partial Mode PLTAR(30h) 1st Parameter: SR[15:8] 2nd Parameter: SR[7:0] 3rd Parameter: ER[15:8] 4th Parameter: ER[7:0] Legend Command Parameter Display Action Mode PTLON(12h) Sequential transfer Partial Mode 2. To Leave Partial Mode Partial Mode Flow Chart Legend DISPOFF(28h) Command Parameter NORON(13h) Display Partial Mode OFF Action Mode RAMRW(2Ch) Sequential transfer Image Data D1[17:0],D2[17:0]..Dn[17:0] DISPON(29h) The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 119 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.26. Vertical Scrolling Definition (33h) 33h VSCRDEF (Vertical Scrolling Definition) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 0 1 1 0 0 1 1 33h 1stParameter 1 ↑ 1 XX TFA [15:8] 00 2ndParameter 1 ↑ 1 XX TFA [7:0] 00 3rdParameter 1 ↑ 1 XX VSA [15:8] 01 4thParameter 1 ↑ 1 XX VSA [7:0] 40 5thParameter 1 ↑ 1 XX BFA [15:8] 00 1 ↑ 1 XX BFA [7:0] 00 6thParameter This command defines the Vertical Scrolling Area of the display. When MADCTL B4=0 The 1st & 2nd parameter TFA [15...0] describes the Top Fixed Area (in No. of lines from Top of the Frame Memory and Display). The 3rd & 4th parameter VSA [15...0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address). The first line read from Frame Memory appears immediately after the bottom most line of the Top Fixed Area. The 5th & 6th parameter BFA [15...0] describes the Bottom Fixed Area (in No. of lines from Bottom of the Frame Memory and Display). TFA, VSA and BFA refer to the Frame Memory Line Pointer. (0, 0) TFA[15:0] Top Fixed Area First line read from memory Description Scroll Area BFA[15:0] Bottom Fixed Area When MADCTL B4=1 The 1st & 2nd parameter TFA [15...0] describes the Top Fixed Area (in No. of lines from Bottom of the Frame Memory and Display). The 3rd & 4th parameter VSA [15...0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address). The first line read from Frame Memory appears immediately after the top most line of the Top Fixed Area. The 5th & 6th parameter BFA [15...0] describes the Bottom Fixed Area (in No. of lines from Top of the Frame Memory and Display). The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 120 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 (0, 0) Bottom Fixed Area BFA[15:0] Scroll Area First line read from memory TFA[15:0] Top Fixed Area X = Don’t care Restriction Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value TFA [15:0] VSA [15:0] BFA [15:0] Power On Sequence 16’h0000h 16’h0140h 16’h0000h SW Reset 16’h0000h 16’h0140h 16’h0000h HW Reset 16’h0000h 16’h0140h 16’h0000h The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 121 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 1. To enter Vertical Scroll Mode : Normal Mode VSCRDEF (33h) 1st & 2nd parameter : TFA[15:0] Legend 3rd & 4th Parameter VSA[15:0] Command Parameter 5th & 6th Parameter BFA[15:0] Display Action CASET(2Ah) 1st & 2nd parameter : SC[15:0] Only required for nonrolling scrolling Mode Only required for nonrolling scrolling Sequential transfer 3rd & 4th Parameter EC[15:0] PASET(2Bh) 1st & 2nd parameter : SP[15:0] Flow Chart 3rd & 4th Parameter EP[15:0] MADCTL Parameter Optional : It may be necessary to redefine the Frame Memory Write Direction RAMRW(2Ch) Scroll Image Data VSCRSADD(37h) 1st & 2nd parameter : VSP[15:0] Normal Mode Note : The Frame Memory Window size ,must be defined correctly otherwise undesirable image will be displayed. 2. Continuous Scroll : The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 122 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 Scroll Mode Legend CASET (2Ah) 1st & 2nd parameter : SC[15:0] 3rd & 4th Parameter EC[15:0] Command Parameter Display Action Mode PASET (2Bh) Sequential transfer 1st & 2nd parameter : SP[15:0] 3rd & 4th Parameter EP[15:0] RAMRW Scroll Image Data VSCRSADD(37h) 3.To Leave Vertical Scroll Mode: Scroll Mode (Optional ) To prevent Tearing Effect Image Display DISOFF(28h) MORON(12h)/PTLON(12h) Scroll Mode Off RAMRW(2Ch) Image Data D1[17:0],D2[17:0]...Dn[17:0] DISON(29h) Note: Scroll Mode can be left by both the Normal Display Mode ON (13h) and Partial Mode ON (12h) commands. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 123 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.27. Tearing Effect Line OFF (34h) 34h Command TEOFF (Tearing Effect Line OFF) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ XX 0 0 1 1 0 1 0 0 34h Parameter No Parameter This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line. Description X = Don’t care. Restriction Register Availability This command has no effect when Tearing Effect output is already OFF. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value Power On Sequence OFF SW Reset OFF HW Reset OFF Legend TE Line Output ON Command Parameter TEOFF(34h) Display Flow Chart Action TE Line Output OFF Mode Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 124 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.28. Tearing Effect Line ON (35h) 35h TEON (Tearing Effect Line ON) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 0 1 1 0 1 0 1 35h Parameter 1 1 ↑ XX 0 0 0 0 0 0 0 M 00 This command is used to turn ON the Tearing Effect output signal from the TE signal line. This output is not affected by changing MADCTL bit B4. The Tearing Effect Line On has one parameter which describes the mode of the Tearing Effect Output Line. When M=0: The Tearing Effect Output line consists of V-Blanking information only: tvdl Description tvdh Vertical Time Scale When M=1: The Tearing Effect Output Line consists of both V-Blanking and H-Blanking information: tvdl tvdh Vertical Time Scale Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low. X = Don’t care. Restriction Register Availability This command has no effect when Tearing Effect output is already ON Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value Power On Sequence OFF SW Reset OFF HW Reset OFF The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 125 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 Legend TE Line Output OFF Command Parameter TEON(35h) Display Flow Chart 1st Parameter: M bit Action Mode TE Line Output ON Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 126 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.29. Memory Access Control (36h) 36h MADCTL (Memory Access Control) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 0 1 1 0 1 1 0 36h Parameter 1 1 ↑ XX MY MX MV ML BGR MH 0 0 00 This command defines read/write scanning direction of frame memory. This command makes no change on the other driver status. Bit MY MX MV ML Name Row Address Order Column Address Order Row / Column Exchange Vertical Refresh Order BGR RGB-BGR Order MH Horizontal Refresh ORDER Description These 3 bits control MCU to memory write/read direction. LCD vertical refresh direction control. Color selector switch control (0=RGB color filter panel, 1=BGR color filter panel) LCD horizontal refreshing direction control. Note: When BGR bit is changed, the new setting is active immediately without update the content in Frame Memory again. X = Don’t care. MV(Vertical refresh order bit)="0" memory display MV(Vertical refresh order bit)=" 1" memory display overwrite Description ML(Vertical refresh order bit)="0" Top-Left (0,0) Top-Left (0,0) (example) me mory ML(Vertical refresh order bit)="1" Top-Left (0,0) Top-Left (0,0) (example) memory display Send 1st (1) Send 2nd (2) display Send last (320 ) Send 3rd (3) Send 3rd (3) Send 2nd (2 ) Send 1st (1) Send last (320 ) BGR(RGB-BGR Order control bit)="0" R G B Driver IC R G B BGR(RGB-BGR Order control bit )="1" R G B Driver IC R G B SIG1 SIG2 SIG240 SIG1 SIG2 SIG240 SIG1 SIG2 SIG240 SIG1 SIG2 SIG240 R G B B G R B G R R G B B G R B G R R G B R G B R G B R G B LCD Panel B G R LCD Panel B G R The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 127 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color MH(Horizontal refresh order control bit)="0" ILI9341 MH(Horizontal refresh order control bit)=" 1" display display Top-Left (0,0) Se nd last (240) Se nd 3rd (3) Se nd 1st (1) Top-Left (0,0) Send 2nd (2 ) Send 3rd (3) Send la st (240) Se nd 1st (1) Se nd 2nd (2) Top-Left (0,0) Top-Left (0,0) memory memory Note: Top-Left (0,0) means a physical memory location. Restriction Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value Power On Sequence 8’h00h SW Reset No change HW Reset 8’h00h Legend Command Parameter MADCTR(36h) Display Flow Chart 1st Parameter: MY, MX, MV, ML, RGB, MH Action Mode Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 128 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.30. Vertical Scrolling Start Address (37h) 37h VSCRSADD (Vertical Scrolling Start Address) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 0 1 1 0 1 1 1 37h 1stParameter 1 ↑ 1 XX VSP [15:8] 00 2ndParameter 1 ↑ 1 XX VSP [7:0] 00 This command is used together with Vertical Scrolling Definition (33h). These two commands describe the scrolling area and the scrolling mode. The Vertical Scrolling Start Address command has one parameter which describes the address of the line in the Frame Memory that will be written as the first line after the last line of the Top Fixed Area on the display as illustrated below:When MADCTL B4=0 Example: When Top Fixed Area = Bottom Fixed Area = 00, Vertical Scrolling Area = 320 and VSP=’3’. Pointer B4=0 Frame Memory (0, 0) Display 0 1 Line Pointer VSP[15:0] 2 3 4 .. .. 317 318 (0, 319) 319 Description When MADCTL B4=1 Example: When Top Fixed Area = Bottom Fixed Area = 00, Vertical Scrolling Area = 320 and VSP=’3’. Pointer B4=1 Frame Memory (0, 0) Display 319 318 317 .. .. 4 Line Pointer VSP[15:0] 3 2 1 0 (0, 319) Note: (1) When new Pointer position and Picture Data are sent, the result on the display will happen at the next Panel Scan to avoid tearing effect. VSP refers to the Frame Memory line Pointer. (2) This command is ignored when the ILI9341 enters Partial mode. X = Don’t care The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 129 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 Restriction Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out No Partial Mode On, Idle Mode On, Sleep Out No Sleep In Yes Status Default Flow Chart Power On Sequence Default Value VSP [15:0] 16’h0000h SW Reset 16’h0000h HW Reset 16’h0000h See Vertical Scrolling Definition (33h) description. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 130 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.31. Idle Mode OFF (38h) 38h Command IDMOFF (Idle Mode OFF) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ XX 0 0 1 1 1 0 0 0 38h Parameter No Parameter This command is used to recover from Idle mode on. Description In the idle off mode, LCD can display maximum 262,144 colors. X = Don’t care. Restriction This command has no effect when module is already in idle off mode. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence Idle mode OFF SW Reset Idle mode OFF HW Reset Idle mode OFF Legend Idle mode on Command Parameter Display Flow Chart IDMOFF(38h) Action Mode Idle mode off Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 131 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.32. Idle Mode ON (39h) 39h Command IDMON (Idle Mode ON) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ XX 0 0 1 1 1 0 0 1 39h Parameter No Parameter This command is used to enter into Idle mode on. In the idle on mode, color expression is reduced. The primary and the secondary colors using MSB of each R, G and B in the Frame Memory, 8 color depth data is displayed. Memory Panel Display Description Black Blue Red Magenta Green Cyan Yellow White Memory Contents vs. Display Color R5 R4 R3 R2 R1 R0 G 5 G 4 G 3 G 2 G 1 G 0 B 5 B 4 B 3 B 2 B 1 B 0 0XXXXX 0XXXXX 0XXXXX 0XXXXX 0XXXXX 1XXXXX 1XXXXX 0XXXXX 0XXXXX 1XXXXX 0XXXXX 1XXXXX 0XXXXX 1XXXXX 0XXXXX 0XXXXX 1XXXXX 1XXXXX 1XXXXX 1XXXXX 0XXXXX 1XXXXX 1XXXXX 1XXXXX X = Don’t care. Restriction This command has no effect when module is already in idle off mode. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value Power On Sequence Idle mode OFF SW Reset Idle mode OFF HW Reset Idle mode OFF The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 132 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 Legend Idle mode off Command Parameter Display Flow Chart IDMON(39h) Action Mode Idle mode on Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 133 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.33. COLMOD: Pixel Format Set (3Ah) 3Ah PIXSET (Pixel Format Set) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 0 1 1 1 0 1 0 3Ah Parameter 1 1 ↑ XX 0 DPI [2:0] 0 DBI [2:0] 66 This command sets the pixel format for the RGB image data used by the interface. DPI [2:0] is the pixel format select of RGB interface and DBI [2:0] is the pixel format of MCU interface. If a particular interface, either RGB interface or MCU interface, is not used then the corresponding bits in the parameter are ignored. The pixel format is shown in the table below. DPI [2:0] Description RGB Interface Format DBI [2:0] MCU Interface Format 0 0 0 Reserved 0 0 0 Reserved 0 0 1 Reserved 0 0 1 Reserved 0 1 0 Reserved 0 1 0 Reserved 0 1 1 Reserved 0 1 1 Reserved 1 0 0 Reserved 1 0 0 Reserved 1 0 1 16 bits / pixel 1 0 1 16 bits / pixel 1 1 0 18 bits / pixel 1 1 0 18 bits / pixel 1 1 1 Reserved 1 1 1 Reserved If using RGB Interface must selection serial interface. X = Don’t care Restriction Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Value Status Default DPI [2:0] Power On Sequence DBI [2:0] 3’b110 3’b110 SW Reset No Change No Change HW Reset 3’b110 3’b110 Legend COLMOD (3Ah) Command Parameter Flow Chart DPI[2:0] RGB pixel format DBI[2:0] MCU pixel format Display Action Mode Any Command Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 134 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.34. Write_Memory_Continue (3Ch) 3Ch Command st Write_Memory_Continue D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ XX 0 0 1 1 1 1 0 0 3Ch D1 D1 D1 D1 D1 D1 D1 D1 D1 000 [17..8] [7] [6] [5] [4] [3] [2] [1] [0] 3FF 1 Parameter 1 1 ↑ Xth Parameter 1 1 ↑ Nth Parameter 1 1 ↑ Dx Dx Dx Dx Dx Dx Dx Dx Dx 000 [17..8] [7] [6] [5] [4] [3] [2] [1] [0] 3FF Dn Dn Dn Dn Dn Dn Dn Dn Dn 000 [17..8] [7] [6] [5] [4] [3] [2] [1] [0] 3FF This command transfers image data from the host processor to the display module’s frame memory continuing from the pixel location following the previous write_memory_continue or write_memory_start command. If set_address_mode B5 = 0: Data is written continuing from the pixel location after the write range of the previous write_memory_start or write_memory_continue. The column register is then incremented and pixels are written to the frame memory until the column register equals the End Column (EC) value. The column register is then reset to SC and the page register is incremented. Pixels are written to the frame memory until the page register equals the End Page (EP) value and the column register equals the EC value, or the host processor sends another command. If the number of pixels exceeds (EC – SC + 1) * (EP – SP + 1) the extra pixels are ignored. If set_address_mode B5 = 1: Data is written continuing from the pixel location after the write range of the previous write_memory_start or write_memory_continue. The page register is then incremented and pixels are written to the frame memory until the page Description register equals the End Page (EP) value. The page register is then reset to SP and the column register is incremented. Pixels are written to the frame memory until the column register equals the End column (EC) value and the page register equals the EP value, or the host processor sends another command. If the number of pixels exceeds (EC – SC + 1) * (EP – SP + 1) the extra pixels are ignored. Sending any other command can stop frame Write. Frame Memory Access and Interface setting (B3h), WEMODE=0 When the transfer number of data exceeds (EC-SC+1)*(EP-SP+1), the exceeding data will be ignored. Frame Memory Access and Interface setting (B3h), WEMODE=1 When the transfer number of data exceeds (EC-SC+1)*(EP-SP+1), the column and page number will be reset, and the exceeding data will be written into the following column and page. A write_memory_start should follow a set_column_address, set_page_address or set_address_mode to define the write Restriction address. Otherwise, data written with write_memory_continue is written to undefined addresses. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 135 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In No Default Status Default Value Power On Sequence Random value SW Reset No change HW Reset No change ILI9341 Flow Chart The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 136 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.35. Read_Memory_Continue (3Eh) 3Eh Read_Memory_Continue D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 0 1 1 1 1 1 0 3Eh 1st Parameter 1 ↑ 1 XX X X X X X X X X X D1 D1 D1 D1 D1 D1 D1 D1 D1 000 3FF nd 2 Parameter 1 ↑ 1 xst Parameter 1 ↑ 1 Nst Parameter 1 ↑ 1 [17..8] [7] [6] [5] [4] [3] [2] [1] [0] Dx Dx Dx Dx Dx Dx Dx Dx Dx 000 [17..8] [7] [6] [5] [4] [3] [2] [1] [0] 3FF Dn Dn Dn Dn Dn Dn Dn Dn Dn 000 [17..8] [7] [6] [5] [4] [3] [2] [1] [0] 3FF This command transfers image data from the display module’s frame memory to the host processor continuing from the location following the previous read_memory_continue (3Eh) or read_memory_start (2Eh) command. If set_address_mode B5 = 0: Pixels are read continuing from the pixel location after the read range of the previous read_memory_start or read_memory_continue. The column register is then incremented and pixels are read from the frame memory until the column register equals the End Column (EC) value. The column register is then reset to SC and the page register is incremented. Pixels are read from the frame memory until the page register equals the End Page (EP) value and the column register equals the EC value, or the host processor sends another command. Description If set_address_mode B5 = 1: Pixels are read continuing from the pixel location after the read range of the previous read_memory_start or read_memory_continue. The page register is then incremented and pixels are read from the frame memory until the page register equals the End Page (EP) value. The page register is then reset to SP and the column register is incremented. Pixels are read from the frame memory until the column register equals the End Column (EC) value and the page register equals the EP value, or the host processor sends another command. This command makes no change to the other driver status. A read_memory_start should follow a set_column_address, set_page_address or set_address_mode to define the read Restriction location. Otherwise, data read with read_memory_continue is undefined. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Default Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Value Power On Sequence Random data SW Reset No change HW Reset No change The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 137 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 Flow Chart The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 138 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.36. Set_Tear_Scanline (44h) 44h Set_Tear_Scanline Command st D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ XX 0 1 0 0 0 1 0 0 44h 1 Parameter 1 1 ↑ XX 2nd Parameter 1 1 ↑ XX STS 0 0 0 0 0 0 0 STS STS STS STS STS STS STS STS [7] [6] [5] [4] [3] [2] [1] [0] [8] 00 00 This command turns on the display Tearing Effect output signal on the TE signal line when the display reaches line STS. The TE signal is not affected by changing set_address_mode bit B4. The Tearing Effect Line On has one parameter that describes the Tearing Effect Output Line mode. tvdl tvdh Description Vertical Time Scale Note that set_tear_scanline with STS=0 is equivalent to set_tear_on with M=0. The Tearing Effect Output line shall be active low when the display module is in Sleep mode. Restriction Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Default Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Value Power On Sequence STS [8:0]=0000h SW Reset STS [8:0]=0000h HW Reset STS [8:0]=0000h Flow Chart The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 139 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.37. Get_Scanline (45h) 45h Get_Scanline D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 1 0 0 0 1 0 1 45h 1st Parameter 1 ↑ 1 XX X X X X X X X X X GTS GTS [9] [8] nd 2 Parameter 1 ↑ 1 XX 3rd Parameter 1 ↑ 1 XX 0 0 0 0 0 0 GTS GTS GTS GTS GTS GTS GTS GTS [7] [6] [5] [4] [3] [2] [1] [0] 00 00 The display returns the current scan line, GTS, used to update the display device. The total number of scan lines on a display device is defined as VSYNC + VBP + VACT + VFP. The first scan line is defined as the first line of V-Sync and is Description denoted as Line 0. When in Sleep Mode, the value returned by get_scanline is undefined. Restriction None Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Power On Sequence Default Value GTS [9:0] GTS [9:0]=0000h SW Reset GTS [9:0]=0000h HW Reset GTS [9:0]=0000h Flow Chart The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 140 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.38. Write Display Brightness (51h) WRDISBV (Write Display Brightness) 51h D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 1 0 1 0 0 0 1 51h Parameter 1 1 ↑ XX DBV[7] DBV[6] DBV[5] DBV[4] DBV[3] DBV[2] DBV[1] DBV[0] 00 This command is used to adjust the brightness value of the display. It should be checked what is the relationship between this written value and output brightness of the display. This relationship Description is defined on the display module specification. In principle relationship is that 00h value means the lowest brightness and FFh value means the highest brightness. Restriction None Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value DBV [7:0] Power On Sequence 8’h00h SW Reset 8’h00h HW Reset 8’h00h Flow Chart The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 141 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.39. Read Display Brightness (52h) 52h RDDISBV (Read Display Brightness Value) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 1 0 1 0 0 1 0 52h 1st Parameter 1 ↑ 1 XX X X X X X X X X X 2nd Parameter 1 ↑ 1 XX DBV[7] DBV[6] DBV[5] DBV[4] DBV[3] DBV[2] DBV[1] DBV[0] 00 This command returns the brightness value of the display. It should be checked what the relationship between this returned value and output brightness of the display. This Description relationship is defined on the display module specification. In principle the relationship is that 00h value means the lowest brightness and FFh value means the highest brightness. The display module is sending 2nd parameter value on the data lines if the MCU wants to read more than one parameter Restriction (= more than 2 RDX cycle) on DBI Mode. Only 2nd parameter is sent on DSI (The 1st parameter is not sent). Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value DBV [7:0] Power On Sequence 8’h00h SW Reset 8’h00h HW Reset 8’h00h Flow Chart The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 142 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.40. Write CTRL Display (53h) 53h WRCTRLD (Write Control Display) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 1 0 1 0 0 1 1 53h Parameter 1 1 ↑ XX 0 0 BCTRL 0 DD BL 0 0 00 This command is used to control display brightness. BCTRL: Brightness Control Block On/Off, This bit is always used to switch brightness for display. 0 = Off (Brightness registers are 00h, DBV[7..0]) 1 = On (Brightness registers are active, according to the other parameters.) DD: Display Dimming, only for manual brightness setting DD = 0: Display Dimming is off DD = 1: Display Dimming is on Description BL: Backlight Control On/Off 0 = Off (Completely turn off backlight circuit. Control lines must be low. ) 1 = On Dimming function is adapted to the brightness registers for display when bit BCTRL is changed at DD=1, e.g. BCTRL: 0 1 or 1 0. When BL bit change from “On” to “Off”, backlight is turned off without gradual dimming, even if dimming-on (DD=1) are selected. Restriction None Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Value Status Default BCTRL DD BL Power On Sequence 1’b0 1’b0 1’b0 SW Reset 1’b0 1’b0 1’b0 HW Reset 1’b0 1’b0 1’b0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 143 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 Legend WRCTRLD Command Parameter BCTRL,DD,BL Flow Chart Display Action New Control Value Loaded Mode Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 144 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.41. Read CTRL Display (54h) 54h RDCTRLD (Read Control Display) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 1 0 1 0 1 0 0 54h 1st Parameter 1 ↑ 1 XX X X X X X X X X XX 2nd Parameter 1 ↑ 1 XX 0 0 BCTRL 0 DD BL 0 0 00 This command is used to return brightness setting. BCTRL: Brightness Control Block On/Off, ‘0’ = Off (Brightness registers are 00h) ‘1’ = On (Brightness registers are active, according to the DBV[7..0] parameters.) DD: Display Dimming Description ‘0’ = Display Dimming is off ‘1’ = Display Dimming is on BL: Backlight On/Off ‘0’ = Off (Completely turn off backlight circuit. Control lines must be low. ) ‘1’ = On The display module is sending 2nd parameter value on the data lines if the MCU wants to read more than one parameter Restriction (= more than 2 RDX cycle) on DBI. Only 2nd parameter is sent on DSI (The 1st parameter is not sent). Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Value Status Default BCTRL DD BL Power On Sequence 1’b0 1’b0 1’b0 SW Reset 1’b0 1’b0 1’b0 HW Reset 1’b0 1’b0 1’b0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 145 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 Flow Chart The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 146 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.42. Write Content Adaptive Brightness Control (55h) 55h WRCABC (Write Content Adaptive Brightness Control) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 1 0 1 0 1 0 1 55h Parameter 1 1 ↑ XX 0 0 0 0 0 0 C [1] C [0] 00 This command is used to set parameters for image content based adaptive brightness control functionality. There is possible to use 4 different modes for content adaptive image functionality, which are defined on a table below. Description C [1:0] Restriction Default Value 2’b00 Off 2’b01 User Interface Image 2’b10 Still Picture 2’b11 Moving Image None Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Default Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Value Power On Sequence C [1:0]=00h SW Reset C [1:0]=00h HW Reset C [1:0]=00h Flow Chart The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 147 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.43. Read Content Adaptive Brightness Control (56h) 56h RDCABC (Read Content Adaptive Brightness Control) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 0 1 0 1 0 1 1 0 56h 1st Parameter 1 ↑ 1 XX X X X X X X X X XX 2nd Parameter 1 ↑ 1 XX 0 0 0 0 0 0 C [1] C [0] 00 This command is used to read the settings for image content based adaptive brightness control functionality. It is possible to use 4 different modes for content adaptive image functionality, which are defined on a table below. Description C [1:0] Default Value 2’b00 Off 2’b01 User Interface Image 2’b10 Still Picture 2’b11 Moving Image The display module is sending 2nd parameter value on the data lines if the MCU wants to read more than one parameter Restriction (= more than 2 RDX cycle) on DBI. Only 2nd parameter is sent on DSI (The 1st parameter is not sent). Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence C [1:0]=00h SW Reset C [1:0]=00h HW Reset C [1:0]=00h Flow Chart The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 148 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.44. Write CABC Minimum Brightness (5Eh) 5Eh Command D/CX 0 RDX 1 WRX ↑ D17-8 XX Parameter 1 1 ↑ XX Backlight Control 1 D6 D5 D4 1 0 1 CMB CMB CMB [6] [5] [4] D7 0 CMB [7] D3 1 CMB [3] D2 1 CMB [2] D1 1 CMB [1] D0 0 CMB [0] HEX 5Eh 00 This command is used to set the minimum brightness value of the display for CABC function. CMB[7:0]: CABC minimum brightness control, this parameter is used to avoid too much brightness reduction. When CABC is active, CABC cannot reduce the display brightness to less than CABC minimum brightness setting. Image processing function is worked as normal, even if the brightness cannot be changed. This function does not affect to the other function, manual brightness setting. Manual brightness can be set the display Description brightness to less than CABC minimum brightness. Smooth transition and dimming function can be worked as normal. When display brightness is turned off (BCTRL=0 of “Write CTRL Display (53h)”), CABC minimum brightness setting is ignored. In principle relationship is that 00h value means the lowest brightness for CABC and FFh value means the highest brightness for CABC. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value CMB [7:0] Power On Sequence 8’h00h SW Reset No Change HW Reset 8’h00h The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 149 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.45. Read CABC Minimum Brightness (5Fh) 5Fh Command 1stParameter D/CX 0 1 RDX 1 ↑ WRX ↑ 1 D17-8 XX XX 2ndParameter 1 ↑ 1 XX D7 0 X CMB [7] Backlight Control 1 D6 D5 D4 1 0 1 X X X CMB CMB CMB [6] [5] [4] D3 1 X CMB [3] D2 1 X CMB [2] D1 1 X CMB [1] D0 1 X CMB [0] HEX 5Fh X 00 This command returns the minimum brightness value of CABC function. In principle the relationship is that 00h value means the lowest brightness and FFh value means the highest brightness. Description CMB[7:0] is CABC minimum brightness specified with “Write CABC minimum brightness (5Eh)” command. In principle relationship is that 00h value means the lowest brightness for CABC and FFh value means the highest brightness for CABC. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value CMB [7:0] Power On Sequence 8’h00h SW Reset No Change HW Reset 8’h00h The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 150 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.46. Read ID1 (DAh) DAh RDID1 (Read ID1) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 1 0 1 1 0 1 0 DAh 1stParameter 1 ↑ 1 XX X X X X X X X X 2ndParameter 1 ↑ 1 XX ID1 [7:0] X 00 This read byte identifies the LCD module’s manufacturer ID and it is specified by User The 1st parameter is dummy data. Description The 2nd parameter is LCD module’s manufacturer ID. X = Don’t care Restriction Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Value Default Value (Before MTP program) (After MTP program) Power On Sequence 8’h00h MTP value SW Reset 8’h00h MTP value HW Reset 8’h00h MTP value Status Default Legend RDID1(DAh) Command Host Parameter Driver Display Flow Chart 1st Parameter: Dummy Read 2nd Parameter: Send ID1[7:0] Action Mode Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 151 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.47. Read ID2 (DBh) DBh RDID2 (Read ID2) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 1 0 1 1 0 1 1 DBh 1st Parameter 1 ↑ 1 XX X X X X X X X X 2ndParameter 1 ↑ 1 XX ID2 [7:0] X 00 This read byte is used to track the LCD module/driver version. It is defined by display supplier (with User’s agreement) and changes each time a revision is made to the display, material or construction specifications. The 1st parameter is dummy data. Description The 2nd parameter is LCD module/driver version ID and the ID parameter range is from 80h to FFh. The ID2 can be programmed by MTP function. X = Don’t care Restriction Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value Default Value (Before MTP program) (After MTP program) Power On Sequence 8’h80h MTP value SW Reset 8’h80h MTP value HW Reset 8’h80h MTP value Legend RDID2(DBh) Command Host Parameter Driver Display Flow Chart 1st Parameter: Dummy Read 2nd Parameter: Send ID2[7:0] Action Mode Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 152 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.2.48. Read ID3 (DCh) DCh RDID3 (Read ID3) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 1 0 1 1 1 0 0 DCh 1stParameter 1 ↑ 1 XX X X X X X X X X 2ndParameter 1 ↑ 1 XX ID3 [7:0] X 00 This read byte identifies the LCD module/driver and It is specified by User. The 1st parameter is dummy data. Description The 2nd parameter is LCD module/driver ID. The ID3 can be programmed by MTP function. X = Don’t care Restriction Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value Default Value (Before MTP program) (After MTP program) Power On Sequence 8’h00h MTP value SW Reset 8’h00h MTP value HW Reset 8’h00h MTP value Legend RDID3(DCh) Command Host Parameter Driver Display Flow Chart 1st Parameter: Dummy Read 2nd Parameter: Send ID3[7:0] Action Mode Sequential transfer The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 153 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3. Description of Level 2 Command 8.3.1. RGB Interface Signal Control (B0h) B0h Command Parameter IFMODE (Interface Mode Control) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ XX 1 0 1 1 0 0 0 0 B0h RCM RCM [1] [0] 0 VSPL HSPL DPL EPL 40 1 1 ↑ XX ByPass_MODE Sets the operation status of the display interface. The setting becomes effective as soon as the command is received. EPL: DE polarity (“0”= High enable for RGB interface, “1”= Low enable for RGB interface) DPL: DOTCLK polarity set (“0”= data fetched at the rising time, “1”= data fetched at the falling time) HSPL: HSYNC polarity (“0”= Low level sync clock, “1”= High level sync clock) VSPL: VSYNC polarity (“0”= Low level sync clock, “1”= High level sync clock) RCM [1:0]: RGB interface selection (refer to the RGB interface section). Description ByPass_MODE: Select display data path whether Memory or Direct to Shift register when RGB Interface is used. Restriction ByPass_MODE Display Data Path 0 Direct to Shift Register (default) 1 Memory EXTC should be high to enable this command Status Normal Mode ON, Idle Mode OFF, Sleep OUT Normal Mode ON, Idle Mode ON, Sleep OUT Partial Mode ON, Idle Mode OFF, Sleep OUT Partial Mode ON, Idle Mode ON, Sleep OUT Sleep IN Register Availability Status Default Power ON Sequence SW Reset HW Reset ByPass_MODE 1’b0 1’b0 1’b0 Availability Yes Yes Yes Yes Yes Default Value RCM [1:0] VSPL HSPL 2’b10 1’b0 1’b0 2’b10 1’b0 1’b0 2’b10 1’b0 1’b0 DPL 1’b0 1’b0 1’b0 EPL 1’b1 1’b1 1’b1 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 154 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.2. Frame Rate Control (In Normal Mode/Full Colors) (B1h) B1h FRMCTR1 (Frame Rate Control (In Normal Mode / Full colors)) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 0 1 1 0 0 0 1 B1h 1st Parameter 1 1 ↑ XX 0 0 0 0 0 0 DIVA [1:0] 2nd Parameter 1 1 ↑ XX 0 0 0 00 RTNA [4:0] 1B Formula to calculate frame frequency: Frame Rate= fosc Clocks per line x Division ratio x (Lines + VBP + VFP) Sets the division ratio for internal clocks of Normal mode at MCU interface. fosc : internal oscillator frequency Clocks per line : RTNA setting Division ratio : DIVA setting Lines : total driving line number VBP : back porch line number VFP : front porch line number RTNA [4:0] Description Frame Rate (Hz) RTNA [4:0] Frame Rate (Hz) 1 0 0 0 0 119 1 1 0 0 0 79 1 0 0 0 1 112 1 1 0 0 1 76 1 0 0 1 0 106 1 1 0 1 0 73 1 0 0 1 1 100 1 1 0 1 1 70(default) 1 0 1 0 0 95 1 1 1 0 0 68 1 0 1 0 1 90 1 1 1 0 1 65 1 0 1 1 0 86 1 1 1 0 1 63 1 0 1 1 1 83 1 1 1 1 1 61 DIVA [1:0] : division ratio for internal clocks when Normal mode. DIVA [1:0] Division Ratio 0 0 fosc 0 1 fosc / 2 1 0 fosc / 4 1 1 fosc / 8 RTNA [4:0] : RTNA[4:0] is used to set 1H (line) period of Normal mode at MCU interface. Clock per RTNA [4:0] Clock per RTNA [4:0] Line Clock per RTNA [4:0] Line Line 0 0 0 0 0 Setting prohibited 0 1 0 1 1 Setting prohibited 1 0 1 1 0 22 clocks 0 0 0 0 1 Setting prohibited 0 1 1 0 0 Setting prohibited 1 0 1 1 1 23 clocks 0 0 0 1 0 Setting prohibited 0 1 1 0 1 Setting prohibited 1 1 0 0 0 24 clocks 0 0 0 1 1 Setting prohibited 0 1 1 1 0 Setting prohibited 1 1 0 0 1 25 clocks 0 0 1 0 0 Setting prohibited 0 1 1 1 1 Setting prohibited 1 1 0 1 0 26 clocks 0 0 1 0 1 Setting prohibited 1 0 0 0 0 16 clocks 1 1 0 1 1 27 clocks 0 0 1 1 0 Setting prohibited 1 0 0 0 1 17 clocks 1 1 1 0 0 28 clocks 0 0 1 1 1 Setting prohibited 1 0 0 1 0 18 clocks 1 1 1 0 1 29 clocks 0 1 0 0 0 Setting prohibited 1 0 0 1 1 19 clocks 1 1 1 1 0 30 clocks 0 1 0 0 1 Setting prohibited 1 0 1 0 0 20 clocks 1 1 1 1 1 31 clocks 0 1 0 1 0 Setting prohibited 1 0 1 0 1 21 clocks The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 155 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Restriction Register Availability EXTC should be high to enable this command Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Normal Mode ON, Idle Mode ON, Sleep OUT Yes Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Status Default ILI9341 Default Value DIVA [1:0] RTNA [4:0] Power ON Sequence 2’b00 5’h1Bh SW Reset 2’b00 5’h1Bh HW Reset 2’b00 5’h1Bh The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 156 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.3. Frame Rate Control (In Idle Mode/8 colors) (B2h) B2h FRMCTR2 (Frame Rate Control (In Idle Mode / 8l colors)) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 0 1 1 0 0 1 0 B2h 1st Parameter 1 1 ↑ XX 0 0 0 0 0 0 DIVB [1:0] 2ndParameter 1 1 ↑ XX 0 0 0 00 RTNB [4:0] 1B Formula to calculate frame frequency Frame Rate= fosc Clocks per line x Division ratio x (Lines + VBP + VFP) Sets the division ratio for internal clocks of Idle mode at MCU interface. fosc : internal oscillator frequency Clocks per line : RTNB setting Division ratio : DIVB setting Lines : total driving line number VBP : back porch line number VFP : front porch line number RTNB [4:0] Description Frame Rate (Hz) RTNB [4:0] Frame Rate (Hz) 1 0 0 0 0 119 1 1 0 0 0 79 1 0 0 0 1 112 1 1 0 0 1 76 1 0 0 1 0 106 1 1 0 1 0 73 1 0 0 1 1 100 1 1 0 1 1 70(default) 1 0 1 0 0 95 1 1 1 0 0 68 1 0 1 0 1 90 1 1 1 0 1 65 1 0 1 1 0 86 1 1 1 0 1 63 1 0 1 1 1 83 1 1 1 1 1 61 DIVB [1:0]: division ratio for internal clocks when Idle mode. DIVB [1:0] Division Ratio 0 0 fosc 0 1 fosc / 2 1 0 fosc / 4 1 1 fosc / 8 RTNB [4:0]: RTNB[4:0] is used to set 1H (line) period of Idle mode at MCU interface. Clock per RTNB [4:0] Clock per RTNB [4:0] Line Clock per RTNB [4:0] Line Line 0 0 0 0 0 Setting prohibited 0 1 0 1 1 Setting prohibited 1 0 1 1 0 22 clocks 0 0 0 0 1 Setting prohibited 0 1 1 0 0 Setting prohibited 1 0 1 1 1 23 clocks 0 0 0 1 0 Setting prohibited 0 1 1 0 1 Setting prohibited 1 1 0 0 0 24 clocks 0 0 0 1 1 Setting prohibited 0 1 1 1 0 Setting prohibited 1 1 0 0 1 25 clocks 0 0 1 0 0 Setting prohibited 0 1 1 1 1 Setting prohibited 1 1 0 1 0 26 clocks 0 0 1 0 1 Setting prohibited 1 0 0 0 0 16 clocks 1 1 0 1 1 27 clocks 0 0 1 1 0 Setting prohibited 1 0 0 0 1 17 clocks 1 1 1 0 0 28 clocks 0 0 1 1 1 Setting prohibited 1 0 0 1 0 18 clocks 1 1 1 0 1 29 clocks 0 1 0 0 0 Setting prohibited 1 0 0 1 1 19 clocks 1 1 1 1 0 30 clocks 0 1 0 0 1 Setting prohibited 1 0 1 0 0 20 clocks 1 1 1 1 1 31 clocks 0 1 0 1 0 Setting prohibited 1 0 1 0 1 21 clocks The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 157 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Restriction Register Availability EXTC should be high to enable this command Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Normal Mode ON, Idle Mode ON, Sleep OUT Yes Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Status Default ILI9341 Default Value DIVB [1:0] RTNB [4:0] Power ON Sequence 2’b00 5’h1Bh SW Reset 2’b00 5’h1Bh HW Reset 2’b00 5’h1Bh The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 158 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.4. Frame Rate control (In Partial Mode/Full Colors) (B3h) B3h FRMCTR3 (Frame Rate Control (In Partial Mode / Full colors)) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 0 1 1 0 0 1 1 B3h 1st Parameter 1 1 ↑ XX 0 0 0 0 0 0 DIVC [1:0] 2ndParameter 1 1 ↑ XX 0 0 0 00 RTNC [4:0] 1B Formula to calculate frame frequency: Frame Rate= fosc Clocks per line x Division ratio x (Lines + VBP + VFP) Sets the division ratio for internal clocks of Partial mode (Idle mode off) at MCU interface. fosc : internal oscillator frequency Clocks per line : RTNC setting Division ratio : DIVC setting Lines : total driving line number VBP : back porch line number VFP : front porch line number RTNC [4:0] Description Frame Rate (Hz) RTNC [4:0] Frame Rate (Hz) 1 0 0 0 0 119 1 1 0 0 0 79 1 0 0 0 1 112 1 1 0 0 1 76 1 0 0 1 0 106 1 1 0 1 0 73 1 0 0 1 1 100 1 1 0 1 1 70(default) 1 0 1 0 0 95 1 1 1 0 0 68 1 0 1 0 1 90 1 1 1 0 1 65 1 0 1 1 0 86 1 1 1 0 1 63 1 0 1 1 1 83 1 1 1 1 1 61 DIVC [1:0]: division ratio for internal clocks when Partial mode. DIVC [1:0] Division Ratio 0 0 fosc 0 1 fosc / 2 1 0 fosc / 4 1 1 fosc / 8 Note: 1clock unit=1.625u sec RTNC [4:0]: RTNC [4:0] is used to set 1H (line) period of Partial mode at MCU interface. Clock per RTNC [4:0] Clock per RTNC [4:0] Line Clock per RTNC [4:0] Line Line 0 0 0 0 0 Setting prohibited 0 1 0 1 1 Setting prohibited 1 0 1 1 0 22 clocks 0 0 0 0 1 Setting prohibited 0 1 1 0 0 Setting prohibited 1 0 1 1 1 23 clocks 0 0 0 1 0 Setting prohibited 0 1 1 0 1 Setting prohibited 1 1 0 0 0 24 clocks 0 0 0 1 1 Setting prohibited 0 1 1 1 0 Setting prohibited 1 1 0 0 1 25 clocks 0 0 1 0 0 Setting prohibited 0 1 1 1 1 Setting prohibited 1 1 0 1 0 26 clocks 0 0 1 0 1 Setting prohibited 1 0 0 0 0 16 clocks 1 1 0 1 1 27 clocks 0 0 1 1 0 Setting prohibited 1 0 0 0 1 17 clocks 1 1 1 0 0 28 clocks 0 0 1 1 1 Setting prohibited 1 0 0 1 0 18 clocks 1 1 1 0 1 29 clocks 0 1 0 0 0 Setting prohibited 1 0 0 1 1 19 clocks 1 1 1 1 0 30 clocks 0 1 0 0 1 Setting prohibited 1 0 1 0 0 20 clocks 1 1 1 1 1 31 clocks 0 1 0 1 0 Setting prohibited 1 0 1 0 1 21 clocks The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 159 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Restriction Register Availability EXTC should be high to enable this command Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Normal Mode ON, Idle Mode ON, Sleep OUT Yes Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Status Default ILI9341 Default Value DIVC [1:0] RTNC [4:0] Power ON Sequence 2’b00 5’h1Bh SW Reset 2’b00 5’h1Bh HW Reset 2’b00 5’h1Bh The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 160 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.5. Display Inversion Control (B4h) B4h INVTR (Display Inversion Control) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 0 1 1 0 1 0 0 B4h 1st Parameter 1 1 ↑ XX 0 0 0 0 0 NLA NLB NLC 02 Display inversion mode set NLA: Inversion setting in full colors normal mode (Normal mode on) NLB: Inversion setting in Idle mode (Idle mode on) NLC: Inversion setting in full colors partial mode (Partial mode on / Idle mode off) Description Restriction Register Availability NLA / NLB / NLC Inversion 0 Line inversion 1 Frame inversion EXTC should be high to enable this command Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Normal Mode ON, Idle Mode ON, Sleep OUT Yes Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Status Default Default Value NLA NLB NLC Power ON Sequence 1’b0 1’b1 1’b0 SW Reset 1’b0 1’b1 1’b0 H/W Reset 1’b0 1’b1 1’b0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 161 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.6. Blanking Porch Control (B5h) B5h PRCTR (Blanking Porch) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 0 1 1 0 1 0 1 B5h 1stParameter 1 1 ↑ XX 0 VFP [6:0] 02 2ndParameter 1 1 ↑ XX 0 VBP [6:0] 02 3rdParameter 1 1 ↑ XX 0 0 0 HFP [4:0] 0A 4thParameter 1 1 ↑ XX 0 0 0 HBP [4:0] 14 VFP [6:0] / VBP [6:0]: The VFP [6:0] and VBP [6:0] bits specify the line number of vertical front and back porch period respectively. VFP [6:0] Number of HSYNC of front/back porch VBP [6:0] Description VFP [6:0] VBP [6:0] Number of HSYNC of front/back porch 0000000 Setting inhibited 1000000 0000001 Setting inhibited 1000001 65 0000010 2 1000010 66 0000011 3 1000011 67 0000100 4 1000100 68 0000101 5 1000101 69 0000110 6 1000110 70 0000111 7 1000111 71 0001000 8 1001000 72 0001001 9 1001001 73 0001010 10 1001010 74 0001011 11 1001011 75 0001100 12 1001100 76 0001101 13 1001101 77 : : : : : : : : 0111101 61 1111101 125 0111110 62 1111110 126 0111111 63 1111111 127 Note: VFP + VBP ≦ 254 HSYNC signals 64 HFP [4:0] / HBP [4:0]: The HFP [4:0] and HBP [4:0] bits specify the line number of horizontal front and back porch period respectively. HFP [4:0] HBP [4:0] Number of DOTCLK of the front/back porch HFP [4:0] HBP [4:0] Number of DOTCLK of front/back porch 00000 Setting prohibited 10000 16 00001 Setting prohibited 10001 17 00010 2 10010 18 00011 3 10011 19 00100 4 10100 20 00101 5 10101 21 00110 6 10110 22 00111 7 10111 23 01000 8 11000 24 01001 9 11001 25 01010 10 11010 26 01011 11 11011 27 01100 12 11100 28 01101 13 11101 29 01110 14 11110 30 01111 15 11111 31 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 162 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Restriction Register Availability EXTC should be high to enable this command Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Normal Mode ON, Idle Mode ON, Sleep OUT Yes Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Status Default ILI9341 Default Value VFP [6:0] VBP [6:0] HFP [4:0] HBP [4:0] Power ON Sequence 7’h02h 7’h02h 5’h0Ah 5’h14h SW Reset 7’h02h 7’h02h 5’h0Ah 5’h14h HW Reset 7’h02h 7’h02h 5’h0Ah 5’h14h The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 163 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.7. Display Function Control (B6h) B6h DISCTRL (Display Function Control) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 0 1 1 0 1 1 0 B6h 1st Parameter 1 1 ↑ XX 0 0 0 0 PTG [1:0] 2nd Parameter 1 1 ↑ XX REV GS SS SM 3 Parameter 1 1 ↑ XX 0 0 NL [5:0] 27 4th Parameter 1 1 ↑ XX 0 0 PCDIV [5:0] XX rd PT [1:0] ISC [3:0] 0A 82 PTG [1:0]: Set the scan mode in non-display area. PTG1 PTG0 Gate outputs in non-display area Source outputs in non-display area VCOM output 0 0 0 Normal scan Set with the PT [2:0] bits VCOMH/VCOML 1 Setting prohibited --- --- 1 0 Interval scan Set with the PT [2:0] bits 1 1 Setting prohibited --- --- PT [1:0]: Determine source/VCOM output in a non-display area in the partial display mode. PT [1:0] Source output on non-display area VCOM output on non-display area Positive polarity Negative polarity Positive polarity Negative polarity V63 V0 VCOML VCOMH 0 0 0 1 V0 V63 VCOML VCOMH 1 0 AGND AGND AGND AGND 1 1 Hi-Z Hi-Z AGND AGND SS: Select the shift direction of outputs from the source driver. SS Source Output Scan Direction 0 S1 S720 1 S720 S1 In addition to the shift direction, the settings for both SS and BGR bits are required to change the assignment of R, G, Description and B dots to the source driver pins. To assign R, G, B dots to the source driver pins from S1 to S720, set SS = 0. To assign R, G, B dots to the source driver pins from S720 to S1, set SS = 1. REV: Select whether the liquid crystal type is normally white type or normally black type. REV Liquid crystal type 0 Normally black 1 Normally white ISC [3:0]: Specify the scan cycle interval of gate driver in non-display area when PTG [1:0] =”10” to select interval scan. Then scan cycle is set as odd number from 0~29 frame periods. The polarity is inverted every scan cycle. ISC [3:0] Scan Cycle fFLM = 60Hz 0000 1 frame 17ms 0001 3 frames 51ms 0010 5 frames 85ms 0011 7 frames 119ms 0100 9 frames 153ms 0101 11 frames 187ms 0110 13 frames 221ms 0111 15 frames 255ms The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 164 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 1000 17 frames 289ms 1001 19 frames 323ms 1010 21 frames 357ms 1011 23 frames 391ms 1100 25 frames 425ms 1101 27 frames 459ms 1110 29 frames 493ms 1111 31 frames 527ms ILI9341 GS: Sets the direction of scan by the gate driver in the range determined by SCN [4:0] and NL [4:0]. The scan direction determined by GS = 0 can be reversed by setting GS = 1. GS Gate Output Scan Direction 0 G1 G320 1 G320 G1 SM: Sets the gate driver pin arrangement in combination with the GS bit to select the optimal scan mode for the module. SM GS 0 0 Scan Direction Gate Output Sequence G1G2G3G4 ……………… G1 to G319 G2 to G320 ….G317G318G319G320 G320G319->G318G317…… G1 to G319 1 G2 to G320 0 …. G4G3G2G1 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 165 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color G2 to G320 1 0 ILI9341 G1G3………...G317G319 G2G4…………G318G320 G1 to G319 G2 to G320 1 1 G320G318………...G4G2 G319G317…………G3G1 G1 to G319 NL [5:0]: Sets the number of lines to drive the LCD at an interval of 8 lines. The GRAM address mapping is not affected by the number of lines set by NL [5:0]. The number of lines must be the same or more than the number of lines necessary for the size of the liquid crystal panel. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 NL [5:0] 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 LCD Drive Line 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Setting prohibited 16 lines 24 lines 32 lines 40 lines 48 lines 56 lines 64 lines 72 lines 80 lines 88 lines 96 lines 104 lines 112 lines 120 lines 128 lines 136 lines 144 lines 152 lines 160 lines 168 lines 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 NL [5:0] 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 Others 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 LCD Driver Line 176 lines 184 lines 192 lines 200 lines 208 lines 216 lines 224 lines 232 lines 240 lines 248 lines 256 lines 264 lines 272 lines 280 lines 288 lines 296 lines 304 lines 312 lines 320 lines Setting inhibited PCDIV [5:0]: The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 166 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color external fosc= Restriction DOTCLK 2 × (PCDIV + 1) EXTC should be high to enable this command Register Availability Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Normal Mode ON, Idle Mode ON, Sleep OUT Yes Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Status Default ILI9341 Default Value PTG [1:0] PT [1:0] REV GS SS SM ISC [3:0] NL [5:0] Power ON Sequence 2’b10 2’b10 1’b1 1’b0 1’b0 1’b0 4’b0010 6’h27h SW Reset 2’b10 2’b10 1’b1 1’b0 1’b0 1’b0 4’b0010 6’h27h HW Reset 2’b10 2’b10 1’b1 1’b0 1’b0 1’b0 4’b0010 6’h27h The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 167 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.8. Entry Mode Set (B7h) B7h ETMOD (Entry Mode Set) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 0 1 1 0 1 1 1 B7h Parameter 1 1 ↑ XX 0 0 0 0 0 GON DTE GAS 06 GAS: Low voltage detection control. GAS Description Restriction Register Availability Low voltage detection 0 Enable 1 Disable GON/DTE: Set the output level of gate driver G1 ~ G320 as follows GON DTE G1~G320 Gate Output 0 0 VGH 0 1 VGH 1 0 VGL 1 1 Normal display EXTC should be high to enable this command Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Normal Mode ON, Idle Mode ON, Sleep OUT Yes Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Status Default Default Value GON DTE GAS Power ON Sequence 1’b1 1’b1 1’b0 SW Reset 1’b1 1’b1 1’b0 HW Reset 1’b1 1’b1 1’b0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 168 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.9. Backlight Control 1 (B8h) B8h Command Parameter D/CX 0 RDX 1 1 WRX ↑ ↑ D17-8 XX XX D7 1 0 Backlight Control 1 D6 D5 D4 D3 0 1 1 1 0 0 0 TH_UI [3] D2 0 TH_UI [2] D1 0 TH_UI [1] D0 0 TH_UI [0] HEX B8h 0C TH_UI [3:0]: These bits are used to set the percentage of grayscale data accumulate histogram value in the user interface (UI) mode. This ratio of maximum number of pixels that makes display image white (=data “255”) to the total of pixels by image processing. Description TH_UI [3:0] Description TH_UI [3:0] Description 4’0h 99% 4’8h 84% 4’1h 98% 4’9h 82% 4’2h 96% 4’Ah 80% 4’3h 94% 4’Bh 78% 4’4h 92% 4’Ch 76% 4’5h 90% 4’Dh 74% 4’6h 88% 4’Eh 72% 4’7h 86% 4’Fh 70% Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value TH_UI [3:0] Power On Sequence 4’b0110 SW Reset No change HW Reset 4’b0110 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 169 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.10. Backlight Control 2 (B9h) B9h Command D/CX 0 RDX 1 WRX ↑ D17-8 XX Parameter 1 1 ↑ XX D7 1 TH_MV [3] Backlight Control 2 D6 D5 D4 0 1 1 TH_MV TH_MV TH_MV [2] [1] [0] D3 1 TH_ST [3] D2 0 TH_ST [2] D1 0 TH_ST [1] D0 1 TH_ST [0] HEX B9h CC TH_ST [3:0]: These bits are used to set the percentage of grayscale data accumulate histogram value in the still picture mode. This ratio of maximum number of pixels that makes display image white (=data “255”) to the total of pixels by image processing. TH_ST [3:0] Description TH_ST [3:0] Description 4’0h 99% 4’8h 84% 4’1h 98% 4’9h 82% 4’2h 96% 4’Ah 80% 4’3h 94% 4’Bh 78% 4’4h 92% 4’Ch 76% 4’5h 90% 4’Dh 74% 4’6h 88% 4’Eh 72% 4’7h 86% 4’Fh 70% TH_MV [3:0]: These bits are used to set the percentage of grayscale data accumulate histogram value in the moving image mode. This ratio of maximum number of pixels that makes display image white (=data “255”) to the total of pixels by image processing. TH_MV [3:0] Description TH_MV [3:0] Description 4’0h 99% 4’8h 84% 4’1h 98% 4’9h 82% 4’2h 96% 4’Ah 80% 4’3h 94% 4’Bh 78% 4’4h 92% 4’Ch 76% 4’5h 90% 4’Dh 74% 4’6h 88% 4’Eh 72% 4’7h 86% 4’Fh 70% Description Histogram 100% TH_MV[3:0] TH_ST[3:0] TH_UI[3:0] Gray Scales Dth 255 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 170 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Value Status Default ILI9341 TH_MV [3:0] TH_ST [3:0] Power On Sequence 4’b1100 4’b1100 SW Reset No change No change HW Reset 4’b1100 4’b1100 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 171 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.11. Backlight Control 3 (BAh) BAh Command D/CX 0 RDX 1 WRX ↑ D17-8 XX D7 1 D6 0 Parameter 1 1 ↑ XX 0 0 Backlight Control 3 D5 D4 D3 1 1 1 DTH_UI 0 0 [3] D2 0 DTH_UI [2] D1 1 DTH_UI [1] D0 0 DTH_UI [0] HEX BAh 04 DTH_UI [3:0]: This parameter is used set the minimum limitation of grayscale threshold value in User Icon (UI) image mode. This register setting will limit the minimum Dth value to prevent the display image from being too white and the display quality is not acceptable. Description DTH_UI [3:0] Description DTH_UI [3:0] Description 4’0h 252 4’8h 220 4’1h 248 4’9h 216 4’2h 244 4’Ah 212 4’3h 240 4’Bh 208 4’4h 236 4’Ch 204 4’5h 232 4’Dh 200 4’6h 228 4’Eh 196 4’7h 224 4’Fh 192 Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value DTH_UI [3:0] Power On Sequence 4’b0100 SW Reset No change HW Reset 4’b0100 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 172 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.12. Backlight Control 4 (BBh) BBh Command D/CX 0 RDX 1 WRX ↑ D17-8 XX Parameter 1 1 ↑ XX Backlight Control 4 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 1 0 1 1 DTH_MV DTH_MV DTH_MV DTH_MV DTH_ST DTH_ST DTH_ST DTH_ST [3] [2] [1] [0] [3] [2] [1] [0] HEX BBh 65 DTH_ST [3:0]/DTH_MV [3:0]: This parameter is used set the minimum limitation of grayscale threshold value. This register setting will limit the minimum Dth value to prevent the display image from being too white and the display quality is not acceptable. Description DTH_ST [3:0] Description DTH_ST [3:0] Description 4’0h 224 4’8h 192 4’1h 220 4’9h 188 4’2h 216 4’Ah 184 4’3h 212 4’Bh 180 4’4h 208 4’Ch 176 4’5h 204 4’Dh 172 4’6h 200 4’Eh 168 4’7h 196 4’Fh 164 DTH_MV [3:0] Description DTH_MV [3:0] Description 4’0h 224 4’8h 192 4’1h 220 4’9h 188 4’2h 216 4’Ah 184 4’3h 212 4’Bh 180 4’4h 208 4’Ch 176 4’5h 204 4’Dh 172 4’6h 200 4’Eh 168 4’7h 196 4’Fh 164 Transmittance Gray Scales DTH 255 Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 173 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Default Value Status Default ILI9341 DTH_MV [3:0] DTH_ST [3:0] Power On Sequence 4’b0110 4’b0101 SW Reset No change No change HW Reset 4’b0110 4’b0101 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 174 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.13. Backlight Control 5 (BCh) BCh Command Parameter D/CX 0 1 RDX 1 1 WRX ↑ ↑ D17-8 XX XX Backlight Control 5 D7 D6 D5 D4 1 0 1 1 DIM2 [3] DIM2 [2] DIM2 [1] DIM2 [0] D3 1 0 D2 D1 1 0 DIM1 [2] DIM1 [1] D0 0 DIM1 [0] HEX BCh 44 DIM1 [2:0]: This parameter is used to set the transition time of brightness level to avoid the sharp brightness transition on vision. DIM1 [2:0] Description 1 frame 3’0h 3’1h 1 frame 3’2h 2 frames 3’3h 4 frames 3’4h 8 frames 3’5h 16 frames 3’6h 32 frames 3’7h 64 frames Brightness =B Description DIM2[2:0] Brightness =C Brightness =A DIM1[2:0] DIM1[2:0] Transition time Transition time Time DIM2 [3:0]: This parameter is used to set the threshold of brightness change. When the brightness transition difference is smaller than DIM2 [3:0], the brightness transition will be ignored. For example: If | brightness B – brightness A| < DIM2 [2:0], the brightness transition will be ignored and keep the brightness A. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Value Status Default DIM2 [3:0] DIM1 [2:0] Power On Sequence 4’b0100 4’b0100 SW Reset No change No change HW Reset 4’b0100 4’b0100 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 175 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.14. Backlight Control 7 (BEh) BEh Command D/CX 0 RDX 1 WRX ↑ D17-8 XX Parameter 1 1 ↑ XX Backlight Control 7 D6 D5 D4 0 1 1 PWM_ PWM_ PWM_ DIV[6] DIV[5] DIV[4] D7 1 PWM_ DIV[7] D3 1 PWM_ DIV[3] D2 1 PWM_ DIV[2] D1 1 PWM_ DIV[1] D0 0 PWM_ DIV[0] HEX BEh 0F PWM_DIV [7:0]: PWM_OUT output frequency control. This command is used to adjust the PWM waveform frequency of PWM_OUT. The PWM frequency can be calculated by using the following equation. fPWM_OUT = 16MHz (PWM_DIV[7 : 0] + 1) × 255 PWM_DIV [7:0] 8’h0 fPWM_OUT 62.74 KHz 8’h1 31.38 KHz 8’h2 20.915KHz 8’h3 15.686KHz 8’h4 12.549 KHz … 8’hFB … 249Hz 8’hFC 248Hz 8’hFD 247Hz Description 8’hFE 246Hz 8’hFF 245Hz fPWM_OUT PWM_OUT tON tOFF Note: The output frequency tolerance of internal frequency divider in CABC is ±10% Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Default Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Value Power On Sequence PWM_DIV [7:0]=0Fh SW Reset No change HW Reset PWM_DIV [7:0]=0Fh The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 176 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.15. Backlight Control 8 (BFh) BFh Command Parameter D/CX RDX 0 1 1 1 WRX ↑ ↑ D17-8 XX XX D7 1 0 D6 0 0 Backlight Control 2 D5 D4 D3 1 1 1 0 0 0 D2 D1 D0 HEX 1 1 1 BFh LEDONR LEDONPOL LEDPWMPOL 00 LEDPWMPOL: The bit is used to define polarity of LEDPWM signal. BL LEDPWMPOL LEDPWM pin 0 0 0 0 1 1 1 0 Original polarity of PWM signal 1 1 Inversed polarity of PWM signal LEDONPOL: This bit is used to control LEDON pin. Description BL LEDONPOL LEDON pin 0 0 0 0 1 1 1 0 LEDONR 1 1 Inversed LEDONR LEDONR: This bit is used to control LEDON pin. LEDONR Description 0 Low 1 High Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Value Status Default LEDONR LEDONPOL Power On Sequence 1’b0 1’b0 LEDPWMPOL 1’b0 SW Reset No change No change No change HW Reset 1’b0 1’b0 1’b0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 177 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.16. Power Control 1 (C0h) C0h PWCTRL 1 (Power Control 1) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 1 0 0 0 0 0 0 C0h 1stParameter 1 1 ↑ XX 0 0 VRH [5:0] 21 VRH [5:0]: Set the GVDD level, which is a reference level for the VCOM level and the grayscale voltage level. Description 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VRH [5:0] 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 GVDD Setting prohibited Setting prohibited Setting prohibited 3.00 V 3.05 V 3.10 V 3.15 V 3.20 V 3.25 V 3.30 V 3.35 V 3.40 V 3.45 V 3.50 V 3.55 V 3.60 V 3.65 V 3.70 V 3.75 V 3.80 V 3.85 V 3.90 V 3.95 V 4.00 V 4.05 V 4.10 V 4.15 V 4.20 V 4.25 V 4.30 V 4.35 V 4.40 V 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Note1: Make sure that VC and VRH setting restriction: GVDD Restriction Register Availability 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VRH [5:0] 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 ≦ (DDVDH - 0.2) V. 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 GVDD 4.45 V 4.50 V 4.55 V 4.60 V 4.65 V 4.70 V 4.75 V 4.80 V 4.85 V 4.90 V 4.95 V 5.00 V 5.05 V 5.10 V 5.15 V 5.20 V 5.25 V 5.30 V 5.35 V 5.40 V 5.45 V 5.50 V 5.55 V 5.60 V 5.65 V 5.70 V 5.75 V 5.80 V 5.85 V 5.90 V 5.95 V 6.00 V EXTC should be high to enable this command Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Normal Mode ON, Idle Mode ON, Sleep OUT Yes Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Status Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Default Value VRH [5:0] Power ON Sequence 6’h21h SW Reset 6’h21h HW Reset 6’h21h The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 178 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.17. Power Control 2 (C1h) C1h PWCTRL 2 (Power Control 2) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 1 0 0 0 0 0 1 C1h Parameter 1 1 ↑ XX 0 0 0 0 0 BT [2:0] 10 BT [2:0]: Sets the factor used in the step-up circuits. Select the optimal step-up factor for the operating voltage. To reduce power consumption, set a smaller factor. BT [2:0] Description Restriction Register Availability DDVDH 0 0 0 0 0 1 0 1 0 0 1 1 VGL VCI x 7 VCI x 2 VCI x 6 -VCI x 4 -VCI x 3 -VCI x 4 -VCI x 3 ≦ 5.8 V. 2: Make sure that VGH and VGL setting restriction: VGH -VGL≦ 28 V. Note1: Make sure that DDVDH setting restriction: DDVDH EXTC should be high to enable this command Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Normal Mode ON, Idle Mode ON, Sleep OUT Yes Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Status Default VGH Default Value BT [2:0] Power ON Sequence 3’b000 SW Reset 3’b000 HW Reset 3’b000 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 179 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.18. VCOM Control 1(C5h) C5h VMCTRL1 (VCOM Control 1) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 1 0 0 0 1 0 1 C5h 1st Parameter 1 1 ↑ XX 0 VMH [6:0] 31 2ndParameter 1 1 ↑ XX 0 VML [6:0] 3C VMH [6:0] : Set the VCOMH voltage. Description VMH [6:0] 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 VCOMH(V) 2.700 2.725 2.750 2.775 2.800 2.825 2.850 2.875 2.900 2.925 2.950 2.975 3.000 3.025 3.050 3.075 3.100 3.125 3.150 3.175 3.200 3.225 3.250 3.275 3.300 3.325 3.350 3.375 3.400 3.425 3.450 3.475 VMH [6:0] 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 VCOMH(V) 3.500 3.525 3.550 3.575 3.600 3.625 3.650 3.675 3.700 3.725 3.750 3.775 3.800 3.825 3.850 3.875 3.900 3.925 3.950 3.975 4.000 4.025 4.050 4.075 4.100 4.125 4.150 4.175 4.200 4.225 4.250 4.275 VMH [6:0] 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001 1010010 1010011 1010100 1010101 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 VCOMH(V) 4.300 4.325 4.350 4.375 4.400 4.425 4.450 4.475 4.500 4.525 4.550 4.575 4.600 4.625 4.650 4.675 4.700 4.725 4.750 4.775 4.800 4.825 4.850 4.875 4.900 4.925 4.950 4.975 5.000 5.025 5.050 5.075 VCOML(V) -1.700 -1.675 -1.650 -1.625 -1.600 -1.575 -1.550 -1.525 -1.500 -1.475 -1.450 -1.425 -1.400 -1.375 -1.350 -1.325 -1.300 -1.275 -1.250 -1.225 VML [6:0] 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001 1010010 1010011 VCOML(V) -0.900 -0.875 -0.850 -0.825 -0.800 -0.775 -0.750 -0.725 -0.700 -0.675 -0.650 -0.625 -0.600 -0.575 -0.550 -0.525 -0.500 -0.475 -0.450 -0.425 VMH [6:0] 1100000 1100001 1100010 1100011 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 1101100 1101101 1101110 1101111 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 1111111 VCOMH(V) 5.100 5.125 5.150 5.175 5.200 5.225 5.250 5.275 5.300 5.325 5.350 5.375 5.400 5.425 5.450 5.475 5.500 5.525 5.550 5.575 5.600 5.625 5.650 5.675 5.700 5.725 5.750 5.775 5.800 5.825 5.850 5.875 VML [6:0] : Set the VCOML voltage VML [6:0] 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 VCOML(V) -2.500 -2.475 -2.450 -2.425 -2.400 -2.375 -2.350 -2.325 -2.300 -2.275 -2.250 -2.225 -2.200 -2.175 -2.150 -2.125 -2.100 -2.075 -2.050 -2.025 VML [6:0] 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 VML [6:0] 1100000 1100001 1100010 1100011 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 1101100 1101101 1101110 1101111 1110000 1110001 1110010 1110011 VCOML(V) -0.100 -0.075 -0.050 -0.025 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 180 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 Restriction Register Availability -2.000 -1.975 -1.950 -1.925 -1.900 -1.875 -1.850 -1.825 -1.800 -1.775 -1.750 -1.725 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 -1.200 -1.175 -1.150 -1.125 -1.100 -1.075 -1.050 -1.025 -1.000 -0.975 -0.950 -0.925 -0.400 -0.375 -0.350 -0.325 -0.300 -0.275 -0.250 -0.225 -0.200 -0.175 -0.150 -0.125 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 1111111 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved EXTC should be high to enable this command Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Normal Mode ON, Idle Mode ON, Sleep OUT Yes Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Status Default 1010100 1010101 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 ILI9341 Power ON Sequence Default Value VMH [6:0] VML [6:0] 7’h31 7’h3C SW Reset 7’h31 7’h3C HW Rest 7’h31 7’h3C The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 181 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.19. VCOM Control 2(C7h) C7h VMCTRL1 (VCOM Control 1) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 1 0 0 0 1 1 1 C7h Parameter 1 1 ↑ XX nVM VMF [6:0] C0 nVM: nVM equals to “0” after power on reset and VCOM offset equals to program MTP value. When nVM set to “1”, setting of VMF [6:0] becomes valid and VCOMH/VCOML can be adjusted. VMF [6:0]: Set the VCOM offset voltage. Description VMF[6:0] 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 VCOMH VMH VMH – 63 VMH – 62 VMH – 61 VMH – 60 VMH – 58 VMH – 58 VMH – 57 VMH – 56 VMH – 55 VMH – 54 VMH – 53 VMH – 52 VMH – 51 VMH – 50 VMH – 49 VMH – 48 VMH – 47 VMH – 46 VMH – 45 VMH – 44 VMH – 43 VMH – 42 VMH – 41 VMH – 40 VMH – 39 VMH – 38 VMH – 37 VMH – 36 VMH – 35 VMH – 34 VMH – 33 VMH – 32 VMH – 31 VMH – 30 VMH – 29 VMH – 28 VMH – 27 VMH – 26 VMH – 25 VMH – 24 VMH – 23 VMH – 22 VMH – 21 VMH – 20 VMH – 19 VMH – 18 VMH – 17 VMH – 16 VMH – 15 VMH – 14 VMH – 13 VMH – 12 VCOML VML VML – 63 VML – 62 VML – 61 VML – 60 VML – 58 VML – 58 VML – 57 VML – 56 VML – 55 VML – 54 VML – 53 VML – 52 VML -51 VML – 50 VML – 49 VML – 48 VML – 47 VML – 46 VML – 45 VML – 44 VML – 43 VML – 42 VML – 41 VML – 40 VML – 39 VML – 38 VML – 37 VML – 36 VML – 35 VML – 34 VML – 33 VML – 32 VML – 31 VML – 30 VML – 29 VML – 28 VML – 27 VML – 26 VML – 25 VML – 24 VML – 23 VML – 22 VML – 21 VML – 20 VML – 19 VML – 18 VML – 17 VML – 16 VML – 15 VML – 14 VML – 13 VML – 12 VMF[6:0] 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001 1010010 1010011 1010100 1010101 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 1100000 1100001 1100010 1100011 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 1101100 1101101 1101110 1101111 1110000 1110001 1110010 1110011 1110100 VCOMH VMH VMH + 1 VMH + 2 VMH + 3 VMH + 4 VMH + 5 VMH + 6 VMH + 7 VMH + 8 VMH + 9 VMH + 10 VMH + 11 VMH + 12 VMH + 13 VMH + 14 VMH + 15 VMH + 16 VMH + 17 VMH + 18 VMH + 19 VMH + 20 VMH + 21 VMH + 22 VMH + 23 VMH + 24 VMH + 25 VMH + 26 VMH + 27 VMH + 28 VMH + 29 VMH + 30 VMH + 31 VMH + 32 VMH + 33 VMH + 34 VMH + 35 VMH + 36 VMH + 37 VMH + 38 VMH + 39 VMH + 40 VMH + 41 VMH + 42 VMH + 43 VMH + 44 VMH + 45 VMH + 46 VMH + 47 VMH + 48 VMH + 49 VMH + 50 VMH + 51 VMH + 52 VCOML VML VML + 1 VML + 2 VML + 3 VML + 4 VML + 5 VML + 6 VML + 7 VML + 8 VML + 9 VML + 10 VML + 11 VML + 12 VML + 13 VML + 14 VML + 15 VML + 16 VML + 17 VML + 18 VML + 19 VML + 20 VML + 21 VML + 22 VML + 23 VML + 24 VML + 25 VML + 26 VML + 27 VML + 28 VML + 29 VML + 30 VML + 31 VML + 32 VML + 33 VML + 34 VML + 35 VML + 36 VML + 37 VML + 38 VML + 39 VML + 40 VML + 41 VML + 42 VML + 43 VML + 44 VML + 45 VML + 46 VML + 47 VML + 48 VML + 49 VML + 50 VML + 51 VML + 52 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 182 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 Restriction VMH – 11 VMH – 10 VMH – 9 VMH – 8 VMH – 7 VMH – 6 VMH – 5 VMH – 4 VMH – 3 VMH – 2 VMH – 1 VML – 11 VML – 10 VML – 9 VML – 8 VML – 7 VML – 6 VML – 5 VML – 4 VML – 3 VML – 2 VML – 1 1110101 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 1111111 VMH + 53 VMH + 54 VMH + 55 VMH + 56 VMH + 57 VMH + 58 VMH + 59 VMH + 60 VMH + 61 VMH + 62 VMH + 63 ILI9341 VML + 53 VML + 54 VML + 55 VML + 56 VML + 57 VML + 58 VML + 59 VML + 60 VML + 61 VML + 62 VML + 63 EXTC should be high to enable this command Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Register Normal Mode ON, Idle Mode ON, Sleep OUT Yes Availability Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Status Default Default Value nVM VMF [6:0] Power ON Sequence 1’b1 7’h40h SW Reset 1’b1 7’h40h HW Reset 1’b1 7’h40h The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 183 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.20. NV Memory Write (D0h) D0h NVMWR (NV Memory Write) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 1 0 1 0 0 0 0 D0h 1st Parameter 1 1 ↑ XX 0 0 0 0 0 2ndParameter 1 1 ↑ XX PGM_ADR [2:0] PGM_DATA [7:0] 00 XX This command is used to program the NV memory data. After a successful MTP operation, the information of PGM_DATA [7:0] will programmed to NV memory. PGM_ADR [2:0]: The select bits of ID1, ID2, ID3 and VMF [6:0] programming. PGM_ADR [2:0] Description Programmed NV Memory Selection 0 0 0 ID1 programming 0 0 1 ID2 programming 0 1 0 ID3 programming 1 0 0 VMF [6:0] programming Others Reserved PGM_DATA [7:0]: The programmed data. Restriction Register Availability EXTC should be high to enable this command Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Normal Mode ON, Idle Mode ON, Sleep OUT Yes Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Status Default Power ON Sequence Default Value PGM_ADR [2:0] PGM_DATA [7:0] 3’b000 MTP value SW Reset 3’b000 MTP value HW Reset 3’b000 MTP value The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 184 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.21. NV Memory Protection Key (D1h) D1h NVMPKEY (NV Memory Protection Key) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 1 0 1 0 0 0 1 D1h 1stParameter 1 1 ↑ XX KEY [23:16] 55h 2ndParameter 1 1 ↑ XX KEY [15:8] AAh 1 1 ↑ XX KEY [7:0] 66h 3rdParameter KEY [23:0]: NV memory programming protection key. When writing MTP data to D1h, this register must be set to Description 0x55AA66h to enable MTP programming. If D1h register is not written with 0x55AA66h, then NV memory programming will be aborted. Restriction Register Availability Default EXTC should be high to enable this command Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Normal Mode ON, Idle Mode ON, Sleep OUT Yes Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Status Default Value Power ON Sequence KEY [23:0]=55AA66h SW Reset KEY [23:0]=55AA66h HW Reset KEY [23:0]=55AA66h The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 185 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.22. NV Memory Status Read (D2h) D2h RDNVM (NV Memory Status Read) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 1 0 1 0 0 1 0 D2h 1st Parameter 1 ↑ 1 XX X X X X X X X X 2ndParameter 1 ↑ 1 XX 0 ID2_CNT [2:0] 0 ID1_CNT [2:0] XX 3rdParameter 1 ↑ 1 XX BUSY VMF_CNT [2:0] 0 ID3_CNT [2:0] XX X ID1_CNT [2:0] / ID2_CNT [2:0] / ID3_CNT [2:0] / VMF_CNT [2:0]: NV memory program record. The bits will increase “+1” automatically after writing the PGM_DATA [7:0] to NV memory. ID1_CNT [2:0] / ID2_CNT [2:0] Description ID3_CNT [2:0] / VMF_CNT [2:0] Status Description Availability 0 0 0 No Programmed 0 0 1 Programmed 1 time 0 1 1 Programmed 2 times 1 1 1 Programmed 3 times BUSY: The status bit of NV memory programming. BUSY Restriction Register Availability Idle 1 Busy EXTC should be high to enable this command Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Normal Mode ON, Idle Mode ON, Sleep OUT Yes Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Status Default The Status of NV Memory 0 Default Value ID3_CNT ID2_CNT ID1_CNT VMF_CNT BUSY Power ON Sequence X X X X X SW Reset X X X X X HW Reset X X X X X The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 186 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.23. Read ID4 (D3h) D3h RDID4 (Read ID4) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 1 0 1 0 0 1 1 D3h 1st Parameter 1 ↑ 1 XX X X X X X X X X X 2ndParameter 1 ↑ 1 XX 0 0 0 0 0 0 0 0 00h 3rdParameter 1 ↑ 1 XX 1 0 0 1 0 0 1 1 93h 4th Parameter 1 ↑ 1 XX 0 1 0 0 0 0 0 1 41h Read IC device code. The 1st parameter is dummy read period. Description The 2nd parameter means the IC version. The 3rd and 4th parameter mean the IC model name. Restriction EXTC should be high to enable this command Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Register Normal Mode ON, Idle Mode ON, Sleep OUT Yes Availability Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Status Default Default Value Power ON Sequence 24’h009341h SW Reset 24’h009341h HW Reset 24’h009341h The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 187 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.24. Positive Gamma Correction (E0h) E0h PGAMCTRL (Positive Gamma Control) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 1 1 0 0 0 0 0 E0h 1st Parameter 1 1 ↑ XX 0 0 0 0 2ndParameter 1 1 ↑ XX 0 0 3rdParameter 1 1 ↑ XX 0 0 4th Parameter 1 1 ↑ X 0 0 0 5th Parameter 1 1 ↑ XX 0 0 0 6th Parameter 1 1 ↑ XX 0 0 0 7th Parameter 1 1 ↑ XX 0 8th Parameter 1 1 ↑ XX 9th Parameter 1 1 ↑ XX 0 10thParameter 1 1 ↑ XX 0 0 0 th VP63 [3:0] VP61 [5:0] 0 VP59 [3:0] 0 VP50 [3:0] VP27 [3:0] 09 VP36 [3:0] VP20 [6:0] 11 Parameter 1 1 ↑ XX 0 0 0 1 1 ↑ XX 0 0 0 13thParameter 1 1 ↑ XX 0 0 14thParameter 1 1 ↑ XX 0 0 15thParameter 1 1 ↑ XX 0 0 0 VP13 [3:0] 0B VP6 [4:0] 0 VP4 [3:0] 00 VP0 [3:0] 00 VP2 [5:0] VP1 [5:0] 0 0 Description Set the gray scale voltage to adjust the gamma characteristics of the TFT panel. Restriction EXTC should be high to enable this command Availability 05 VP57 [4:0] VP43 [6:0] 12thParameter Register 08 VP62 [5:0] Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Normal Mode ON, Idle Mode ON, Sleep OUT Yes Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Default The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 188 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.25. Negative Gamma Correction (E1h) E1h NGAMCTRL (Negative Gamma Correction) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 1 1 0 0 0 0 1 E1h 1st Parameter 1 1 ↑ XX 0 0 0 0 2ndParameter 1 1 ↑ XX 0 0 3rdParameter 1 1 ↑ XX 0 0 4th Parameter 1 1 ↑ XX 0 0 0 5th Parameter 1 1 ↑ XX 0 0 0 6th Parameter 1 1 ↑ XX 0 0 0 7th Parameter 1 1 ↑ XX 0 8th Parameter 1 1 ↑ XX 9th Parameter 1 1 ↑ XX 0 10thParameter 1 1 ↑ XX 0 0 0 th VN63 [3:0] VN61 [5:0] 0 VN59 [3:0] 0 VN50 [3:0] VN36 [3:0] 05 VN27 [3:0] VN20 [6:0] 11 Parameter 1 1 ↑ XX 0 0 0 1 1 ↑ XX 0 0 0 13thParameter 1 1 ↑ XX 0 0 14thParameter 1 1 ↑ XX 0 0 15thParameter 1 1 ↑ XX 0 0 0 VN13 [3:0] 04 VN6 [4:0] 0 VN4 [3:0] 0F VN0 [3:0] 0F VN2 [5:0] VN1 [5:0] 0 0 Description Set the gray scale voltage to adjust the gamma characteristics of the TFT panel. Restriction EXTC should be high to enable this command Availability 07 VN57 [4:0] VN43 [6:0] 12thParameter Register 08 VN62 [5:0] Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Normal Mode ON, Idle Mode ON, Sleep OUT Yes Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Default The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 189 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.26. Digital Gamma Control 1 (E2h) E2h DGAMCTRL (Digital Gamma Control 1) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 1 1 0 0 0 1 0 E2h 1st Parameter 1 1 ↑ XX RCA0 [3:0] BCA0 [3:0] XX : 1 1 ↑ XX RCAx [3:0] BCAx [3:0] XX 1 1 ↑ XX RCA15 [3:0] BCA15 [3:0] XX th 16 Parameter RCAx [3:0]: Gamma Macro-adjustment registers for red gamma curve. Description BCAx [3:0]: Gamma Macro-adjustment registers for blue gamma curve. Restriction EXTC should be high to enable this command Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Register Normal Mode ON, Idle Mode ON, Sleep OUT Yes Availability Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Status Default Default Value RCAx [3:0] BCAx [3:0] Power ON Sequence TBD TBD SW Reset TBD TBD HW Reset TBD TBD The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 190 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.27. Digital Gamma Control 2(E3h) E3h DGAMCTRL (Digital Gamma Control 2) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 1 1 0 0 0 1 1 E3h 1st Parameter 1 1 ↑ XX : 1 1 ↑ XX 64rdParameter 1 1 ↑ XX RFA0 [3:0] BFA0 [3:0] XX RFAx [3:0] BFAx [3:0] XX RFA63 [3:0] BFA63 [3:0] XX RFAx [3:0]: Gamma Micro-adjustment register for red gamma curve. Description BFAx [3:0]: Gamma Micro-adjustment register for blue gamma curve. Restriction EXTC should be high to enable this command Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Register Normal Mode ON, Idle Mode ON, Sleep OUT Yes Availability Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Status Default Default Value RFAx [3:0] BFAx [3:0] Power ON Sequence TBD TBD SW Reset TBD TBD HW Reset TBD TBD The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 191 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.3.28. Interface Control (F6h) F6h Command IFCTL (16bits Data Format Selection) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ XX 1 1 1 1 0 1 1 0 F6h MY_ MX_ MV_ EOR EOR EOR BGR_ 1stParameter 1 1 ↑ XX 2ndParameter 1 1 ↑ XX 0 0 EPF [1] EPF [0] 0 0 1 1 ↑ XX 0 0 ENDIAN 0 DM [1] DM [0] 3rdParameter 0 0 EOR WE 0 MODE MDT MDT [1] [0] RM RIM 01 00 00 MY_EOR / MX_EOR / MV_EOR / BGR_EOR: The set value of MADCTL is used in the IC is derived as exclusive OR between 1st Parameter of IFCTL and MADCTL Parameter. MDT [1:0]: Select the method of display data transferring. WEMODE: Memory write control WEMODE=0: When the transfer number of data exceeds (EC-SC+1)*(EP-SP+1), the exceeding data will be ignored. WEMODE=1: When the transfer number of data exceeds (EC-SC+1)*(EP-SP+1), the column and page number will be reset, and the exceeding data will be written into the following column and page. ENDIAN: Select Little Endian Interface bit. At Little Endian mode, the host sends LSB data first. ENDIAN Data transfer Mode 0 Normal (MSB first, default) 1 Little Endian (LSB first) Note: Little Endian is valid on only 65K 8-bit and 9-bit MCU interface mode. Description 1st transfer (Lower byte) Input Data 16-bit display Data (Before expanding to 18 bits data) DB[7] DB[6] DB[5] DB[4] DB[3] DB[7] DB[6] DB[5] DB[4] R4 R3 R2 R1 DB[2] 2nd transfer (Upper byte) DB[1] DB[0] DB[7] DB[6] DB[5] DB[3] DB[2] DB[1] DB[0] DB[7] DB[6] DB[5] R0 G5 G4 G3 G2 G1 G0 DB[4] DB[4] DB[3] DB[2] DB[3] B4 B3 DB[1] DB[0] DB[2] DB[1] DB[0] B2 B1 B0 DM [1:0]: Select the display operation mode. DM [1] DM [0] Display Operation Mode 0 0 Internal clock operation 0 1 RGB Interface Mode 1 0 VSYNC interface mode 1 1 Setting disabled The DM [1:0] setting allows switching between internal clock operation mode and external display interface operation mode. However, switching between the RGB interface operation mode and the VSYNC interface operation mode is prohibited. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 192 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 RM: Select the interface to access the GRAM. Set RM to “1” when writing display data by the RGB interface. RM Interface for RAM Access 0 System interface/VSYNC interface 1 RGB interface RIM: Specify the RGB interface mode when the RGB interface is used. These bits should be set before display operation through the RGB interface and should not be set during operation. RIM 0 1 COLMOD [6:4] RGB Interface Mode 110 (262K color) 18- bit RGB interface (1 transfer/pixel) 101 (65K color) 16- bit RGB interface (1 transfer/pixel) 110 (262K color) 6- bit RGB interface (3 transfer/pixel) 101 (65K color) 6- bit RGB interface (3 transfer/pixel) EPF [1:0]: 65K color mode data format. Data Bus DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 Read Data DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Data Bus DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R4 R3 R2 R1 0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 Read Data DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Data Bus DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R4 R3 R2 R1 1 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 Read Data DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Data Bus DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 EPF=00 Frame Data R5 B0 EPF=01 Frame Data R5 0 EPF=10 Frame Data R5 EPF=11 Frame Data Read Data Condition Copy Condition Copy R5 1 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 B0 Input data Green Data Green data = odd Green data = even By-pass R=B R/B Data R != B G0 is copied to R0/B0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 193 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color EPF [1:0] 01 10 Exception: R [4:0], B[4:0] = 5’h1F → r [5:0], b[5:0] = 6’h3F “1” is inputted to LSB r [5:0] = {R [4:0], 1} g [5:0] = {G [5:0]} b [5:0] = {B [4:0], 1} 11 Restriction Expand 16 bbp (R,G,B) to 18bbp (R,G,B) MSB is inputted to LSB r [5:0] = {R [4:0], R [4]} g [5:0] = {G [5:0]} b [5:0] = {B [4:0], B [4]} “0” is inputted to LSB r [5:0] = {R [4:0], 0} g [5:0] = {G [5:0]} b [5:0] = {B [4:0], 0} 00 ILI9341 Exception: R [4:0], B[4:0] = 5’h00 → r [5:0], b[5:0] = 6’h00 Compare R [4:0], G [5:1], B [4:0] case: Case 1: R=G=B → r [5:0] = {R [4:0], G [0]}, g [5:0] = {G [5:0]}, b [5:0] = {B [4:0], G [0]} Case 2: R=B≠G → r [5:0] = {R [4:0], R [4]}, g [5:0] = {G [5:0]}, b [5:0] = {B [4:0], B [0]} Case 3: R=G≠B → r [5:0] = {R [4:0], G [0]}, g [5:0] = {G [5:0]}, b [5:0] = {B [4:0], B [0]} Case 4: B=G≠R → r [5:0] = {R [4:0], R [4]}, g [5:0] = {G [5:0]}, b [5:0] = {B [4:0], G [0]} EXTC should be high to enable this command Register Availability Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Normal Mode ON, Idle Mode ON, Sleep OUT Yes Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Default Value Status Default EPF [1:0] MDT [1:0] ENDIAN WEMODE DM [1:0] RM RIM Power ON Sequence 2’b00 2’b00 1’b0 1’b1 2’b00 1’b0 1’b0 SW Reset 2’b00 2’b00 1’b0 1’b1 2’b00 1’b0 1’b0 HW Reset 2’b00 2’b00 1’b0 1’b1 2’b00 1’b0 1’b0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 194 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.4 Description of Extend register command 8.4.1 Power control A (CBh) CBh Power control A D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 1 1 1 0 1 1 0 CBh 1stParameter 1 1 ↑ XX 0 0 1 1 1 0 0 1 39 2ndParameter 1 1 ↑ XX 0 0 1 0 1 1 0 0 2C 3rdParameter 1 1 ↑ XX 0 0 0 0 0 0 0 0 4rdParameter 1 1 ↑ XX 0 0 1 1 0 REG_VD[2:0] 34 5rd 1 1 ↑ XX 0 0 0 0 0 VBC[2:0] 02 Parameter 00 REG_VD[2:0]: vcore control Description REG_VD[2:0] 000 001 010 011 100 101 110 111 Vcore(V) 1.55 1.4 1.5 1.65 1.6 1.7 reserved reserved VBC[2:0]: ddvdh control VBC[2:0] 000 001 010 011 100 101 110 111 Restriction DDVDH(V) 5.8 5.7 5.6 5.5 5.4 5.3 5.2 Reserved EXTC should be high to enable this command Register Availability Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Normal Mode ON, Idle Mode ON, Sleep OUT Yes Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Default Value Status Default Parameter1 Parameter2 Parameter3 Parameter4 Parameter5 Power ON Sequence 39 2C 00 34 02 SW Reset 39 2C 00 34 02 HW Reset 39 2C 00 34 02 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 195 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.4.2 Power control B (CFh) CFh Power control B D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 1 0 0 1 1 1 1 CFh 1stParameter 1 1 ↑ XX 0 0 0 0 0 0 0 0 00 2ndParameter 1 1 ↑ XX 1 0 0 Power control[1:0] 0 0 1 81 1 1 ↑ XX 0 0 1 DC_ena 0 0 0 30 3rdParameter 0 2nd parameter: power control[1:0] Only setting power control [1:0]=11, the VGH and VGL voltage level follow the table below. BT [2:0] Description DDVDH 0 0 0 0 0 1 0 1 0 0 1 1 VGH VGL VCI x 7 VCI x 2 VCI x 6 -VCI x 4 -VCI x 3 -VCI x 4 -VCI x 3 rd 3 parameter: Discharge path enable. Enable high for ESD protection Restriction Register Availability EXTC should be high to enable this command Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Normal Mode ON, Idle Mode ON, Sleep OUT Yes Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Default Value Status Default Parameter1 Parameter2 Parameter3 Power ON Sequence 00 A2 F0 SW Reset 00 A2 F0 HW Reset 00 A2 F0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 196 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.4.3 Driver timing control A (E8h) F6h Driver timing control A D7 D6 D5 D4 D3 D2 D1 D0 HEX XX 1 1 1 0 1 0 0 0 E8h XX 1 0 0 0 0 1 0 NOW 0 0 EQ 0 0 0 CR 1 1 1 1 0 PC[1:0] D/CX RDX WRX D17-8 Command 0 1 ↑ 1stParameter 1 1 ↑ nd 2 Parameter 1 1 ↑ XX 0 3rdParameter 1 1 ↑ XX 0 84 11 7A 1st parameter:gate driver non-overlap timing control 0:default non-overlap time 1:default + 1unit 2nd parameter:EQ timing control 0: default – 1unit 1:default EQ timing parameter:CR timing control Description 0: default – 1unit 1:default CR timing 3rd parameter:pre-charge timing control 11: reserved 10: default pre-charge timing 01:default – 1unit 00:default – 2unit Restriction EXTC should be high to enable this command Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Register Normal Mode ON, Idle Mode ON, Sleep OUT Yes Availability Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Default Value Status Parameter1 Parameter2 Parameter3 84 11 7A SW Reset 84 11 7A HW Reset 84 11 7A Power ON Default Sequence The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 197 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.4.4 Driver timing control B (EAh) F6h Driver timing control B D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 1 1 0 1 0 1 0 EAh 1stParameter 1 1 ↑ XX VG_SW_T4 2ndParameter 1 1 ↑ XX X VG_SW_T3 X X X VG_SW_T2 VG_SW_T1 66 X 0 00 X 0 st 1 parameter:gate driver timing control VG_SW_T1[1:0]:EQ to GND VG_SW_T2[1:0]:EQ to DDVDH VG_SW_T3[1:0]:EQ to DDVDH VG_SW_T4[1:0]:EQ to GND Description 00: 0 unit 01: 1 unit 10: 2 unit 11: 3 unit Restriction Register Availability EXTC should be high to enable this command Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Normal Mode ON, Idle Mode ON, Sleep OUT Yes Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Status Default Default Value Parameter1 Parameter2 Power ON Sequence 66 00 SW Reset 66 00 HW Reset 66 00 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 198 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.4.5 Power on sequence control (EDh) F6h Power on sequence control D/CX RDX WRX D17- D7 8 D6 D5 D4 1 0 D3 D2 D1 D0 HEX 0 1 EDh Command 0 1 ↑ XX 1 1 1 1 1stParameter 1 1 ↑ XX X 1 CP1 soft start X 1 CP23 soft start 55 2ndParameter 1 1 ↑ XX X 0 En_vcl X 0 En_ddvdh 01 3rdParameter 1 1 ↑ XX X 0 En_vgh X 0 En_vgl 23 4thParameter 1 1 ↑ XX DDVDH_ENH 0 0 0 0 0 0 1 1 1st parameter:soft start control 00:soft start keep 3 frame 01:soft start keep 2 frame 01:soft start keep 1 frame 11:disable 2nd/ 3rd parameter:power on sequence control 00:1st frame enable Description 01:2nd frame enable 10:3rd frame enable 11:4th frame enable 4th parameter:DDVDH enhance mode(only for 8 external capacitors) 0: disable 1: enable Restriction EXTC should be high to enable this command Register Availability Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Normal Mode ON, Idle Mode ON, Sleep OUT Yes Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Status Default Default Value Parameter1 Parameter2 Parameter3 Parameter4 Power ON Sequence 55 01 23 01 SW Reset 55 01 23 01 HW Reset 55 01 23 01 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 199 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.4.6 Enable 3G (F2h) F6h Enable_3G D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 1 1 1 0 0 1 0 F2h 1stParameter 1 1 ↑ XX 0 0 0 0 0 0 1 3G_enb 02 st 1 Parameter: Enable 3 gamma control 3G_enb high for 3 gamma control enable Description Restriction Register Availability EXTC should be high to enable this command Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Normal Mode ON, Idle Mode ON, Sleep OUT Yes Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Status Default Power ON Sequence Default Value Parameter1 02 SW Reset 02 HW Reset 02 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 200 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 8.4.7 Pump ratio control (F7h) F6h Pump ratio control D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ XX 1 1 1 1 0 1 1 0 F7h 1stParameter 1 1 ↑ XX X X 0 0 0 0 10 Ratio[1:0] st 1 parameter:ratio control 00:reserved 01:reserved 10:DDVDH=2xVCI Description Restriction Register Availability 11:DDVDH=3xVCI EXTC should be high to enable this command Status Availability Normal Mode ON, Idle Mode OFF, Sleep OUT Yes Normal Mode ON, Idle Mode ON, Sleep OUT Yes Partial Mode ON, Idle Mode OFF, Sleep OUT Yes Partial Mode ON, Idle Mode ON, Sleep OUT Yes Sleep IN Yes Status Default Power ON Sequence Default Value Parameter1 10 SW Reset 10 HW Reset 10 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 201 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 9. Display Data RAM 9.1. Configuration The display data RAM stores display dots and consists of 1,382,400 bits (240x18x320 bits). There is no restriction on access to the RAM even when the display data on the same address is loaded to DAC. There will be no abnormal visible effect on the display when there is a simultaneous panel read and interface read or write display data to the same location of the frame memory. MCU Interface Column Counter Panel Side Line Pointer Page Counter 240 x 320 x 18 bits Frame Memory Interface Side Line Latch (720 ch) DAC (720ch) Amp (720 ch) The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 202 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 9.2. Memory to Display Address Mapping 9.2.1. Normal Display ON or Partial Mode ON, Vertical Scroll Mode OFF In this mode, the content of frame memory within an area where column pointer is 0000h to 00EFh and page pointer is 0000h to 013Fh is displayed. To display a dot on leftmost top corner, store the dot data at (column pointer, page pointer) = (0, 0) 14 20 21 22 23 30 31 32 05 0U 001h 0V 0W 0X 0Y 0Z 000h 00 01 02 03 04 1V 1W 1X 1Y 1Z 001h 10 11 12 13 14 2W 2X 2Y 2Z 20 21 22 23 3X 3Y 3Z 30 31 32 240 X 320 X 18 Bits Fr ame Memory 320 Lines W0 W1 W2 13Fh X1 X2 Y0 Y1 Y2 Y3 Z0 Z1 Z2 Z3 Z4 ZU 0U 0 V 0W 0X 0Y 0Z 1 V 1W 1X 1Y 1Z 2W 2X 2Y 2Z 3X 3Y 3Z 240 X 32 0 X 18 Bits LCD Panel WX WY WZ X0 05 EFh 04 13 EEh 03 12 EDh 02 11 EFh 01 10 EFh 00 001 h EDh 000 h 000h 240 Col umns 001h 000h 240 Columns W0 W1 W2 WX WY WZ XW XX XY XZ X 0 X1 X2 YV YW YX YY YZ Y 0 Y1 Y2 Y3 ZV ZW ZX ZZ Z0 Z2 Z3 ZY 13 Fh Z1 Z4 XW XX XY YV YW YX YY XZ YZ ZU ZV ZW ZX ZY ZZ 240 Columns The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 203 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 9.2.2. Vertical Scroll Mode There is a vertical scrolling mode, which is determined by the commands “Vertical Scrolling Definition” (33h) and “Vertical Scrolling Start Address” (37h). The Vertical Scroll Mode function is explained by these examples in the following. 21 22 23 30 31 32 0U 001 h 000 h 0V 0W 0X 0Y 0Z 000 h 00 01 02 03 04 1V 1W 1X 1Y 1Z 001 h 10 11 12 13 14 2W 2X 2Y 2Z 30 31 32 33 3X 3Y 3Z 40 41 42 05 0U EF h 20 05 EEh 04 14 ED h 03 13 0V 0W 0X 0Y 0Z 000h 1V 1W 1X 1Y 1Z 001h 3W 3X 3Y 3Z 4X 4Y 4Z XX XY XZ YW YX YY YZ XZ 13Dh ZV ZW ZX ZY ZZ 13 Eh 2V 2W 2X 2Y 2Z 13 Fh EDh 02 12 EF h 01 11 EF h 00 10 ED h 001 h 000 h TFA=2, VSA=318, BFA=0 when MADCTL ML bit = 0 Top fixed area Scroll Pointer = 03h 24 0 X 32 0 X 18 Bits F rame Mem ory 240 X 32 0 X 18 Bits LCD Panel Scroll area Scroll area W0 W1 W 2 X0 X1 WX WY WZ X2 Y0 Y1 Y2 Y3 Z0 Z1 Z2 Z3 Z4 ZU X0 X1 X2 XW XX XY XZ 13D h Y0 Y1 Y2 YV YW YX YY YZ 13Eh Z0 Z1 Z2 Z3 ZV ZW ZX ZY ZZ 13Fh 20 21 22 23 24 2U = 318 lines 20 21 22 23 30 31 32 05 0U 0V 0W 0X 0Y 0Z 000 h 00 01 02 03 04 1V 1W 1X 1Y 1Z 001 h 10 11 12 13 14 2W 2X 2Y 2Z 30 31 32 33 3X 3Y 3Z 40 41 42 05 0U EFh 14 EEh 04 13 001h 03 12 000h 02 11 EFh 01 10 EFh 001h 00 EDh 000h TFA=2, VSA=316, BFA=2 when MADCTL ML bit = 0 0V 0W 0X 0Y 0Z 000 h 1V 1W 1X 1Y 1Z 001 h 3W 3X 3Y 3Z 4X 4Y 4Z Top fixed area Scroll Pointer = 03h WX WY WZ X0 X1 X2 Y0 Y1 Y2 Y3 Z0 Z1 Z2 Z3 Scroll area = 316lines X0 X1 X2 XW XX XY XZ 13Dh 20 21 22 23 2W 2X 2Y 2Z 13Dh YV YW YX YY YZ 13Eh Y0 Y1 Y2 Y3 YV YW YX YY YZ 13Eh ZV ZW ZX ZY ZZ 13Fh Z0 Z1 Z2 Z3 ZU ZV ZW ZX ZY ZZ 13Fh EFh W0 W1 W2 240 X 320 X 18 Bits LCD Panel EEh 240 X 320 X 18 Bits Frame Memory Scroll area XX XY XZ 0U 0V 0W 0X 0Y 0Z 000 h 1V 1W 1X 1Y 1Z 001 h 3W 3X 3Y 3Z 4X 4Y 4Z Bottom fixed area Z4 ZU Z4 14 20 21 22 23 30 31 32 05 0U EDh 04 13 001h 03 12 000h 02 11 EFh 01 10 EFh 001h 00 EDh 000h TFA=2, VSA=316, BFA=4 when MADCTL ML bit = 0 0V 0W 0X 0Y 0Z 000 h 00 01 02 03 04 1V 1W 1X 1Y 1Z 001 h 10 11 12 13 14 2W 2X 2Y 2Z 30 31 32 33 3X 3Y 3Z 40 41 42 05 Top fixed area 240 X 320 X 18 Bits Frame Memory Scroll area Scroll area 240 X 320 X 18 Bits LCD Panel = 316lines Scroll Pointer = 05h W0 W1 W2 WX WY WZ X0 X1 X2 Y0 Y1 Y2 Y3 Z0 Z1 Z2 Z3 30 31 32 3X 3Y 3Z XW XX XY XZ 13Dh 40 41 42 43 4W 4X 4Y 4Z 13Dh YV YW YX YY YZ 13Eh Y0 Y1 Y2 Y3 YV YW YX YY YZ 13Eh ZV ZW ZX ZY ZZ 13Fh Z0 Z1 Z2 Z3 ZV ZW ZX ZY ZZ 13Fh Bottom fixed area Z4 ZU Z4 ZU Note: When Vertical Scrolling Definition Parameters (TFA+VSA+BFA) ≠ 320, Scrolling Mode is undefined. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 204 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 9.2.3. Vertical Scroll Example 9.2.4. Case1: TFA+VSA+BFA < 320 This setting is prohibited, unless unexpected picture will be shown. 9.2.5. Case2: TFA+VSA+BFA = 320 (Rolling Scrolling) The operation of Rolling Scrolling is explained by these examples in the following. When TFA=0, VSA=320, BFA=0, VSCRSADD=40 and MADCTL ML bit = 1 Memory Physical Axis (0,0) Physical Line Pointer Display Axis (0,0) 2 1 1 VSCRSADD 2 When TFA=0, VSA=320, BFA=0, VSCRSADD=40 and MADCT L ML bit = 0 Physical Line Pointer Display Axis (0,0) 2 Memory Physical Axis (0,0) 1 1 VSCRSADD 2 Increment VSCRSADD Memory Physical Axis (0,0) Physical Line Pointer Display Axis (0,0) 2 1 1 VSCRSADD 2 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 205 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 When TFA=30, VSA=290, BFA=0, VSCRSADD=80 and MADCTL ML bit = 0 Memory Physical Axis (0 ,0) Physical Line Pointer TFA 3 2 2 VSCRSADD 1 1 TFA Display Axis (0,0) 3 When TFA=30, VSA=290, BFA=0, VSCRSADD=80 and MADCTL ML bit = 1 Memory Physical Axis (0 ,0) Physical Line Pointer 2 3 1 1 TFA 3 2 VSCRSADD Display Axis (0,0) TFA Increment VSCRSADD Memory Physical Axis (0 ,0) Physical Line Pointer Display Axis (0,0) 2 3 3 VSCRSADD 2 1 1 TFA TFA The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 206 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 9.3. MCU to memory write/read direction B Data stream from MCU is like this figure ILITEK E The data is written in the order illustrated above. The Counter which dictates where in the physical memory the data is to be written is controlled by “Memory Data Access Control” Command, Bits B5, B6, and B7 as described below. MADCTL CASET PASET Bit B7 Bit B6 Bit B5 Virtual Physical Pointer Translator ’ Virtual (0,0) when B5=don t care, B6= 0", B7= 0" ” ” Physical Column Pointer ’ Virtual (0,0) when B5=don t care, B6= 1", B7= 0" ” ” (0,0) Physical Page Pointer Physical axes (0,319) (239,319) ’ Virtual (0,0) when B5=don t care, B6= 0", B7= 1" ” B5 0 0 0 0 1 1 1 1 ’ Virtual (0,0) when B5=don t care, B6= 1", B7= 1" ” ” ” B6 0 0 1 1 0 0 1 1 B7 CASET PASET 0 Direct to Physical Column Pointer Direct to Physical Page Pointer 1 Direct to Physical Column Pointer Direct to (319-Physical Page Pointer) 0 Direct to (239-Physical Column Pointer) Direct to Physical Page Pointer 1 Direct to (239-Physical Column Pointer) Direct to (319-Physical Page Pointer) 0 Direct to Physical Page Pointer Direct to Physical Column Pointer 1 Direct to (319-Physical Page Pointer) Direct to Physical Column Pointer 0 Direct to Physical Page Pointer Direct to (239-Physical Column Pointer) 1 Direct to (319-Physical Page Pointer) Direct to (239-Physical Column Pointer) Condition Column Counter Page counter When RAMWR/RAMRD command is accepted Return to “Start column” Return to “Start Page” Complete Pixel Read/Write action Increment by 1 No change The Column values is large than “End Column” Return to “Start column” Increment by 1 The Page counter is large than “End Page” Return to “Start column” Return to “Start Page” The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 207 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 Note: Data is always written to the Frame Memory in the same order, regardless of the Memory Write Direction set by MADCTL bits B7, B6 and B5. The write order for each pixel unit is One pixel unit represents 1 column and 1 page counter value on the Frame Memory. Display Data Direction MADCTR Parameter MV MX MY Image in the Memory (MPU) B Normal 0 0 Image in the Driver (Frame Memory) Memory(0,0) 0 B Counter(0,0) E E Y-Mirror 0 0 1 E B X-Mirror 0 1 Counter(0,0) 1 Memory(0,0) 0 Memor(0,0) 0 Counter(0,0) E Memory(0,0) 0 1 c E XY Exchange X-Mirror B 1 1 Counter(0,0) 1 B Counter(0,0) 0 B 1 B Memory(0,0) E E XY Exchange XY-Mirror E B 1 Counter(0,0) B E X-Y Exchange Y-Mirror B E 1 B 1 Counter(0,0) E E X-Y Exchange B 0 B 0 B Memory(0,0) E X-Mirror Y-Mirror E Memory(0,0) B Memory(0,0) E 1 E B Counter(0,0) The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 208 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 10. Tearing Effect Output The Tearing Effect output line supplies to the MCU a Panel synchronization signal. This signal can be enabled or disabled by the Tearing Effect Line Off & On commands. The mode of the Tearing Effect Signal is defined by the parameter of the Tearing Effect Line Off & On commands. The signal can be used by the MCU to synchronize Frame Memory Writing when displaying video images. 10.1. Tearing Effect Line Modes Mode 1, the Tearing Effect Output signal consists of V-Sync information only: tvdl tvdh Vertical Time Scale tvdh = The LCD display is not updated from the Frame Memory. tvdl = The LCD display is updated from the Frame Memory (except Invisible Line – see below). Mode 2, the tearing effect output signal consists of V-Sync and H-Sync information; there is one V-sync and 320 H-sync pulses per field: thdl thdl thdh V-Sync V-Sync Invisible Line 1st Line 320th Line thdh = The LCD display is not updated from the Frame Memory. thdl = The LCD display is updated from the Frame Memory (except Invisible Line – see above). Bottom Line 1st Line 2nd Line TE (mode 2) TE (mode 1) Note: During Sleep In Mode, the Tearing Effect Output Pin is active Low. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 209 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 10.2. Tearing Effect Line Timings The tearing effect signal is described below: tvd l t vdh Vertical Timing Horizontal Timing thdl thdh AC characteristics of Tearing Effect Signal (Frame Rate = 60Hz) Symbol Parameter Min. Typ. Max. Unit tvdl Vertical timing low duration -- -- -- ms tvdh Vertical timing high duration 1000 -- -- us thdl Horizontal timing low duration -- -- -- us thdh Horizontal timing high duration -- -- 500 us Description Note: 1. The timings in Table as above apply when MADCTL B4=0 and B4=1 2. The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns. tr tf 80% 80% 20% 20% The Tearing Effect Output Line is fed back to the MCU and should be used to avoid Tearing Effect. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 210 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 11. Sleep Out – Command and Self-Diagnostic Functions of the Display Module 11.1. Register loading Detection Sleep Out-command (Command “Sleep Out (11h)”) is a trigger for an internal function of the display module, which indicates, if the display module loading function of factory default values from EV Memory(or similar device) to registers of the display controller is working properly. If the register loading detection is successfully, there is inverted (= increased by 1) a bit, which is defined in command “Read Display Self-Diagnostic Result (0Fh)” (= RDDSDR) (The used bit of this command is D7). If it is failure, this bit (D7) is not inverted (= not increased by 1). The flow chart for this internal function is following: Power on sequence HW reset SW reset Sleep IN (10h) Sleep OUT mode Sleep IN mode RDDSDR(0Fh)'s D7 = '0' Sleep OUT (11h) Register Loading Detection Successful ? NO YES D7 inverted The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 211 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 11.2. Functionality Detection Sleep Out-command (Command “Sleep Out (11h)”) is a trigger for an internal function of the display module, which indicates, if the display module is still running and meets functionality requirements. The internal function (= the display controller) is comparing, if the display module is still meeting functionality requirements (e.g. booster voltage levels, timings, etc.) If functionality requirement is met, there is an inverted (= increased by 1) bit, which defined in command “Read Display Self- Diagnostic Result (0Fh)” (= RDDSDR) (The used bit of this command is D6). If functionality requirement is not same, this bit (D6) is not inverted (= increased by 1). The flow chart for this internal function is shown as below. The flow chart for this internal function is following: Power on sequence HW reset SW reset Sleep IN (10h) Sleep OUT mode Sleep IN mode RDDSDR(0Fh)'s D6 = '0' Sleep OUT (11h) Check timings, valtage levels, and other functionalities Is the required functionality present? NO YES D6 inverted Note 1: There is needed 120msec after Sleep Out -command, when there is changing from Sleep In –mode to Sleep Out -mode, before there is possible to check if User’s functionality requirements are met and a value of RDDSDR’s D6 is valid. Otherwise, there is 5msec delay for D6’s value, when Sleep Out –command is sent in Sleep Out -mode. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 212 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 12. Power ON/OFF Sequence VDDI and VCI can be applied in any order. VCI and VDDI can be powered down in any order. During power off, if LCD is in the Sleep Out mode, VCI and VDDI must be powered down minimum 120msec after RESX has been released. During power off, if LCD is in the Sleep In mode, VDDI or VCI can be powered down minimum 0msec after RESX has been released. CSX can be applied at any timing or can be permanently grounded. RESX has priority over CSX. Note 1: There will be no damage to the display module if the power sequences are not met. Note 2: There will be no abnormal visible effects on the display panel during the Power On/Off Sequences. Note 3: There will be no abnormal visible effects on the display between end of Power On Sequence and before receiving Sleep Out command. Also between receiving Sleep In command and Power Off Sequence. Note 4: If RESX line is not held stable by host during Power On Sequence as defined in Sections 12.1 and 12.2, then it will be necessary to apply a Hardware Reset (RESX) after Host Power On Sequence is complete to ensure correct operation. Otherwise function is not guaranteed. 12.1. Case 1 – RESX line is held High or Unstable by Host at Power ON If RESX line is held High or unstable by the host during Power On, then a Hardware Reset must be applied after both VCI and VDDI have been applied – otherwise correct functionality is not guaranteed. There is no timing restriction upon this hardware reset. Note 1: Unless otherwise specified, timings herein show cross point at 50% of signal power level. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 213 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 12.2. Case 2 – RESX line is held Low by Host at Power ON If RESX line is held Low (and stable) by the host during Power On, then the RESX must be held low for minimum 10µsec after both VCI and VDDI have been applied. Note 1: Unless otherwise specified, timings herein show cross point at 50% of signal power level. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 214 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 12.3. Uncontrolled Power Off The uncontrolled power off means a situation when e.g. there is removed a battery without the controlled power off sequence. There will not be any damages for the display module or the display module will not cause any damages for the host or lines of the interface. At an uncontrolled power off event, ILI9341 will force the display to blank and will not be any abnormal visible effects with in 1 second on the display and remains blank until “Power On Sequence” actives. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 215 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 13. Power Level Definition 13.1. Power Levels 7 level modes are defined they are in order of Maximum Power consumption to Minimum Power Consumption: 1. Normal Mode On (full display), Idle Mode Off, Sleep Out. In this mode, the display is able to show maximum 262,144 colors. 2. Partial Mode On, Idle Mode Off, Sleep Out. In this mode part of the display is used with maximum 262,144 colors. 3. Normal Mode On (full display), Idle Mode On, Sleep Out. In this mode, the full display area is used but with 8 colors. 4. Partial Mode On, Idle Mode On, Sleep Out. In this mode, part of the display is used but with 8 colors. 5. Sleep In Mode. In this mode, the DC : DC converter, Internal oscillator and panel driver circuit are stopped. Only the MCU interface and memory works with VDDI power supply. Contents of the memory are safe. 6. Power Off Mode. In this mode, both VCI and VDDI are removed. Note1: Transition between modes 1-5 is controllable by MCU commands. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 216 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 13.2. Power Flow Chart Normal display mode ON = NORON Partial mode ON = PTLON Idle mode OFF = IDMOFF Sleep OUT = SLPOUT Sleep IN = SLPIN NORON PTLON Power ON sequence HW reset SW reset Sleep OUT Normal display mode ON Idle mode OFF IDMON Sleep OUT Partial mode ON Idle mode OFF PTLON NORON SLPOUT SLPIN SLPOUT SLPIN SLPOUT IDMOFF Sleep OUT Partial mode ON Idle mode ON Sleep IN Normal display mode ON Idle mode OFF IDMON IDMOFF Sleep OUT Normal display mode ON Idle mode ON IDMON SLPIN SLPOUT PTLON IDMOFF Sleep IN Normal display mode ON Idle mode ON Sleep IN Partial mode ON Idle mode OFF IDMON SLPIN NORON IDMOFF Sleep IN Partial mode ON Idle mode ON PTLON NORON Note 1: There is not any abnormal visual effect when there is changing from one power mode to another power mode. Note 2: There is not any limitation, which is not specified by User, when there is changing from one power mode to another power mode. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 217 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 14. Gamma Curves Selection ILI9341 provide one gamma curve Gamma2.2. The gamma curve can be selected by the GC0 settings. 14.1. Gamma Default Values (for NW type LC) Data 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Output Voltage VCOM = Low VCOM = High Gamma 2.2 Gamma 2.2 V0P 4.084 V0N 0.277 V1P 4.015 V1N 0.346 V2P 3.843 V2N 0.482 V3P 3.681 V3N 0.629 V4P 3.518 V4N 0.776 V5P 3.445 V5N 0.924 V6P 3.371 V6N 1.071 V7P 3.285 V7N 1.157 V8P 3.199 V8N 1.242 V9P 3.128 V9N 1.314 V10P 3.056 V10N 1.385 V11P 2.985 V11N 1.456 V12P 2.928 V12N 1.513 V13P 2.871 V13N 1.570 V14P 2.802 V14N 1.619 V15P 2.733 V15N 1.668 V16P 2.674 V16N 1.710 V17P 2.615 V17N 1.753 V18P 2.557 V18N 1.795 V19P 2.508 V19N 1.830 V20P 2.458 V20N 1.865 V21P 2.425 V21N 1.899 V22P 2.391 V22N 1.932 V23P 2.357 V23N 1.966 V24P 2.323 V24N 2.000 V25P 2.289 V25N 2.034 V26P 2.256 V26N 2.068 V27P 2.222 V27N 2.102 V28P 2.193 V28N 2.129 V29P 2.165 V29N 2.155 V30P 2.136 V30N 2.182 V31P 2.108 V31N 2.208 V32P 2.080 V32N 2.235 V33P 2.051 V33N 2.262 V34P 2.023 V34N 2.288 V35P 1.994 V35N 2.315 V36P 1.966 V36N 2.342 V37P 1.942 V37N 2.368 V38P 1.917 V38N 2.395 V39P 1.893 V39N 2.421 V40P 1.869 V40N 2.448 V41P 1.845 V41N 2.475 V42P 1.820 V42N 2.501 V43P 1.796 V43N 2.528 V44P 1.776 V44N 2.549 V45P 1.755 V45N 2.571 V46P 1.730 V46N 2.597 V47P 1.706 V47N 2.623 V48P 1.681 V48N 2.649 V49P 1.653 V49N 2.679 V50P 1.624 V50N 2.710 V51P 1.598 V51N 2.735 V52P 1.573 V52N 2.761 V53P 1.541 V53N 2.793 V54P 1.508 V54N 2.825 V55P 1.476 V55N 2.857 V56P 1.438 V56N 2.895 V57P 1.400 V57N 2.933 V58P 1.359 V58N 2.982 V59P 1.319 V59N 3.031 V60P 1.246 V60N 3.109 V61P 1.173 V61N 3.186 V62P 1.070 V62N 3.289 V63P 0.279 V63N 4.083 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 218 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 14.2. Gamma Curves 14.2.1. Gamma Curve 1 (GC0), applies the function y=x2.2 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 219 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 14.3. Gamma Curves 14.3.1. Grayscale Voltage Generation The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 220 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 14.3.2. Positive Gamma Correction The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 221 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 14.3.3. Negative Gamma Correction The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 222 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 15. Reset 15.1. Registers The registers that are initialized are listed as below: Frame Memory Sleep Display Mode Display Idle Column Start Address After Powered ON Random In Normal Off Off 0000 h After Hardware Reset Repair data In Normal Off Off 0000 h Column End Address 00EF h 00EF h Page Start Address 0000 h 0000 h Page End Address 013F h 013F h Gamma Setting Partial Area Start Partial Area End Memory Data Access Control RDDPM RDDMADCTL RDDCOLMOD RDDIM RDDSM RDDSDR TE Output Line TE Line Mode GC0 0000 h 013F h GC0 0000 h 013F h After Software Reset No Change In Normal Off Off 0000 h If MADCTL’s B5=0:00EF h If MADCTL’s B5=1:013F h 0000 h If MADCTL’s B5 = 0:013F h If MADCTL’s B5=1:00EF h GC0 0000 h 013F h 00 h 00 h No Change 08 h 00 h 06 h 00 h 00 h 00 h Off Mode 1 (Note 3) 08 h 00 h 06 h 00 h 00 h 00 h Off Mode 1 (Note 3) 08 h No Change 06 h 00 h 00 h 00 h Off Mode 1 (Note 3) Note 1: There will be no abnormal visible effects on the display when S/W or H/W Resets are applied. Note 2: After Powered-On Reset finishes within 10µs after both VCI & VDDI are applied. Note 3: Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 223 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 15.2. Output Pins, I/O Pins TE line D[17:0] (output driver) After Power ON Low Hi-Z (Inactive) After Hardware Reset Low Hi-Z (Inactive) After Software Reset Low Hi-Z (Inactive) Note 1: There will be no output from D [17:0] during Power ON/OFF sequence, hardware reset and software reset. 15.3. Input Pins RESX CSX D/CX WRX RDX D[17:0] (input driver) During Power ON Process See Chapter 12 Input invalid Input invalid Input invalid Input invalid Input invalid After Power ON Input valid Input valid Input valid Input valid Input valid Input valid After Hardware Reset Input valid Input valid Input valid Input valid Input valid Input valid After Software Reset Input valid Input valid Input valid Input valid Input valid Input valid During Power OFF Process See Chapter 12 Input invalid Input invalid Input invalid Input invalid Input invalid The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 224 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 15.4. Reset Timing Shorter than 5us tRW RESX tRT Display Status Signal RESX Symbol tRW tRT Normal operation Parameter Reset pulse duration Initial condition (Default for H/W reset) Resetting Min 10 Max 5 (note 1,5) 120 (note 1,6,7) Reset cancel Unit uS mS mS Note 1: The reset cancel includes also required time for loading ID bytes, VCOM setting and other settings from NV memory to registers. This loading is done every time when there is HW reset cancel time (tRT) within 5 ms after a rising edge of RESX. Note 2: Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below: - RESX Pulse Action Shorter than 5us Reset Rejected Longer than 10us Reset Between 5us and 10us Reset starts Note 3: During the Resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time is 120 ms, when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep In -mode.) And then return to Default condition for Hardware Reset. Note 4: Spike Rejection also applies during a valid reset pulse as shown below: Note 5: When Reset applied during Sleep In Mode. Note 6: When Reset applied during Sleep Out Mode. Note 7: It is necessary to wait 5msec after releasing RESX before sending commands. Also Sleep Out command cannot be sent for 120msec. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 225 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 16. Configuration of Power Supply Circuit The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 226 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 VCOM To Panel < 5 ohm < 5 ohm < 5 ohm VCI < 5 ohm < 10 ohm < 5 ohm < 60 ohm < 60 ohm < 60 ohm < 60 ohm DB12 DB14 < 60 ohm < 60 ohm < 60 ohm < 60 ohm DB16 < 60 ohm < 60 ohm TE BC < 60 ohm < 60 ohm < 60 ohm < 60 ohm < 30 ohm < 5 ohm < 5 ohm ………………… 2 2 0 < 5 ohm 2 1 0 < 5 ohm 2 0 0 < 5 ohm G[320] G[318] G[316] G[314] G[312] G[310] G[308] G[306] G[304] G[302] 1 9 0 1uF/6.3V S[709] S[710] S[711] S[712] S[713] S[714] S[715] S[716] S[717] S[718] S[719] S[720] 1 8 0 < 10 ohm 1 7 0 1uF/6.3V 1 6 0 < 5 ohm IOVCC y < 60 ohm < 60 ohm < 60 ohm < 60 ohm DB8 DB10 1 5 0 DB17 SDO BC_CT VDDI_LED DB4 DB6 x DB13 DB15 < 60 ohm < 60 ohm < 60 ohm < 60 ohm < 60 ohm S[361] S[362] S[363] S[364] S[365] S[366] 1 4 0 DB9 DB11 DB0 DB2 Face Up (Bump View) DB5 DB7 HSYNC DOTCLK 1 3 0 SDI/SDA DB1 DB3 IOVCC 1 2 0 VSYNC ENABLE IM3 IM1 RESX DCX RDX S[355] S[356] S[357] S[358] S[359] S[360] 1 1 0 FPC IM2 IM0 CSX WRX < 20 ohm < 60 ohm < 60 ohm < 60 ohm < 60 ohm < 60 ohm < 60 ohm < 60 ohm < 60 ohm < 60 ohm < 60 ohm < 60 ohm < 60 ohm < 60 ohm < 60 ohm 1 0 0 < 5 ohm 9 0 < 5 ohm 8 0 1uF/6.3V 7 0 < 5 ohm 6 0 < 5 ohm S[1] S[2] S[3] S[4] S[5] S[6] S[7] S[8] S[9] S[10] 5 0 < 5 ohm 1uF/6.3V G[303] G[305] G[307] G[309] G[311] G[313] G[315] G[317] G[319] 4 0 1uF/6.3V < 5 ohm 3 0 1uF/6.3V 2 0 1uF/25V < 5 ohm ……………………. < 10 ohm < 10 ohm 1uF/25V ……………………. < 10 ohm ………………… < 10 ohm 1 0 1uF/10V DUMMY DUMMY DUMMY G[1] G[3] G[5] G[7] G[9] G[11] G[13] G[15] 1 < 5 ohm 1uF/10V 2 3 0 DUMMY DUMMY VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM DUMMY C22P C22P C22M C22M C21P C21P C21M C21M VGH VGH VGH VGH VGH DUMMY VGL VGL VGL VGL VGL VGL DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH C12P C12P C12P C12P C12P C12P C12P C12M C12M C12M C12M C12M C12M C12M C11P C11P C11P C11P C11P C11P C11P C11M C11M C11M C11M C11M C11M C11M DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY VCI VCI VCI VCI VCI VCI VCI VCI VSS3 VSS3 VSS3 VSS VSS VSS VSS VSS VSS VSSC VSSC VSSC VSSC VSSC VSSC VSSC VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA TREGB VGS VGS EXTC IM[3] IM[2] IM[1] IM[0] RESX CSX DCX WRX RDX DUMMY VSYNC HSYNC ENABL DOTCL DUMMY SDA DB[0] DB[1] DB[2] DB[3] DUMMY DB[4] DB[5] DB[6] DB[7] DUMMY DB[8] DB[9] DB[10] DB[11] DUMMY DB[12] DB[13] DB[14] DB[15] DUMMY DB[16] DB[17] DUMMY TE SDO BC BC_CT VDDI_LED VDDI_LED DB[18]_Dummy DB[19]_Dummy DB[20]_Dummy DB[21]_Dummy DB[22]_Dummy DB[23]_Dummy DUMMY VDDI VDDI VDDI VDDI VDDI VDDI VDDI Vcore Vcore Vcore Vcore Vcore Vcore Vcore Vcore Vcore Vcore Vcore Vcore Vcore Vcore DUMMY GVDD GVDD GVDD GVDD DUMMY DUMMY VCL VCL VCL VCL VCL VCL VCL VCL C31P C31P C31P C31P C31P C31P C31P C31P C31M C31M C31M C31M C31M C31M C31M C31M DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM DUMMY DUMMY G[16] G[14] G[12] G[10] G[8] G[6] G[4] G[2] DUMMY DUMMY DUMMY VCOM To Panel The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 227 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 The Following tables shows specifications of external elements connected to the ILI9341’s power supply circuit. Items Capacity 1 µF (B characteristics) Recommended Specification 6.3V 10V 25V Pin connection DDVDH ,VCL,C11P/M,C12P/M,Vcore,VCI C21P/M,C22P/M VGL, VGH The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 228 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 17. NV Memory Programming Flow Start Reset Sleep out(11h) Wait 100ms Check(D2h) ID3_ CNT/ID2_ CNT ID1_ CNT/ VMF_ CNT =3'b111 Y N Wait 10ms NV Memory Write(D0h) 1 st Parameter: PGM_ ADR[2:0]=3' bxxx 2nd Parameter: PGM_ DATA[7:0]=8'bxx (xx=8 bit OTP value) NV Memory Protection Key (D1h) 1 st Parameter: 55h 2nd Parameter: AAh 3rd Parameter: 66h Wait 10ms Reset End The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 229 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 18. Electrical Characteristics 18.1 Absolute Maximum Ratings The absolute maximum rating is listed on following table. When ILI9341 is used out of the absolute maximum ratings, ILI9341 may be permanently damaged. To use ILI9341 within the following electrical characteristics limitation is strongly recommended for normal operation. If these electrical characteristic conditions are exceeded during normal operation, ILI9341 will malfunction and cause poor reliability. Item Symbol Unit Value Supply voltage VCI V -0.3 ~ +4.6 Supply voltage (Logic) VDDI V -0.3 ~ +4.6 Supply voltage (Digital) VCORE V -0.3 ~ +2.0 Driver supply voltage VGH-VGL V -0.3 ~ +32.0 Logic input voltage range VIN V -0.3 ~ VDDI + 0.3 Logic output voltage range VO V -0.3 ~ VDDI + 0.3 Operating temperature Topr -40 ~ +85 Storage temperature Tstg -55 ~ +110 Note: If the absolute maximum rating of even is one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings. ℃ ℃ The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 230 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 18.2 DC Characteristics 18.2.1 General DC Characteristics Item Symbol Unit Condition Power and Operation Voltage Analog Operating VCI V Operating voltage Voltage Logic Operating VDDI V I/O supply voltage Voltage Digital Operating VCORE V Digital supply voltage voltage Gate Driver High VGH V Voltage Gate Driver Low VGL V Voltage Driver Supply Voltage V |VGH-VGL| Current consumption during standby mode IST µA Input and Output Logic High Level Input VIH V Voltage Logic Low Level Input VIL V Voltage Logic High Level VOH V Output Voltage Logic Low Level VOL V Output Voltage Logic High Level Input IIH uA Current Logic Low Level input IIL uA Current Logic Input Leakage ILEA uA Current VCOM Operation VCOM High Voltage VCOMH V VCOM Low Voltage VCOML V VCOM Amplitude VCOMA V Voltage Source Driver Source Output Range Vsout V Gamma Reference GVDD V Voltage Output Deviation Voltage (Source Vdev mV Output channel) Output Offset Voltage VOFSET mV Booster Operation st 1 Booster (VCIx2) DDVDH V Voltage st 1 Booster (VCIx2 VCIx2 % Drop Voltage drop Liner Range Vliner V Min. Typ. Max. Note 2.5 2.8 3.3 Note2 1.65 2.8 3.3 Note2 - 1.5 - Note2 10.0 - 16.0 Note3 -10.0 - -5.0 Note3 15 - 28 Note3 - - 100 - - 0.7*VDDI - VDDI Note1,2,3 - VSS - 0.3*VDDI Note1,2,3 IOL=-1.0mA 0.8*VDDI - VDDI Note1,2,3 IOL=1.0mA VSS - 0.2*VDDI Note1,2,3 - - - 1 Note1,2,3 - -1 - - Note1,2,3 VIN=VDDI or VSS -0.1 - +0.1 Note1,2,3 Ccom=12nF Ccom=12nF 2.5 -2.5 - 5.0 0.0 Note3 Note3 |VCOMH-VCOML| 4.0 - 5.5 Note3 - 0.1 - DDVDH-0.1 Note4 - 3.0 - 5.0 Note3 - - 20 Note4 - - 15 35 Note7 4.95 (Note 5) - 5.8 (Note 6) Note3 - - 5 Note3 0.2 - DDVDH-0.2 VCI=2.8V , Ta=25 °C Sout>=4.2V Sout<=0.8V 4.2V>Sout>0.8V loading=1mA - The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 231 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 Note 1: VDDI=1.65 to 3.3V, VCI=2.5 to 3.3V, AGND=VSS=0V, Ta=-30 to 70 (to +85 no damage) ℃. Note2: Please supply digital VDDI voltage equal or less than analog VCI voltage. Note3: CSX, RDX, WRX, D[17:0], D/CX, RESX, TE, DOTCLK, VSYNC, HSYNC, DE, SDA, SCL, IM3, IM2, IM1, IM0, and Test pins. Note4: When the measurements are performed with LCD module. Measurement Points are like Note3. Note5: VCI=2.6V Note6: VCI=3.3V Note7: The Max. Value is between with Note 4 measure point and Gamma setting value The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 232 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 18.3 AC Characteristics 18.3.1 Display Parallel 18/16/9/8-bit Interface Timing Characteristics (8080-Ⅰ Ⅰ system) D/CX tchw tast taht CSX tcsf twc WRX twrl twrh tdht tdst D[17:0] (Write) tchw tcs tast RDX trcs / trcsfm trc / trcfm trdl / trdlfm taht trdh / trdhfm trodh trat / tratfm D[17:0] (Read) Signal DCX CSX WRX RDX (FM) RDX (ID) D[17:0], D[15:0], D[8:0], D[7:0] Symbol tast taht tchw tcs trcs trcsfm tcsf twc twrh twrl trcfm trdhfm trdlfm trc trdh trdl tdst tdht trat tratfm trod Parameter Address setup time Address hold time (Write/Read) CSX “H” pulse width Chip Select setup time (Write) Chip Select setup time (Read ID) Chip Select setup time (Read FM) Chip Select Wait time (Write/Read) Write cycle Write Control pulse H duration Write Control pulse L duration Read Cycle (FM) Read Control H duration (FM) Read Control L duration (FM) Read cycle (ID) Read Control pulse H duration Read Control pulse L duration Write data setup time Write data hold time Read access time Read access time Read output disable time min 0 0 0 15 45 355 10 66 15 15 450 90 355 160 90 45 10 10 20 max 40 340 80 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description For maximum CL=30pF For minimum CL=8pF Note: Ta = -30 to 70 °C, VDDI=1.65V to 3.3V, VCI=2.5V to 3.3V, VSS=0V tr ≦15ns tf ≦15ns 70% 30% 70% 30% The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 233 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 CSX timings : tchw CSX WRX, RDX tcsf Min. 5ns Note: Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. Write to read or read to write timings: CSX ‘ 0’ WRX RDX twrh trdh trdhfm Note: Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 234 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 18.3.2 Display Parallel 18/16/9/8-bit Interface Timing Characteristics(8080-Ⅱ Ⅱ system) D/CX tchw tast taht CSX tcsf twc WRX twrl twrh tdht tdst D[17:0] (Write) tchw tcs tast taht trcs / trcsfm trc / trcfm trdl / trdlfm RDX trdh / trdhfm trat / tratfm trodh D[17:0] (Read) Signal DCX CSX WRX RDX (FM) RDX (ID) D[17:0], D[17:10]&D[8:1], D[17:10], D[17:9] Symbo l tast taht tchw tcs trcs trcsfm tcsf twc twrh twrl trcfm trdhfm trdlfm trc trdh trdl tdst tdht trat tratfm trod Parameter min max Unit Address setup time Address hold time (Write/Read) CSX “H” pulse width Chip Select setup time (Write) Chip Select setup time (Read ID) Chip Select setup time (Read FM) Chip Select Wait time (Write/Read) Write cycle Write Control pulse H duration Write Control pulse L duration Read Cycle (FM) Read Control H duration (FM) Read Control L duration (FM) Read cycle (ID) Read Control pulse H duration Read Control pulse L duration Write data setup time Write data hold time Read access time Read access time Read output disable time 0 0 0 15 45 355 10 66 15 15 450 90 355 160 90 45 10 10 20 40 340 80 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description For maximum CL=30pF For minimum CL=8pF Note: Ta = -30 to 70 °C, VDDI=1.65V to 3.3V, VCI=2.5V to 3.3V, VSS=0V. tr ≦15ns tf ≦15ns 70% 30% 70% 30% The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 235 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 CSX timings : tchw CSX WRX, RDX tcsf Min. 5ns Note: Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. Write to read or read to write timings: CSX ‘ 0’ WRX RDX twrh trdh trdhfm Note: Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 236 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 18.3.3 Display Serial Interface Timing Characteristics (3-line SPI system) Signal SCL SDA / SDI (Input) SDA / SDO (Output) CSX Symbol tscycw tshw tslw tscycr tshr tslr tsds tsdh tacc toh tscc tchw tcss tcsh Parameter Serial Clock Cycle (Write) SCL “H” Pulse Width (Write) SCL “L” Pulse Width (Write) Serial Clock Cycle (Read) SCL “H” Pulse Width (Read) SCL “L” Pulse Width (Read) Data setup time (Write) Data hold time (Write) Access time (Read) Output disable time (Read) SCL-CSX CSX “H” Pulse Width CSX-SCL Time min 100 40 40 150 60 60 30 30 10 10 20 40 60 65 max 50 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Note: Ta = 25 °C, VDDI=1.65V to 3.3V, VCI=2.5V to 3.3V, AGND=VSS=0V tr ≦15ns tf ≦15ns 70% 30% 70% 30% The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 237 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 18.3.4 Display Serial Interface Timing Characteristics (4-line SPI system) CSX tcss t csh D/CX tas tah twc/trc t wrl/t rdl tw rh/trd h SCL tds t dh SDA (SDI) ta cc tod SDA (SDO) Signal CSX SCL D/CX SDA / SDI (Input) SDA / SDO (Output) Symbol tcss tcsh twc twrh twrl trc trdh trdl tas tah tds tdh tacc tod Parameter Chip select time (Write) Chip select hold time (Read) Serial clock cycle (Write) SCL “H” pulse width (Write) SCL “L” pulse width (Write) Serial clock cycle (Read) SCL “H” pulse width (Read) SCL “L” pulse width (Read) D/CX setup time D/CX hold time (Write / Read) Data setup time (Write) Data hold time (Write) Access time (Read) Output disable time (Read) min 40 40 100 40 40 150 60 60 10 10 30 30 10 10 max 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns Description For maximum CL=30pF For minimum CL=8pF Note: Ta = 25 °C, VDDI=1.65V to 3.3V, VCI=2.5V to 3.3V, AGND=VSS=0V tr ≦15ns tf ≦15ns 70% 30% 70% 30% The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 238 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 18.3.5 Parallel 18/16/6-bit RGB Interface Timing Characteristics t rgbf trgbr tSYNCS VSYNC HSYNC VIH VIL t ENS tENH VIH VIL ENABLE t rgbf PWDL VIH VIL trgbr VIH DOTCLK PWDH VIH VIL VIL VIH t CYCD t PDS VIH VIL D[17:0] Signal VSYNC / HSYNC DE D[17:0] DOTCLK VSYNC / HSYNC DE D[17:0] DOTCLK t PDH Symbol tSYNCS tSYNCH tENS tENH tPOS tPDH PWDH PWDL tCYCD trgbr , trgbf tSYNCS tSYNCH tENS tENH tPOS tPDH PWDH PWDL tCYCD trgbr , trgbf VIH VIL Write Data Parameter VSYNC/HSYNC setup time VSYNC/HSYNC hold time DE setup time DE hold time Data setup time Data hold time DOTCLK high-level period DOTCLK low-level period DOTCLK cycle time DOTCLK,HSYNC,VSYNC rise/fall time VSYNC/HSYNC setup time min 15 15 15 15 15 15 15 15 100 15 max 15 - Unit ns ns ns ns ns ns ns ns ns ns ns VSYNC/HSYNC hold time 15 - ns DE setup time DE hold time Data setup time Data hold time DOTCLK high-level pulse period DOTCLK low-level pulse period DOTCLK cycle time DOTCLK,HSYNC,VSYNC rise/fall time 15 15 15 15 15 15 100 - 15 ns ns ns ns ns ns ns ns Description 18/16-bit bus RGB interface mode 6-bit bus RGB interface mode Note: Ta = -30 to 70 °C, VDDI=1.65V to 3.3V, VCI=2.5V to 3.3V, AGND=VSS=0V tr ≦15ns tf ≦15ns 70% 30% 70% 30% The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 239 of 240 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9341 19 Revision History Version No. Date Page V1.00 2010/10/12 All New Created. Description V1.01 2010/10/12 179 Update charge pump ratio V1.02 2010/12/17 35,195~200 V1.03 2010/12/20 196 Modify description of pumping V1.04 2010/12/24 All Update extend register and OTP flow V1.05 2011/01/05 All Update extend register V1.06 2011/01/20 16,230 V1.07 2011/02/24 199,226,227 V1.08 2011/03/04 179,196,227,228 V1.09 2011/03/15 9,159,197,199,226 V1.10 2011/04/15 226 Add description of extend register command No.75 pad location, DC Characteristics Modify register, external element. Analog supply voltage naming, external element, DDVDH Max, Modify C1h,CFh default setting Update clock timing, IC Configuration, E8h, EDh Update for general FPC application The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 240 of 240