NTHD3100C D

AND PIN A
NTHD3100C
Power MOSFET
20 V, +3.9 A /−4.4 A,
Complementary ChipFETt
Features
•
•
•
•
•
•
Complementary N−Channel and P−Channel MOSFET
Small Size, 40% Smaller than TSOP−6 Package
Leadless SMD Package Provides Great Thermal Characteristics
Trench P−Channel for Low On Resistance
Low Gate Charge N−Channel for Test Switching
Pb−Free Packages are Available
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V(BR)DSS
RDS(on) Typ
N−Channel
20 V
58 mW @ 4.5 V
P−Channel
−20 V
64 mW @ −4.5 V
Applications
•
•
•
•
DC−DC Conversion Circuits
Load Switch Applications Requiring Level Shift
Drive Small Brushless DC Motors
Ideal for Power Management Applications in Portable, Battery
Powered Products
Drain−to−Source Voltage
Gate−to−Source Voltage
N−Ch
Symbol
Value
Unit
VDSS
20
V
VGS
"12
V
P−Ch
N−Channel
Continuous Drain
Current (Note 1)
P−Channel
Continuous Drain
Current (Note 1)
Power Dissipation
(Note 1)
TA = 25°C
TA = 85°C
2.1
t ≤ 10 s
TA = 25°C
3.9
Steady
State
TA = 25°C
TA = 85°C
−2.3
t ≤ 10 s
TA = 25°C
−4.4
Steady
State
ID
ID
PD
G2
t = 10 ms
P−Ch
t = 10 ms
Operating Junction and Storage Temperature
IDM
PIN
CONNECTIONS
A
12
−55 to
150
°C
IS
2.5
A
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 seconds)
TL
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq
[1 oz] including traces).
March, 2006 − Rev. 3
MARKING
DIAGRAM
W
1.1
Source Current (Body Diode)
© Semiconductor Components Industries, LLC, 2006
ChipFET
CASE 1206A
STYLE 2
A
−3.2
−13
TJ,
TSTG
P−Channel MOSFET
1
3.1
N−Ch
N−Channel MOSFET
1
D1
8
1
S1
1
8
D1
7
2
G1
2
7
D2
6
3
S2
3
D2
5
4
G2
4
C9
M
G
C9 M
G
Pulsed Drain Current
(Note 1)
D2
S1
A
TA = 25°C
t≤5s
S2
8
2.9
−4.4 A
85 mW @ −2.5 V
G1
"8.0
Steady
State
3.9 A
77 mW @ 2.5 V
D1
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
ID MAX
6
5
= Specific Device Code
= Month Code
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Publication Order Number:
NTHD3100C/D
NTHD3100C
THERMAL RESISTANCE RATINGS
Symbol
Max
Unit
Junction−to−Ambient − Steady State (Note 2)
Parameter
RqJA
113
°C/W
Junction−to−Ambient − t ≤ 10 s (Note 2)
RqJA
60
°C/W
2. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces).
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
N/P
V(BR)DSS
N
Test Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS (Note 3)
Drain−to−Source Breakdown Voltage
VGS = 0 V
P
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
IGSS
N
VGS = 0 V, VDS = 16 V
P
VGS = 0 V, VDS = −16 V
N
VGS = 0 V, VDS = 16 V
P
VGS = 0 V, VDS = −16 V
ID = 250 mA
20
ID = −250 mA
−20
V
1.0
TJ = 25 °C
mA
−1.0
5.0
TJ = 125 °C
−5.0
N
VDS = 0 V, VGS = ±12 V
±100
P
VDS = 0 V, VGS = ±8.0 V
±100
nA
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
VGS(TH)
N
VGS = VDS
P
Drain−to−Source On Resistance
Forward Transconductance
RDS(on)
gFS
ID = 250 mA
0.6
1.2
ID = −250 mA
−.45
−1.5
N
VGS = 4.5 V , ID = 2.9 A
58
80
P
VGS = −4.5 V , ID = −3.2 A
64
80
N
VGS = 2.5 V , ID = 2.3 A
77
115
P
VGS = −2.5 V, ID = −2.2 A
85
110
N
VDS = 10 V, ID = 2.9 A
6.0
P
VDS = −10 V , ID = −3.2 A
8.0
V
mW
S
CHARGES AND CAPACITANCES
Input Capacitance
CISS
N
VDS = 10 V
165
P
VDS = −10 V
680
VDS = 10 V
80
Output Capacitance
COSS
N
VDS = −10 V
100
Reverse Transfer Capacitance
CRSS
N
VDS = 10 V
25
P
VDS = −10 V
70
P
Total Gate Charge
Threshold Gate Charge
Gate−to−Source Gate Charge
Gate−to−Drain “Miller” Charge
QG(TOT)
f = 1 MHz, VGS = 0 V
N
VGS = 4.5 V, VDS = 10 V, ID = 2.9 A
2.3
P
VGS = −4.5 V, VDS = −10 V, ID = −3.2 A
7.4
QG(TH)
N
VGS = 4.5 V, VDS = 10 V, ID = 2.9 A
0.2
P
VGS = −4.5 V, VDS = −10 V, ID = −3.2 A
0.6
QGS
N
VGS = 4.5 V, VDS = 10 V, ID = 2.9 A
0.4
P
VGS = −4.5 V, VDS = −10 V, ID = −3.2 A
1.4
N
VGS = 4.5 V, VDS = 10 V, ID = 2.9 A
0.7
P
VGS = −4.5 V, VDS = −10 V, ID = −3.2 A
2.5
QGD
3. Pulse Test: pulse width v 250 ms, duty cycle v 2%.
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2
pF
nC
NTHD3100C
ELECTRICAL CHARACTERISTICS (continued) (TJ = 25°C unless otherwise noted)
Parameter
Symbol
N/P
Test Conditions
Min
Typ
Max
Unit
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
tr
N
VGS = 4.5 V, VDD = 10 V,
ID = 2.9 A, RG = 2.5 W
td(OFF)
10.7
9.6
tf
1.5
td(ON)
5.8
tr
td(OFF)
ns
6.3
VGS = −4.5 V, VDD = −10 V,
ID = −3.2 A, RG = 2.5 W
P
tf
11.7
16
12.4
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
N
IS = 2.5 A
0.8
1.15
IS = −2.5 A
−0.8
−1.2
N
IS = 1.5 A
12.5
P
IS = −1.5 A
13.5
N
IS = 1.5 A
9.0
IS = −1.5 A
9.5
IS = 1.5 A
3.5
P
IS = −1.5 A
4.0
N
IS = 1.5 A
6.0
P
IS = −1.5 A
6.5
P
Reverse Recovery Time
Charge Time
tRR
ta
P
Discharge Time
Reverse Recovery Charge
tb
QRR
N
VGS = 0 V, TJ = 25 °C
VGS = 0 V,
dIS / dt = 100 A/ms
4. Switching characteristics are independent of operating junction temperatures.
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3
V
ns
nC
NTHD3100C
TYPICAL N−CHANNEL PERFORMANCE CURVES
(TJ = 25°C unless otherwise noted)
VGS = 5 V to 3 V
VGS = 2.4 V
2V
2.2 V
6
8
TJ = 25°C
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
8
4
1.8 V
2
1.6 V
1.4 V
2
3
5
4
6
7
4
2
8
9
0
10
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
ID = 2.9 A
TJ = 25°C
0.1
0.05
0
1
3
5
2
4
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0
6
TJ = 25°C
VGS = 2.5 V
0.07
VGS = 4.5 V
0.04
7
5
100
VGS = 0 V
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
3
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.3
1.1
0.9
−25
1
ID, DRAIN CURRENT (AMPS)
ID = 2.9 A
VGS = 4.5 V
0.7
−50
3
0.1
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
1.5
0
100°C
0.5
1
1.5
2
2.5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.15
1.7
TC = −55°C
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
1
6
25°C
0
0
VDS ≥ 10 V
0
25
50
75
100
125
150
TJ = 100°C
10
1
2
4
6
8
10
12
14
16
18
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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4
20
NTHD3100C
TYPICAL N−CHANNEL PERFORMANCE CURVES
C, CAPACITANCE (pF)
CISS
VDS = 0 V
VGS = 0 V
TJ = 25°C
300
CRSS
200
100
COSS
0
10
5
VGS
0
VDS
5
10
15
20
5
4
12
VDS
9
0
ID = 2.9 A
TJ = 25°C
0
0.5
t, TIME (ns)
IS, SOURCE CURRENT (AMPS)
tf
1
1
10
1.5
2
0
3
2.5
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
VGS = 0 V
TJ = 25°C
4
3
2
1
0
0.3
100
1
3
Qg, TOTAL GATE CHARGE (nC)
5
td(off)
td(on)
6
1
100
tr
QGD
QGS
2
Figure 7. Capacitance Variation
10
VGS
3
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VDS = 10 V
ID = 2.9 A
VGS = 4.5 V
15
QG
0.4
0.5
0.6
0.7
0.8
0.9
RG, GATE RESISTANCE (OHMS)
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
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5
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
400
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
(TJ = 25°C unless otherwise noted)
1.0
NTHD3100C
TYPICAL P−CHANNEL PERFORMANCE CURVES
(TJ = 25°C unless otherwise noted)
VGS = −5 V to −3.6 V
VGS = −3 V
−2.6 V
8
7
6
9
TJ = 25°C
−ID, DRAIN CURRENT (AMPS)
−ID, DRAIN CURRENT (AMPS)
9
−2.4 V
−2.2 V
5
4
−2 V
3
2
−1.8 V
1
−1.6 V
−1.4 V
0
1
0
2
3
4
5
6
7
8
9
7
6
5
4
3
TC = −55°C
2
1
0
10
VDS ≥ −10 V
8
25°C
0
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
3.5
0.5
1
1.5
2
2.5
3
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 12. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
Figure 11. On−Region Characteristics
0.2
ID = −3.2 A
TJ = 25°C
0.175
0.2
TJ = 25°C
0.175
0.15
0.15
VGS = −2.5 V
0.125
0.125
0.1
0.1
VGS = −4.5 V
0.075
0.075
0.05
1
3
5
2
4
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
6
0.05
2
4
6
5
7
8
Figure 14. On−Resistance vs. Drain Current
and Gate Voltage
1000
1.4
ID = −3.2 A
VGS = −4.5 V
VGS = 0 V
−IDSS, LEAKAGE (A)
1.3
3
−ID, DRAIN CURRENT (AMPS)
Figure 13. On−Resistance vs. Gate−to−Source
Voltage
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
100°C
1.2
1.1
1
0.9
TJ = 100°C
100
0.8
0.7
−50
−25
0
25
50
75
100
125
150
10
2
4
6
8
10
12
14
16
18
20
−TJ, JUNCTION TEMPERATURE (°C)
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 15. On−Resistance Variation with
Temperature
Figure 16. Drain−to−Source Leakage Current
vs. Voltage
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NTHD3100C
TYPICAL P−CHANNEL PERFORMANCE CURVES
VGS = 0 V
TJ = 25°C
Ciss
1200
900
VDS = 0 V
600
Crss
300
Coss
0
5
−VGS
0
−VDS
5
10
15
20
10
5
QT
4 −V
DS
6
3
Qgs
2
4
2
0
ID = −3.2 A
TJ = 25°C
0
2
4
6
8
0
Qg, TOTAL GATE CHARGE (nC)
Figure 18. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
Figure 17. Capacitance Variation
1000
5
−IS, SOURCE CURRENT (AMPS)
VDS = −10 V
ID = −3.2 A
VGS = −4.5 V
td(off)
100
t, TIME (ns)
Qgd
1
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
tf
tr
td(on)
10
1
1
8
−VGS
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
1500
−VGS, GATE−TO−SOURCE VOLTAGE (V)
(TJ = 25°C unless otherwise noted)
10
100
VGS = 0 V
TJ = 25°C
4
3
2
1
0
0.3
0.6
0.9
RG, GATE RESISTANCE (OHMS)
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 19. Resistive Switching Time Variation
vs. Gate Resistance
Figure 20. Diode Forward Voltage vs. Current
1.2
DEVICE ORDERING INFORMATION
Package
Shipping †
NTHD3100CT1
ChipFET
3000 / Tape & Reel
NTHD3100CT1G
ChipFET
(Pb−Free)
3000 / Tape & Reel
NTHD3100CT3
ChipFET
10000 / Tape & Reel
NTHD3100CT3G
ChipFET
(Pb−Free)
10000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
NTHD3100C
PACKAGE DIMENSIONS
ChipFET]
CASE 1206A−03
ISSUE G
D
8
7
q
6
L
5
HE
1
e1
5
6
7
8
4
3
2
1
E
2
3
e
4
b
c
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL
AND VERTICAL SHALL NOT EXCEED 0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD
SURFACE.
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
DIM
A
b
c
D
E
e
e1
L
HE
q
MILLIMETERS
NOM
MAX
1.05
1.10
0.30
0.35
0.15
0.20
3.05
3.10
1.65
1.70
0.65 BSC
0.55 BSC
0.28
0.35
0.42
1.80
1.90
2.00
5° NOM
MIN
1.00
0.25
0.10
2.95
1.55
INCHES
NOM
0.041
0.012
0.006
0.120
0.065
0.025 BSC
0.022 BSC
0.011
0.014
0.071
0.075
5° NOM
MIN
0.039
0.010
0.004
0.116
0.061
MAX
0.043
0.014
0.008
0.122
0.067
0.017
0.079
0.05 (0.002)
SOLDERING FOOTPRINT*
2.032
0.08
1.092
0.043
0.635
0.025
0.178
0.007
0.457
0.018
0.254
0.010
0.66
0.026
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ChipFET is a trademark of Vishay Siliconix.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer
purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Literature Distribution Center for ON Semiconductor
USA/Canada
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Phone: 81−3−5773−3850
Email: [email protected]
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Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
NTHD3100C/D