INTEGRATED CIRCUITS
DATA SHEET
PCD5013
FLEX roaming decoder II
Product specification
Supersedes data of 1999 Mar 15
File under Integrated Circuits, IC17
1999 Apr 12
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
CONTENTS
1
FEATURES
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
QUICK REFERENCE DATA
5
ORDERING INFORMATION
6
BLOCK DIAGRAM
7
PINNING
8
FUNCTIONAL DESCRIPTION
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
General
Clocking, reset and start-up
Serial Peripheral Interface (SPI)
Configuration and synchronisation
Receiver control interface
Configuration of the FLEX CAPCODE
Call data packets
Message reception
9
LIMITING VALUES
10
HANDLING
11
THERMAL CHARACTERISTICS
12
DC CHARACTERISTICS
13
AC CHARACTERISTICS
14
OSCILLATOR CHARACTERISTICS
15
TEST AND APPLICATION INFORMATION
15.1
15.2
15.3
FLEX protocol
Example applications
System block diagram
16
PACKAGE OUTLINE
17
SOLDERING
17.1
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
17.2
17.3
17.4
17.5
18
DEFINITIONS
19
LIFE SUPPORT APPLICATIONS
1999 Apr 12
2
Philips Semiconductors
Product specification
FLEX roaming decoder II
1
PCD5013
2
FEATURES
APPLICATIONS
• FLEX paging protocol decoder
• Numeric FLEX pagers
• 16 programmable user address words
• Alphanumeric FLEX pagers
• 16 fixed temporary addresses
• Roaming FLEX pagers
• 16 operator messaging addresses
• Remote metering
• 1600, 3200 and 6400 bits/s decoding
• Car security systems
• Any-phase or single-phase decoding
• Personal digital assistants.
• Uses standard Serial Peripheral Interface (SPI) in slave
mode
3
• SSID and NID roaming support
This data sheet describes the operation of the PCD5013
integrated paging decoder. It is fully compatible with other
FLEXchip ICs including the PCD5008.
• Backward compatible to the standard and roaming
FLEX decoder ICs
• Allows low current power-down mode operation of host
processor
The PCD5013, also referred to as the decoder, simplifies
implementation of a FLEX paging device, by being able
to interface with several off-the-shelf paging receivers and
host microcontrollers/processors. Its primary function is to
process information received and demodulated from a
FLEX radio paging channel, select messages addressed
to the paging device and communicate the message
information to the host.
• Highly programmable receiver control
• Real-time clock time base
• FLEX fragmentation and group messaging support
• Real-time clock over-the-air update support
• Compatible with synthesized receivers
• Low battery indication (external detector)
The PCD5013 fully supports the FLEX protocol
(version G1.9) including all roaming aspects.
• Low cost LQFP32 plastic package
• Optional internal 4-level FSK demodulator and data
slicer
Motorola FLEXstack software, installed on the product
host processor, communicates with the PCD5013 and
interprets the codewords that are passed to the host.
• Operates using a 76.8 or 160 kHz crystal
• Very low power consumption
The PCD5013 operates the paging receiver in an efficient
power consumption mode and enables the host to operate
in a low-power mode when monitoring a single channel for
message information.
• Operates at low supply voltage
• Full support for revision 1.9 of the FLEX protocol.
4
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VDD
supply voltage
IDD
supply current
Tamb
operating ambient temperature
fEXTAL
external clock frequency
5
GENERAL DESCRIPTION
CONDITIONS
see Chapters 12 and 14
MIN.
TYP.
MAX.
UNIT
1.8
2.2
3.6
V
−
6.0
−
µA
−25
+25
+70
°C
internal demodulator not in use
−
76.8
−
kHz
internal demodulator in use
−
160.0 −
kHz
ORDERING INFORMATION
TYPE
NUMBER
PCD5013H
1999 Apr 12
PACKAGE
NAME
LQFP32
DESCRIPTION
plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm
3
VERSION
SOT358-1
Philips Semiconductors
Product specification
FLEX roaming decoder II
6
PCD5013
BLOCK DIAGRAM
handbook, full pagewidth
S1
S2
S3
S4
S5
S6
S7
22
21
20
19
PCD5013
RECEIVER
CONTROL
18
16
15
S0
S0/IFIN
EXTS0
EXTS1
SYMCLK
OSCPD
XTAL
EXTAL
CLKOUT
23
IFIN
INTERNAL
CONTROL
UNIT
DEMODULATOR
&
DATA SLICER
12
3, 13
11
SYMBOL
SYNC
14
NOISE
DETECTOR
7, 29
VSS1, VSS2
2
5
6
32
76.8 kHz
OR 160 kHz
OSCILLATOR
4
SYNC
CORRELATOR
CLOCK
GENERATOR
1
TOUT0
25
DEINTERLEAVER
ERROR
CORRECTOR
ADDRESS
COMPARATOR/
CORRELATOR
LOCAL
MESSAGE
FILTER
TOUT1
17
TOUT2
8
EXTERNAL
CONTROL
UNIT
9
10
26
SPI
27
28
SS
TOUT3
24
TEST3
RESET
LOBAT
30
READY
31
MOSI
SCK
MISO
Fig.1 Functional block diagram for PCD5013 pager decoder.
4
TEST2
CONTROL/STATUS
REGISTERS
SPI
BUFFER
1999 Apr 12
VDD1, VDD2
MGR616
Philips Semiconductors
Product specification
FLEX roaming decoder II
7
PCD5013
PINNING
SYMBOL
PIN
I/O
DESCRIPTION
TOUT0
1
O
3-state test output; note 1
OSCPD
2
I
internal oscillator power-down; connected to VSS when using the internal oscillator,
connected to VDD when using an external source
VDD1
3
−
supply voltage
TEST2
4
I
manufacturing test mode input pin; has to be connected to VSS
XTAL
5
O
76.8 or 160 kHz crystal oscillator output
EXTAL
6
I
76.8 or 160 kHz crystal oscillator input or external clock input
VSS1
7
−
ground supply
TEST3
8
I
manufacturing test mode input pin; has to be connected to VSS
TOUT3
9
O
3-state test output; note 1
LOBAT
10
I
low battery voltage detect input
EXTS1
11
I
most significant bit (MSB) of the symbol currently being decoded
EXTS0
12
I
least significant bit (LSB) of the symbol currently being decoded
VDD2
13
−
supply voltage
SYMCLK
14
O
recovered symbol clock output
S7
15
O
receiver control output port, 3-state
S6
16
O
receiver control output port, 3-state
TOUT2
17
O
3-state test output; note 1
S5
18
O
receiver control output port, 3-state
S4
19
O
receiver control output port, 3-state
S3
20
O
receiver control output port, 3-state
S2
21
O
receiver control output port, 3-state
S1
22
O
receiver control output port, 3-state
S0/IFIN
23
I/O
receiver control output port, 3-state when using external demodulator; limited
IF input 455 or 140 kHz when using internal demodulator
RESET
24
I
active LOW reset input
TOUT1
25
O
3-state test output; note 1
READY
26
O
output driven LOW when the PCD5013 is ready for an SPI packet
SS
27
I
slave select input for SPI communications
SCK
28
I
serial clock input for SPI communications
VSS2
29
−
ground supply
MOSI
30
I
data input for SPI communications
MISO
31
O
data output for SPI communications, 3-state
CLKOUT
32
O
38.4 kHz clock output (derived from 76.8 kHz oscillator); note 2
Notes
1. These test outputs may be either left unconnected or connected to VSS in the application.
2. For a 160 kHz oscillator either a 38.4 or a 40 kHz output frequency can be selected. See Section 8.4.4.
1999 Apr 12
5
Philips Semiconductors
Product specification
25 TOUT1
26 READY
27 SS
28 SCK
29 VSS2
30 MOSI
handbook, full pagewidth
31 MISO
PCD5013
32 CLKOUT
FLEX roaming decoder II
TOUT0
1
24 RESET
OSCPD
2
23 S0/IFIN
VDD1
3
22 S1
TEST2
4
21 S2
PCD5013
18 S5
TEST3
8
17 TOUT2
TOUT3
Fig.2 Pin configuration.
1999 Apr 12
6
S6 16
7
S7 15
VSS1
SYMCLK 14
19 S4
VDD2 13
6
EXTS0 12
EXTAL
EXTS1 11
20 S3
LOBAT 10
5
9
XTAL
MGR619
Philips Semiconductors
Product specification
FLEX roaming decoder II
8
8.1
PCD5013
host.The host can use receiver control lines which are not
required by the receiver as expansion ports to control other
peripheral devices.
FUNCTIONAL DESCRIPTION
General
The PCD5013 simplifies implementation of a FLEX
paging device by interfacing with off-the-shelf components
such as a paging receiver and a microcontroller or
microprocessor (called a host). The PCD5013 is fully
compatible with FLEXstack software which provides a
complete, platform independent, software driver for the
PCD5013.
8.2
8.2.1
OSCILLATOR
The PCD5013 uses an inverting crystal oscillator.
The clock signal for the internal circuitry is derived via an
amplifier from the oscillator input pin EXTAL. Alternatively,
an external clock signal can be fed in at input pin EXTAL.
In this case the internal oscillator can be disabled by
pulling the OSCPD input pin HIGH. This reduces current
consumption and routes EXTAL directly to the internal
clock signal. When using a crystal, an external feedback
resistor and the load capacitances need to be connected
to pins EXTAL and XTAL (Fig.19). See Chapter 14 for the
recommended crystal parameters and the specification of
the oscillator transconductance to guarantee correct
start-up.
The PCD5013 fully supports all aspects of the FLEX
protocol (version G1.9), and can operate in either
single-phase or any-phase mode. The PCD5013 supports
FLEX dynamic grouping, allowing up to 16 temporary
addresses to be enabled simultaneously. It is also capable
of retrieving real time information from a FLEX channel.
The PCD5013 connects to any receiver capable of
providing a 2-bit digital signal. The PCD5013 operates the
paging receiver in an efficient power consumption mode.
The PCD5013 has 8 receiver control lines used for
warming up, operating and shutting down a receiver in
stages.
The PCD5013 oscillator can operate at either 76.8 kHz or
160 kHz by selecting the appropriate crystal. The choice of
frequency is determined by the setting of the IDE bit in the
configuration packet; see Section 8.4.4.
The PCD5013 has the ability to detect a battery-low signal
from an external detector during the receiver control
sequences.
8.2.2
The PCD5013 carries out the following functions:
RESET AND START-UP CONDITIONS
The PCD5013 is reset by pulling the RESET input LOW.
After releasing the RESET by pulling it HIGH, the
PCD5013 counts 76 800 clock cycles (independent of the
oscillator frequency) before pulling READY LOW to
indicate that the decoder is ready for configuration via
the SPI.
• Synchronises to a FLEX data stream
• Processes received, demodulated information
• Performs de-interleaving and error correction
• Selects calls addressed to the paging device using up to
16 programmable addresses
See Fig.3 and Chapter 13 for the PCD5013 timing
specifications when power is applied.
• Communicates the message information to the host.
The PCD5013 interfaces to a host through a serial
peripheral interface (SPI). The host can then interpret the
message information in an appropriate manner (numeric,
alphanumeric, binary, etc.). This function is provided by
the FLEXstack software.
See Fig.4 and Chapter 13 for the PCD5013 timing
specifications when it is reset.
After switch-on, the PCD5013 operates in Asynchronous
mode, periodically sampling the channel for incoming
data. As soon as data is detected, the PCD5013 maintains
the receiver on to synchronize to the channel. Once the
pager is synchronized to the channel it enters
Synchronous mode, switching the receiver on only for the
programmed frames.
When configured to use the internal demodulator, the
PCD5013 connects to a receiver capable of generating a
limited (i.e. 1-bit digitized) 455 or 140 kHz IF signal
(IF frequency automatically detected).
The PCD5013 enables the host to operate in a low-power
mode when monitoring a single channel for message
information. It has a 38.4 kHz clock output (40 kHz
available when using the internal demodulator) capable of
driving other devices, and has a 1-minute timer that offers
low-power support for a real-time clock function on the
1999 Apr 12
Clocking, reset and start-up
When the receiver is programmed for Roaming operation,
the PCD5013 sends information which allows the host to
calculate when to switch frequencies in a roaming
network.
7
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
handbook, full pagewidth
VDD
tstrt(osc)
oscillator
RESET
READY
tWUL(osc-READY)
tHL(RESET-READY)
th(rst)
MBK031
Fig.3 Start-up timing.
handbook, full pagewidth
RESET
tW(rst)
READY
tHL(RESET-READY)
tLH(RESET-READY)
MBK033
Fig.4 Reset timing.
1999 Apr 12
8
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.3
8.3.1
PCD5013
2. The PCD5013 indicates that it is ready to start the
SPI transfer by driving the READY pin LOW.
Serial Peripheral Interface (SPI)
GENERAL
3. The host clocks each of the 32 bits of the SPI packet
by pulsing SCK. Both the host and the PCD5013
sample data on the rising edge of SCK. Packets are
sent MSB first.
All data communication between the PCD5013 and the
host is done via the SPI using 32-bit data packets at data
rates up to 1 Mbits/s. SPI transfers are full-duplex and can
be initiated by either the host which acts as the SPI master
providing the data clock for packet transfer, or the
PCD5013 as an SPI slave.
4. The PCD5013 pulls the READY line HIGH, to indicate
that the transfer is complete.
5. The host waits until the READY line is pulled HIGH,
then de-selects the PCD5013 SPI by driving the
SS pin HIGH.
The host can send packets to configure or control the
PCD5013 or a checksum packet to validate SPI
communication (Section 8.4.2). The PCD5013 buffers
data packets, relating to received data, into a 32 packet
transmit buffer. The PCD5013 can send either a status
packet, a part ID packet, or packets from the transmit
buffer. In the event of a buffer overflow, the PCD5013
stops decoding and clears the transmit buffer.
8.3.2
6. The first 5 steps are repeated for each additional
packet.
8.3.4
SPI TRANSFER INITIATED BY THE DECODER
The following steps occur when the PCD5013 initiates an
SPI packet transfer, see Fig.6 for event timings:
SPI INTERCONNECT
1. The PCD5013 initiates the SPI transfer by driving the
READY pin LOW.
Connection on the PCD5013 consists of a READY pin and
4 SPI pins (SS, SCK, MOSI and MISO):
2. If the PCD5013 is not already selected, the host
selects the PCD5013 SPI by driving the SS pin LOW.
READY: output signal; indicates that data is available
from the PCD5013
SCK: serial clock; output from the host used for clocking
data
3. The host clocks each of the 32 bits of the SPI packet
by pulsing SCK. Both the host and the PCD5013
sample data on the rising edge of SCK. Packets are
sent MSB first.
MOSI: master output slave input; data output from the
host
4. The PCD5013 pulls the READY line HIGH, to indicate
that the transfer is complete.
SS: SPI select; used as PCD5013 chip select
5. The host may then either de-select the SPI interface of
the PCD5013 (Fig.7) by driving the SS pin HIGH or
maintain SS LOW to continue sending packets to the
PCD5013.
MISO: master input slave output; data output from the
PCD5013.
8.3.3
SPI TRANSFER INITIATED BY THE HOST
The following steps occur when the host initiates an SPI
packet transfer, see Fig.5 for event timings:
1. The host selects the PCD5013 by driving the
SS pin LOW.
1999 Apr 12
9
Philips Semiconductors
Product specification
FLEX roaming decoder II
handbook, full pagewidth
SS
(1)
READY
(5)
(2)
SCK
(4)
(3)
MOSI
MISO
PCD5013
Zo(off)
D31
D1
D0
D31
D1
D0
Zo(off)
D31
D1
D0
D31
D1
D0
Zo(off)
D31
D1
D0
D31
D1
D0
Zo(off)
MGK262
Numbers within parenthesis refer to sequence numbers, see Section 8.3.3.
Fig.5 Typical multiple SPI transfers initiated by the host.
handbook, full pagewidth
SS
READY
(2)
(1)
SCK
(4)
(3)
MOSI
MISO
(5)
Zo(off)
D31
D1
D0
D31
D1
D0
Zo(off)
D31
D1
D0
D31
D1
D0
Zo(off)
D31
D1
D0
D31
D1
D0
Zo(off)
MGK263
Numbers within parenthesis refer to sequence numbers, see Section 8.3.4.
Fig.6 Typical multiple SPI transfers initiated by the PCD5013.
1999 Apr 12
10
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
handbook, full pagewidth
SS
READY
SCK
MOSI
MISO
Zo(off)
D31
D1
D0
D31
D1
D0
D31
D1
D0
D31
D1
D0
D31
D1
D0
D31
D1
D0
MGK264
Fig.7 Multiple SPI transfers initiated by the PCD5013 with SS maintained LOW.
1999 Apr 12
11
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.3.5
PCD5013
SPI PACKET FORMAT
8.3.6
SPI data packets consist of an 8-bit ID (byte 3), followed
by 24 bits of information (byte 2 to byte 0). See Table 1,
note that bit 7 of byte 3 is the first bit on the bus.
Table 1
SPI TIMING
See Fig.8 and Chapter 13 for the timing specifications of
the SPI.
Packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
D31
D30
D29
D28
D27
D26
D25
D24
2
D23
D22
D21
D20
D19
D18
D17
D16
1
D15
D14
D13
D12
D11
D10
D9
D8
0
D7
D6
D5
D4
D3
D2
D1
D0
handbook, full pagewidth
SS
tSSH
READY
tREADYH
td(SS-READY)
tLAG2
tLEAD2
tLEAD1
Tcy(SCK)
tr
tf
tLAG1
SCK
tSCKL
MISO
Zo(off)
tSCKH
D31
tDOV
tACC(o)
MOSI
D0
D31
tsu(i)(D)
D0
MBK032
th(i)(D)
Fig.8 SPI timing.
1999 Apr 12
to(dis)
th(o)(D)
12
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.3.7
PCD5013
HOST-TO-DECODER PACKETS OVERVIEW
This section summarises the packets which can be sent from the host to the decoder.
Table 2
Host-to-decoder packet ID map2
PACKET
ID (HEX)
TYPE
SECTION
00
checksum
8.4.6
01
configuration
8.4.4
02
control
8.4.7
03
all frame mode
8.8.4
04
operator message address enable
8.6.9
05
roaming control
8.4.9
06
timing control
8.4.10
07 to 0E
reserved (host should never send)
−
0F
receiver line control
8.5.7
10
receiver control configuration (off setting)
8.5.4
11
receiver control configuration (warm-up 1 setting)
8.5.5.3
12
receiver control configuration (warm-up 2 setting)
8.5.5.3
13
receiver control configuration (warm-up 3 setting)
8.5.5.3
14
receiver control configuration (warm-up 4 setting)
8.5.5.3
15
receiver control configuration (warm-up 5 setting)
8.5.5.3
16
receiver control configuration (3200 sps sync setting)
8.5.6.2
17
receiver control configuration (1600 sps sync setting)
8.5.6.2
18
receiver control configuration (3200 sps data setting)
8.5.6.2
19
receiver control configuration (1600 sps data setting)
8.5.6.2
1A
receiver control configuration (shut-down 1 setting)
8.5.8.1
1B
receiver control configuration (shut-down 2 setting)
8.5.8.1
1C to 1F
special (ignored by decoder)
−
20
frame assignment (frames 112 to 127)
8.6.7
21
frame assignment (frames 96 to 111)
8.6.7
22
frame assignment (frames 80 to 95)
8.6.7
23
frame assignment (frames 64 to 79)
8.6.7
24
frame assignment (frames 48 to 63)
8.6.7
25
frame assignment (frames 32 to 47)
8.6.7
26
frame assignment (frames 16 to 31)
8.6.7
27
frame assignment (frames 0 to 15)
8.6.7
28 to 77
reserved (host should never send)
−
78
user address enable
8.6.6
79 to 7F
reserved (host should never send)
−
80
user address assignment (user address 0)
8.6.6
81
user address assignment (user address 1)
8.6.6
82
user address assignment (user address 2)
8.6.6
1999 Apr 12
13
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
PACKET
ID (HEX)
TYPE
SECTION
83
user address assignment (user address 3)
8.6.6
84
user address assignment (user address 4)
8.6.6
85
user address assignment (user address 5)
8.6.6
86
user address assignment (user address 6)
8.6.6
87
user address assignment (user address 7)
8.6.6
88
user address assignment (user address 8)
8.6.6
89
user address assignment (user address 9)
8.6.6
8A
user address assignment (user address 10)
8.6.6
8B
user address assignment (user address 11)
8.6.6
8C
user address assignment (user address 12)
8.6.6
8D
user address assignment (user address 13)
8.6.6
8E
user address assignment (user address 14)
8.6.6
8F
user address assignment (user address 15)
8.6.6
90 to FF
reserved (host should never send)
−
8.3.8
DECODER-TO-HOST PACKETS OVERVIEW
This section summarises the packets which can be sent from the PCD5013 to the host (Table 3).
Table 3
Decoder-to-host packet ID map
PACKET
ID (HEX)
TYPE
SECTION
00
block information word
8.7.9
01
address
8.7.2
02 to 57
vector or message (ID is word number in frame)
8.7.3 and 8.7.8
58 to 5F
reserved
−
60
roaming status
8.4.13
61 to 7D
reserved
−
7E
receiver shutdown
8.4.12
7F
status
8.4.11
80 to FE
reserved
−
FF
part ID
8.4.5
1999 Apr 12
14
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.4
8.4.1
PCD5013
sending a checksum packet for which the checksum value
matches the checksum register.
Configuration and synchronisation
GENERAL
Checksum packets sent when the SPI transmit is enabled,
are ignored by the PCD5013 irrespective of the value of
the checksum packet data bits. Thus when the PCD5013
initiates an SPI transfer and the host has no data to send,
the host should send the checksum packet so as not to
disable the SPI transmit. The data in the checksum packet
could be a null packet (32-bit stream of all zeros).
After a reset, all configuration data has to be (re)loaded
into the PCD5013 by the host using the SPI. PCD5013
features which do not change during operation are
configured using the configuration packet (Section 8.4.4),
the receiver control packets (Section 8.5) and the address
configuration packets (Section 8.6). PCD5013 features
which can be changed during operation are configured
using the control packet. The checksum packet ensures
proper communication between the host and the
PCD5013.
8.4.2
Sending a packet other than the checksum packet when
the SPI transmit is enabled causes the SPI transmit to be
disabled until a checksum packet is sent with the correct
value. Thus when the host re-configures the PCD5013
after a reset, the SPI transmit is disabled until the host
sends a checksum packet at the end of the configuration
data, with the checksum value equal to the result of
XORing together the data bits of each of the configuring
packets and the data bits of the part ID packet.
SPI SECURITY ALGORITHM
The PCD5013 provides a security algorithm to verify
correct SPI operation (Figs 9 and 10). The PCD5013
maintains a checksum register equal to the result of
XORing the 24 data bits of every packet it receives, except
the checksum packet 00H and special packets
1CH to 1FH. When the PCD5013 is reset, the internal
checksum register is initialized to the 24-bit part ID defined
in the part ID packet.
If the SPI transmit is enabled and a receiver shutdown
packet is pending, the receiver shutdown packet is sent. If
there is no receiver shutdown packet pending, but there is
a roaming status packet pending, the roaming status
packet is sent. If neither the receiver shutdown packet nor
the roaming status packet is pending and there is data in
the transmit buffer, the PCD5013 initiates an SPI transfer
sending a packet from its transmit buffer. The PCD5013
sends the status packet (which is not buffered) when the
host initiates an SPI transfer and the transmit buffer is
empty.
Immediately following a reset and whenever the host
sends a packet other than a checksum packet, the
SPI output of status and data (SPI transmit) is disabled.
The PCD5013 then initiates SPI transfers continuously,
sending the part ID packet (Section 8.4.5). Note that when
SPI transmit is disabled all decoding and timing functions
are unaffected. The SPI transmit can be enabled by
handbook, full pagewidth
PART ID REGISTER
RECEIVER SHUTDOWN REGISTER
ROAMING STATUS REGISTER
32 × 32 DATA PACKET
FIFO TRANSMIT
BUFFER
32
32
32
MUX
32
32
SPI TRANSMIT REGISTER
MGR618
STATUS REGISTER
32
SPI
SECURITY
ALGORITHM
Fig.9 SPI transmit functional block diagram.
1999 Apr 12
15
MISO
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
handbook, full pagewidth
reset
PCD5013 disables
SPI transmit
PCD5013 initializes
checksum register
to part ID value
PCD5013 initiates
part ID packet
PCD5013 waits for
SPI packet from host
Y
Y
checksum packet?
PCD5013
SPI transmit
enabled?
PCD5013 disables
SPI transmit
PCD5013 sets
checksum registers to
the XOR of the packet
data bits with the
checksum register bits
N
packet data
matches checksum
register data?
N
N
MGR617
Y
PCD5013 enables
SPI transmit
Fig.10 SPI security algorithm.
1999 Apr 12
16
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.4.3
PCD5013
5. At the end of each packet the PCD5013 pulls the
READY line HIGH, and then LOW again to indicate
that packet processing is complete.
CONFIGURATION SEQUENCE
A typical configuration and synchronisation sequence
would be as follows, see Fig.11 for event timings:
1. The PCD5013 is reset by the host.
6. The host writes a control packet to enable FLEX
decoding in the PCD5013 (Section 8.4.7).
2. After 76800 clock cycles the PCD5013 interrupts the
host to read the part ID by pulling the READY
line LOW.
7. The host writes a checksum packet to enable SPI data
output by the PCD5013 (Section 8.4.2).
8. On recognising a SYNC word, the PCD5013
synchronises to the channel.
3. The host pulls SS LOW at the start of each
SPI transfer and clocks out the part ID data.
9. The PCD5013 initiates an SPI transfer writing the
status packet, indicating that it is now in synchronous
mode.
4. The host configures the following aspects of PCD5013
operation:
a) General configuration (Section 8.4.4)
b) Receiver operation (Section 8.5)
c) FLEX CAPCODE configuration (Section 8.6).
The PCD5013 writes a part ID packet in response to
each incoming packet.
configuration packets
(addresses, receiver etc.)
handbook, full pagewidth
control packet (6)
checksum packet (7)
SPI
HOST-TO-DECODER
partid packet (4)
status packet (9)
SPI
DECODER-TO-HOST
partid packet (4)
RESET
(1)
(5)
READY
SS
(5)
(5)
(2)
(3)
(8)
FLEX DATASTREAM
SYNC
MBK097
Numbers within parenthesis refer to sequence numbers, see Section 8.4.3.
Fig.11 Typical configuration and synchronization sequence.
1999 Apr 12
17
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.4.4
PCD5013
SP: signal polarity (Tables 8, 5 and 6). These bits set the
polarity of EXTS1 and EXTS0 input signals. The polarity of
the EXTS1 and EXTS0 bits is determined by the receiver
design. Value after reset = 0.
CONFIGURATION PACKET (ID = 01H)
The configuration packet defines a number of different
configuration options for the PCD5013. The PCD5013
ignores this packet when decoding is enabled,
i.e. the ON bit in the control packet is set (Table 12).
Table 5
DFC: disable fractional clock (Table 8). When this bit is set
and IDE is set, the CLKOUT signal generates a 40 kHz
signal (EXTAL divided-by-4). When this bit is cleared and
IDE is set, the CLKOUT signal generates a 38.4 kHz signal
(EXTAL fractionally divided by 25⁄6). This bit has no effect
when IDE is cleared. Value after reset = 0.
SIGNAL POLARITY
IDE: internal demodulator enable (Table 8). When this bit
is set, the internal demodulator is enabled and the clock
frequency at EXTAL is expected to be 160 kHz. When this
bit is cleared, the internal demodulator is disabled and the
clock frequency at EXTAL is expected to be 76.8 kHz.
Value after reset = 0.
0
0
±300
0
1
±150
1
0
±75
1
1
±0
0
normal
normal
0
1
normal
inverted
1
0
inverted
normal
1
1
inverted
inverted
EXTS0
FLEX 4 level FSK modulation (SP = 00)
EXTS1
EXTS0
DEVIATION
(Hz)
1
0
+4800
1
1
+1600
0
1
−1600
0
0
−4800
• Setting and clearing this bit can cause pulses on the
CLKOUT pin that are less than one half the 38.4 kHz
period.
• When the clock output is enabled and not set for
intermittent operation (see ICO in this packet), the
CLKOUT pin always outputs the clock signal even when
the PCD5013 is in reset (as long as a clock signal is
available to the PCD5013 oscillator).
PCE: partial correlation enable (Table 8). When this bit is
set, partial correlation of addresses is enabled. When
partial correlation is enabled, the PCD5013 shuts down
the receiver before the end of the last FLEX block which
contains addresses if it can determine that none of the
addresses in that FLEX block matches any enabled
address in the PCD5013. When this bit is cleared, the
receiver is controlled as in the PCD5008. Value after
reset = 0.
1999 Apr 12
0
EXTS1
COD: clock output disable (Table 8). When this bit is
cleared, a 38.4 or 40 kHz signal is output on the
CLKOUT pin (depending on the values of IDE and DFC).
When this bit is set, the CLKOUT pin is driven LOW. Value
after reset = 0.
FREQUENCY DIFFERENCE
(ppm)
OFD0
SP0
SME: synchronous mode enable (Table 8). When this bit
is set, a status packet is sent automatically whenever the
synchronous mode update (SMU) bit in the status packet
is set. This happens whenever a change occurs in the
synchronous mode (SM) status bit, which indicates that
the decoder is synchronized to a FLEX data stream.
The host can use the SM bit in the status packet as an
in-range/out-of-range indication. Value after reset = 0.
Oscillator frequency difference
OFD1
SP1
Table 6
OFD: oscillator frequency difference (Tables 4 and 8).
These bits represent the maximum frequency difference
between the 76.8 kHz oscillator (accounting for ageing,
temperature variation, manufacturing tolerance etc.) and
the worst case transmitter bit rate (specified as ±25 parts
per million (ppm) in the FLEX specification).
For example, if the transmitter tolerance is ±25 ppm and
the 76.8 kHz oscillator tolerance is ±140 ppm, the
transmitter-oscillator frequency difference is ±165 ppm
and OFD should be cleared (300 ppm maximum). Value
after reset = 0. Note that configuring a smaller frequency
difference in this packet results in lower power
consumption due to higher receiver battery save ratios.
Table 4
Input signal polarity
• When the PCD5013 is used in internal demodulator
mode (i.e. uses a 160 kHz oscillator), the CLKOUT pin
is 80 kHz from reset until the time the IDE bit is set.
18
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
Note that when the clock is automatically enabled and
disabled (i.e. when ICO is set), the CLKOUT signal
transitions are clean (i.e. no pulses less than half the clock
period) when it transitions between no clock and clocked
output. This bit has no effect when COD is set. Value after
reset = 0.
LBP: low battery polarity (Table 8). This bit defines the
polarity of the PCD5013’s LOBAT pin: When this bit is set,
a HIGH at input LOBAT represents a low battery condition.
The LB bit in the status packet is initialized to the inverse
(i.e. inactive) value of the LBP bit when the PCD5013 is
turned on (by setting the ON bit in the control packet).
When the PCD5013 is turned on, the first low battery
update in the status packet is sent to the host when a low
battery condition is detected on the LOBAT pin. Value
after reset = 0.
8.4.5
The part ID packet is output by the PCD5013 SPI
whenever the SPI transmit is disabled due to the
checksum feature. The value of the part ID packet for the
PCD5013 is FF000308H.
MOT: maximum off time (Table 8). When this bit is set, the
PCD5013 assumes that the service provider leaves up to
1 minute between transmitted frames. When this bit is
clear, the PCD5013 assumes that there can be up to
4 minutes between transmitted frames. This bit has no
effect if AST in the Timing Control Packet is non-zero.
Value after reset = 0.
MDL: model (Table 9). The PCD5013 model value is 0.
CID: compatibility ID (Table 9). This value describes other
parts with the same model number, which are compatible
with this part.
MTE: minute timer enable (Table 8). When this bit is set,
a status packet is sent at one minute intervals with the
minute time-out (MT) bit in the status packet set. When
this bit is clear, the internal 1-minute timer stops counting.
See Section 8.4.8 for details of 1-minute timer operation.
Note that the minute timer is not accurate using a 160 kHz
oscillator until the IDE bit is set. Value after reset = 0.
Table 7
CID Compatibilities
BIT
COMPATIBILITY
VALUE FOR
PCD5013
CID0 Alphanumeric Decoder I
ICO: intermittent clock out (Table 8). When this bit is clear
and COD is clear, a 38.4 or 40 kHz (depending on the
values of IDE and DFC) signal is output on the CLKOUT
pin. When this bit is set and COD is clear, the clock is only
output on the CLKOUT pin while the receiver is not in the
Off state. The clock is output for a few cycles before the
receiver transitions from the off state and for a few cycles
after the receiver transitions to the off state (this is to insure
that the receiver receives enough clocks to detect and
process the changes to and from the off state).
The CLKOUT pin is driven LOW when it is not driving a
clock.
Table 8
PART ID PACKET (ID = FFH)
1 (true)
CID1 Roaming Decoder I
1 (true)
CID2 Numeric Decoder
0 (false)
REV: revision (Table 9). This identifies the manufacturing
version of the PCD5013. For the PCD5013 the value is 8.
8.4.6
CHECKSUM PACKET (ID = 00H)
See Table 10 for checksum packet bit assignment.
CV: checksum value (24 bits), see Section 8.4.2.
Configuration packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
0
0
0
0
0
0
0
1
2
0
DFC
0
0
0
IDE
OFD1
OFD0
1
0
0
0
0
0
PCE
SP1
SP0
0
SME
MOT
COD
MTE
LBP
ICO
0
0
1999 Apr 12
19
Philips Semiconductors
Product specification
FLEX roaming decoder II
Table 9
PCD5013
Part ID packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
1
1
1
1
1
1
1
1
2
MDL1
MDL0
CID13
CID12
CID11
CID10
CID9
CID8
1
CID7
CID6
CID5
CID4
CID3
CID2
CID1
CID0
0
REV7
REV6
REV5
REV4
REV3
REV2
REV1
REV0
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Table 10 Checksum packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
3
0
0
0
0
0
0
0
0
2
CV23
CV22
CV21
CV20
CV19
CV18
CV17
CV16
1
CV15
CV14
CV13
CV12
CV11
CV10
CV9
CV8
0
CV7
CV6
CV5
CV4
CV3
CV2
CV1
CV0
1999 Apr 12
20
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.4.7
PCD5013
SBI: send block information words (BIW) 2 to 4
(Table 12). When this bit is set, BIWs with time and date
information and BIWs received in error are sent to the host,
(Section 8.7.9). Value after reset = 0.
CONTROL PACKET (ID = 02H)
The control packet defines a number of different control
bits for the PCD5013.
FF: force frame 0 to 7 (Table 12). When set, each of these
bits forces the PCD5013 to decode one of the FLEX
frames 0 to 7 irrespective of the system collapse value (for
details of collapse values see Section 8.6.2). For example,
if the system collapse causes the PCD5013 to decode
frames 0, 32, 64 and 96, setting FF2 causes the PCD5013
to also decode FLEX frame 2. This may be used to
acquire transmitted time information or channel attributes
(e.g. Local ID). Value after reset = 0.
MTC: minute timer clear (Table 12). Setting this bit causes
the 1-minute timer to restart from 0 (Section 8.4.8).
ON: turn on decoder (Table 12). When this bit is set, the
PCD5013 decodes FLEX signals. If this bit is cleared,
signal processing stops. However, to assure proper
operation, the PCD5013 requires that it be set into
asynchronous mode when turned off. To achieve that the
following sequence must be used:
1. Send control packet with ON bit clear (decoder off)
SPM: single phase mode (Table 12). When this bit is set,
the PCD5013 decodes only one of the transmitted phases.
When this bit is clear, the PCD5013 decodes all
transmitted phases. This value is determined by the
CAPCODE (Section 8.6). A change to this bit while the
PCD5013 is on does not take effect until the next block 0
of a frame. Value after reset = 0.
2. Send control packet with ON bit set (decoder on)
3. Send control packet with ON bit clear (decoder off).
Timing between these steps is specified below and is
measured from the positive edge of the last clock of one
packet to the positive edge of the last clock of the next
packet.
PS: phase select (Tables 11 and 12). When the SPM bit is
set, these bits define which phase the PCD5013 shall
decode. This value is determined by the CAPCODE
(Section 8.6). A change to these bits, while the PCD5013
is on, does not take effect until the next block 0 of a frame.
Value after reset = 0.
• The minimum time between steps 1 and 2 is the greater
of 2 ms or the programmed shut-down time.
The programmed shut-down time is the sum of all of the
times programmed in the used receiver shut-down
settings packets.
• There is no maximum time between steps 1 and 2.
• The minimum time between steps 2 and 3 is 2 ms.
Table 11 Phase selection (by PS bits)
PS1
• The maximum time between steps 2 and 3 is the
programmed warm-up time minus 2 ms.
The programmed warm-up time is the sum of all the
times programmed in the used receiver warm-up
settings packets.
DECODED PHASE (BASED ON
FLEX DATA RATE)
PS0
1600 bits/s 3200 bits/s 6400 bits/s
0
0
A
A
A
0
1
A
A
B
1
0
A
C
C
1
1
A
C
D
EAE: end of addresses enable. When this bit is set, the EA
bit in the Status Packet is PCD5013 set immediately after
the PCD5013 decodes the last address word in the frame
if any of the enabled PCD5013 addresses was detected in
the frame. When this bit is cleared, the EA bit is never set.
Table 12 Control packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
0
0
0
0
0
0
1
0
2
FF7
FF6
FF5
FF4
FF3
FF2
FF1
FF0
1
0
SPM
PS1
PS0
0
0
0
0
0
0
SBI
0
MTC
0
0
EAE
ON
1999 Apr 12
21
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.4.8
PCD5013
If the PCD5013 is in asynchronous mode when this
occurs, it stays in asynchronous mode and end the A-word
search. This is done to avoid synchronizing to a
non-roaming channel when searching for roaming
channels. This bit is set and cleared by the host. Value
after reset = 0.
OPERATING THE 1-MINUTE TIMER
The PCD5013 provides a 1-minute timer which allows the
host to implement a time-of-day function while maintaining
low-power operation. The 1-minute timer is enabled using
the MTE bit in the configuration packet (Section 8.4.4).
When the 1-minute timer is enabled, a status packet is
sent at 1-minute intervals with the MT bit set
(Section 8.4.11). When the MTE bit is clear, the internal
1-minute timer stops counting. When the host sends a
control packet with MTC bit set, the 1-minute timer restarts
from 0. This allows accurate setting of a time-of-day
function.
MCM: manual collapse mode (Table 13). When this bit is
set, the PCD5013 behaves as if the system collapse
was 7. The PCD5013 does not apply the received system
collapse to the AF bits. When this bit is set, the received
system collapse is reported to the host via SCU and RSC
in the Roaming Status Packet. This is so the host can
modify the AF bits based on the system collapse of the
channel. This bit is set and cleared by the host. Value after
reset = 0.
ROAMING CONTROL PACKET (ID = 05H)
8.4.9
The roaming control packet controls the features of the
PCD5013 that allow implementation of a roaming pager.
IS1: invert EXTS1 (Table 13). Setting this bit inverts the
expected polarity of the EXTS1 pin from the way it is
configured by SP 1 in the Configuration Packet (e.g. if both
IS1 and SP 1 are set, the polarity of the EXTS1 pin is
untouched). This bit is intended to be changed when a
change in a channel changes the polarity of the received
signal. This bit is set and cleared by the host. This bit has
the equivalent effect when using the internal demodulator.
Value after reset = 0.
IRS: ignore re-synchronization signal (Table 13). When
this bit is set, the PCD5013 does not go asynchronous
when detecting an Ar or Ar signal during searches for
A-words. It merely reports that the re-synchronization
signal was received by setting RSR to 1 in the Roaming
Status packet. This allows the host to decide what to do
when the paging device is synchronous to more than one
channel and only one channel is sending the
re-synchronization signal. It also prevents the PCD5013
from losing synchronization when it detects the
re-synchronization signal while the paging device is
checking an unknown channel. This bit is set and cleared
by the host. Value after reset = 0.
SDF: stop decoding frame (Table 13). Setting this bit
causes the PCD5013 to stop decoding a frame without
losing frame synchronization. This bit is set by the host,
and cleared by the PCD5013 once it has been processed.
The packet with the SDF bit set must be sent after
receiving the status packet with EA bit set. It must be sent
within 40 ms of the end of block in which the PCD5013 set
the EA bit. Value after reset = 0.
NBC: network bit check (Table 13). Setting this bit enables
reporting of the received network bit value (NBU and n) in
the Roaming Status Packet. Setting this bit also makes the
PCD5013 abandon a frame after the Frame Info word
without synchronizing to the frame if the frame information
word is uncorrectable or if the n bit in the frame information
word is not set. If the PCD5013 is in synchronous mode
when this occurs (probably due to synchronizing to a
second channel), it maintains synchronization to the
original channel.
RSP: receiver shutdown packet enable (Table 13). When
this bit is set, a Receiver Shutdown Packet is sent
whenever the receiver is shut down. The receiver
shutdown packet informs the host that the receiver
shutdown, and gives the time period before the PCD5013
automatically warms the receiver back up. Value after
reset = 0.
Table 13 Roaming Control Packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
0
0
0
0
0
1
0
1
2
IRS
NBC
MCM
IS1
SDF
RSP
SND
CND
1
RND
ABI
SAS
DAS
AF11
AF10
AF9
AF8
0
0
0
MFC1
MFC0
0
0
MCO1
MCO0
1999 Apr 12
22
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
SND: start noise detect (Table 13). Setting this bit while
the PCD5013 is battery saving causes it to warm-up the
receiver, run a noise detect, and report the result of the
noise detect via NDR in the Roaming Status Packet.
This bit is set by the host, and cleared by the PCD5013
once it has been processed. If the time comes for the
PCD5013 to warm-up automatically or the SAS bit is set
while an SND is being processed, the noise detect is
abandoned and the abandoned noise detect result
(NDR = 01) is sent in the Roaming Status Packet. Value
after reset = 0.
The time-out for the A-word searches is controlled by the
AST bits in the Timing Control Packet and the MOT bit in
the Configuration Packet. The A-word search takes priority
over noise detects. Therefore, if the PCD5013 is
performing an A-word search and the time comes to do
automatic noise detect, the noise detect is not performed.
This bit is set by the host, and cleared by the PCD5013
once it has been acted on. Value after reset = 0.
MFC: missed frame control (Tables 14 and 13). These bits
control the frames for which missing frame data (MS1,
MFI, MS2, MBI, and MAW) is reported in the Roaming
Status Packet. Value after reset = 0.
CND: continuous noise detect (Table 13). Setting this bit
causes the PCD5013 to do continuous noise detects
during the decoded block data of a frame. The results of
the noise detect is only reported if noise is detected
(NDR = 11). Only one noise detected result (NDR = 11) is
sent per block. If the PCD5013 has not completed a noise
detect when it shuts down for the frame, that noise detect
is abandoned, but no abandon result (NDR = 01) is sent.
This bit is set and cleared by the host. Value after
reset = 0.
Table 14 Missed Frame Control (MFC bits)
RND: report noise detects (Table 13). Setting this bit
causes the PCD5013 to report the results of the noise
detects it does under normal asynchronous operation
(when first turned on and when asynchronous).
The results of the noise detect is reported via NDR in the
Roaming Status Packet. This bit is set and cleared by the
host. Value after reset = 0.
MFC0
0
0
never
0
1
only during frames 0 through 3
1
0
only during frames 0 through 7
1
1
always
MISSING FRAME DATA REPORTED
MCO: maximum carry on (Table 13). The value of these
bits sets the maximum carry on that the PCD5013 follows.
For example, if the PCD5013 receives a carry on of 3 over
the air and MCO is set to 1, the PCD5013 only carries on
for one frame. Value after reset = 3.
DAS: disable A-word search (Table 13). When this bit is
set, an A-word search does not automatically occur after a
noise detect in asynchronous mode finds FLEX signal.
This includes automatic noise detects and noise detects
initiated by the host by setting SND. The PCD5013 shuts
down the receiver after the noise detect completes
regardless of the result. When this bit is cleared, A-word
searches occur after a noise detect finds signal in
asynchronous mode. Value after reset = 0.
ABI: all block information words (Table 13). When this bit
is set, the PCD5013 sends all received Block Information
words 2-4 to the host. Note: Setting the SBI bit in the
Control Packet only enables errored and real-time clock
related block info words. Value after reset = 0.
SAS: start A-word search (Table 13). Setting this bit while
in asynchronous battery save mode causes the PCD5013
to warm-up the receiver and run an A-word search.
If, during the A-word search, the PCD5013 finds sufficient
FLEX signal, it enters synchronous mode and start
decoding the frame. If the A-word search times-out without
finding sufficient FLEX signal, it enters a battery save
mode and continue doing periodic noise detects.
1999 Apr 12
MFC1
23
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.4.10
PCD5013
– LBU bit in the status packet is set
TIMING CONTROL PACKET (ID = 06H)
– EA bit in the status packet is set
The timing control packet gives the host control of the
timing used when the PCD5013 is in asynchronous mode.
The packet ID for the timing control packet is 6.
– BOE bit in the status packet is set.
FIV: frame information valid (Table 16). This bit is set,
when a valid frame information word has been received
since becoming synchronous to the system and the
f and c fields contain valid values. If this bit is clear, no
valid frame information words have been received since
the PCD5013 became synchronous to the system.
This value changes from 0 to 1 at the end of block 0
(Fig.18) of the frame in which the first frame information
word was properly received. It is cleared when the
PCD5013 goes into asynchronous mode (see SM bit
below). This bit is initialized to 0 when the PCD5013 is
reset and when the PCD5013 is turned off by clearing the
ON bit in the control packet.
AST: A-word search time (Table 15). The value of these
bits sets the A-word search time for all asynchronous
A-word searches in units of 80 ms (e.g. value of 1 is 80 ms,
a value of 2 is 160 ms, etc.). If the value is 0, the PCD5013
defaults to the 1-minute (MOT = 1) or 4-minute (MOT = 0)
A-word search time controlled by the MOT bit in the
configuration packet. Value after reset = 0.
ABT: asynchronous battery-save time (Table 15).
The value of these bits sets the battery save time (time
from the beginning of one automatic noise detect to the
beginning of the next automatic noise detect) in
asynchronous mode in units of 80 ms (e.g. value of 1 is
80 ms, a value of 2 is 160 ms, etc.) If the value is 0, the
battery save time is set to the default value of 1.5 seconds.
The minimum allowed ABT is 320 ms, therefore values of
1, 2, 3, and 4 are invalid. Value after reset = 0.
8.4.11
f: current frame number (Table 16). This value is updated
every frame regardless of whether the PCD5013 needs to
decode the frame. This value changes to its proper value
for a frame at the end of block 0 of the frame. The value of
these bits is not guaranteed when FIV is 0.
STATUS PACKET (ID = 7FH)
c: current system cycle number (Table 16). This value is
updated every frame regardless of whether the PCD5013
needs to decode the frame. This value changes to its
proper value for a frame at the end of block 0 of the frame.
The value of these bits is not guaranteed when FIV is 0.
The status packet contains various types of information
that the host may require and is sent to the host:
• Whenever the PCD5013 is polled and has no other data
to send
• On events for which the PCD5013 is configured to send
the status packet (Sections 8.4.4 and 8.4.7). In this
case, the PCD5013 prompts the host to read a status
packet for the following conditions:
SM: synchronous mode (Table 16). This bit is set, when
the PCD5013 is synchronous to the system.
The PCD5013 sets this bit when the first synchronization
words are received. It clears this bit when the PCD5013
has not properly received both synchronization words in
any frame for 8, 16, or 32 minutes (depending on the
number of assigned frames and the system collapse). This
bit is initialized to 0 when the PCD5013 is reset and when
it is turned off by clearing the ON bit in the control packet.
– SMU bit in the status packet and the SME bit in the
configuration packet are set
– MT bit in the status packet and the MTE bit in the
configuration packet are set
– EOF bit in the status packet is set
Table 15 Timing Control Packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
0
0
1
0
0
f2
f1
f0
2
0
0
0
0
0
0
0
0
1
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
0
ABT7
ABT6
ABT5
ABT4
ABT3
ABT2
ABT1
ABT0
1999 Apr 12
24
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
EA: end of addresses (Table 16). If EAE of the control
packet is set and an address is detected in a frame, EA is
set after the PCD5013 processes the last address in the
frame. Since data packets take priority over the status
packet, the status packet with the EA bit set is guaranteed
to come after all address packets for the frame. Cleared
when read. This bit is initialized to 0 when the PCD5013 is
reset.
SMU: synchronous mode update (Table 16). This bit is set
if the SM bit has been updated in this packet. After the
PCD5013 has been turned on, this bit is set when the first
synchronization words are found (SM changes to 1) or
when the first synchronization search period (meaning the
receiver is active during this time) expires (SM stays 0),
after the PCD5013 is turned on. The latter condition gives
the host the option of assuming the paging device is in
range when it is turned on, and displaying out-of-range
only after the initial search period expires. After the initial
synchronous mode update, the SMU bit is set whenever
the PCD5013 switches from/to synchronous mode. The bit
is cleared when read. Changes in the SM bit due to turning
off the PCD5013 does not set the SMU bit. This bit is
initialized to 0 when the PCD5013 is reset.
x: unused bits (Table 16). The value of these bits is not
guaranteed.
8.4.12
The Receiver Shutdown Packet is sent in both
synchronous and asynchronous mode. It is designed to
indicate to the host that the receiver is turned off and how
much time there is until the PCD5013 automatically turns
it back on. This enables the host to perform other tasks
such as monitoring other pager channels.
LB: low battery (Table 16). Set to the value last read from
the LOBAT pin. The host controls when the LOBAT pin is
read via the receiver control packets. This bit is initialized
to 0 at reset. It is also initialized to the inverse of the
LBP bit in the configuration packet, when the PCD5013 is
turned on, by setting the ON bit in the control packet.
FNV: frame number valid (Table 17). This bit is set if the
last decoded frame information word was correctable and
the frame number was the expected value. When in
asynchronous mode, this value is 0.
LBU: low battery update (Table 16). This bit is set if the
value on two consecutive reads of the LOBAT pin yielded
different results. The bit is cleared when read. The host
controls when the LOBAT pin is read via the receiver
control packets. Changes in the LB bit due to turning on
the PCD5013 do not cause the LBU bit to be set. This bit
is initialized to 0 when the PCD5013 is reset.
CF: current frame (Table 17). When in synchronous mode,
this is the current frame number. This value is latched on
the negative edge of the READY line when this packet is
sent to the host. The value of this field is valid only if the
PCD5013 is in synchronous mode and the FIV bit in the
status packet is set. When in asynchronous mode, this
value is 0.
EOF: end of frame (Table 16). Set when the PCD5013 is
in all frame mode (AFM) (Section 8.8.4), and the end of
the frame has been reached. The PCD5013 is in the AFM
if the AFM enable counter is non-zero, if any temporary
address enabled (TAE) counter is non-zero (Section 8.8.4)
or if the FAF bit in the AFM packet is set. The bit is cleared
when read and initialized to 0 when the PCD5013 is reset.
TNF: time to next frame (Table 17). When in synchronous
mode TNF indicates the time to the start of the A-word
check if the PCD5013 were to warm-up for the next frame.
When in asynchronous mode TNF indicates the time to the
start of the next automatic noise detect. See section 8.8.9
for an explanation on how to use this value. This value is
latched on the negative edge of the READY line when this
packet is sent to the host.
MT: minute time-out (Table 16). Set if one minute has
elapsed. The bit is cleared when read. This bit is initialized
to 0 when the PCD5013 is reset.
FCO: frame carried on (Table 17). Set if the PCD5013 is
decoding the next frame due to the reception of a non-zero
carry-on value in the current or a previous frame. When in
asynchronous mode, this value is 0.
BOE: buffer overflow error (Table 16). Set when
information has been lost owing to slow host response
time. When the PCD5013 detects that its SPI transmit
buffer has overflowed, it clears the transmit buffer, turns off
decoding by clearing the ON bit in the control packet, and
sets this bit. The bit is cleared when read. This bit is
initialized to 0 when the PCD5013 is reset.
1999 Apr 12
RECEIVER SHUTDOWN PACKET (ID = 7EH)
NAF: next assigned frame (Table 17). This is the frame
number of the next frame the PCD5013 was scheduled to
decode when the receiver shut down. The value of this
field is valid only if the PCD5013 is in synchronous mode
and the FIV bit in the status packet is set. When in
asynchronous mode this value is 0.
25
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
Table 16 Status packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
0
1
1
1
1
1
1
1
2
FIV
f6
f5
f4
f3
f2
f1
f0
1
SM
LB
x
x
c3
c2
c1
c0
0
SMU
LBU
x
MT
x
EOF
EA
BOE
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Table 17 Receiver Shutdown Packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
3
0
1
1
1
1
1
1
0
2
FNV
CF6
CF5
CF4
CF3
CF2
CF1
CF0
1
TNF7
TNF6
TNF5
TNF4
TNF3
TNF2
TNF1
TNF0
0
FCO
NAF6
NAF5
NAF4
NAF3
NAF2
NAF1
NAF0
1999 Apr 12
26
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.4.13
PCD5013
NBU: network bit update (Table 19). Set when the NBC bit
in the roaming control packet is set and a frame
information word is received with a correctable number of
errors. This bit is not set when the frame information word
is not received due to missing the first synchronization
pattern (A/A). This bit is cleared when read.
ROAMING STATUS PACKET (ID = 60H)
The PCD5013 automatically prompts the host to read a
Roaming Status Packet if RSR, MS1, MFI, MS2, MBI,
MAW, NBU, NDR 1, NDR 0, or SCU is set.
RSR: re-synchronization signal received (Table 19).
Set when the PCD5013 detected a re-synchronization
signal (Ar/Ar) and the host configured the PCD5013 to
ignore it via the IRS bit in the roaming control packet. This
bit is cleared when read.
n: network bit value (Table 19). When NBU is set, this is
the value of the n bit in the last received frame information
word.
NDR: noise detect result (Tables 18 and 19). These bits
indicate the result of a noise detect. The results of noise
detects initiated by setting the SND bit in the roaming
control packet is always reported. The results of the
automatic noise detects performed in asynchronous mode
is only reported if the RND bit is set in the roaming control
packet. When continuous noise detects during block data
are enabled by setting the CND bit in the roaming control
packet, only the ‘No FLEX signal detected’ result is
reported. These bits are cleared when read.
MS1: missed synchronization 1 (Table 19). Set when the
PCD5013 fails to detect the first synchronization pattern
(A/A) of a FLEX frame and the PCD5013 was configured
to report missed frame information via the MFC bit in the
roaming control packet. This bit is cleared when read.
MFI: missed frame information word (Table 19). Set when
the frame information word is received with an
uncorrectable number of errors and the PCD5013 was
configured to report missed frame information via the MFC
bit in the roaming control packet. This bit is cleared when
read.
Table 18 Noise Detect Result (NDR bits)
MS2: missed synchronization 2 (Table 19). Set when the
PCD5013 failed to detect the second synchronization
pattern (C/C) of a frame and PCD5013 was configured to
report missed frame information via the MFC bit in the
roaming control packet. This bit is cleared when read.
NDR1
NDR0
0
0
No Information
0
1
Noise Detect was abandoned
1
0
FLEX signal detected
MBI: missed block information word 1 (Table 19).
Set when at least one of the block information word ones
is received with an uncorrectable number of errors and
PCD5013 was configured to report missed frame
information via the MFC bit in the roaming control packet.
This bit is set no more than once per frame regardless of
the number of missed block information word 1’s in the
frame. This bit is cleared when read.
1
1
FLEX signal not detected
NOISE DETECT RESULT
SCU: system collapse update (Table 19). Set when the
PCD5013 is configured for manual collapse mode by
setting the MCM bit in the roaming control packet and the
system collapse of a frame is received. This bit is set no
more than once per frame regardless of the number of
phases in the frame. This bit is not set in frames in which
no block information word 1’s is received properly. This bit
is cleared when read.
MAW: missed address word (Table 19). Set when any
address words in the address field is received with an
uncorrectable number of errors and PCD5013 was
configured to report missed frame information via the MFC
bit in the roaming control packet. This bit is set no more
than once per frame regardless of the number of missed
address words in the frame. This bit is cleared when read.
RSC: received system collapse (Table 19). When SCU is
set, this value represents the system collapse value that
was received in the frame.
Table 19 Roaming Status packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
0
1
1
0
0
0
1
0
2
RSR
MS1
MFI
MS2
MBI
MAW
NBU
n
1
x
x
x
x
x
x
NDR1
NDR0
0
x
x
x
x
SCU
RSC2
RSC1
RSC0
1999 Apr 12
27
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.5
PCD5013
This allows the designer to force the receiver control lines
to the receiver off setting with external pull-up or pull-down
resistors before the host can configure these settings in
the PCD5013.
Receiver control interface
8.5.1
GENERAL
The PCD5013 has 8 programmable receiver control lines,
S0 to S7. The host can program via SPI packets what
setting is applied to the receiver control lines, the duration
of warm-up and shut-down stages and the polling of the
LOBAT pin. This programmability allows the PCD5013 to
interface with many off-the-shelf receiver ICs. Note that
these packets are ignored when sent while decoding is
enabled (ON bit is set in the control packet).
8.5.2
8.5.4
The receiver off state is configured by the receiver off
setting packet (Table 20), which defines the settings to be
applied when the PCD5013 decides to switch the
receiver off.
LBC: low battery check (Table 20). If this bit is set, the
PCD5013 checks the status of the LOBAT port just before
leaving the receiver off state. Value after reset = 0.
LOW BATTERY DETECTION
The PCD5013 can be configured to poll the LOBAT pin at
the end of every receiver control setting. This check can be
enabled or disabled for each receiver control setting. If the
poll is enabled for a setting, the pin is read just before the
PCD5013 activates the next setting on the receiver control
lines. The PCD5013 sends a status packet whenever the
value differs from the previous time that the LOBAT pin
was polled.
8.5.3
RECEIVER OFF STATE (ID = 10H)
CLS: control line setting (Table 20). This is the value to be
output on the receiver control lines for the receiver off
state. Value after reset = 0.
ST: step time (Table 20). This sets the duration of the
warm-up off time. The setting is in steps of 625 µs. Valid
values are 625 µs (ST = 01H) to 159.375 ms (ST = FFH).
Value after reset = 01H.
RECEIVER SETTINGS AT RESET
The receiver control ports are 3-state outputs which are set
to high impedance when the PCD5013 is reset, until the
corresponding FRS bit in the receiver line control packet is
set or the PCD5013 is turned on for the first time after a
reset (by setting the ON bit in the control packet).
Table 20 Receiver off setting packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
3
0
0
0
2
0
0
0
1
CLS7
CLS6
0
ST7
ST6
1999 Apr 12
BIT 3
BIT 2
BIT 1
BIT 0
1
0
0
0
0
0
LBC
0
0
0
CLS5
CLS4
CLS3
CLS2
CLS1
CLS0
ST5
ST4
ST3
ST2
ST1
ST0
28
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.5.5
PCD5013
160 ms, the receiver remains in the 1600 sps sync setting
or the 3200 sps sync setting from the end of the last used
warm-up setting until valid signals are expected (160 ms
after the start of the warm-up off time). Figure 12 shows
the receiver warm-up sequence while decoding, when all
warm-up settings are enabled.
RECEIVER WARM-UP SEQUENCES
8.5.5.1
Normal receiver warm-up sequence
The PCD5013 allows for up to 6 steps associated with
warming-up the receiver. When the PCD5013 turns on the
receiver while decoding, it starts the warm-up sequence
160 ms before it requires valid signals at the EXTS1 and
EXTS0 input pins.
8.5.5.2
1. The PCD5013 leaves the receiver control lines in the
off state for the programmed warm-up off time.
A host can initiate a receiver warm-up sequence is by one
of the following actions:
2. The first warm-up setting, if enabled, is applied to the
receiver control lines for the amount of time
programmed for that setting.
• Turning on the PCD5013 by setting the ON bit in the
control packet
• Requesting a noise detect by setting the SND bit in the
roaming control packet
3. Subsequent warm-up settings are applied to the
receiver control lines for their corresponding time until
a disabled warm-up setting is found.
• Requesting an A-word search by setting the SAS bit in
the roaming control packet.
4. At the end of the last used warm-up setting, the
1600 symbols per second (sps) sync setting or the
3200 sps sync setting is applied to the receiver control
lines depending on the PCD5013 current state.
A host initiated receiver warm-up sequence (see Fig.13)
differs from the sequence described in Section 8.5.5.1.
No receiver warm-up off time is applied, instead the
PCD5013 immediately begins to apply the receiver
warm-up settings. Once a disabled warm-up setting is
found, the “3200 sps sync setting” (for ON and SND
warm-ups) or the “1600 sps sync setting” (for SAS
warm-ups) is applied to the receiver control lines.
The decoder then expects valid signals after the 3200 sps
sync warm-up time.
The PCD5013 must be configured such that the sum of all
of the used warm-up times and the warm-up off time does
not exceed 160 ms. If it exceeds 160 ms, the PCD5013
executes the receiver shut-down sequence 160 ms after
the start of the warm-up off time. If the sum of all of the
used warm-up times and the warm-up off times is less than
160 ms
handbook, full pagewidth
warm-up
off time
receiver
control
line setting
Host initiated receiver warm-up sequence
off
possible
LOBAT
check
warm-up
time 1
warm-up
time 2
warm-up
time 3
warm-up
time 4
warm-up
time 5
warm-up
setting 1
warm-up
setting 2
warm-up
setting 3
warm-up
setting 4
warm-up
setting 5
possible
LOBAT
check
possible
LOBAT
check
possible
LOBAT
check
possible
LOBAT
check
1600 sps or 3200 sps
sync setting
possible
LOBAT
check
EXTS1 & EXTS0
signals are expected
to be valid here
MGK265
Fig.12 Receiver warm-up sequence while decoding.
handbook, full pagewidth
receiver
control
line setting
off
possible
LOBAT
check
warm-up
time 1
warm-up
time 2
warm-up
time 3
warm-up
time 4
warm-up
time 5
warm-up
setting 1
warm-up
setting 2
warm-up
setting 3
warm-up
setting 4
warm-up
setting 5
possible
LOBAT
check
possible
LOBAT
check
possible
LOBAT
check
possible
LOBAT
check
3200 sps sync
warm-up
time
possible
LOBAT
check
3200 sps
sync setting
EXTS1 & EXTS0
signals are expected
to be valid here
MGK266
Fig.13 First receiver warm-up sequence after turning decoding on.
1999 Apr 12
29
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.5.5.3
PCD5013
ST: step time (Table 22). This sets the duration time for
receiver warm-up until the next receiver state. The setting
is in 625 µs steps and valid values are:
Receiver warm-up setting packets
(ID = 11H to 15H)
CLS: control line setting (Table 22). This is the value to be
output on the receiver control lines (S0 to S7) for this
receiver warm-up state. Value after reset = 0.
625 µs (ST = 01H) to 79.375 ms (ST = 7FH).
Value after reset = 01H.
SE: step enable (Table 22). The receiver setting is
enabled when the bit is set. If the bit is cleared then that
step in the receiver warm-up sequence is disabled and all
following steps are ignored. Value after reset = 0.
s: setting number, see Tables 21 and 22 for the s names
and values and location in the receiver warm-up packet.
LBC: low battery check (Table 22). If this bit is set, the
PCD5013 checks the status of the LOBAT port just before
leaving this receiver warm-up state. Value after reset = 0.
Table 21 Receiver warm-up setting numbers
s3
s2
s1
s0
SETTING NAME
0
0
0
1
warm-up 1
0
0
1
0
warm-up 2
0
0
1
1
warm-up 3
0
1
0
0
warm-up 4
0
1
0
1
warm-up 5
Table 22 Receiver warm-up setting packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
0
0
0
1
s3
s2
s1
s0
2
SE
0
0
0
LBC
0
0
0
1
CLS7
CLS6
CLS5
CLS4
CLS3
CLS2
CLS1
CLS0
0
0
ST6
ST5
ST4
ST3
ST2
ST1
ST0
1999 Apr 12
30
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.5.6
8.5.6.1
PCD5013
ACTIVE RECEIVER STATES
General
In addition to the warm-up and shut-down states, the PCD5013 has four active receiver states. When these settings are
applied to the receiver control lines, the PCD5013 is decoding the EXTS1 and EXTS0 input signals. The timing of these
signals and their duration depends on the FLEX data stream. Because of this, there is no time setting associated with
these settings (with the exception of the 3200 sps sync setting).
The four settings are as follows:
1600 sps sync setting: applied when the PCD5013 searches for a 1600 sps signal.
3200 sps sync setting: applied when the PCD5013 searches for a 3200 sps signal.
1600 sps data setting: applied after the PCD5013 has found the C or C sync word in the sync 2 section of a
1600 sps frame.
3200 sps data setting: applied after the PCD5013 has found the C or C sync word in the sync 2 section of a
3200 sps frame.
Figure 14 shows some examples of how these settings are used in the PCD5013.
TM
handbook, full
pagewidth
FLEX
signal
block 10
receiver
control
line setting
example #1
1600 sps data or 3200 sps data
or last used warm up setting
receiver
control
line setting
example #2
frame
info
sync 1
3200 sps
sync setting
1600 sps
sync setting
possible
LOBAT
check
sync 2
possible
LOBAT
check
1600 sps data or 3200 sps data
or last used warm up setting
3200 sps
data setting
possible
LOBAT
check
1600 sps
sync setting
1600 sps
data setting
MGK268
possible
LOBAT
check
possible
LOBAT
check
Fig.14 Examples of receiver control transitions.
1999 Apr 12
block 0
31
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.5.6.2
PCD5013
Receiver on setting packets (ID = 16H to 19H)
Table 23 s names and values
LBC: low battery check (Tables 24 and 25). If this bit is
set, the PCD5013 checks the status of the LOBAT port just
before leaving this receiver sync setting state. Value after
reset = 0.
CLS: control line setting (Tables 24 and 25). This is the
value to be output on the receiver control lines for this
receiver sync setting state. Value after reset = 0.
s3
s2
s1
s0
SETTING NAME
0
1
1
1
1600 sps sync
1
0
0
0
3200 sps data
1
0
0
1
1600 sps data
8.5.7
FORCING RECEIVER LINES (ID = 0FH)
This packet (Table 26) enables host control over the
receiver control line (S0 to S7) settings in all modes except
reset. In reset, the receiver control lines are high
impedance.
ST: step time (Table 24). This sets the waiting time, before
expecting good signals at EXTS1 and EXTS0 at the end of
the warm-up sequence, after turning decoding on.
The setting is in steps of 625 µs. Valid values are:
625 µs (ST = 01H) to 79.375 ms (ST = 7FH). Value after
reset = 01H.
FRS: force receiver setting (Table 26). Setting a bit causes
the associated CLS bit in this packet to override the
internal receiver control settings on the corresponding
receiver control line. Clearing a bit returns control of the
corresponding receiver control line to the PCD5013. Value
after reset = 0.
s: setting number, see Tables 23 and 25 for the s names
and values and location in the receiver on setting packet.
CLS: control line setting (Table 26). This bit setting is
applied to the corresponding receiver control line if the
associated FRS bit is set in this packet. Value after
reset = 0.
Table 24 3200 sps sync setting packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
0
0
0
2
0
0
0
1
0
1
1
0
0
LBC
0
0
0
1
CLS7
CLS6
CLS5
CLS4
CLS3
CLS2
CLS1
CLS0
0
0
ST6
ST5
ST4
ST3
ST2
ST1
ST0
Table 25 Receiver on setting packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
0
0
0
1
s3
s2
s1
s0
2
0
0
0
0
LBC
0
0
0
1
CLS7
CLS6
CLS5
CLS4
CLS3
CLS2
CLS1
CLS0
0
0
0
0
0
0
0
0
0
Table 26 Receiver line control packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
0
0
0
0
1
1
1
1
2
0
0
0
0
0
0
0
0
1
FRS7
FRS6
FRS5
FRS4
FRS3
FRS2
FRS1
FRS0
0
CLS7
CLS6
CLS5
CLS4
CLS3
CLS2
CLS1
CLS0
1999 Apr 12
32
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.5.8
PCD5013
LBC: low battery check (Table 28). If this bit is set, the
PCD5013 checks the status of the LOBAT port just before
leaving this receiver shut-down state. Value after
reset = 0.
RECEIVER SHUT-DOWN SEQUENCE
The PCD5013 allows up to 3 steps associated with
shutting down the receiver. When the PCD5013 decides to
turn off the receiver, the first shut-down setting, if enabled,
is applied to the receiver control lines for the
corresponding shut-down time. At the end of the last used
shut-down time, the receiver off setting is applied to the
receiver control lines. If the first shut-down setting is not
enabled, the PCD5013 switches directly from the
receiver on to the receiver off setting.
CLS: control line setting (Table 28). This is the value to be
output on the receiver control lines (S0 to S7) for this
receiver shut-down state. Value after reset = 0.
ST: step time (Table 28). This sets the duration time for
receiver shut-down, until the next receiver state.
The setting is in steps of 625 µs. Valid values are
625 µs (ST = 01H) to 39.375 ms (ST = 3FH). Value after
reset = 01H.
Figure 15 shows the receiver shut-down sequence when
all shut-down settings are enabled. If the receiver is on or
being warmed up when the decoder is turned off (by
clearing the ON bit in the control packet), the PCD5013
immediately executes the receiver shut-down sequence.
If the PCD5013 is executing the shut-down sequence
when turned on (with the ON bit in the control packet set)
the PCD5013 completes the shut-down sequence before
starting the warm-up sequence.
8.5.8.1
s: setting number, see Tables 27 and 28 for the s names
and values and location in the receiver shut-down packet.
Table 27 s names and values
Receiver shut-down setting packets
(ID = 1AH to 1BH)
s
SETTING NAME
0
shut-down 1
1
shut-down 2
SE: step enable (Table 28). The receiver setting is
enabled when the bit is set. If the bit is cleared then that
step in the receiver shut-down sequence is disabled and
all following steps are ignored. Value after reset = 0.
Table 28 Receiver shut-down stages
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
0
0
0
1
1
0
1
s
2
SE
0
0
0
LBC
0
0
0
1
CLS7
CLS6
CLS5
CLS4
CLS3
CLS2
CLS1
CLS0
0
0
0
ST5
ST4
ST3
ST2
ST1
ST0
handbook, full pagewidth
receiver
control
line setting
1600 sps or 3200 sps
sync or data setting
shut down
time 1
shut down
time 2
shut down
setting 1
shut down
setting 2
off
MGK267
possible
LOBAT
check
possible
LOBAT
check
possible
LOBAT
check
Fig.15 Receiver shut-down sequence.
1999 Apr 12
33
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.6
8.6.1
PCD5013
When the FLEX standard pager collapse value of 4
(battery cycle of 16 frames) is used, the pager collapse
field can be omitted.
Configuration of the FLEX CAPCODE
GENERAL
A CAPCODE specifies a decoder address, the collapse
value of the address and whether single-phase, any-phase
or all-phase address. The PCD5013 supports
single-phase and any-phase operation. The FLEX
protocol provides a standard mechanism to derive phase
and frame in which an address should be transmitted.
If this mechanism is not used, a CAPCODE also specifies
the phase and frame assigned to the address.
8.6.2
The collapse value is a number between 0 and 7 and
defines how often the decoding device looks for messages
on the FLEX channel. For a given collapse value b, the
decoding device looks in every 2b frames. Thus an
address with an assigned base frame of 3 and a collapse
value of 5 typically looks for messages in frame 3 and
every 32 frames thereafter (i.e. frames 3, 35, 67 and 99).
CAPCODE FORMAT
The FLEX CAPCODE consist of a series of decimal and
alphabetic fields, see Fig.16 for the field definitions.
Frame field, optional 3 digit decimal
handbook, full pagewidth
field, represents the frame number if
standard frame and phase
embedding rules are not used.
CAPCODE type, mandatory
alphabetic character, indicates rules
for deriving phase and frame from
address field.
P 1 2 2 5 U 2 2 3 4 5 5 0 1 2 1
Roaming capability, optional
alphabetic character 'P'
indicates no roaming capabilities.
Pager collapse (battery cycle),
optional 1 digit decimal field
(mandatory if frame number
field is included) indicates pager
collapse value.
Address field, mandatory 7, 9 or 10 digit
decimal field, contains the information from
which the BCH address codewords for this
CAPCODE are derived.
Fig.16 CAPCODE format.
1999 Apr 12
34
MBK096
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.6.3
PCD5013
A long CAPCODE represents addresses situated
above 2101248 subdivided into categories
(uncoordinated, global, country) to allow different
allocation schemes to coexist.
CAPCODE RANGES
A CAPCODE represents user addresses ranging
from 1 to 5370810366. A short CAPCODE can have
address values below 2031615 and are represented in the
data stream by a single address codeword. Some short
addresses have been reserved for special purposes:
information service addresses, network addresses,
temporary (group) addresses and operator messaging
addresses.
Table 29 defines the address usage assignment.
All addresses not listed in this table are not defined and
reserved for future use.
Table 29 CAPCODE assignment table
CAPCODE ADDRESS VALUE
DESCRIPTION
from
to
0000000000
illegal
0000000001
0001933312
short addresses
0001933313
0001998848
illegal
0001998849
0002009087
reserved for future use
0002009088
0002025471
Information service addresses
0002025472
0002029567
network addresses
0002029568
0002029583
temporary addresses
0002029584
0002029599
operator messaging addresses
0002029600
0002031614
reserved for future use
0002031615
0002101248
invalid, not used
0002101249
0102101250
long address set 1-2 uncoordinated
0102101251
0402101250
long address set 1-2 country; note 1
0402101251
1075843072
long address set 1-2 global; note 2
1075843073
2149584896
long address set 1-3 global; note 2
2149584897
3223326720
long address set 1-4 global; note 2
3223326721
3923326750
long address set 2-3 country; note 1
3923326751
4280000000
long address set 2-3 reserved
4280000001
4285000000
long address set 2-3 information service, global; notes 2 and 3
4285000001
4290000000
long address set 2-3 information service, country; notes 1 and 3
4290000001
4291000000
long address set 2-3 information service, world-wide; notes 3 and 4
4291000001
4297068542
reserved for future use
Notes
1. Country: the addresses are coordinated within each country and with countries along borders.
2. Global: address is coordinated to be unique world-wide.
3. Information service: currently, the rules governing the use of these addresses are not defined.
4. World-wide: 1000 addresses are assigned to each country for world-wide use.
1999 Apr 12
35
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.6.4
PCD5013
ADDRESS CALCULATION
Table 30 Address word range definitions
Address codeword values generally do not coincide with
(part of) the user address as specified in the CAPCODE.
To find the address codewords corresponding to a user
address a conversion has to be done (Table 31). The type
of conversion depends on the CAPCODE range in which
the user address is located. Note that addresses are
transmitted LSB first (differently to POCSAG).
TYPE
Short addresses, are transmitted in a single address
codeword where as long addresses are transmitted in two
consecutive address codewords. The first codeword of a
long address contains the lower part of the address, the
second codeword the upper part. By combining two long
address codewords from different banks 6 long address
ranges are created: 1 to 2, 1 to 3, 1 to 4, 2 to 3, 2 to 4 and
3 to 4. Ranges 2 to 4 and 3 to 4 are as yet undefined and
reserved.
HEX VALUE
Idle word (illegal address)
000000
Long address 1
000001 to 008000
Short address
008001 to 1E0000
Long address 3
1E0001 to 1E8000
Long address 4
1E8001 to 1F0000
Short address (reserved)
1F0001 to 1F27FF
Information service address
1F2800 to 1F67FF
Network address
1F6800 to 1F77FF
Temporary address
1F7800 to 1F780F
Operator messaging address 1F7810 to 1F781F
Table 31 describes how to calculate the 21-bit address
codeword which is transmitted over the air.
Short address (reserved)
1F7820 to 1F7FFE
Long address 2
1F7FFF to 1FFFFE
Idle word (illegal address)
1FFFFF
Table 31 Address word calculation
TYPE
LOWER ADDRESS CODEWORD;
notes 1, 2 and 3
UPPER ADDRESS CODEWORD;
notes 1, 3 and 4
Short address
CAPCODE + 8000
note 5
Long address,
range 1 to 2; note 6
1 + ((CAPCODE − 1F9001) MOD 8000)
1FFFFF − ((CAPCODE − 1F9001) DIV 8000)
Long address,
ranges 1 to 3 and
1 to 4
1 + ((CAPCODE − 1F9001) MOD 8000)
1D8000 + ((CAPCODE − 1F9001) DIV 8000)
Long address,
range 2 to 3
1F7FFF + ((CAPCODE − 1F8FFF) MOD 8000) 1C8000 + ((CAPCODE − 1F8FFF) DIV 8000)
Notes
1. All numbers are in hexadecimal format.
2. The MOD operator gives the remainder of an integer division.
3. CAPCODE refers to the value of the address field in a FLEX CAPCODE.
4. The DIV operator is the integer division.
5. A short address consists of a single codeword.
6. The upper codeword range in bank 2 is used from the highest address downwards, i.e. the lowest value of the
CAPCODE produces a codeword value of 1FFFFEH.
1999 Apr 12
36
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.6.5
PCD5013
Phase number = ((Address − Offset) DIV 4) MOD 4
PHASE AND FRAME CALCULATION
Frame = ((Address − Offset) DIV 16) MOD 128
The method for specifying phase and base frame of a
pager is specified in the CAPCODE type.
where DIV is the integer division and MOD is the
remainder of an integer division.
• The phase and base frame are extracted by standard
rules from the user address field in the CAPCODE
(CAPCODE types A to L)
For a CAPCODE not using the standard rules for
extracting phase and base frame (types U to Z) the 3-digit
frame field 000 to 127 and a single digit decimal pager
collapse 0 to 5 can precede the CAPCODE type. When
these fields are not included, the paging device or the
subscriber database must be accessed to determine the
assigned frame and collapse value.
• The phase is indicated by the CAPCODE type
(Table 32) and the base frame is specified in the frame
field of the CAPCODE (CAPCODE types U to Z).
For easy allocation of (up to 4) consecutive CAPCODEs
having the same phase and frame, an offset in the
range 0 to 3 is subtracted from the user address for the
purposes of phase and frame extraction. The offset is
determined by the CAPCODE type.
The CAPCODE for a roaming pager uses an Alpha
character to describe the level of roaming capability.
The Alpha characters descriptions are shown in Table 33.
The standard rules for extracting phase and base frame
from the user address are (phase numbers 0 to 3
correspond to phases A to D):
Table 32 Frame and phase extraction for different CAPCODE types
CAPCODE TYPE
PAGER TYPE
FRAME/PHASE EXTRACTION
A
single-phase
standard rules; Offset: 0
B
single-phase
standard rules; Offset: 1
C
single-phase
standard rules; Offset: 2
D
single-phase
standard rules; Offset: 3
E
any-phase
standard rules; Offset: 0
F
any-phase
standard rules; Offset: 1
G
any-phase
standard rules; Offset: 2
H
any-phase
standard rules; Offset: 3
I
all-phase; note 1
standard rules; Offset: 0
J
all-phase; note 1
standard rules; Offset: 1
K
all-phase; note 1
standard rules; Offset: 2
L
all-phase; note 1
standard rules; Offset: 3
U
single-phase
no frame extraction rules, phase-A
V
single-phase
no frame extraction rules, phase-B
W
single-phase
no frame extraction rules, phase-C
X
single-phase
no frame extraction rules, phase-D
Y
any-phase
no frame extraction rules, any-phase
Z
all-phase; note 1
no frame extraction rules, all-phase
Note
1. All-phase decoding is not defined in FLEX G1.8 and, therefore, is not supported by the PCD5013.
1999 Apr 12
37
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
In this case, the host must disable the user address
location(s) by clearing the corresponding user address
enable (UAE) bit in the UAE packet before changing any
of the bits in the corresponding address assignment
packet.
Table 33 Roaming CAPCODE character
CHARACTER
DESCRIPTION
P
non-roaming or single frequency pager
Q
no frame offset, follows the Traffic
Management Flags
R
frame offset BIW101, does not follow
the Traffic Management Flags
S
frame offset BIW101, follows the Traffic
Management Flags
8.6.6
a: address location (Table 34). This specifies which
address location is being configured. A zero in this field
corresponds to address index zero (AI = 0) in the address
packet received from the PCD5013 when an address is
detected (Section 8.7.2).
LA: long address (Table 34). When this bit is set, the
address is configured as a long address. Both words of a
long address must have this bit set.
CONFIGURATION OF USER ADDRESSES
(ID = 78H, 80H TO 8FH)
The PCD5013 has 16 user address locations which can be
programmed as network IDs or as long or short addresses,
which can be configured as priority and/or tone-only. After
a reset all address locations are disabled. Short addresses
and network IDs occupy a single location, long addresses
occupy two locations. The first word of a long address
must be in an even address location and the second word
must be in the address index immediately following the first
word. Address location containing long addresses of the
2-3 and 2-4 set (Section 8.6.3) must follow any address
locations programmed as long addresses of the 1-2, 1-3
and 1-4 set.
TOA: tone-only address (Table 34). When this bit is set,
the PCD5013 considers this address a tone-only address
and does not decode a vector word when the address is
received. Both words of a long, tone only address must
have this bit set.
A: address word (Table 34). This is the 21-bit value of the
address word (A20 = MSB). Valid FLEX messaging
addresses or Network ID’s must be used. For the
conversion from a CAPCODE (Section 8.6.4).
UAE: user address enable (Table 35). When a bit is set,
the corresponding user address location is enabled. When
it is cleared, the corresponding user address location is
disabled. UAE0 corresponds to the user address location
configured using a packet ID of 80H and UAE15
corresponds to the user address location configured using
a packet ID of 8FH. In some instances, if an invalid
FLEX messaging address is programmed, it is not
detected even when the address is enabled. Value after
reset = 0.
User addresses are programmed using the address
assignment packets, and are enabled and disabled using
the address enable packet. To allow easy reprogramming
of user addresses without disrupting normal operation, the
host can send address assignment packets while the
PCD5013 is on.
Table 34 Address assignment packet bit assignments (ID = 80H to 8FH)
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
1
0
0
0
a3
a2
a1
a0
2
0
LA
TOA
A20
A19
A18
A17
A16
1
A15
A14
A13
A12
A11
A10
A9
A8
0
A7
A6
A5
A4
A3
A2
A1
A0
Table 35 Address enable packet bit assignments (ID = 78H)
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
0
1
1
1
1
0
0
0
2
0
0
0
0
0
0
0
0
1
UAE15
UAE14
UAE13
UAE12
UAE11
UAE10
UAE9
UAE8
0
UAE7
UAE6
UAE5
UAE4
UAE3
UAE2
UAE1
UAE0
1999 Apr 12
38
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.6.7
PCD5013
CONFIGURATION OF ASSIGNED FRAMES AND PAGER
(ID = 20H TO 27H)
8.6.8
COLLAPSE
CONFIGURATION OF ASSIGNED PHASE
The assigned phase is required only for single-phase
devices. It determines the phase (A, B, C, or D) in which
the messages are received.
The assigned frame and collapse value determine the
frames in which the decoding device typically looks for
messages (other system factors can cause the decoding
device to look in other frames in addition to the typical
frames).
For details of phase calculation see Section 8.6.5.
For details of programming the assigned phase
see Section 8.4.7.
The PCD5013 must be configured explicitly to receive all
required frames by setting the associated assigned
frame (AF) bits. For each enabled CAPCODE these are
the base frame and the associated frames implied by the
pager collapse value. For example if the PCD5013 has
one enabled address and it is assigned to base frame 3
with a collapse value of 4, the AF bits for
frames 3, 19, 35, 51, 67, 83, 99 and 115 should be set
and the AF bits for all other frames should be cleared.
Table 36 Frame assignment ranges
When the PCD5013 is configured for manual collapse
mode by setting the MCM bit in the Roaming Control
Packet, the PCD5013 does not apply the received system
collapse to the AF bits. The host should set the AF bits for
all frames that should be decoded on all channels.
For example, if frames 0 and 64 should be decoded on one
channel and frames 4, 36, 68, and 100 should be decoded
on another channel, all six of the corresponding AF bits
should be set. The host can then change the receiver’s
carrier frequency after the PCD5013 decodes frames 0,
36, 64, and 100.
f2
f1
f0
AF15
AF0
0
0
0
frame 127
frame 112
0
0
1
frame 111
frame 96
0
1
0
frame 95
frame 80
0
1
1
frame 79
frame 64
1
0
0
frame 63
frame 48
1
0
1
frame 47
frame 32
1
1
0
frame 31
frame 16
1
1
1
frame 15
frame 0
OPERATOR MESSAGING ADDRESS ENABLE PACKET
(ID = 04H)
8.6.9
The operator messaging address enable packet is used to
enable and disable the built-in FLEX operator messaging
addresses. Enabling and disabling operator messaging
addresses does not affect on which frames the decoder IC
decodes. To ensure that the correct frames are decoded,
the host must modify the FF bits in the Control Packet or
the AF bits in the Frame Assignment Packets.
There are 8 frame assignment packets each capable of
assigning a range of 16 consecutive frame numbers.
f: frame range, see Table 38 for location in the frame
assignment packet and Table 36 for the AFs and values.
The value determines which 16 frames out of a range
of 128 correspond to the 16 AF bits in the packet. At least
one of these bits must have been set when the PCD5013
is turned on by setting the ON bit in the control packet.
Value after reset = 0.
OAE: operator messaging address enable (Table 37).
When a bit is set, the corresponding operator messaging
address is enabled. When it is cleared, the corresponding
operator messaging address is disabled. OAE0 to OAE15
corresponds to the hexadecimal operator messaging
address values of 1F7810 through to 1F781F
respectively. Value after reset = 0.
AF: assigned frame (Table 38). If a bit is set, the PCD5013
decodes the associated FLEX frame and scans its
contents for enabled addresses. Value after reset = 0.
Table 37 Operator messaging address enable packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
0
0
0
0
0
1
0
0
2
0
0
0
0
0
0
0
0
1
OAE15
OAE14
OAE13
OAE12
OAE11
OAE10
OAE9
OAE8
0
OAE7
OAE6
OAE5
OAE4
OAE3
OAE2
OAE1
OAE0
1999 Apr 12
39
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
Table 38 Frame assignment packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
0
0
1
0
0
f2
f1
f0
2
0
0
0
0
0
0
0
0
1
AF15
AF14
AF13
AF12
AF11
AF10
AF9
AF8
0
AF7
AF6
AF5
AF4
AF3
AF2
AF1
AF0
8.7
8.7.1
For long addresses, the address packet is only sent once
with AI referring to the second word of the address.
Call data packets
GENERAL
TOA: tone-only address (Table 39). This bit is set if the
address was programmed as a tone-only address.
No vector word is sent for tone-only addresses. This bit is
never set for temporary or operator messaging addresses.
The PCD5013 sends data extracted from the
FLEX signal to the host in SPI packets using the
following packet types:
• BIW packets which contain data transmitted in BIWs
• Address packets which indicate that a call has been
detected and give additional information about call
attributes
WN: word number of vector (2 to 87 decimal) (Table 39).
The location of the vector within this frame for the detected
address. This value is invalid for this packet if the TOA bit
is set.
• Vector packets which indicate the call type and indicate
which message word numbers (WN) are associated
with the call
x: unused bits (Table 39). The value of these bits is not
guaranteed.
• Message packets which contain the information
contained within the message codewords of a call.
8.7.3
For more information about the function of these packets
within the FLEX data stream see Section 8.8.
Information from vector codewords in received calls is sent
to the host in vector packets. For any address packet sent
to the host (except tone-only addresses), a corresponding
vector packet is always sent.
8.7.2
ADDRESS PACKET (ID = 01H)
VECTOR PACKETS (ID = 02H TO 57H)
The ID of the vector packet is the word number where the
vector word was received in the frame. The host must
associate vector packets with a call by searching for an
address packet previously received on the same phase
and with WN bits which match the ID of the vector packet.
Information from address codewords in received calls is
sent to the host in address packets. If less than 3-bit errors
are detected in a received address word and it matches an
enabled address assigned to the PCD5013, the address
packet is sent to the host processor. The address packet
contains the call address, the location in the data stream
of the associated vector, and other miscellaneous call
data.
The vector type of a vector packet indicates the format of
a call as one of:
• Numeric (3 types)
• Short message/tone-only
PA: priority address (Table 39). This bit is set if the
address was received as a priority address.
• Hex/binary
p: phase (Table 39). This is the phase on which the
address was detected (0 = A, 1 = B, 2 = C and 3 = D).
• Alphanumeric
LA: long address (Table 39). This bit is set if the address
was programmed in the PCD5013 as a LA.
• Short instruction.
• Secure message
The numeric, hex/binary, alphanumeric, and secure
message vector packets indicate the location and number
of message word packets in the message field. If more
than two bit errors are detected in the vector word (via
BCH calculations, parity calculations, check character
calculations, or value validation) the e bit is set and the
message words are not sent.
AI: address index (Table 39). This index identifies which
address was detected. Valid values are 00H to 0FH,
corresponding to the 16 programmable address words
and 80H to 8FH, corresponding to the 16 temporary
addresses (Section 8.8.5). Values 144 through to 159
correspond to 16 operator messaging addresses.
1999 Apr 12
40
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
Table 39 Address packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
0
0
0
0
0
0
0
1
2
PA
p1
p0
LA
x
x
x
x
1
AI7
AI6
AI5
AI4
AI3
AI2
AI1
AI0
0
TOA
WN6
WN5
WN4
WN3
WN2
WN1
WN0
8.7.4
K: first check bits of the message checksum
(Table 40 and Section 8.8.7).
NUMERIC VECTOR PACKET
WN: word number of vector (2 to 87 decimal) (Table 40).
WN describes the location of the vector word in the frame.
n: number of message words in the message (Table 40),
including the second vector word for long addresses,
(000 = 1 word message, 001 = 2 word message, etc.).
For long addresses, the first message word is located in
the word location that immediately follows the associated
vector.
e: error (Table 40). Set if more than 2-bit errors are
detected in the word, if the check character calculation fails
after error correction has been performed, or if the vector
value is determined to be invalid.
p: phase (Table 40). This is the phase on which the vector
was found (0 = A, 1 = B, 2 = C and 3 = D).
b: word number of message start in the message field
(3 to 87 decimal) (Table 40). For long addresses, the word
number indicates the location of the second message
word.
x: unused bits (Table 40). The value of these bits is not
guaranteed.
V: vector type identifier (Table 41).
Table 40 Numeric vector packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
0
WN6
WN5
WN4
WN3
WN2
WN1
WN0
2
e
p1
p0
x
x
V2
V1
V0
1
x
x
K3
K2
K1
K0
n2
n1
0
n0
b6
b5
b4
b3
b2
b1
b0
Table 41 Numeric vector definitions
V2
V1
V0
0
1
1
standard numeric
No special formatting of characters is specified.
1
0
0
special format numeric
Formatting of the received characters is predetermined by
special rules in the host (e.g. inserting spaces and dashes).
1
1
1
numbered numeric
Received information is numbered by the service provider to
indicate all messages have been properly received.
1999 Apr 12
TYPE
DESCRIPTION
41
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.7.5
PCD5013
t: message type (Tables 42 and 43). These bits define the
meaning of the d bits in this packet.
SHORT MESSAGE/TONE-ONLY VECTOR PACKET
V: vector type identifier, these bits set to 010 for a
short message/tone-only vector (Table 42).
x: unused bits (Table 42). The value of these bits is not
guaranteed.
WN: word number of vector (2 to 87 decimal) (Table 42).
WN describes the location of the vector word in the frame.
d: data bits whose definition depends on the value of t in
this packet according to Table 43. Note that if this vector is
received on a long address and the e bit in this packet is
not set, the decoder sends a message packet from the
word location immediately following the vector packet.
Except for the short message on a non-network address
(t = 0), all messages bits in the message packet are
unused and should be ignored.
e: error (Table 42). Set if more than 2-bit errors are
detected in the word, if the check character calculation fails
after error correction has been performed, or if the vector
value is determined to be invalid.
p: phase (Table 42). This is the phase on which the vector
was found (0 = A, 1 = B, 2 = C and 3 = D).
Table 42 Short message/tone-only vector packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
0
WN6
WN5
WN4
WN3
WN2
WN1
WN0
2
e
p1
p0
x
x
V2
V1
V0
1
x
x
d11
d10
d9
d8
d7
d6
0
d5
d4
d3
d2
d1
d0
t1
t0
Table 43 Short message/tone-only vector definitions; note 1
t1
t0
d11
d10
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
DESCRIPTION
0
0
c3
c2
c1
c0
b3
b2
b1
b0
a3
a2
a1
a0
first 3 numeric characters; note 2
0
1
s8
s7
s6
s5
s4
s3
s2
s1
s0
S2
S1
S0
8 sources (S) and 9 unused bits (s)
1
0
s1
s0
R0
N5
N4
N3
N2
N1
N0
S2
S1
S0
8 sources (S), message retrieval
flag (R), message number (N) and
2 unused bits (s)
1
1
spare message type
Notes
1. When this vector is sent in conjunction with a Network Address, the t1,to value ‘00’ represents Network ID information.
In this case the bit definitions are: T3 T2 T1 T0 M2 M1 M0 A4 A3 A2 A1 A0
Where T are Traffic Management Flags, M represents a multiplier and A is the service area.
2. For long addresses, an extra 5 characters are sent in the message packet immediately following the vector packet.
t0 and t1 are also set to ‘00’ when defining the last 12 bits of a Network Address.
1999 Apr 12
42
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.7.6
PCD5013
b: word number of message start in the message field
(Table 45). Valid values are 3 to 87 decimal.
HEX/BINARY, ALPHANUMERIC AND SECURE
MESSAGE VECTORS
x: unused bits (Table 45). The value of these bits is not
guaranteed.
V: vector type identifier (Table 44).
WN: word number of vector (2 to 87 decimal) (Table 45).
WN describes the location of the vector word in the frame.
Note that for long addresses, the first message packet is
sent from the word location immediately following the word
location of the vector packet. The b bits indicate the
second message word in the message field if one exists.
e: error (Table 45). Set if more than 2-bit errors are
detected in the word, if the check character calculation fails
after error correction has been performed, or if the vector
value is determined to be invalid.
Table 44 Non-numeric vector definitions
p: phase (Table 45). This is the phase on which the vector
was found (0 = A, 1 = B, 2 = C and 3 = D).
n: number of message words in this frame (Table 45),
including the first message word that immediately follows
a long address vector. Valid values are 1 to 85 decimal.
V2
V1
V0
0
0
0
secure
1
0
1
alphanumeric
1
1
0
hex/binary
TYPE
Table 45 Hex/binary, alphanumeric and secure message vector packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
0
WN6
WN5
WN4
WN3
WN2
WN1
WN0
2
e
p1
p0
x
x
V2
V1
V0
1
x
x
n6
n5
n4
n3
n2
n1
0
n0
b6
b5
b4
b3
b2
b1
b0
1999 Apr 12
43
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.7.7
PCD5013
i: instruction type (Tables 46 and 47). These bits define
the meaning of the d bits in this packet.
SHORT INSTRUCTION VECTOR
V: these bits are set 001 for a short instruction vector.
x: unused bits (Table 46). The value of these bits is not
guaranteed.
WN: word number of vector (2 to 87 decimal) (Table 46).
WN describes the location of the vector word in the frame.
d: data bits whose definition depend on the value of the
i bits in this packet according to Table 47. Note that if this
vector is received on a long address and the e bit in this
packet is not set, the decoder sends a message packet
immediately following the vector packet. All message bits
in the message packet are unused and should be ignored.
e: error (Table 46). Set if more than 2-bit errors are
detected in the word, if the check character calculation fails
after error correction has been performed, or if the vector
value is determined to be invalid.
p: phase (Table 46). This is the phase on which the vector
was found (0 = A, 1 = B, 2 = C and 3 = D).
Table 46 Short instruction vector packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
0
WN6
WN5
WN4
WN3
WN2
WN1
WN0
2
e
p1
p0
x
x
V2
V1
V0
1
x
x
d10
d9
d8
d7
d6
d5
0
d4
d3
d2
d1
d0
i2
i1
i0
Table 47 Short instruction vector definitions
i2
i1
i0
d10
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
DESCRIPTION
0
0
0
a3
a2
a1
a0
f6
f5
f4
f3
f2
f1
f0
0
0
1
d10
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
system event; note 2
0
1
0
a3
a2
a1
a0
f6
N5
N4
N3
N2
N1
N0
temporary address with message
sequence number; note 2
0
1
1
reserved
1
0
0
reserved
1
0
1
reserved
1
1
0
reserved
1
1
1
reserved for test
temporary address assignment,
note 1
Notes
1. Assigned temporary address index a and associated frame number f (Section 8.8.5).
2. Refer to”FLEX Protocol specification G1.9”.
1999 Apr 12
44
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.7.8
PCD5013
Only codewords containing the numeric message are to
be transmitted. The space character CH is used to fill any
unused 4-bit characters in the last word and zeros to fill
any remaining partial characters. The checksum includes
only the codewords comprising the shortened message,
along with the space and fill characters used to fill in the
last word.
MESSAGE PACKETS (ID = 03H TO 57H)
8.7.8.1
General
The message field follows the vector field in the FLEX
protocol. It contains the message data, checksum
information, and may contain fragment and message
numbers (Sections 8.8.8 and 8.8.6). If the error bit of a
vector word is not set and the vector word indicates that
there are message words associated with the page, the
message words are sent in message packets to the host.
Table 48 Standard and alternate numeric character sets;
Peoples Republic of China (PRC) option ‘on’
and ‘off’
The ID of the message packet is the word number where
the message word was received in the frame.
CHARACTER
B3
B2
B1
B0
0
0
0
0
0
0
e: error (Table 49). Set if more than 2-bit errors are
detected in the word.
0
0
0
p: phase (Table 49). This is the phase on which the vector
was found (0 = A, 1 = B, 2 = C and 3 = D).
0
WN: word number of message word (3 to 87 decimal)
(Table 49). WN describes the location of the message
word in the frame.
i: these are the information bits of the message word
(Table 49). The definition of these i bits depends on the
vector type and which word of the message is being
received.
8.7.8.2
Numeric Message
FLEX numeric messages are encoded using the
4-bit BCD encoded characters sets described in Table 48.
Characters are placed in codewords along with additional
information about the message as described in
Tables 50 and 51 and the following definitions. The 4-bit
numeric characters of the message are designated as
letters a, b, c, d, ... z, A, B etc.
PRC ‘on’
PRC ‘off’
0
0
0
1
1
1
1
0
2
2
0
1
1
3
3
1
0
0
4
4
0
1
0
1
5
5
0
1
1
0
6
6
0
1
1
1
7
7
1
0
0
0
8
8
1
0
0
1
9
9
1
0
1
0
A
spare
1
0
1
1
B
U
1
1
0
0
space
space
1
1
0
1
C
−
1
1
1
0
D
]
1
1
1
1
E
[
Table 49 Message packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
0
WN6
WN5
WN4
WN3
WN2
WN1
WN0
2
e
p1
p0
i20
i19
i18
i17
i16
1
i15
i14
i13
i12
i11
i10
i9
i8
0
i7
i6
i5
i4
i3
i2
i1
i0
1999 Apr 12
45
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
K: least significant 2 bits of 6-bit message checksum
(Tables 50 and 51), most significant 4 bits are in the
vector word. See Section 8.8.7 for a description of
message checksums.
S: special format, (Table 51). In the numbered message
format, when this bit is set, a special display format should
be used. Spaces and dashes, specified by the host, are
inserted into the received message to ease reading of the
message. This feature may avoid the transmission of an
additional word on the channel. The actual format is
undefined in FLEX and may be determined by the
manufacturer.
N: message number (Table 51). See Section 8.8.8 for a
description of message numbering.
R: message retrieval flag (Table 51). When this bit is set,
the pager expects this message to be numbered.
See Section 8.8.8 for a description of message
numbering.
Table 50 Standard (V = 011) or special format (V = 100) 4, 10, 15, 20, 25, 31, 36, or 41 characters
MESSAGE
WORD
i0
i1
i2
i3
i4
i5
i6
i7
i8
i9
i10
i11
i12
i13
i14
i15
i16
i17
i18
i19
i20
1st
K4
K5
a0
a1
a2
a3
b0
b1
b2
b3
c0
c1
c2
c3
d0
d1
d2
d3
e0
e1
e2
2nd
e3
f0
f1
f2
f3
g0
g1
g2
g3
h0
h1
h2
h3
i0
i1
i2
i3
j0
j1
j2
j3
3rd
k0
k1
k2
k3
l0
l1
l2
l3
m0 m1 m2 m3
n0
n1
n2
n3
o0
o1
o2
o3
q0
4th
q1
q2
q3
r0
r1
r2
r3
s0
s1
t1
t2
t3
u0
u1
u2
u3
v0
v1
s2
s3
t0
5th
v2
v3
w0
w1
w2
w3
y0
y1
y2
y3
z0
z1
z2
z3
A0
A1
A2
A3
B0
B1
B2
6th
B3
C0
C1
C2
C3
D0
D1
D2
D3
E0
E1
E2
E3
F0
F1
F2
F3
G0
G1
G2
G3
7th
H0
H1
H2
H3
I0
I1
I2
I3
J0
J1
J2
J3
V0
V1
V2
V3
L0
L1
L2
L3
M0
8th
M1 M2 M3 O0
O1
O2
O3
P0
P1
P2
P3
Q0
Q1
Q2
Q3
T0
T1
T2
T3
U0
U1
i18
i19
i20
Table 51 Numbered (V = 111) 2, 8, 13, 18, 23, 29, 34, or 39 numeric characters
MESSAGE
WORD
i0
i1
i2
i3
i4
i5
i6
i7
i8
i9
i10
i11
i12
i13
i14
i15
i16
i17
1st
K4
K5
N0
N1
N2
N3
N4
N5
R0
S0
a0
a1
a2
a3
b0
b1
b2
b3
c0
c1
c2
2nd
c3
d0
d1
d2
d3
e0
e1
e2
e3
f0
f1
f2
f3
g0
g1
g2
g3
h0
h1
h2
h3
3rd
i0
i1
i2
i3
j0
j1
j2
j3
k0
k1
k2
k3
l0
l1
l2
l3
m0 m1 m2 m3
n0
4th
n1
n2
n3
o0
o1
o2
o3
q0
q1
q2
q3
r0
r1
r2
r3
s0
s1
s2
s3
t0
t1
5th
t2
t3
u0
u1
u2
u3
v0
v1
v2
v3
w0
w1
w2
w3
y0
y1
y2
y3
z0
z1
z2
6th
z3
A0
A1
A2
A3
B0
B1
B2
B3
C0
C1
C2
C3
D0
D1
D2
D3
E0
E1
E2
E3
H0
H1
H2
7th
F0
F1
F2
F3
G0
G1
G2
G3
H3
I0
I1
I2
I3
J0
J1
J2
J3
V0
8th
V1
V2
V3
L0
L1
L2
L3
M0 M1 M2 M3 O0
O1
O2
O3
P0
P1
P2
P3
Q0
Q1
1999 Apr 12
46
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.7.8.3
PCD5013
Where symbolic characters (e.g. Chinese, Kanji etc.) are
being transmitted, special rules for fragment and message
termination are defined in Section 8.8.6.1.
Alphanumeric Message
FLEX alphanumeric messages are encoded using the
7-bit encoded alphanumeric character set defined in
Table 52. Characters are placed in codewords along with
additional information about the message as described in
Tables 53 and 54 and the following definitions. The 7-bit
characters of the message are designated lower case
letters a, b, c, d, etc.
Each 7-bit field, starting with the second character of the
second word in the message (first character of the second
word in all remaining fragments), represents standard
ASCII (ISO 646-1983E) characters with options for certain
international characters.
Alphanumeric messages can be sent as fragments.
See Section 8.8.6 for a description of message
fragmentation.
Control characters that are not acted upon by the pager
are ignored in the display process (do not require display
space) but are stored in memory for possible download to
an external device. The ASCII character ETX (03H) should
be used to fill any unused 7-bit characters in a word.
Table 52 FLEX alphanumeric character set
LEAST SIGNIFICANT 4 BITS
OF CHARACTER (HEX)
1999 Apr 12
MOST SIGNIFICANT 3 BITS OF CHARACTER (HEX)
0
1
2
3
4
5
6
7
0
NUL
DLE
SP
0
@
P
‘
p
1
SOH
DC1
!
1
A
Q
a
q
2
STX
DC2
“
2
B
R
b
r
3
ETX
DC3
#
3
C
S
c
s
4
EOT
DC4
$
4
D
T
d
t
5
ENQ
NAK
%
5
E
U
e
u
6
ACK
SYN
&
6
F
V
f
v
7
BEL
ETB
’
7
G
W
g
w
8
BS
CAN
(
8
H
X
h
x
9
TAB
EM
)
9
I
Y
i
y
A
LF
SUB
*
:
J
Z
j
z
B
VT
ESC
+
;
K
[
k
{
C
FF
FS
,
<
L
\
l
D
CR
GS
-
=
M
]
m
}
E
SO
RS
.
>
N
^
n
~
F
SI
US
/
?
O
_
o
DEL
47
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
K: 10-bit fragment checksum (Tables 53 and 54).
See Section 8.8.7 for a description of message checksum.
R: message retrieval flag (Table 53). When this bit is set,
the pager expects this message to be numbered.
See Section 8.8.8 for a description of message
numbering.
C: 1-bit message continued flag (Tables 53 and 54).
When this bit is set, fragments of this message are to be
expected in following frames. See Section 8.8.6 for a
description of message fragmentation.
S: 7-bit signature field (Table 53). The signature is defined
to be the 1’s complement of the binary sum over the total
message (all fragments). 7 bits at a time are taken (on
alpha character boundary) starting with the first 7 bits
directly following the signature field, a6a5a4a3a2a1a0,
b6b5b4b3b2b1b0, etc. The 7 LSBs of the result are
transmitted as the message signature.
F: 2-bit message fragment number (Tables 53 and 54).
This is a modulo 3 message fragment number which is
incremented by 1 in successive message fragments.
See Section 8.8.6 for a description of message
fragmentation.
U, V: fragmentation control bits (Table 54). This field exists
in all fragments except the first fragment. It is used to
support character position tracking in each fragment when
symbolic characters (character made up of 1, 2 or 3
ASCII characters) are transmitted using the alphanumeric
message type. The default value is 0,0.
See Section 8.8.6.1 for a description of fragment control.
N: message number (Tables 53 and 54).
See Section 8.8.8 for a description of message
numbering.
M: 1-bit mail drop flag (Table 53). When this bit is set, it
indicates the message is to be stored in a special area in
memory and is written over existing data automatically in
that memory space.
Table 53 Vector type V = 101 first fragment
MESSAGE
WORD
i0
i1
i2
i3
i4
i5
i6
i7
i8
i9
i10
i11
i12
i13
i14
i15
i16
i17
i18
i19
i20
1st
K0
K1
K2
K3
K4
K5
K6
K7
K8
K9
C0
F0
F1
N0
N1
N2
N3
N4
N5
R0
M0
2nd
S0
S1
S2
S3
S4
S5
S6
a0
a1
a2
a3
a4
a5
a6
b0
b1
b2
b3
b4
b5
b6
3rd
c0
c1
c2
c3
c4
c5
c6
d0
d1
d2
d3
d4
d5
d6
e0
e1
e2
e3
e4
e5
e6
4th
f0
f1
f2
f3
f4
f5
f6
g0
g1
g2
g3
g4
g5
g6
h0
h1
h2
h3
h4
h5
h6
5th
i0
i1
i2
i3
i4
i5
i6
j0
j1
j2
j3
j4
j5
j6
k0
k1
k2
k3
k4
k5
k6
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
...
nth
Table 54 Vector type V = 101 other fragments
MESSAGE
WORD
i0
i1
i2
i3
i4
i5
i6
i7
i8
i9
i10
i11
i12
i13
i14
i15
i16
i17
i18
i19
i20
1st
K0
K1
K2
K3
K4
K5
K6
K7
K8
K9
C0
F0
F1
N0
N1
N2
N3
N4
N5
U0
V0
2nd
a0
a1
a2
a3
a4
a5
a6
b0
b1
b2
b3
b4
b5
b6
c0
c1
c2
c3
c4
c5
c6
3rd
d0
d1
d2
d3
d4
d5
d6
e0
e1
e2
e3
e4
e5
e6
f0
f1
f2
f3
f4
f5
f6
4th
g0
g1
g2
g3
g4
g5
g6
h0
h1
h2
h3
h4
h5
h6
i0
i1
i2
i3
i4
i5
i6
5th
j0
j1
j2
j3
j4
j5
j6
k0
k1
k2
k3
k4
k5
k6
l0
l1
l2
l3
l4
l5
l6
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
...
nth
1999 Apr 12
48
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.7.8.4
PCD5013
R: message retrieval flag (Table 55). When this bit is set,
the pager expects this message to be numbered.
See Section 8.8.8 for a description of message
numbering.
Hex/binary message
FLEX hexadecimal/binary messages may be encoded
using any word size (blocking length) in the
range 1 to 16 bits. Words are placed in codewords along
with additional information about the message as
described in Tables 55 and 56 and these definitions.
The message data in Tables 55 and 56 have blocking
lengths of 4 bits; words are designated lower case letters
a, b, c, d etc.
s: 5-bit field reserved for future use (Table 55).
Default value = 00000.
M: 1-bit mail drop flag, see Table 55. When this bit is set,
the message is to be stored in a special area in memory to
overwrite existing data in the same memory space.
Hexadecimal/binary messages can be sent as fragments.
See Section 8.8.6 for a description of message
fragmentation. Messages and message fragments are
terminated, or interrupted in the case of a non-terminating
fragment, on the last full character boundary in the last
codeword. Unused bits are cleared if the last valid data bit
is logic 1, or set if the last valid data bit is logic 0. If the
terminating fragment exactly fills its last codeword, an
additional codeword is sent to indicate the location of the
last character. This codeword is filled with logic 0s if the
last valid data bit is logic 1 and filled with logic 1s if the last
valid data bit is logic 0.
D: 1-bit display direction field (Table 55). D = 0 display left
to right, D = 1 display right to left (valid only when data sent
as characters i.e. blocking length not equal 0001).
B: 4-bit blocking length (Table 55). Indicates bits per
character. B3B2B1B0 = 0001 = 1-bit per character
(binary/transparent data), 1111 = 15 bits per character,
0000 = 16 bits per character. Data with a blocking length
other than 1 is assumed to be displayed on a character by
character basis (default value = 0001). Note: Tables 55
and 56 show B = 4-bit blocking length.
S: 8-bit signature field (Table 55). The 1’s complement of
the binary sum, taken 8 bits at a time, over the total
message prior to formatting into fragments. The first 8 bits
following the signature field are summed with the following
8 bits, b3b2b1b0a3a2a1a0 + d3d2d1d0c3c2c1c0, etc.
continuing to the last valid data bit in the last word of the
last fragment (the sum does not include termination bits).
The 8 LSBs of the result are inverted (1’s complement)
and transmitted as the message signature.
Fields K to N make up the first word of a message and the
first word of every fragment in a long message.
K: 12-bit fragment checksum (Tables 55 and 56).
See Section 8.8.7 for a description of message
checksums.
C: 1-bit message continued flag (Tables 55 and 56).
When this bit is set, fragments of this message are to be
expected in following frames. See Section 8.8.6 for a
description of message fragmentation.
8.7.8.5
FLEX secure messages are encoded using the 7-bit
FLEX alphanumeric character set (Section 8.7.8.3).
These characters are placed in codewords along with
additional information about the message as described in
Table 57 and the following definitions. In Table 57, 7-bit
characters of the message are designated lower case
letters a, b, c, d etc.
F: 2-bit message fragment number (Tables 55 and 56).
This is a modulo 3 message fragment number which is
incremented by 1 in successive message fragments.
See Section 8.8.6 for a description of message
fragmentation.
N: message number (Tables 55 and 56).
See Section 8.8.8 for a description of message
numbering.
Secure messages follow the same fragmentation and
termination rules as alphanumeric messages
(Section 8.7.8.3).
H: 1-bit header message flag (Table 55). It is a header
message only when this bit is set, otherwise it is a data
message. A header message is a displayable tag
associated with a non-displayable data message.
The header message (which is sent first) and the data
message, both have the same message number.
K: 10-bit fragment checksum (Table 57).
See Section 8.8.7 for a description of message
checksums.
C: 1-bit message continued flag (Table 57). When this bit
is set, fragments of this message are to be expected in
following frames. See Section 8.8.6 for a description of
message fragmentation.
The second codeword of the first fragment of a hex/binary
message contains fields R to S. These fields are only
transmitted in the first fragment of a message.
1999 Apr 12
Secure message
49
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
F: 2-bit message fragment number (Table 57). This is a
modulo 3 message fragment number which is
incremented by 1 in successive message fragments.
See Section 8.8.6 for a description of message
fragmentation.
N: message number (Table 57). See Section 8.8.8 for a
description of message numbering.
s: spare bits (Table 57), are not used and are set to 0.
Table 55 Vector type V = 110 first fragment
MESSAGE
WORD
i0
i1
i2
i3
i4
i5
i6
i7
i8
i9
i12
i13
i14
i15
i16
i17
i18
i19
i20
1st
K0
K1
K2
K3
K4
K5
K6
K7
K8
K9 K10 K11 C0
F0
F1
N0
N1
N2
N3
N4
N5
2nd
R0
M0
D0
H0
B0
B1
B2
B3
s0
s1
s2
s3
s4
S0
S1
S2
S3
S4
S5
S6
S7
3rd
a0
a1
a2
a3
b0
b1
b2
b3
c0
c1
c2
c3
d0
d1
d2
d3
e0
e1
e2
e3
f0
4th
f1
f2
f3
g0
g1
g2
g3
h0
h1
h2
h3
i0
i1
i2
i3
j0
j1
j2
j3
k0
k1
5th
k2
k3
l0
l1
l2
l3
m0 m1 m2 m3
n0
n1
n2
n3
o0
o1
o2
o3
q0
q1
q2
6th
q3
r0
r1
r2
r3
s0
s1
s2
s3
t0
t1
t2
t3
u0
u1
u2
u3
v0
v1
v2
v3
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i10
i11
i10
i11
...
nth
Table 56 Vector type V = 110 all other fragments
MESSAGE
WORD
i0
i1
i2
i3
i4
i5
i6
i7
i8
i9
i12
i13
i14
i15
i16
i17
i18
i19
i20
1st
K0
K1
K2
K3
K4
K5
K6
K7
K8
K9 K10 K11 C0
F0
F1
N0
N1
N2
N3
N4
N5
2nd
a0
a1
a2
a3
b0
b1
b2
b3
c0
c1
c2
c3
d0
d1
d2
d3
e0
e1
e2
e3
f0
3rd
f1
f2
f3
g0
g1
g2
g3
h0
h1
h2
h3
i0
i1
i2
i3
j0
j1
j2
j3
k0
k1
4th
k2
k3
l0
l1
l2
l3
m0 m1 m2 m3
n0
n1
n2
n3
o0
o1
o2
o3
q0
q1
q2
5th
q3
r0
r1
r2
r3
s0
s1
s2
s3
t0
t1
t2
t3
u0
u1
u2
u3
v0
v1
v2
v3
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
...
nth
Table 57 Vector type V = 000 all fragments
MESSAGE
WORD
i0
i1
i2
i3
i4
i5
i6
i7
i8
i9
i10
i11
i12
i13
i14
i15
i16
i17
i18
i19
i20
1st
K0
K1
K2
K3
K4
K5
K6
K7
K8
K9
C0
F0
F1
N0
N1
N2
N3
N4
N5
s0
s1
2nd
a0
a1
a2
a3
a4
a5
a6
b0
b1
b2
b3
b4
b5
b6
c0
c1
c2
c3
c4
c5
c6
3rd
d0
d1
d2
d3
d4
d5
d6
e0
e1
e2
e3
e4
e5
e6
f0
f1
f2
f3
f4
f5
f6
4th
g0
g1
g2
g3
g4
g5
g6
h0
h1
h2
h3
h4
h5
h6
i0
i1
i2
i3
i4
i5
i6
5th
j0
j1
j2
j3
j4
j5
j6
k0
k1
k2
k3
k4
k5
k6
l0
l1
l2
l3
l4
l5
l6
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
...
nth
1999 Apr 12
50
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.7.9
PCD5013
System providers supporting local time transmissions are
required to transmit at least one time related BIW in each
phase transmitted in frame 0, cycle 0. The time
transmitted is the local time for the transmitted time zone
and refers to the actual time at the leading edge of the first
bit of sync 1 of frame 0 of the current cycle. See Tables 58,
59, and 60 and the following bit definitions of the time
related BIWs.
BLOCK INFORMATION WORD PACKET (ID = 00H)
The FLEX protocol allows systems to transmit time
information using block information words. The information
carried in a BIW depends on the BIW word format
(Table 58). The first BIW of each phase, carrying
information about the frame structure, is used internally by
the PCD5013 and is never transmitted to the host with the
exception of the system collapse which is sent to the host
when the PCD5013 is in manual collapse mode.
e: error (Table 58). Set if more than 2-bit errors are
detected in the word or if the check character calculation
fails after error correction has been performed.
The PCD5013 can be configured to send all time and date
BIWs (BIW001, BIW010 and BIW101) to the host by
setting the SBI bit in the control packet, see Section 8.4.7.
All block information words 2-4 can be optionally sent to
the host by setting the ABI bit in the roaming control
packet. When the SBI or ABI bit is set and a BIW is
received with an uncorrectable number of bit errors, the
PCD5013 sends the BIW to the host indicating that the
codeword was received in error (regardless of the BIW
word format). The PCD5013 does not support decoding of
vector and message words associated with the
data/system message BIW101.
p: phase (Table 58), is the phase on which the BIW was
found (0 = A, 1 = B, 2 = C and 3 = D).
x: unused bits (Table 58). Their value is not guaranteed.
f: word format type (Table 58). The value of these bits
modify the meaning of the s bits in this packet as described
in Table 59.
s: BIW information bits (Table 58). The definition of these
bits depend on the f bits in this packet.
Table 58 BIW packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
0
0
0
0
0
0
0
0
2
e
p1
p0
x
x
f2
f1
f0
1
x
x
s13
s12
s11
s10
s9
s8
0
s7
s6
s5
s4
s3
s2
s1
s0
Table 59 BIW definitions
f2
f1
f0
s13 s12 s11 s10
0
0
0
i8
i7
i6
0
0
1
m3
m2
0
1
0
S2
S1
0
1
1
Reserved by FLEX protocol for future use (1)
1
0
0
Reserved by FLEX protocol for future use (1)
1
0
1
1
1
0
1
1
1
z9
z8
s9
s8
s7
s6
s5
s4
s3
s2
s1
s0
i5
i4
i3
i2
i1
i0
C4
C3
C2
C1
C0 Local ID, Coverage Zone(1)
m1
m0
d4
d3
d2
d1
d0
Y4
Y3
Y2
Y1
Y0 month/day/year(2)
S0
M5
M4
M3
M2
M1
M0
H4
H3
H2
H1
H0 second/minute/hour(2)
z0
0
1
0
X
system message;
T4
T3
T2
T1
T0
Country Code, Traffic
Management Flags(1)
z7
z6
z5
z4
z3
z2
z1
(2)
Reserved by FLEX protocol for future use (1)
c8
c7
c6
c5
c4
c3
c2
c1
c0
Notes
1. Decoded only if ABI bit is set.
2. Decoded only if SBI or ABI bit is set.
1999 Apr 12
DESCRIPTION
51
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
H: hour field (Table 59). 00000 to 10111 binary
correspond to 0 to 23 hours.
i: Local ID (Table 59). A Local ID along with the Coverage
Zone, Country Code and Traffic Management Flags define
a specific simulcast coverage area for SSID roaming.
L: daylight savings time (Table 59). When this bit is set,
the time being transmitted is local standard time. When it
is clear, the time being transmitted is daylight savings time.
C: Coverage Zone (Table 59). A Coverage Zone along
with a Local ID, Country Code and Traffic Management
Flags define a specific simulcast coverage area for SSID
roaming.
m: month field (Table 59). 0001 to 1100 binary
correspond to January to December in month order.
z: time zone (Table 59). These bits indicate the time zone
for the time which is being transmitted. The offset
from GMT is the offset for local standard time. Table 60
describes the values for z.
d: day field (Table 59). 00001 to 11111 binary correspond
to 1 to 31 days in the month.
c: Country code (Table 59) identified in the CCITT (ITU-T)
Standard E.212, Annex A.
Y: year field (Table 59). This represents the year with
modulo 32 arithmetic. 00000 to 11111 binary representing
years 1994 to 2025 and 2026 to 2057.
T: Traffic management flags (Table 59). indicate a
possible assignment of any combination of 4 groups of
traffic to an RF channel. Each roaming subscriber unit,
after finding an RF channel which matches its
programmed Local ID, Coverage Zone and Country Code
responds to only one of the 4 Traffic Management Flags.
When one or more of the transmitted Traffic Management
Flags are set to O, subscriber units assigned to those
traffic groups must find another RF channel with the same
LID, Coverage Zone and Country Code information with its
assigned Traffic Flag set to 1.
S: seconds field (Table 59). This represents a coarse
value of the seconds field. These bits represent the
seconds in 1⁄8 minute (7.5 s) increments.
000 to 111 binary correspond to 0 to 52.5 seconds.
M: minute field (Table 59). 000000 to 111011 binary
correspond to 0 to 59 minutes.
Table 60 Time zone values
z4
z3
z2
z1
z0
TIME ZONE
z4
z3
z2
z1
z0
TIME ZONE
0
0
0
0
0
GMT
1
0
0
0
0
reserved
0
0
0
0
1
GMT + 01:00h
1
0
0
0
1
GMT + 05:45h
0
0
0
1
0
GMT + 02:00h
1
0
0
1
0
GMT + 06:30h
0
0
0
1
1
GMT + 03:00h
1
0
0
1
1
GMT + 09:30h
0
0
1
0
0
GMT + 04:00h
1
0
1
0
0
GMT − 03:30h
0
0
1
0
1
GMT + 05:00h
1
0
1
0
1
GMT − 11:00h
0
0
1
1
0
GMT + 06:00h
1
0
1
1
0
GMT − 10:00h
0
0
1
1
1
GMT + 07:00h
1
0
1
1
1
GMT − 09:00h
0
1
0
0
0
GMT + 08:00h
1
1
0
0
0
GMT − 08:00h
0
1
0
0
1
GMT + 09:00h
1
1
0
0
1
GMT − 07:00h
0
1
0
1
0
GMT + 10:00h
1
1
0
1
0
GMT − 06:00h
0
1
0
1
1
GMT + 11:00h
1
1
0
1
1
GMT − 05:00h
0
1
1
0
0
GMT + 12:00h
1
1
1
0
0
GMT − 04:00h
0
1
1
0
1
GMT + 03:30h
1
1
1
0
1
GMT − 03:00h
0
1
1
1
0
GMT + 04:30h
1
1
1
1
0
GMT − 02:00h
0
1
1
1
1
GMT + 05:30h
1
1
1
1
1
GMT − 01:00h
1999 Apr 12
52
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.8
8.8.1
PCD5013
The synchronization portion consists of: a first sync signal
at 1600 bps; a frame information word having the frame
number 0 to 127 (7 bits) and the cycle number
0 to 14 (4 bits); and a second sync signal at the data rate
of the interleaved portion.
Message reception
FLEX SIGNAL STRUCTURE
The FLEX signal transmitted on the radio channel (see
Fig.18) consists of a series of four minute cycles, each
cycle having 128 frames at 1.875 seconds per frame.
A pager may be assigned to process any number of the
frames. Battery saving is performed for frames which are
not assigned. The FLEX signal can assign additional
frames to the pager using collapse, fragmentation,
temporary addressing or carry-on information within the
FLEX signal.
The block information field contains BIWs. These can be
used for determining time and date information and certain
paging system information.
The address field contains addresses assigned to paging
devices. Addresses are used to identify information sent to
individual paging devices and/or groups of paging devices.
Information in the FLEX signal may indicate that an
address is a priority address. An address may be either a
short (one word) address or a long (two word) address.
An address may be a tone-only address in which case
there is no additional information associated with the
address. If an address is not a tone-only address, then
there is an associated vector word in the vector field.
Information in the FLEX signal indicates the location of
the vector word in the vector field associated with the
address. A pager may perform battery saving at the end of
the address field when its address(es) is not detected.
Each FLEX frame has a synchronization portion followed
by an eleven block data portion, each block lasting
160 milliseconds. The synchronization portion indicates
the rate at which the data portion is transmitted,
1600, 3200 or 6400 bits per second (bps). The 1600 bps
rate is transmitted at 1600 symbols per second (sps)
using 2 level FSK modulation and consists of a single
phase of information at 1600 bps, phase-A. The 3200 bps
rate is transmitted at either 1600 sps using 4 level FSK
modulation or 3200 sps using 2 level FSK modulation and
consists of two concurrent phases of information at
1600 bps, phase-A and phase-C. The 6400 bps rate is
transmitted at 3200 sps using 4 level FSK modulation and
consists of four concurrent phases of information at
1600 bps (phase-A, -B, -C and -D).
The vector field consists of a series of vector words.
Depending upon the type of message, a vector word (or
words in the case of a long address) may either contain all
of the information necessary for the message, or indicate
the location of message words in the message field
comprising the message information. Short addresses
have one associated vector word in the vector field. Long
addresses have one associated vector word in the vector
field directly followed by the first message codeword of the
call.
Each block has eight interleaved words per phase, thus
there are 88 codewords (numbered 0 to 87) per phase in
every frame. Each word has information contained within
an error correcting code which allows for bit error
correction and detection. The 88 words in each phase are
organized into a block information field, an address field, a
vector field, a message field, and an idle field.
The boundaries between the fields are independent of the
block boundaries. Furthermore, at 3200 and 6400 bps,
the information in one phase is independent of the
information in a concurrent phase, and the boundaries
between the fields of one phase are unrelated to the
boundaries between the fields in a concurrent phase.
1999 Apr 12
The message field consists of a series of information
words containing message information. The message
information may be formatted in ASCII, BCD or binary
depending upon the message type.
53
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.8.2
PCD5013
NIDs and SSIDs are referred to as Roaming IDs.
In addition pagers may be programmed to search for calls
on a channel without finding an SSID or an NID in order to
receive calls on that RF channel. In this case the Roaming
ID associated with the channel is programmed within the
pager as having ANY ID.
FLEX ROAMING STRUCTURE
The FLEX paging protocol defines two methods for
supporting roaming pagers:
• Simulcast System identification (SSID) roaming, where
pagers scan a pre-programmed set of channels and
identify each simulcast area which is to be included in
the desired roaming area
8.8.2.1
• Network identification (NID) roaming where pagers
examine all frequencies within the subscriber units’s
range for the presence of a marker (NID). The NID
indicates whether the channel is affiliated with the
desired roaming network.
Example Roaming System
Figure 17 shows six RF frequencies servicing three cities.
NID1 is used to identify a network covering all three cities
and SSIDs A, B and C identify the specific simulcast areas
covering cities A, B and C. In city C, the large amount of
traffic has resulted in the service provider activating
additional RF channels identified as a, b, d, e and f. In this
example, the pager is assigned Roaming IDs as follows:
A Simulcast System Identifier (SSID) is carried in the Block
Identification Field. A SSID is composed of a Local
Identifier (LID), a Coverage Zone, a Country Code and
Traffic Management Flags. These components define a
simulcast area which is unique worldwide. An LID is
unique within a Country Code and cannot be reassigned to
another operator in any paging RF band.
SSIDC
NID1
traffic management group 2 (0100)
Thus the pager will monitor frequencies as follows:
A Network Identifier (NID) is carried in the address and
vector fields. NIDs are unique within an RF band and are
composed of a Network Address, a Service Area Identifier,
a Multiplier and Traffic Management Flags. An RF channel
may combine roaming traffic from several different Service
Providers by carrying their respective NIDs.
fb when in the area of city A
fc when in the area of city B
fd when in the area of city C.
For further information on FLEX Roaming, see the
“FLEX™ specification G1.9”.
handbook, full pagewidth
NID1 - 0011 SSIDC - 0000
ff
NID1 - 0000 SSIDC - 1000
fe
NID1 - 0000 SSIDC - 0100
fd
fc
NID1 - 1111 SSIDB - 1111
NID1 - 1111 SSIDA - 1111
City A
NID1 - 0000 SSIDC - 0010
fb
NID1 - 1100 SSIDC - 0001
fa
City B
City C
Pager is assigned SSIDC as Home with NID1 active away from Home.
Pager is assigned to TMG 2 (0100 - 3rd flag from right).
Frequency list contains fa, fb, fc, fd, fe and ff.
MGL555
Fig.17 Roaming system example.
1999 Apr 12
54
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
15 cycles (1 hour)
handbook, full pagewidth
cycle 0
cycle 1
cycle 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . cycle 13
cycle 14
1 cycle (4 minutes) = 128 frames
frame 0
frame 1
frame 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . frame 126
frame 127
1 frame (1.875 seconds) = sync + 11 blocks
sync
block 0
block 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . block 9
interleaved block (160 ms)
sync (115 ms)
sync 1
frame info
sync 2
8 × 32 bits @ 1600 bps
16 × 32 bits @ 3200 bps
32 × 32 bits @ 6400 bps
8 + 32 bits @ 1600 bps
48 + 32 bits @ 3200 bps
128 + 32 bits @ 6400 bps
32 bits @ 1600 bps (20 ms)
112 bits @ 1600 bps (70 ms)
Fig.18 FLEX signal structure.
1999 Apr 12
block 10
55
2 - level FM
2 or 4 level FM
4 - level FM
MGK469
(25 ms)
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.8.3
PCD5013
Tables 61 and 62 show an example of receiving three
messages (possibly portions of fragmented or group
messages), and two BIW packets in the first two blocks of
a 2 phase 3200 bps FLEX frame in case of an
any-phase pager. Table 61 shows the block number, word
number and word content of both phase-A and phase-C
(subscripts indicate the call number). In a 6400 bps
FLEX frame, there would be four phases: A, B, C and D;
in a 1600 bps signal there would be only phase-A.
Table 62 shows the sequence of packets transmitted to
the host.
MESSAGE BUILDING
The PCD5013 sends data from the FLEX signal to the
host in packets. Data is transmitted one block at a time,
and one phase at a time. For a 2 phase transmission,
information in block 0 phase-A is converted into packets
and sent to the host, then information in block 0 phase-C
is sent to the host followed by information in
block 1 phase-A and then information in block 1 phase-C
etc. Codewords for different calls may therefore be
interleaved, so the host must use the phase and word
number embedded in each packet to associate that packet
with a particular call.
Table 62 PCD5013 packet sequence
The phase and word number of the vector packet provides
a unique key which allows the host to associate all the data
for a particular call within a frame. The host must then use
information embedded in the vector word to calculate what
message word locations are associated with the vector.
PACKET PHASE
WORD
0
A
address
7
note 1
2
A
address
8
note 1
3
A
vector
7
pointer to
phase-A
word 9
BIW1; note 1
4
C
BIW
n.a.
note 2
C
BIW
n.a.
note 2
0
PHASE-A
BIW1; note 1
COMMENT
1
Table 61 FLEX transmission sequence
BLOCK
PACKET WORD
TYPE
NO.
PHASE-C
1
addr; note 2
BIW
5
2
addr; note 2
BIW
6
C
10
note 1
3
addr1
addr; note 2
long
address
4
addr2
addr; note 2
7
A
vector
8
5
vect; note 2
long addr3 (cw 1)
pointer to
phase-A
word 12
6
vect; note 2
long addr3 (cw 2)
8
A
message 9
mess1 (cw 1)
7
vect1
addr; note 2
9
A
message 10
mess1 (cw 2)
8
vect2
vect; note 2
10
A
message 11
mess1 (cw 3)
9
mess1 (cw 1)
vect; note 2
11
A
message 12
mess2 (cw 1)
10
mess1 (cw 2)
vect3; note 3
12
A
message 13
mess2 (cw 2)
11
mess1 (cw 3)
mess3 (cw 1);
note 4
13
A
message 14
mess2 (cw 3)
14
A
message 15
mess2 (cw 4)
15
C
vector
pointer to
phase-A
word 14
16
C
message 11
mess3 (cw 1)
17
C
message 14
mess3 (cw 2)
18
C
message 15
mess3 (cw 3)
1
12
mess2 (cw 1)
mess; note 2
13
mess2 (cw 2)
mess; note 2
14
mess2 (cw 3)
mess3 (cw 2)
15
mess2 (cw 4)
mess3 (cw 3)
Notes
1. Phases begin with BIW1, which is not sent to the host.
10
2. Codewords not addressed to the pager.
Notes
3. Vector for long address indicates the location of the
second and third message words.
1. Word number in an address is that of the
corresponding vector.
4. For long addresses, the first message word
immediately follows the vector.
2. BIW sent if BIW reception enabled by SBI bit in the
control packet.
1999 Apr 12
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Philips Semiconductors
Product specification
FLEX roaming decoder II
8.8.4
PCD5013
AFM remains active until the host determines that no
further data can be sent to it outside programmed frames,
i.e:
ALL FRAME MODE (ID = 03H)
The FLEX protocol requires pagers to be capable of
receiving data in frames other than pagers’ programmed
frames and frames implied by collapse values. This is
achieved in the PCD5013 by all frame mode (AFM) which
is required to implement the following features:
• The TAE counters are all zero indicating that no further
temporary message data is expected
• Fragmented messages (Section 8.8.6)
• The AFM counter is zero indicating that no further data
is expected for fragmented messages
• Temporary addresses (Section 8.8.5).
• The FAF bit is clear.
The PCD5013 enters AFM automatically and when
in AFM, it decodes every FLEX frame irrespective of
whether it is a programmed frame. In AFM the PCD5013
sends a status packet with the end-of-frame (EOF) bit set
at the end of every frame. In addition the host can force
AFM by sending an AFM packet with the force all frame
mode (FAF) bit set.
Both the AFM counter and the TAE counters can only be
incremented internally by the PCD5013 and can only be
decremented by the host via AFM packet. Neither the
TAE counters nor the AFM counter can be incremented
past the value 127 (it does not roll-over) or decremented
past the value 0. The TAE counters and the AFM counter
are cleared on a reset and when the decoder is turned off.
The PCD5013 contains a number of counters which are
used to track the number of active calls requiring AFM.
These consist of an AFM counter for tracking the number
of active fragmented messages and 16 temporary address
enable (TAE) counters which count the number of times
each temporary address has been enabled. These
counters are automatically incremented when a
corresponding vector is received, i.e.:
DAF: decrement all frame mode counter, see Table 63.
Setting this bit decrements the AFM counter by one. If a
packet is sent with this bit clear, the AFM counter is not
affected. Value after reset = 0.
FAF: force all frame mode, see Table 63. Setting this bit
forces the PCD5013 to enter AFM. If this bit is clear, the
PCD5013 may or may not be in AFM depending on the
status of the AFM counter and the TAE counters. This
functionality may be useful in acquiring transmitted time
information. Value after reset = 0.
• A short instruction vector indicating a temporary address
has been assigned to this pager
• A vector indicating a message for this pager with a
format which allows fragmentation.
DTA: decrement temporary address enable counter, see
Table 63. When a bit in this word is set, the corresponding
TAE counter is decremented by one. When a bit is clear,
the corresponding TAE counter is not affected. When a
TAE counter reaches zero, the temporary address is
disabled. Value after reset = 0.
The host must determine when no further data can be
received for a message associated with a temporary
address, or a fragmented message, and send an
AFM packet, see Table 63, to decrement the appropriate
counter.
Table 63 All frame mode packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
0
0
0
0
0
0
1
1
2
DAF
FAF
0
0
0
0
0
0
1
DTA15
DTA14
DTA13
DTA12
DTA11
DTA10
DTA9
DTA8
0
DTA7
DTA6
DTA5
DTA4
DTA3
DTA2
DTA1
DTA0
1999 Apr 12
57
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.8.5
PCD5013
3. The host examines the vector packet to identify
which TA is assigned and the frame in which the TA is
expected.
TEMPORARY ADDRESSES
FLEX allows dynamic group calls in which a common
message is sent to a group of paging devices. This is
achieved by assigning the same temporary address (TA)
to each pager in the group using the pagers’ personal
addresses and the short instruction vector. The short
instruction vector causes the TA to be active in the next
occurrence of a specific frame (if the designated frame is
equal to the present frame the host is to interpret this as
the next occurrence of this frame in the following cycle).
4. The PCD5013 continues to decode all of the frames
and passes any address information, vector
information and message information to the host
followed by a status packet indicating the end of each
frame and the current frame number.
5. The host processes data packets received while the
PCD5013 is in AFM. It uses the AFM packet to
decrement the appropriate TA counter when no further
data can be expected for the corresponding TA. This
occurs when:
FLEX specifies sixteen TAs which remain valid for one
message starting in the specified frame and remaining
valid throughout the following frames to the completion of
the message. The FLEX protocol restricts the placement
of TAs such that once assigned to a specific frame they
cannot occur in the FLEX transmission before that
frame.
a) The TA is not found in the assigned frame.
b) The TA is found in the frame it was assigned and
was not a fragmented message.
c) The TA is found in the assigned frame was a
fragmented message and the rules for message
fragmentation (Section 8.8.6) indicate that no
further data can be expected. In this case the host
must send an AFM packet with both the DAF and
the appropriate DTA bits set in order to terminate
both the fragmented message and the TA.
The PCD5013 uses AFM (Section 8.8.4) to allow the
reception of TAs outside programmed frames.
The sequence for the host and the PCD5013 to operate
a TA is:
1. The PCD5013 receives an address codeword followed
by a vector codeword with
V2V1V0 = 001 and I2I1I0 = 000 indicating a short
instruction vector which assigns a TA to this pager.
6. The above operation is repeated for every enabled TA.
2. The PCD5013 passes the address and vector
codeword to the host as packets and increments the
corresponding TA counter and enters AFM.
1999 Apr 12
58
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.8.6
PCD5013
If the fragmented message was received on a
temporary address, then the appropriate DTA bit
should also be set in the AFM packet.
MESSAGE FRAGMENTATION
The FLEX frame length limits the maximum number of
message codewords that can be associated with an
address codeword. Messages longer than 84 codewords
must be sent as several fragments. The PCD5013
uses AFM (Section 8.8.4) to allow the reception of
fragmented messages.
b) If this is the first fragment of a fragmented message
(C is set and no fragmented messages are in
progress for this address and message number),
then the host does not decrement the AFM counter
and expects further fragments to be received for
this address in subsequent frames.
The fragments of a message are sent in sequence. Each
fragment contains a checksum character to detect errors
in the fragment, a message number to identify which
message the fragment is a part, and the continue bit which
either indicates that more fragments are in queue or that
the last fragment has been received. Each fragment also
contains a fragment number starting with 3 for the first
fragment and then incremented through the
sequence 0, 1 or 2 in subsequent fragments. This allows
the detection of missing fragments.
c) If this is the second or subsequent fragment of a
fragmented message and further fragments will
follow, (C is set and a fragmented message is in
progress for this address and message number),
then the host decrements the AFM counter by
sending an AFM packet to the PCD5013 with the
DAF bit set.
d) If this is the last fragment of a fragmented
message, (C is clear and a fragmented message is
in progress for this address and message number),
then the host decrements the AFM counter by 2,
sending 2 AFM packets to the PCD5013 with the
DAF bit set. If the fragmented message was
received on a TA, then one of these AFM packets
should also have the appropriate DTA bit set.
Message fragments may not be separated by more than
32 frames (1 minute) or 128 frames (4 minutes), as
indicated by the service provider. During the reception of a
fragmented message, the PCD5013 examines every
frame for additional fragments until the last fragment is
encountered or the host determines that more than
32 or 128 frames have elapsed since the reception of the
previous message fragment.
4. If, on receiving a status packet, the host determines
that more than 32 or 128 frames have elapsed since
the reception of a fragment for a fragmented message
then the host decrements the AFM counter by sending
an AFM packet to the PCD5013 with the DAF bit set.
If the fragmented message was received on a TA, then
the appropriate DTA bit should also be set in the
AFM packet.
The sequence for the host and the PCD5013 to receive a
fragmented message is as follows:
1. The PCD5013 receives an address codeword followed
by a vector indicating one of:
a) Secure (vector type = 000)
b) Alphanumeric (vector type = 101)
5. When no fragmented messages are in progress
(the AFM counter = 0) and no TAs are pending
(all TA counters = 0) and the FAF bit is clear in the
AFM packet, the PCD5013 leaves AFM.
c) Hexadecimal/binary (vector type = 110).
The PCD5013 passes the address, vector and
message codewords to the host as packets and
increments its internal AFM counter and enters AFM.
As an alternative to the above scheme, the host may
choose to decrement the AFM counter at the end of the
entire message by decrementing it once for each fragment
received. This method is limited to a maximum of
127 fragments.
2. While in AFM, the PCD5013 decodes all of the frames
passing any address, vector and message information
to the host followed by a status packet indicating the
end of each frame and the current frame number.
3. Every time the host receives a secure, alphanumeric
or hexadecimal/binary vector packet, it inspects the
message continued flag (C) in the first message
packet:
Tables 64 and 65 show examples of message reception
with and without message fragmentation.
a) If this is not a fragmented message (C is clear and
no fragmented messages are in progress for this
address and message number), then the host
decrements the AFM counter by sending an
AFM packet to the PCD5013 with the DAF bit set.
1999 Apr 12
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Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
Table 64 Alphanumeric message without fragmentation
PACKET
PHASE
AFM
COUNTER
COMMENT
NUMBER
TYPE
1st
address 1
A
0
address 1 is received
2nd
vector 1
A
1
vector = alphanumeric type
3rd
message
A
1
message word received; C bit = 0; no more fragments are expected
4th
AFM
0
host writes AFM packet to the PCD5013 with the DAF bit = 1
Table 65 Alphanumeric message with fragmentation
PACKET
NUMBER
PHASE
AFM
COUNTER
TYPE
COMMENT
1st
address 1
A
0
address 1 is received
2nd
vector 1
A
1
vector = alphanumeric type
3rd
message
A
1
message word received; C bit = 1;
message is fragmented, more expected
4th
status
1
end of frame indication (EOF = 1)
5th
address 1
B
1
address 1 is received
6th
vector 1
B
2
vector = alphanumeric type
7th
message
B
2
message word received; C bit = 1;
message is fragmented, more expected
8th
AFM
1
host writes AFM packet to the PCD5013 with the DAF bit = 1
9th
status
1
end of frame indication (EOF = 1)
10th
address 1
A
1
address 1 is received
11th
vector 1
A
2
vector = alphanumeric type
12th
message
A
2
message word received; C bit = 0; no more fragments are expected
13th
AFM
1
host writes AFM packet to the PCD5013 with the DAF bit = 1
14th
AFM
0
host writes AFM packet to the PCD5013 with the DAF bit = 1
1999 Apr 12
60
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.8.6.1
PCD5013
codeword are added to form a binary sum. The message
checksum is the 1’s complement of the LSBs of the
binary sum, where the number of bits taken is determined
by the message type (Section 8.7.8).
Fragmentation of non-7-bit character sets
FLEX alphanumeric messages can be used to send
symbolic characters like Chinese, Kanji, etc. In this case
several ASCII characters are used to represent each
symbolic character. Enhanced fragmentation (EF) rules
are provided by FLEX to allow character positions within
a fragment to be determined in the event of missing
fragments under poor signal conditions.
In the case of the 6-bit message checksum used in
numeric messages, a binary sum is first calculated as
described above. The binary sum is then truncated to its
8 LSBs, then the 2 MSBs are shifted right by 6 bits and
added to the least significant 6 bits to form a new
binary sum. The 6 LSBs of this new sum are taken and
1’s complemented to form the 6-bit message checksum.
1. The pager must remove <NUL> characters from the
end of fragments (where they are used as fill
characters) so that the displayed message is not
affected. To determine character boundaries,
<NUL> (00H) characters in all other positions must be
considered a result of channel errors. This allows each
fragment to end with a complete character and does
not disrupt pagers which do not follow all the EF rules.
8.8.8
FLEX messages may be numbered (Section 8.7.8), in
this case the system controller assigns message numbers
(for each paging address separately) starting at 0 and
progressing up to a maximum of 63 in numerical order.
The maximum roll-over number is defined in the pager
code plug to accommodate values set in the system
infrastructure. When message numbers are not received
in order, the subscriber should assume a message has
been missed. When a message number is missed, the
subscriber or the pager may determine the missing
message number(s) allowing a request to be made for
retrieval.
2. The last fragment of a message containing symbolic
characters is completed by filling unused character
positions with <ETX> (03H) characters or
<NUL> characters. When a message ends at exactly
the last character position of the last BCH codeword,
no additional <ETX> is required.
3. The U and V bits (Table 54) which aid decoding, are
available in all fragments following the initial fragment.
In the first fragment the message starts in the default
character mode (U and V = 10). For subsequent
fragments the definition of the U and V field is as
shown in Table 66. When the U and V field is 00,
characters may be split between fragments. When the
U and V field is not 00, each fragment starts on a
character boundary with the character mode defined
as in Table 66.
8.8.7
MESSAGE NUMBERING
Messages which can be received out of sequence are
indicated by clearing the message retrieval flag R.
Messages with R cleared number should not be included
in the missed message calculation.
In case of fragmented messages, this number is also used
to identify fragments of the same message. Multiple
messages to the same address must have separate
message numbers.
MESSAGE CHECKSUMS
FLEX provides a message checksum facility for
alphanumeric, numeric, hex/binary, and secure
messages. The checksum is calculated by summing the
information bits of each codeword in the message or
message fragment (including control information and
termination characters and bits in the last message
codeword). Information bits of each codeword are broken
into three groups as indicated in Table 67. Bits i0, i8 and i16
are the LSBs of each group and bit i0 is the first bit of the
codeword to be transmitted. The 3 groups are for each
Table 66 Fragmentation control bit definitions
U0
V0
0
0
EF not supported in controller
0
1
reserved (for a second alternate character
mode)
1
0
default character mode start position 1
1
1
alternate character mode start position 1
i11
i12
DEFINITION
Table 67 Bit groups for message checksums
i0
i1
i2
i3
i4
i5
i6
i7
i8
i9
i10
group 1
1999 Apr 12
group 2
61
i13
i14
i15
i16
i17
i18
group 3
i19
i20
Philips Semiconductors
Product specification
FLEX roaming decoder II
8.8.9
8.8.9.1
PCD5013
This can occur either because the pager has entered a
new area or because the Roaming IDs or Traffic
Management Flags change.
USING THE RECEIVER SHUTDOWN PACKET
Operation of Roaming features
A roaming pager scans channels in a frequency list to
determine the channel or channels to monitor. The pager
matches the Roaming IDs (SSIDs, NIDs or any IDs)
transmitted on monitored channels against those
contained in the pager’s Roaming ID list. Each item in the
Roaming ID list is assigned a priority to ensure
determinative behaviour for roaming pagers.
A pager can stop monitoring a channel either because
the channel’s Roaming ID changes or because no signal
has been encountered on the channel for a given period.
When all the monitored channels have been lost, the
pager must start a global scan.
The PCD5013 sends information to the host in the
Receiver Shutdown Packet (see Section 8.4.12) every
time it shuts the receiver down. This allows the host to
calculate whether it will have enough time to switch
frequencies before the receiver next switches on
(see Section 8.8.9.2).
Implementation of a Roaming Pager using the PCD5013 is
greatly simplified using the FLEX software.
Items in the Roaming ID list are assigned priorities to
arbitrate in the case where a pager is in a coverage in
which there is more than one RF channel. In the case that
a pager receives data from two channels both of Roaming
Identifiers of the highest priority, it can enter one of two
modes of operation (as determined by the pager
programming).
The PCD5013 allows the identification of Roaming IDs
by the support for the reception of SSID Block
Information words and Short Messaging Vectors
(see Sections 8.7.5 and 8.7.9)
8.8.9.2
Channel scanning is done to determine whether to switch
channel because there is a channel of higher priority than
the currently monitored channel.
Calculating time left
The receiver shutdown packet gives timing information to
the host. Two times are of particular interest when
implementing a roaming algorithm.
• Global scanning: the scan of all RF channels after switch
on. Once the global scan is completed, the pager starts
to monitor all channels with a programmed priority which
is equal to or higher than the highest priority channel on
which a FLEX transmission was encountered. If no
FLEX transmission is encountered the pager must
restart the global scan after some battery saving period.
TimeToWarmUpStart: Defined as the amount of time
there is before the receiver starts to warm-up (i.e.
transition from the off state to the first warm-up state).
TimeToTasksDisabled: Defined as the amount of time
the host has to complete any host initiated tasks (e.g. by
setting SND or SAS in the roaming control packet).
• Background scanning: scanning done to determine
whether the pager one of the monitored RF channels
carries a FLEX signal with higher priority than the
currently monitored channel.
The formulae for calculating these times are shown below
and depend on whether the PCD5013 is in Synchronous
mode or Asynchronous mode.
Synchronous mode:
TimeToWarmupStart ≥ ( TNF × 80 ms ) + ( SkippedFrames × 1874.375 ms ) + ( ReceiverOffTime – 167.5 ms )
TimeToTasksDisabled ≥ ( TNF × 80 ms ) + ( SkippedFrames × 1874.375 ms ) + ( ReceiverOffTime – 247.5 ms )
Asynchronous mode:
TimeToWarmupStart ≥ [ ( TNF – 2 ) × 80 ms ] + ReceiverOffTime
TimeToTasksDisabled ≥ [ ( TNF – 3 ) × 80 ms ]
Where:
TNF (Time to Next Frame): value from the receiver shutdown packet. SkippedFrames: the number of frames that will not
be decoded. Calculated from the Current Frame (CF) and Next Needed Frame (NAF) fields in the receiver shutdown
packet (e.g. if CF is 10 and NAF is 12, then SkippedFrames is 1). ReceiverOffTime: the time programmed in the receiver
off setting packet.
1999 Apr 12
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Philips Semiconductors
Product specification
FLEX roaming decoder II
8.8.9.3
PCD5013
Equation (1) calculates how long it takes to complete a
Noise Detect started by setting the SND bit in the roaming
control packet. This formula assumes that:
Calculating how long tasks take
Since the TimeToTaskDisabled discussed in the previous
section limits how much the host can do while the
PCD5013 is battery saving, it is necessary for the host to
know how long it can take the PCD5013 to perform a task.
• the noise detect was performed while in synchronous
mode OR
• the noise detect was performed in asynchronous mode
and did not find FLEX signal OR
The formulae below calculate how long the two types of
host initiated tasks take to complete as measured from the
last SPI clock of the packet that initiates the task to the
time the receiver shutdown sequence starts. Note that the
receiver shutdown sequence must start before tasks are
disabled.The following definitions are used:
• the noise detect found FLEX signal but the DAS bit of
the roaming control packet was set.
Equation (2) calculates how long it will take to complete an
A-word search initiated by setting the SAS bit in the
roaming control packet. This formula assumes that the
A-word search failed to find roaming FLEX channel.
TotalWarmUpTime: The sum of the times programmed
for the used warm-up steps plus the time programmed for
the 3200 sps Sync Setting in the receiver control
configuration packets
AST: The value configured using the timing control packet.
Equation (3) calculates how long it will take to complete a
Noise Detect/A-word search combination. This can occur
when the noise detect is performed while in asynchronous
mode, the noise detect finds FLEX signal, and the DAS
bit of the roaming control packet is not set.
TimeToPerformNoiseDetect ≤ TotalWarmUpTime + 82 ms
(1)
TimeToPerformAwordSearch ≤ TotalWarmupTime + AST + 47 ms
(2)
TimeToPerformBoth ≤ TotalWarmUpTime + AST + 127 ms
(3)
1999 Apr 12
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Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
9 LIMITING VALUES
In accordance with the absolute maximum rating system (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDD
supply voltage
−0.5
4.0
V
IDD
supply current
−
50
mA
II
DC input current (any input)
−10
+10
mA
IO
DC output current (any output)
−10
+10
mA
VI
input voltages (all inputs)
−0.5
VDD + 0.5
V
Ptot
total power dissipation
−
300
mW
PO
power dissipation per output
−
10
mW
Tamb
operating ambient temperature
−25
+70
°C
Tstg
storage temperature
−65
+150
°C
note 1
note 2
Notes
1. VDD1 and VDD2 respectively and VSS1 and VSS2 must be connected at the same potential.
2. VI(max) = 4.0 V.
10 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.
11 THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
1999 Apr 12
PARAMETER
CONDITIONS
thermal resistance from junction to ambient in free air
64
VALUE
UNIT
90
K/W
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
12 DC CHARACTERISTICS
Tamb = −25 to +70 °C; VDD = 2.2 V; f = 76.8 kHz; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDD
supply voltage
1.8
2.2
3.6
V
IDD(stby)
standby supply current
on = 0; note 1
−
4.9
24
µA
IDD
operating supply current
on = 1; note 2
−
6.0
−
µA
Digital inputs: OSCPD, TEST2, TEST3, RESET, LOBAT, EXTS0, EXTS1, SS and MOSI
VIL
LOW-level input voltage
−
−
0.2VDD
V
VIH
HIGH-level input voltage
0.8VDD
−
−
V
ILI
LOW/HIGH-level input leakage current
−
−
1
µA
−
0.1
0.4
V
Digital outputs: MISO, READY, CLKOUT, SYMCLK and S0 to S7
VOL
LOW-level output voltage
Isink = 0.8 mA
VOH
HIGH-level output voltage
Isource = −0.8 mA
ILO
LOW/HIGH-level output leakage current 3-state outputs
VDD − 0.4 VDD − 0.1 −
V
−
µA
−
1
Notes
1. External clock signal (frequency = 76.8 kHz, amplitude = VSS to VDD) at pin EXTAL; OSCPD = HIGH;
test inputs = LOW; other inputs = HIGH; outputs unconnected; SPI transmit enabled; COD bit set to logic 1 (see
Section 8.4.4); to obtain the supply current of an application with a crystal connected as in Fig.19, a typical oscillator
current of 2 µA needs to be added to this value (see Chapter 14); Tamb = 25 °C.
2. As note 1, but PCD5013 and synchronous to a typical FLEX data stream (collapse value = 4), Tamb = 25 °C.
13 AC CHARACTERISTICS
Tamb = −25 to +70 °C, VDD = 1.8 to 3.6 V, fEXTAL = 76.8 kHz, maximum load capacitance = 50 pF connected to any
digital output; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Reset timing
tW(rst)
RESET pulse width
200
−
−
ns
tLH(RESET-READY)
RESET LOW to READY HIGH
−
−
200
ns
tHL(RESET-READY)
RESET HIGH to READY LOW stable 76.8 kHz clock
−
1
−
s
tstrt(osc)
oscillator start-up time
−
0.5
−
s
th(rst)
RESET hold time
200
−
−
ns
tHL(RESET-READY)
RESET HIGH to READY LOW note 1
−
76800 −
T
tWUL(osc-READY)
oscillator warmed up to
READY LOW
−
76800 −
T
Start-up timing
see Fig.19
note 1
SPI timing
fSCK
operating frequency
0
−
1
MHz
Tcy(SCK)
cycle time
1000
−
−
ns
tLEAD1
select lead time
200
−
−
ns
tLAG1
de-select lag time
200
−
−
ns
1999 Apr 12
65
Philips Semiconductors
Product specification
FLEX roaming decoder II
SYMBOL
td(SS-READY)
PCD5013
PARAMETER
SS-to-READY delay time
CONDITIONS
MIN.
TYP.
MAX.
UNIT
previous packet did not program −
an address word; note 2
−
80
µs
−
−
420
µs
previous packet programmed
an address word; note 2
tREADYH
READY HIGH time
50
−
−
µs
tLEAD2
READY lead time
200
−
−
ns
tLAG2
READY lag time
−
−
200
ns
tsu(i)(D)
MOSI data setup time
200
−
−
ns
th(i)(D)
MOSI data hold time
200
−
−
ns
tACC(o)
MISO access time
0
−
200
ns
to(dis)
MISO disable time
−
−
300
ns
tDOV
MISO data valid time
−
−
200
ns
th(o)(D)
MISO data hold time
0
−
−
ns
tSSH
SS HIGH time
200
−
−
ns
tSCKH
SCK HIGH time
300
−
−
ns
tSCKL
SCK LOW time
200
−
−
ns
tr
SCK rise time
10% to 90% VDD
−
−
1
µs
tf
SCK fall time
10% to 90% VDD
−
−
1
µs
Notes
1. T is one period of the clock source either generated by the internal oscillator, or applied at the input EXTAL. Note
that from power-up, the oscillator start-up time can influence the availability and period of clock strobes. This can
affect the RESET HIGH to READY LOW timing.
2. When the host re-programs an address word with a host-to-decoder packet ID > 7FH, there is an added delay before
the PCD5013 is ready for another packet.
14 OSCILLATOR CHARACTERISTICS
Tamb = −25 to +70 °C; note 1.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
note 1
−
15
−
pF
external capacitor at pin XTAL
note 1
−
15
−
pF
external feedback resistor
note 1
−
10
−
MΩ
9.4
27
70
µS
−
2
−
µA
C1
external capacitor at pin EXTAL
C2
Rf
gm(osc)
oscillator transconductance
Iosc
oscillator operating supply current
VDD = 2.2 V; note 2
Notes
1. Designed for quartz crystal type: SEIKO VTC200 or equivalent; parameters: f = 76800Hz, RS = 35 kΩ (max.),
CL = C1.C2/(C1 + C2) + Cstray = 8 to 12 pF, C0 = crystal shunt capacitance = 0.8 pF (typ.),
Cf = typical parasitic pin capacitance = 2 pF; maximum overall frequency tolerance (including transmitter)
is 300 ppm (Section 8.4.4).
2. Extracted from evaluations under conditions as in Fig.19; this value is strongly dependent on external conditions
(load and parasitic capacitances).
1999 Apr 12
66
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
Please note that the issuing of this document is not part of
the “FLEX Total Messaging Solution” agreement.
Enquiries about the FLEX protocol not covered by the
“FLEX Total Messaging Solution” should be directed to:
15 TEST AND APPLICATION INFORMATION
15.1
FLEX protocol
The PCD5013 conveys a licence to manufacture Pagers
using the “FLEX Total Messaging Solution” agreement.
For the terms and conditions of this agreement please
contact Philips Semiconductors.
Motorola Inc.
FLEX Licensing Manager,
Mail Stop 99,
1500 Gateway Boulevard,
Boynton Beach,
Florida 33426.
FAX: (561) 739-2519
Telephone: (561) 739-8281.
Further details of the FLEX protocol are contained in the
document “FLEX Protocol and FLEX Encoding and
Decoding Requirements”.
15.2
Example applications
handbook, full pagewidth
Vsup
DC/DC
CONVERTER
10 µF
VDD
100 nF
3
OSCPD,
TEST2, TEST3
KEYPAD
VDD1, VDD2
SYMCLK
READY, SS, SCK,
MOSI, MISO
CLKOUT
RECEIVER
FRONT-END
5
MICROCONTROLLER
P87CL881
PCD5013
RESET
S0 to S7
IF AND
4-LEVEL
DEMODULATOR
8
EXTS0, EXTS1
I2C-bus
TOUT0 to
TOUT3
2
LOBAT
EEPROM
4
EXTAL
76.8 kHz
XTAL 2 VSS1, VSS2
LCD
DRIVER
MGR621
10 MΩ
15 pF
15 pF
Fig.19 Example application using external demodulation.
1999 Apr 12
LCD
67
Philips Semiconductors
Product specification
FLEX roaming decoder II
handbook, full pagewidth
Vsup
PCD5013
DC/DC
CONVERTER
10 µF
VDD
100 nF
3
OSCPD,
TEST2, TEST3
KEYPAD
VDD1, VDD2
SYMCLK
READY, SS, SCK,
MOSI, MISO
CLKOUT
RECEIVER
FRONT-END
5
MICROCONTROLLER
P87CL881
PCD5013
RESET
S1 to S7
IF
8
S0/IFIN
I2C-bus
TOUT0 to
TOUT3
LOBAT
EEPROM
4
EXTAL
160 kHz
XTAL 2 VSS1, VSS2
LCD
DRIVER
MGR622
10 MΩ
15 pF
15 pF
Fig.20 Example application using internal demodulator.
1999 Apr 12
LCD
68
Philips Semiconductors
Product specification
FLEX roaming decoder II
15.3
PCD5013
System block diagram
handbook, full pagewidth
BATTERY
LOW DETECTOR
HOST
MICROPROCESSOR
battery low
indication
PAGING RECEIVER
receiver
control
lines
reset
RF RECEIVER
USER INTERFACE
7
PCD5013
API
455 kHz IF
data
IF BACKEND
serial
peripheral
interface
1
5
FLEXstackTM SOFTWARE
SPI INTERFACE
MGR620
160 kHz crystal
Fig.21 System block diagram.
1999 Apr 12
69
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
16 PACKAGE OUTLINE
LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm
SOT358-1
c
y
X
24
A
17
25
16
ZE
e
E HE
A A2 A
1
(A 3)
wM
θ
bp
Lp
L
pin 1 index
32
9
detail X
8
1
e
ZD
v M A
wM
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.60
0.20
0.05
1.45
1.35
0.25
0.4
0.3
0.18
0.12
7.1
6.9
7.1
6.9
0.8
9.15
8.85
9.15
8.85
1.0
0.75
0.45
0.2
0.25
0.1
Z D (1) Z E (1)
0.9
0.5
0.9
0.5
θ
o
7
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
95-12-19
97-08-04
SOT358 -1
1999 Apr 12
EUROPEAN
PROJECTION
70
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
17 SOLDERING
17.1
Introduction to soldering surface mount
packages
• For packages with leads on two sides and a pitch (e):
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
17.2
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
17.3
17.4
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
1999 Apr 12
Manual soldering
71
Philips Semiconductors
Product specification
FLEX roaming decoder II
17.5
PCD5013
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, SQFP
not suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not
PLCC(3),
SO, SOJ
suitable
suitable(2)
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended(3)(4)
suitable
SSOP, TSSOP, VSO
not recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 Apr 12
72
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
18 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
19 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Apr 12
73
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
NOTES
1999 Apr 12
74
Philips Semiconductors
Product specification
FLEX roaming decoder II
PCD5013
NOTES
1999 Apr 12
75
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1999
SCA63
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
465008/00/02/pp76
Date of release: 1999 Apr 12
Document order number:
9397 750 05593