INTEGRATED CIRCUITS 74LV373 Octal D-type transparent latch (3-State) Product specification Supersedes data of 1997 March 04 IC24 Data Handbook 1998 Jun 10 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) FEATURES 74LV373 DESCRIPTION • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0V to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, The 74LV373 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT373. The 74LV373 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches. Tamb = 25°C The ‘373’ consists of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes. • Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V, Tamb = 25°C • Common 3-State output enable input • Output capability: bus driver • ICC category: MSI When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. The ‘373’ is functionally identical to the ‘573’, but the ‘573’ has a different pin arrangement. QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf 2.5 ns PARAMETER SYMBOL CONDITIONS tPHL/tPLH Propagation delay Dn to Qn LE to Qn CL = 15pF VCC = 3.3V CI Input capacitance CPD Power dissipation capacitance per latch Notes 1, 2 TYPICAL UNIT 10 12 ns 3.5 pF 22 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD VCC2 x fi (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL VCC2 fo) = sum of the outputs. 2. The condition is VI = GND to VCC. ORDERING AND PACKAGE INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 20-Pin Plastic DIL PACKAGES –40°C to +125°C 74LV373 N 74LV373 N SOT146-1 20-Pin Plastic SO –40°C to +125°C 74LV373 D 74LV373 D SOT163-1 20-Pin Plastic SSOP Type II –40°C to +125°C 74LV373 DB 74LV373 DB SOT339-1 20-Pin Plastic TSSOP Type I –40°C to +125°C 74LV373 PW 74LV373PW DH SOT360-1 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 1 OE Output enabled input (active LOW) 2, 5, 6, 9, 12, 15, 16, 19 Q0–Q7 3-State latch outputs 3, 4, 7, 8, 13, 14, 17, 18 D0–D7 Data inputs 10 GND Ground (0V) 11 LE 20 VCC 1998 Jun 10 Latch enable input (active HIGH) Positive supply voltage 2 853–1934 19545 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) PIN CONFIGURATION LOGIC SYMBOL OE 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 74LV373 4 17 11 LE D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D3 8 Q3 GND 3 D0 Q0 2 4 D1 Q1 5 7 D2 Q2 6 8 D3 Q3 9 13 D4 Q4 12 D5 14 D5 Q5 15 13 D4 17 D6 Q6 16 9 12 Q4 18 D7 Q7 19 10 11 LE OE 1 SV00657 LOGIC SYMBOL (IEEE/IEC) 11 1 3 SV00658 FUNCTIONAL DIAGRAM C1 3 D0 Q0 2 4 D1 Q1 5 7 D2 Q2 6 8 D3 Q3 9 Q4 12 EN1 2 1D 4 5 7 6 8 9 13 12 14 15 17 16 18 19 LATCH 1 to 8 3–STATE OUTPUTS 13 D4 14 D5 Q5 15 17 D6 Q6 16 18 D7 Q7 19 11 LE 1 OE SV00659 SV00660 LOGIC DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 Q D LATCH 1 Q D LATCH 2 Q D LATCH 3 Q D LATCH 4 Q D LATCH 5 Q D LATCH 6 Q D LATCH 7 Q D LATCH 8 LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 SV00661 1998 Jun 10 3 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) 74LV373 FUNCTION TABLE LE Dn INTERNAL LATCHES OUTPUTS OE INPUTS Enable and read register (transparent mode) L L H H L H L H L H Latch and read register L L L L I h L H L H Latch register and disable outputs H H L L I h L H Z Z OPERATING MODES H h L I X Z Q0 to Q7 = HIGH voltage level = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition = LOW voltage level = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition = Don’t care = High impedance OFF-state RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER CONDITIONS MIN TYP. See Note1 1.0 0 0 DC supply voltage VI Input voltage VO Output voltage Tamb Operating ambient temperature range in free air tr, tf Input rise and fall times See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V MAX UNIT 3.3 5.5 V – VCC V – VCC V +85 +125 °C 500 200 100 50 ns/V –40 –40 – – – – – – – – NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V. ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). SYMBOL PARAMETER CONDITIONS RATING UNIT VCC DC supply voltage –0.5 to +7.0 V ±IIK DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA ±IOK DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA ±IO DC output source or sink current – bus driver outputs –0.5V < VO < VCC + 0.5V 35 mA 70 mA –65 to +150 °C ±IGND, ±ICC DC VCC or GND current for types with –bus driver outputs Tstg Storage temperature range Ptot t t Power dissipation per package –plastic DIL –plastic mini-pack (SO) –plastic shrink mini-pack (SSOP and TSSOP) for temperature range: –40 to +125°C above +70°C derate linearly with 12mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K 750 500 400 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Jun 10 4 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) 74LV373 DC CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0V). LIMITS SYMBOL PARAMETER -40°C to +85°C TEST CONDITIONS MIN VIH VIL HIGH level Input voltage LOW level Input voltage TYP1 HIGH level output voltage; BUS driver outputs LOW level l l output t t voltage out uts voltage; all outputs VOL LOW level output voltage; BUS driver outputs MIN 0.9 0.9 VCC = 2.0V 1.4 1.4 VCC = 2.7 to 3.6V 2.0 2.0 VCC = 4.5 to 5.5V 0.7*VCC 0.7*VCC UNIT MAX V VCC = 1.2V 0.3 0.3 VCC = 2.0V 0.6 0.6 VCC = 2.7 to 3.6V 0.8 0.8 0.3*VCC 0.3*VCC VCC = 1.2V; VI = VIH or VIL; –IO = 100µA VOH MAX VCC = 1.2V VCC = 4.5 to 5.5 HIGH level l l output t t voltage out uts voltage; all outputs -40°C to +125°C V 1.2 VCC = 2.0V; VI = VIH or VIL; –IO = 100µA 1.8 2.0 1.8 VCC = 2.7V; VI = VIH or VIL; –IO = 100µA 2.5 2.7 2.5 VCC = 3.0V; VI = VIH or VIL; –IO = 100µA 2.8 3.0 2.8 VCC = 4.5V; VI = VIH or VIL; –IO = 100µA 4.3 4.5 4.3 VCC = 3.0V; VI = VIH or VIL; –IO = 8mA 2.40 2.82 2.20 VCC = 4.5V; VI = VIH or VIL; –IO = 16mA 3.60 4.20 3.50 V VCC = 1.2V; VI = VIH or VIL; IO = 100µA 0 VCC = 2.0V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 2.7V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 4.5V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0V; VI = VIH or VIL; IO = 8mA 0.20 0.40 0.50 VCC = 4.5V; VI = VIH or VIL; IO = 16mA 0.35 0.55 0.65 1.0 1.0 µA 5 10 µA V Input leakage current VCC = 5.5V; VI = VCC or GND IOZ 3-State output OFF-state current VCC = 5.5V; VI = VIH or VIL; VO = VCC or GND ICC Quiescent supply current; MSI VCC = 5.5V; VI = VCC or GND; IO = 0 20.0 160 µA ∆ICC Additional quiescent supply current per input VCC = 2.7V to 3.6V; VI = VCC – 0.6V 500 850 µA II NOTE: 1. All typical values are measured at Tamb = 25°C. 1998 Jun 10 5 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) 74LV373 AC CHARACTERISTICS GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = K LIMITS SYMBOL tPHL/tPLH tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tW tsu th PARAMETER Propagation delay Dn to Qn Propagation delay LE to Qn 3-State output out ut enable time OE tto Qn 3-State output out ut disable time OE tto Qn LE pulse width HIGH Setup time Dn to LE Hold time Dn to LE WAVEFORM Figure 1, 5 Figure 2, 5 Figure 3 Figure 3 Figure 2 Figure 4 Figure 4 CONDITION VCC(V) MIN TYP1 1.2 – 2.0 – –40 to +125 °C MAX MIN 65 – – – 22 37 – 48 2.7 – 16 28 – 35 – 132 22 – 28 4.5 to 5.5 – – 16 – 20 1.2 – 80 – – – 2.0 – 27 43 – 54 2.7 – 20 26 – 33 3.0 to 3.6 – 152 25 – 31 4.5 to 5.5 – 9.53 19 – 24 1.2 – 80 – – – 2.0 – 27 46 – 58 2.7 – 20 28 – 35 3.0 to 3.6 – 152 27 – 34 4.5 to 5.5 – – 23 – 29 1.2 – 75 – – – 2.0 – 27 46 – 58 2.7 – 21 28 – 35 3.0 to 3.6 – 162 27 – 34 4.5 to 5.5 – – 23 – 29 2.0 34 10 – 41 – 2.7 25 8 – 30 – 3.0 to 3.6 20 62 – 24 – 1.2 – 25 – – – 2.0 17 9 – 20 – 2.7 13 6 – 15 – 3.0 to 3.6 10 52 – 12 – 1.2 – –15 – – – 2.0 5 –5 – 5 – 2.7 5 –3 – 5 – 3.0 to 3.6 5 –32 – 5 – 6 UNIT MAX 3.0 to 3.6 NOTES: 1. All typical values are measured at Tamb = 25°C 2. Typical values are measured at VCC = 3.3V 3. Typical values are measured at VCC = 5.0V 1998 Jun 10 –40 to +85 °C ns ns ns ns ns ns ns Philips Semiconductors Product specification Octal D-type transparent latch (3-State) 74LV373 ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ AC WAVEFORMS VM = 1.5V at VCC 2.7V and 3.6V VM = 0.5V * VCC at VCC 2.7V and 4.5V VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC 2.7V and 3.6V VX = VOL + 0.1VCC at VCC < 2.7V and 4.5V VY = VOH – 0.3V at VCC 2.7V and 3.6V VY = VOH – 0.1VCC at VCC < 2.7V and 4.5V VI Dn INPUT VM GND th tsu LE INPUT Dn INPUT GND VM VM NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. GND tPHL tPLH Qn OUTPUT SV00665 Figure 4. Data set-up and hold times for the Dn input to the LE input. VOH VM VOL TEST CIRCUIT SV00662 Figure 1. Data input (Dn) to output (Qn) propagation delays and the output transition times. VCC VI VI VM 2 * VCC Open GND RL = 1k VO PULSE GENERATOR D.U.T. RT GND tW CL RL = 1k 50 pF tPLH tPHL Test Circuit for Outputs VOH Qn OUTPUT DEFINITIONS VM RL = Load resistor CL = Load capacitance includes jig and probe capacitiance. RT = Termination resistance should be equal to ZOUT of pulse generators. VOL SV00663 SWITCH POSITION Figure 2. Latch enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays and the output transition times. S1 VCC tPLH/tPHL Open < 2.7V VCC tPLZ/tPZL 2 * VCC 2.7–3.6V 2.7V tPHZ/tPZH GND TEST VI OE INPUT tsu VI VI LE INPUT th 4.5V VI VCC VM SV00896 GND tPLZ VCC Qn OUTPUT LOW-to-OFF OFF-to-LOW VOL Figure 5. Load circuitry for switching times tPZL VM VX tPZH tPHZ VOH Qn OUTPUT HIGH-to-OFF OFF-to-HIGH GND VY VM outputs enabled outputs disabled outputs enabled SV00664 Figure 3. 3-State enable and disable times. 1998 Jun 10 7 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) DIP20: plastic dual in-line package; 20 leads (300 mil) 1998 Jun 10 8 74LV373 SOT146-1 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) SO20: plastic small outline package; 20 leads; body width 7.5 mm 1998 Jun 10 9 74LV373 SOT163-1 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm 1998 Jun 10 10 74LV373 SOT339-1 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm 1998 Jun 10 11 74LV373 SOT360-1 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) 74LV373 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: 1998 Jun 10 12 Date of release: 05-96 9397-750-04447