INTEGRATED CIRCUITS 74LVC841A 10-bit transparent latch with 5-volt tolerant inputs/outputs (3-State) Product specification IC24 Data Handbook 1998 Jun 17 Philips Semiconductors Product specification 10-bit transparent latch with 5-volt tolerant inputs/outputs (3-State) FEATURES 74LVC841A DESCRIPTION • 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with the JEDEC standard no. 8-1 A • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct interface with TTL levels • Flow-through pin-out architecture The 74LVC841A is a low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. In 3-State operation, outputs can handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 V/5 V environment. The 74LVC841A is a 10-bit transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches. The 74LVC841A consists of ten transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the ten latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr =tf ≤ 2.5 ns PARAMETER SYMBOL CONDITIONS tPHL/tPLH Propagation delay Dn to Qn; LE to Qn CL = 50 pF; VCC = 3.3 V CI Input capacitance CPD Power dissipation capacitance per latch VI = GND to VCC1 TYPICAL UNIT 4.5 5.0 ns 5.0 pF 22 pF NOTE: 1 CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of the outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 24-Pin Plastic SO –40°C to +125°C 74LVC841A D 74LVC841A D SOT137-1 24-Pin Plastic SSOP Type II –40°C to +125°C 74LVC841A DB 74LVC841A DB SOT340-1 24-Pin Plastic TSSOP Type I –40°C to +125°C 74LVC841A PW 7LVC841APW DH SOT355-1 PIN CONFIGURATION PIN DESCRIPTION OE 1 24 D0 2 23 Q0 D1 3 22 Q1 D2 4 21 Q2 D3 5 20 Q3 D4 6 19 Q4 D5 7 18 Q5 D6 8 17 Q6 D7 9 16 D8 10 15 D9 11 14 Q9 13 LE GND 12 PIN NUMBER VCC SYMBOL NAME AND FUNCTION 1 OE Output enable input (active Low) 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 D0 to D9 Data inputs 23, 22, 21, 20, 19, Q0 to Q9 18, 17, 16, 15, 14 3-state latch outputs 12 GND Ground (0 V) Q7 13 LE Latch enable input (active HIGH) Q8 24 VCC Positive supply voltage SV01723 1998 Jun 17 2 853-2071 19589 Philips Semiconductors Product specification 10-bit transparent latch with 5-volt tolerant inputs/outputs (3-State) LOGIC SYMBOL (IEEE/IEC) 74LVC841A LOGIC SYMBOL 13 13 C1 1 LE 2 D0 Q0 23 3 D1 Q1 22 4 D2 Q2 21 5 D3 Q3 20 D4 Q4 19 D5 Q5 18 D6 Q6 17 9 D7 Q7 16 10 D8 Q8 15 Q9 14 6 7 8 11 D9 OE 1 EN 2 23 1D 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 SV01724 SV01725 LOGIC DIAGRAM D0 D1 D Q D3 D2 D Q D Q D4 D Q D5 D Q D6 D Q D7 D Q D8 D Q D9 D Q D Q LATCH 1 LATCH 2 LATCH 3 LATCH 4 LATCH 5 LATCH 6 LATCH 7 LATCH 8 LATCH 9 LATCH 10 LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 SV01726 FUNCTION TABLE for register An or Bn INPUTS OPERATING MODES INTERNAL LATCHES OUTPUTS L H L H L H ↓ ↓ l h L H L H H H X X l h L H Z Z L L X NC NC OE LE Dn Enable and read register (transparent mode) L L H H Latch and read register L L latch register and disable outputs Hold NOTES: H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition X = don’t care Z = high impedance OFF-state NC = no change 1998 Jun 17 3 Q0 TO Q9 Philips Semiconductors Product specification 10-bit transparent latch with 5-volt tolerant inputs/outputs (3-State) 74LVC841A RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER CONDITIONS LIMITS MIN MAX DC supply voltage (for max. speed performance) 2.7 3.6 DC supply voltage (for low-voltage applications) 1.2 3.6 UNIT V VI DC input voltage range 0 5.5 VO DC output voltage range 0 VCC V –40 +85 °C 0 0 20 10 ns/V Tamb Operating free-air temperature range tr, tf Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V V ABSOLUTE MAXIMUM RATINGS1 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). SYMBOL VCC PARAMETER CONDITIONS DC supply voltage RATING UNIT –0.5 to +6.5 V IIK DC input diode current VI t 0 –50 mA VI DC input voltage Note 2 –0.5 to +5.5 V IOK DC output diode current VO uVCC or VO t 0 "50 mA VO DC output voltage Note 2 IO DC output source or sink current VO = 0 to VCC IGND, ICC Tstg PTOT DC VCC or GND current Storage temperature range Power dissipation per package – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K –0.5 to VCC +0.5 V "50 mA "100 mA –65 to +150 °C 500 500 mW NOTES: 1 Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Jun 17 4 Philips Semiconductors Product specification 10-bit transparent latch with 5-volt tolerant inputs/outputs (3-State) 74LVC841A DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C TYP1 MIN VIH HIGH level Input In ut voltage VIL Input LOW level In ut voltage VOH HIGH level output out ut voltage VCC = 1.2V VCC VCC = 2.7 to 3.6V 2.0 MAX V VCC = 1.2V GND VCC = 2.7 to 3.6V 0.8 VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC*0.5 VCC = 3.0V; VI = VIH or VIL; IO = –100µA VCC*0.2 VCC = 3.0V; VI = VIH or VIL; IO = –18mA VCC*0.6 VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC*1.0 VCC LOW level output voltage 0.40 VCC = 3.0V; VI = VIH or VIL; IO = 100µA GND 0.20 VCC = 3.0V; VI = VIH or VIL; IO = 24mA II V 0.55 "0 1 "0.1 "5 µA VCC = 3.6V; VI = VIH or VIL; VO = VCC or GND 0.1 "5 µA VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 10 µA 5 500 µA Input In ut leakage current VCC = 3 3.6V; 6V; VI = 5 5.5V 5V or GND IOZ 3-State output OFF-state current ICC Quiescent supply current Additional quiescent supply current per input pin VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 ∆ICC V V VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL UNIT NOTE: 1 All typical values are at VCC = 3.3V and Tamb = 25°C. AC CHARACTERISTICS GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF; RL = 500; Tamb = –40C to +85C LIMITS SYMBOL PARAMETER VCC = 3.3V ±0.3V WAVEFORM VCC = 2.7V MIN TYP1 MAX MIN MAX UNIT tPHL/tPLH Propagation delay Dn to Qn Figures 1, 5 1.5 4.5 6.7 1.5 7.5 ns tPHL/tPLH Propagation delay LE to Qn Figures 2, 5 1.5 4.9 7.6 1.5 8.6 ns tPZH/tPZL 3-state output enable time OE to Qn Figures 3, 5 1.5 5.4 7.9 1.5 8.9 ns tPHZ/tPLZ 3-state output disable time OE to Qn Figures 3, 5 1.5 3.8 5.9 1.5 6.9 ns tw LE pulse width, HIGH Figure 4 2.0 0.7 – 2.0 ns tsu Set-up time Dn to LE Figure 4 2.0 0.5 – 2.0 ns th Hold time Dn to LE Figure 4 1.0 –0.5 – 1.0 ns NOTE: 1 All typical values are at VCC = 3.3V and Tamb = 25°C. 1998 Jun 17 5 Philips Semiconductors Product specification 10-bit transparent latch with 5-volt tolerant inputs/outputs (3-State) 74LVC841A AC WAVEFORMS VM = 1.5 V at VCC ≥ 2.7 V VM = 0.5 V × VCC at VCC < 2.7 V VM = 1.5 V at VCC = 3.0 V VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3 V at VCC ≥ 2.7 V VX = VOL + 0.1 × VCC at VCC < 2.7 V VY = VOH – 0.3 V at VCC ≥ 2.7 V VY = VOH – 0.1 × VCC at VCC < 2.7 V VI D n INPUT VM GND th th t su t su VI LE INPUT VI VM GND SV01730 Dn Input VM Figure 4. Data set-up and hold times for the Dn input to LE input. Note to Figure 4: The shaded areas indicate when the input is permitted to change for predictable output performance GND tPHL tPLH VOH Qn Output TEST CIRCUIT VM S1 VCC VOL SV01727 Figure 1. Input (Dn) to output (Qn) propagation delays. PULSE GENERATOR VI LE INPUT VI 2 x VCC Open GND 500Ω VO D.U.T. RT VM 50pF CL 500Ω GND tW Test t PLH t PHL VOH Q n OUTPUT VM VOL S1 VCC VI tPLH/tPHL Open 2.7V VCC tPLZ/tPZL 2 x VCC 2.7V – 3.6V 2.7V tPHZ/tPZH GND SY00003 SV01729 Figure 5. Load circuitry for switching times. Figure 2. Latch enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays. VI OE INPUT VM GND tPLZ tPZL VCC Qn OUTPUT LOW-to-OFF OFF-to-LOW VM VX VOL tPZH tPHZ VOH Qn OUTPUT HIGH-to-OFF OFF-to-HIGH GND VY VM outputs enabled outputs disabled outputs enabled SV01728 Figure 3. 3-State enable and disable times. 1998 Jun 17 6 Philips Semiconductors Product specification 10-bit transparent latch with 5-volt tolerant inputs/outputs (3-State) SO24: plastic small outline package; 24 leads; body width 7.5 mm 1998 Jun 17 7 74LVC841A SOT137-1 Philips Semiconductors Product specification 10-bit transparent latch with 5-volt tolerant inputs/outputs (3-State) SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm 1998 Jun 17 8 74LVC841A SOT340-1 Philips Semiconductors Product specification 10-bit transparent latch with 5-volt tolerant inputs/outputs (3-State) TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm 1998 Jun 17 9 74LVC841A SOT355-1 Philips Semiconductors Product specification 10-bit transparent latch with 5-volt tolerant inputs/outputs (3-State) 74LVC841A Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 10 Date of release: 06-98 9397-750-04522