Data Sheet Complete Quad, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC AD5764 FEATURES GENERAL DESCRIPTION Complete quad, 16-bit digital-to-analog converter (DAC) Programmable output range ±10 V, ±10.2564 V, or ±10.5263 V ±1 LSB maximum INL error, ±1 LSB maximum DNL error Low noise: 60 nV/√Hz Settling time: 10 μs maximum Integrated reference buffers Output control during power-up/brownout Programmable short-circuit protection Simultaneous updating via LDAC Asynchronous CLR to zero code Digital offset and gain adjust Logic output control pins DSP-/microcontroller-compatible serial interface Temperature range: −40°C to +85°C iCMOS process technology1 The AD5764 is a quad, 16-bit, serial input, bipolar voltage output DAC that operates from supply voltages of ±11.4 V to ±16.5 V. Nominal full-scale output range is ±10 V. The AD5764 provides integrated output amplifiers, reference buffers, and proprietary power-up/power-down control circuitry. The part also features a digital I/O port that is programmed via the serial interface. The part incorporates digital offset and gain adjust registers per channel. APPLICATIONS Industrial automation Open-loop/closed-loop servo control Process control Data acquisition systems Automatic test equipment Automotive test and measurement High accuracy instrumentation The AD5764 is a high performance converter that offers guaranteed monotonicity, integral nonlinearity (INL) of ±1 LSB, low noise, and 10 μs settling time. During power-up (when the supply voltages are changing), VOUTx is clamped to 0 V via a low impedance path. The AD5764 uses a serial interface that operates at clock rates of up to 30 MHz and is compatible with DSP and microcontroller interface standards. Double buffering allows the simultaneous updating of all DACs. The input coding is programmable to either twos complement or offset binary formats. The asynchronous clear function clears the data register to either bipolar zero or zero scale depending on the coding used. The AD5764 is ideal for both closed-loop servo control and open-loop control applications. The AD5764 is available in a 32-lead TQFP, and offers guaranteed specifications over the −40°C to +85°C industrial temperature range. See Figure 1 for the functional block diagram. Table 1. Related Devices Part No. AD5764R AD5744R 1 Description AD5764 with internal voltage reference Complete quad, 14-bit, high accuracy, serial input, bipolar voltage output DAC with internal voltage reference For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels, iCMOS® is a technology platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies, allowing dramatic reductions in power consumption and package size, and increased ac and dc performance. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved. AD5764 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Function Register ....................................................................... 21 Applications....................................................................................... 1 Data Register............................................................................... 21 General Description ......................................................................... 1 Coarse Gain Register ................................................................. 21 Revision History ............................................................................... 2 Fine Gain Register...................................................................... 22 Functional Block Diagram .............................................................. 3 Offset Register ............................................................................ 22 Specifications..................................................................................... 4 Offset and Gain Adjustment Worked Example...................... 23 AC Performance Characteristics ................................................ 5 Design Features............................................................................... 24 Timing Characteristics ................................................................ 6 Analog Output Control ............................................................. 24 Absolute Maximum Ratings............................................................ 9 Digital Offset and Gain Control............................................... 24 ESD Caution.................................................................................. 9 Programmable Short-Circuit Protection ................................ 24 Pin Configuration and Function Descriptions........................... 10 Digital I/O Port........................................................................... 24 Typical Performance Characteristics ........................................... 12 Local Ground Offset Adjust...................................................... 24 Terminology .................................................................................... 17 Applications Information .............................................................. 25 Theory of Operation ...................................................................... 18 Typical Operating Circuit ......................................................... 25 DAC Architecture....................................................................... 18 Layout Guidelines........................................................................... 27 Reference Buffers........................................................................ 18 Galvanically Isolated Interface ................................................. 27 Serial Interface ............................................................................ 18 Microprocessor Interfacing....................................................... 27 Simultaneous Updating via LDAC ........................................... 19 Evaluation Board ........................................................................ 27 Transfer Function ....................................................................... 20 Outline Dimensions ....................................................................... 28 Asynchronous Clear (CLR)....................................................... 20 Ordering Guide .......................................................................... 28 REVISION HISTORY 9/11—Rev. E to Rev. F Changed 30 MHz to 50 MHz Throughout.................................... 1 Changes to t1, t2, and t3 Parameters, Table 4.................................. 6 7/11—Rev. D to Rev. E Changed 30 MHz to 50 MHz Throughout.................................... 1 Changes to t1, t2, and t3 Parameters, Table 4.................................. 6 8/09—Rev. C to Rev. D Changes to Table 2 and Table 3 Endnotes ..................................... 6 Changes to t6 Parameter and Endnotes, Table 4 ........................... 7 1/09—Rev. B to Rev. C Changes to General Description Section ...................................... 1 Changes to Figure 1.......................................................................... 3 Changes to Table 2 Conditions ....................................................... 4 Changes to Table 3 Conditions ....................................................... 5 Changes to Table 4 Conditions ....................................................... 6 Changes to Figure 5.......................................................................... 8 Changes to Table 5............................................................................ 9 Changes to Table 6.......................................................................... 10 Changes to Figure 34...................................................................... 19 Changes to Table 7 and Table 10................................................... 20 Added Table 8; Renumbered Sequentially .................................. 20 Changes to Table 11 and Table 12 ................................................ 21 Changes to Digital Offset and Gain Control Section ................ 24 Changes to Table 20 ....................................................................... 26 Deleted AD5764 to MC68HC11 Interface Section.................... 27 Deleted Figure 38; Renumbered Sequentially ............................ 27 Deleted AD5764 to 8XC51 Interface Section, Figure 39, AD5764 to ADSP-2101 Interface Section, Figure 40, and AD5764 to PIC16C6x/PIC16C7x Interface Section .................. 28 04/08—Rev. A to Rev. B Changes to Table Summary Statement, Specifications Section...4 Changes to Power Requirements Parameter, Table 2 and Table Summary Statement................................................................5 Changes to t16 Parameter, Table 4 ....................................................6 Changes to Table 6.......................................................................... 10 Changed VSS/VDD to AVSS/AVDD in Typical Performance Characteristics Section .................................................................. 13 Changes to Table 16 ....................................................................... 22 Changes to Table 18 ....................................................................... 23 Changes to Typical Operating Circuit Section........................... 28 Changes to AD5764 to ADSP-2101 Section ............................... 29 Changes to Ordering Guide .......................................................... 30 1/07—Rev. 0 to Rev. A Changes to Absolute Maximum Ratings..................................... 10 Changes to Figure 25 and Figure 26............................................. 16 3/06—Revision 0: Initial Version Rev. F | Page 2 of 28 Data Sheet AD5764 FUNCTIONAL BLOCK DIAGRAM PGND AVDD AVSS AVDD AVSS REFGND DVCC DGND REFERENCE BUFFERS AD5764 16 SDIN SCLK SYNC SDO INPUT SHIFT REGISTER AND CONTROL LOGIC INPUT REG A DATA REG A RSTOUT REFAB 16 RSTIN VOLTAGE MONITOR AND CONTROL ISCC G1 DAC A VOUTA G2 GAIN REG A AGNDA OFFSET REG A INPUT REG B DATA REG B 16 G1 DAC B VOUTB G2 GAIN REG B AGNDB OFFSET REG B D0 D1 INPUT REG C DATA REG C 16 G1 DAC C VOUTC G2 GAIN REG C AGNDC OFFSET REG C BIN/2sCOMP INPUT REG D DATA REG D 16 G1 DAC D VOUTD G2 GAIN REG D AGNDD OFFSET REG D REFERENCE BUFFERS LDAC Figure 1. Rev. F | Page 3 of 28 REFCD 05303-001 CLR AD5764 Data Sheet SPECIFICATIONS AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGNDx = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V; DVCC = 2.7 V to 5.25 V, RLOAD = 10 kΩ, CL = 200 pF. Temperature range: −40°C to +85°C; typical at +25°C. Device functionality is guaranteed to +105°C with degraded performance. All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter ACCURACY Resolution Relative Accuracy (INL) Differential Nonlinearity Bipolar Zero Error A Grade B Grade C Grade Unit 16 ±4 ±1 ±2 16 ±2 ±1 ±2 16 ±1 ±1 ±2 Bits LSB max LSB max mV max Bipolar Zero Temperature Coefficient (TC) 1 Zero-Scale Error ±2 ±2 ±2 ppm FSR/°C max ±2 ±2 ±2 mV max Zero-Scale TC1 Gain Error ±2 ±0.02 ±2 ±0.02 ±2 ±0.02 ppm FSR/°C max % FSR max ±2 0.5 ±2 0.5 ±2 0.5 ppm FSR/°C max LSB max 5 1 ±10 1 to 7 5 1 ±10 1 to 7 5 1 ±10 1 to 7 V nom MΩ min μA max V min to V max ±1% for specified performance Typically 100 MΩ Typically ±30 nA ±10.5263 ±14 ±13 ±10.5263 ±14 ±13 ±10.5263 ±14 ±13 AVDD/AVSS = ±11.4 V, VREFIN = 5 V AVDD/AVSS = ±16.5 V, VREFIN = 7 V ±15 ±15 ±15 10 ±1 10 ±1 10 ±1 V min to V max V min to V max ppm FSR/ 500 hours typ ppm FSR/ 1000 hours typ mA typ mA max 200 1000 0.3 200 1000 0.3 200 1000 0.3 pF max pF max Ω max 2 0.8 ±1 10 2 0.8 ±1 10 2 0.8 ±1 10 V min V max μA max pF max Gain TC1 DC Crosstalk1 REFERENCE INPUT1 Reference Input Voltage DC Input Impedance Input Current Reference Range OUTPUT CHARACTERISTICS1 Output Voltage Range 2 Output Voltage Drift vs. Time Short-Circuit Current Load Current Capacitive Load Stability RLOAD = ∞ RLOAD = 10 kΩ DC Output Impedance DIGITAL INPUTS Input High Voltage, VIH Input Low Voltage, VIL Input Current Pin Capacitance Test Conditions/Comments Outputs unloaded Guaranteed monotonic At 25°C; error at other temperatures obtained using bipolar zero TC At 25°C; error at other temperatures obtained using zero-scale TC At 25°C; error at other temperatures obtained using gain TC RISCC = 6 kΩ, see Figure 31 For specified performance DVCC = 2.7 V to 5.25 V, JEDEC compliant Rev. F | Page 4 of 28 Per pin Per pin Data Sheet Parameter DIGITAL OUTPUTS (D0, D1, SDO)1 Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance POWER REQUIREMENTS AVDD/AVSS DVCC Power Supply Sensitivity1 ∆VOUT/∆ΑVDD AIDD AISS DICC Power Dissipation 1 2 AD5764 A Grade B Grade C Grade Unit Test Conditions/Comments 0.4 DVCC − 1 0.4 DVCC − 0.5 ±1 5 0.4 DVCC − 1 0.4 DVCC − 0.5 ±1 5 0.4 DVCC − 1 0.4 DVCC − 0.5 ±1 5 V max V min V max V min μA max pF typ DVCC = 5 V ± 5%, sinking 200 μA DVCC = 5 V ± 5%, sourcing 200 μA DVCC = 2.7 V to 3.6 V, sinking 200 μA DVCC = 2.7 V to 3.6 V, sourcing 200 μA SDO only SDO only ±11.4 to ±16.5 2.7 to 5.25 ±11.4 to ±16.5 2.7 to 5.25 ±11.4 to ±16.5 2.7 to 5.25 V min to V max −85 3.5 2.75 1.2 275 −85 3.5 2.75 1.2 275 −85 3.5 2.75 1.2 275 dB typ mA/channel max mA/channel max mA max mW typ V min to V max Outputs unloaded Outputs unloaded VIH = DVCC, VIL = DGND, 750 μA typical ±12 V operation output unloaded Guaranteed by design and characterization; not production tested. Output amplifier headroom requirement is 1.4 V minimum. AC PERFORMANCE CHARACTERISTICS AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGNDx = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V; DVCC = 2.7 V to 5.25 V, RLOAD = 10 kΩ, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE 1 Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Channel-to-Channel Isolation DAC-to-DAC Crosstalk Digital Crosstalk Digital Feedthrough Output Noise (0.1 Hz to 10 Hz) Output Noise (0.1 Hz to 100 kHz) 1/f Corner Frequency Output Noise Spectral Density Complete System Output Noise Spectral Density 2 1 2 A Grade B Grade C Grade Unit Test Conditions/Comments 8 10 2 5 8 25 80 8 2 2 8 10 2 5 8 25 80 8 2 2 8 10 2 5 8 25 80 8 2 2 μs typ μs max μs typ V/μs typ nV-sec typ mV max dB typ nV-sec typ nV-sec typ nV-sec typ Full-scale step to ±1 LSB 0.1 45 1 60 80 0.1 45 1 60 80 0.1 45 1 60 80 LSB p-p typ μV rms max kHz typ nV/√Hz typ nV/√Hz typ Guaranteed by design and characterization; not production tested. Includes noise contributions from integrated reference buffers, 16-bit DAC, and output amplifier. Rev. F | Page 5 of 28 512 LSB step settling Effect of input bus activity on DAC outputs Measured at 10 kHz Measured at 10 kHz AD5764 Data Sheet TIMING CHARACTERISTICS AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGNDx = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V; DVCC = 2.7 V to 5.25 V, RLOAD = 10 kΩ, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter 1, 2, 3 t1 t2 t3 t4 t5 4 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 5, 6 t16 t17 t18 Limit at TMIN, TMAX 33 13 13 13 13 90 2 5 1.7 480 10 500 10 10 2 25 13 2 170 Unit ns min ns min ns min ns min ns min ns min ns min ns min μs min ns min ns min ns max μs max ns min μs max ns max ns min μs max ns min Description SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time 24th SCLK falling edge to SYNC rising edge Minimum SYNC high time Data setup time Data hold time SYNC rising edge to LDAC falling edge (all DACs updated) SYNC rising edge to LDAC falling edge (single DAC updated) LDAC pulse width low LDAC falling edge to DAC output response time DAC output settling time CLR pulse width low CLR pulse activation time SCLK rising edge to SDO valid SYNC rising edge to SCLK falling edge SYNC rising edge to DAC output response time (LDAC = 0) LDAC falling edge to SYNC rising edge 1 Guaranteed by design and characterization; not production tested. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. See Figure 2, Figure 3, and Figure 4. 4 Standalone mode only. 5 Measured with the load circuit of Figure 5. 6 Daisy-chain mode only. 2 3 Rev. F | Page 6 of 28 Data Sheet AD5764 Timing Diagrams t1 SCLK 1 2 24 t3 t6 t2 t4 t5 SYNC t8 t7 SDIN DB0 DB23 t10 t9 LDAC t10 t18 t12 t11 VOUTx LDAC = 0 t12 t17 VOUTx t13 CLR t14 05303-002 VOUTx Figure 2. Serial Interface Timing Diagram t1 SCLK 24 t3 t6 48 t2 t5 t16 t4 SYNC t7 SDIN t8 DB23 DB0 INPUT WORD FOR DAC N DB23 DB0 t15 INPUT WORD FOR DAC N–1 DB23 SDO UNDEFINED DB0 INPUT WORD FOR DAC N t9 t10 05303-003 LDAC Figure 3. Daisy-Chain Timing Diagram Rev. F | Page 7 of 28 AD5764 Data Sheet SCLK 24 48 SYNC DB23 DB0 DB23 DB0 NOP CONDITION INPUT WORD SPECIFIES REGISTER TO BE READ DB23 SDO UNDEFINED DB0 SELECTED REGISTER DATA CLOCKED OUT Figure 4. Readback Timing Diagram 200µA VOH (MIN) OR VOL (MAX) CL 50pF 200µA IOH 05303-005 TO SDO PIN IOL Figure 5. Load Circuit for SDO Timing Diagram Rev. F | Page 8 of 28 05303-004 SDIN Data Sheet AD5764 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 5. Parameter AVDD to AGNDx, DGND AVSS to AGNDx, DGND DVCC to DGND Digital Inputs to DGND Digital Outputs to DGND REFAB, REFCD to AGNDx, PGND VOUTA, VOUTB, VOUTC, VOUTD to AGNDx AGNDx to DGND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) 32-Lead TQFP θJA Thermal Impedance θJC Thermal Impedance Lead Temperature Soldering Rating −0.3 V to +17 V +0.3 V to −17 V −0.3 V to +7 V −0.3 V to DVCC + 0.3 V or 7 V (whichever is less) −0.3 V to DVCC + 0.3 V −0.3 V to AVDD + 0.3 V AVSS to AVDD Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −0.3 V to +0.3 V −40°C to +85°C −65°C to +150°C 150°C 65°C/W 12°C/W JEDEC industry standard J-STD-020 Rev. F | Page 9 of 28 AD5764 Data Sheet REFAB REFCD NC REFGND NC AVSS AVDD BIN/2sCOMP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 32 31 30 29 28 27 26 25 24 AGNDA 23 VOUTA 22 VOUTB 21 AGNDB 20 AGNDC LDAC 6 19 VOUTC D0 7 18 VOUTD D1 8 17 AGNDD SYNC 1 PIN 1 SDIN 3 AD5764 SDO 4 TOP VIEW (Not to Scale) CLR 5 ISCC AVSS PGND AVDD DVCC DGND 10 11 12 13 14 15 16 RSTIN RSTOUT 9 NC = NO CONNECT 05303-006 SCLK 2 Figure 6. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 Mnemonic SYNC 2 SCLK 3 4 5 SDIN SDO CLR 6 LDAC 7, 8 D0, D1 9 RSTOUT 10 RSTIN 11 12 13, 31 14 15, 30 16 DGND DVCC AVDD PGND AVSS ISCC 17 18 AGNDD VOUTD 19 VOUTC 20 AGNDC Description Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in on the falling edge of SCLK. Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This operates at clock speeds up to 30 MHz. Serial Data Input. Data must be valid on the falling edge of SCLK. Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Negative Edge Triggered Input. Asserting this pin sets the data register to 0x0000. There is an internal pull-up device on this logic input. Therefore, this pin can be left floating and defaults to a Logic 1 condition. Load DAC. Logic input. This is used to update the data register and consequently the analog outputs. When tied permanently low, the addressed data register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the DAC input shift register is updated but the output update is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. The LDAC pin must not be left unconnected. Digital I/O Port. The user can set up these pins as inputs or outputs that are configurable and readable over the serial interface. When configured as inputs, these pins have weak internal pull-ups to DVCC. When programmed as outputs, D0 and D1 are referenced by DVCC and DGND. Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. If desired, it can be used to control other system components. Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to this input clamps the DAC outputs to 0 V. In normal operation, RSTIN should be tied to Logic 1. Register values remain unchanged. Digital Ground. Digital Supply. Voltage ranges from 2.7 V to 5.25 V. Positive Analog Supply. Voltage ranges from 11.4 V to 16.5 V. Ground Reference Point for Analog Circuitry. Negative Analog Supply. Voltage ranges from −11.4 V to −16.5 V. Resistor Connection for Pin Programmable Short-Circuit Current. This pin is used in association with an optional external resistor to AGND to program the short-circuit current of the output amplifiers. Refer to the Design Features section for further details. Ground Reference Pin for DAC D Output Amplifier. Analog Output Voltage of DAC D. This pin is a buffered output with a nominal full-scale output range of ±10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load. Analog Output Voltage of DAC C. This pin is a buffered output with a nominal full-scale output range of ±10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load. Ground Reference Pin for DAC C Output Amplifier. Rev. F | Page 10 of 28 Data Sheet Pin No. 21 22 Mnemonic AGNDB VOUTB 23 VOUTA 24 25 AGNDA REFAB 26 REFCD 27, 29 28 32 NC REFGND BIN/2sCOMP AD5764 Description Ground Reference Pin for DAC B Output Amplifier. Analog Output Voltage of DAC B. Buffered output with a nominal full-scale output range of ±10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load. Analog Output Voltage of DAC A. Buffered output with a nominal full-scale output range of ±10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load. Ground Reference Pin for DAC A Output Amplifier. External Reference Voltage Input for Channel A and Channel B. Reference input range is 1 V to 7 V; programs the full-scale output voltage. VREFIN = 5 V for specified performance. External Reference Voltage Input for Channel C and Channel D. Reference input range is 1 V to 7 V; programs the full-scale output voltage. VREFIN = 5 V for specified performance. No Connect. Reference Ground Return for the Reference Generator and Buffers. Determines the DAC Coding. This pin should be hardwired to either DVCC or DGND. When hardwired to DVCC, input coding is offset binary. When hardwired to DGND, input coding is twos complement (see Table 7 and Table 8). Rev. F | Page 11 of 28 AD5764 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 TA = 25°C AVDD/AVSS = ±15V VREFIN = 5V 0.8 0.6 0.6 DNL ERROR (LSB) 0.2 0 –0.2 –0.4 0.2 0 –0.2 –0.4 –0.6 05303-007 –0.6 0.4 –0.8 0 10000 20000 30000 40000 50000 05303-012 INL ERROR (LSB) 0.4 –1.0 TA = 25°C AVDD/AVSS = ±12V VREFIN = 5V 0.8 –0.8 –1.0 60000 0 10000 20000 DAC CODE 40000 50000 60000 DAC CODE Figure 7. Integral Nonlinearity Error vs. Code, AVDD/AVSS = ±15 V Figure 10. Differential Nonlinearity Error vs. Code, AVDD/AVSS = ±12 V 1.0 0.5 TA = 25°C 0.8 AVDD/AVSS = ±12V VREFIN = 5V 0.6 0.4 TA = 25°C AVDD/AVSS = ±15V VREFIN = 5V 0.3 INL ERROR (LSB) 0.4 INL ERROR (LSB) 30000 0.2 0 –0.2 –0.4 0.2 0.1 0 –0.6 0 10000 20000 30000 40000 50000 –0.2 –40 60000 05303-015 –1.0 –0.1 05303-008 –0.8 –20 0 DAC CODE Figure 8. Integral Nonlinearity Error vs. Code, AVDD/AVSS = ±12 V 1.0 80 100 TA = 25°C AVDD/AVSS = ±12V VREFIN = 5V 0.4 INL ERROR (LSB) 0.4 0.2 0 –0.2 –0.4 –0.6 0.3 0.2 0.1 0 10000 20000 30000 40000 50000 –0.1 –40 60000 DAC CODE 05303-016 0 –0.8 –1.0 60 0.5 05303-011 DNL ERROR (LSB) 0.6 40 Figure 11. Integral Nonlinearity Error vs. Temperature, AVDD/AVSS = ±15 V TA = 25°C AVDD/AVSS = ±15V VREFIN = 5V 0.8 20 TEMPERATURE (°C) –20 0 20 40 60 80 TEMPERATURE (°C) Figure 9. Differential Nonlinearity Error vs. Code, AVDD/AVSS = ±15 V Figure 12. Integral Nonlinearity Error vs. Temperature, AVDD/AVSS = ±12 V Rev. F | Page 12 of 28 100 AD5764 0.15 0.15 0.10 0.10 0.05 0.05 DNL ERROR (LSB) 0 –0.05 –0.10 –0.15 0 –0.05 –0.10 –0.15 –20 0 20 40 –0.20 05303-019 TA = 25°C AVDD/AVSS = ±15V VREFIN = 5V –0.20 –0.25 –40 TA = 25°C VREFIN = 5V 60 80 –0.25 11.4 100 05303-025 DNL ERROR (LSB) Data Sheet 12.4 TEMPERATURE (°C) Figure 13. Differential Nonlinearity Error vs. Temperature, AVDD/AVSS = ±15 V 0.8 0.10 0.6 INL ERROR (LSB) 16.4 TA = 25°C AVDD/AVSS = ±16.5V 0 –0.05 –0.10 –0.15 0.2 0 –0.2 –0.4 –0.6 –0.20 –20 0 20 40 –0.8 05303-020 TA = 25°C AVDD/AVSS = ±12V VREFIN = 5V 60 80 –1.0 100 05303-027 DNL ERROR (LSB) 15.4 0.4 0.05 1 2 3 4 5 6 Figure 14. Differential Nonlinearity Error vs. Temperature, AVDD/AVSS = ±12 V Figure 17. Integral Nonlinearity Error vs. Reference Voltage, AVDD/AVSS = ±16.5 V 0.5 0.4 TA = 25°C VREFIN = 5V 0.4 TA = 25°C AVDD/AVSS = ±16.5V 0.3 0.2 DNL ERROR (LSB) 0.3 0.2 0.1 0 0.1 0 –0.1 –0.2 12.4 13.4 14.4 15.4 –0.4 16.4 05303-031 –0.3 05303-023 –0.1 –0.2 11.4 7 REFERENCE VOLTAGE (V) TEMPERATURE (°C) INL ERROR (LSB) 14.4 Figure 16. Differential Nonlinearity Error vs. Supply Voltage 0.15 –0.25 –40 13.4 SUPPLY VOLTAGE (V) 1 2 3 4 5 6 7 REFERENCE VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 18. Differential Nonlinearity Error vs. Reference Voltage, AVDD/AVSS = ±16.5 V Figure 15. Integral Nonlinearity Error vs. Supply Voltage Rev. F | Page 13 of 28 AD5764 Data Sheet 0.6 0.8 TA = 25°C 0.4 AVDD/AVSS = ±16.5V VREFIN = 5V BIPOLAR ZERO ERROR (mV) 0.2 0 –0.4 –0.6 –0.8 –1.0 –1.2 0.4 AVDD/AVSS = ±12V 0.2 0 05303-035 –0.2 –1.4 1 2 3 4 5 6 –0.4 –40 7 05303-039 TUE (mV) –0.2 –1.6 AVDD/AVSS = ±15V 0.6 –20 0 20 REFERENCE VOLTAGE (V) 40 60 80 100 TEMPERATURE (°C) Figure 19. Total Unadjusted Error vs. Reference Voltage, AVDD/AVSS = ±16.5 V Figure 22. Bipolar Zero Error vs. Temperature 1.4 14 VREFIN = 5V TA = 25°C VREFIN = 5V 1.2 13 1.0 GAIN ERROR (mV) |IDD| 11 10 9 13.4 0.4 AVDD/AVSS = ±15V 0 05303-037 12.4 0.6 0.2 |ISS| 8 11.4 AVDD/AVSS = ±12V 0.8 14.4 15.4 –0.2 –40 16.4 05303-040 IDD/ISS (mA) 12 –20 0 20 0.0014 0.20 0.10 5V 0.0012 AVDD/AVSS = ±12V 0.0011 DICC (mA) 0.05 0 –0.05 –0.10 0.0010 0.0009 0.0008 –0.15 3V –0.20 –20 0 20 40 60 80 0.0006 100 05303-041 0.0007 05303-038 ZERO-SCALE ERROR (mV) 100 0.0013 0.15 –0.25 –40 80 TA = 25°C AVDD/AVSS = ±15V VREFIN = 5V 60 Figure 23. Gain Error vs. Temperature Figure 20. IDD/ISS vs. AVDD/AVSS 0.25 40 TEMPERATURE (°C) AVDD/AVSS (V) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VLOGIC TEMPERATURE (°C) Figure 21. Zero-Scale Error vs. Temperature Figure 24. DICC vs. Logic Input Voltage Rev. F | Page 14 of 28 4.0 4.5 5.0 Data Sheet 7000 TA = 25°C VREFIN = 5V RISCC = 6kΩ AVDD/AVSS = ±15V TA = 25°C VREFIN = 5V AVDD/AVSS = ±15V 5000 AVDD/AVSS = ±12V 4000 3000 2000 1000 –1000 –10 05303-042 0 –5 0 5 1 1µs/DIV CH1 3.00V 10 05303-044 OUTPUT VOLTAGE DELTA (µV) 6000 AD5764 M1.00µs CH1 –120mV SOURCE/SINK CURRENT (mA) Figure 27. Full-Scale Settling Time Figure 25. Source and Sink Capability of Output Amplifier with Positive Full Scale Loaded 8000 –6 –8 15V SUPPLIES –10 7000 –12 6000 VOUT (mV) 12V SUPPLIES 5000 4000 –14 –16 3000 –18 2000 –20 1000 –22 05303-043 OUTPUT VOLTAGE DELTA (µV) 9000 –4 TA = 25°C VREFIN = 5V RISCC = 6kΩ 0 –1000 –12 –7 –2 3 AVDD/AVSS = ±12V VREFIN = 5V TA = 25°C 0x8000 TO 0x7FFF 500ns/DIV –24 05303-047 10000 –26 –2.0–1.5–1.0–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 8 TIME (µs) SOURCE/SINK CURRENT (mA) Figure 28. Major Code Transition Glitch Energy, AVDD/AVSS = ±12 V Figure 26. Source and Sink Capability of Output Amplifier with Negative Full Scale Loaded Rev. F | Page 15 of 28 AD5764 Data Sheet 10 AVDD/AVSS = ±15V MIDSCALE LOADED VREFIN = 0V 50µV/DIV M1.00s CH4 8 7 6 5 4 3 2 05303-050 SHORT-CIRCUIT CURRENT (mA) 05303-048 4 CH4 50.0µV AVDD/AVSS = ±15V TA = 25°C VREFIN = 5V 9 1 0 26µV 0 20 40 60 80 RISCC (kΩ) Figure 31. Short-Circuit Current vs. RISCC Figure 29. Peak-to-Peak Noise (100 kHz Bandwidth) T AVDD/AVSS = ±12V VREFIN = 5V TA = 25°C RAMP TIME = 100µs LOAD = 200pF||10kΩ 1 2 05303-055 3 CH1 10.0V BW CH2 10.0V CH3 10.0mV BW M100µs A CH1 7.80mV T 29.60% Figure 30. VOUT vs. AVDD/AVSS on Power-Up Rev. F | Page 16 of 28 100 120 Data Sheet AD5764 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 7. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic. A typical DNL vs. code plot can be seen in Figure 9. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5764 is monotonic over its full operating temperature range. Bipolar Zero Error Bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 V when the data register is loaded with 0x8000 (offset binary coding) or 0x0000 (twos complement coding). A plot of bipolar zero error vs. temperature can be seen in Figure 22. Bipolar Zero Temperature Coefficient (TC) Bipolar zero TC is the measure of the change in the bipolar zero error with a change in temperature. It is expressed in ppm FSR/°C. Full-Scale Error Full-scale error is a measure of the output error when full-scale code is loaded to the data register. Ideally, the output voltage should be 2 × VREF − 1 LSB. Full-scale error is expressed in percentage of full-scale range. Negative Full-Scale Error/Zero-Scale Error Negative full-scale error is the error in the DAC output voltage when 0x0000 (offset binary coding) or 0x8000 (twos complement coding) is loaded to the data register. Ideally, the output voltage should be −2 × VREF. A plot of zero-scale error vs. temperature can be seen in Figure 21. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. Slew Rate The slew rate of a device is a limitation in the rate of change of the output voltage. The output slewing speed of a voltage-output DAC is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is given in V/μs. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed as a percentage of the full-scale range. A plot of gain error vs. temperature can be seen in Figure 23. Total Unadjusted Error Total unadjusted error (TUE) is a measure of the output error considering all the various errors. A plot of total unadjusted error vs. reference voltage can be seen in Figure 19. Zero-Scale Error Temperature Coefficient (TC) Zero-scale error TC is a measure of the change in zero-scale error with a change in temperature. Zero-scale error TC is expressed in ppm FSR/°C. Gain Error Temperature Coefficient (TC) Gain error TC is a measure of the change in gain error with changes in temperature. Gain error TC is expressed in ppm FSR/°C. Digital-to-Analog Glitch Energy Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the data register changes state. It is normally specified as the area of the glitch in nV-sec, and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000); see Figure 28. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s, and vice versa. Power Supply Sensitivity Power supply sensitivity indicates how the output of the DAC is affected by changes in the power supply voltage. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC, and is expressed in LSBs. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-sec. Channel-to-Channel Isolation Channel-to-channel isolation is the ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of another DAC. It is measured in dB. Digital Crosstalk Digital crosstalk is a measure of the impulse injected into the analog output of one DAC from the digital inputs of another DAC, but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s, and vice versa. Rev. F | Page 17 of 28 AD5764 Data Sheet THEORY OF OPERATION The AD5764 is a quad, 16-bit, serial input, bipolar voltage output DAC and operates from supply voltages of ±11.4 V to ±16.5 V and has a buffered output voltage of up to ±10.5263 V. Data is written to the AD5764 in a 24-bit word format, via a 3-wire serial interface. The device also offers an SDO pin that is available for daisychaining or readback. SERIAL INTERFACE The AD5764 incorporates a power-on reset circuit, which ensures that the data register powers up loaded with 0x0000. The AD5764 features a digital I/O port that can be programmed via the serial interface, on-chip reference buffers and per channel digital gain, and offset registers. The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK. The input shift register consists of a read/ write bit, three register select bits, three DAC address bits, and 16 data bits, as shown in Table 9. The timing diagram for this operation is shown in Figure 2. DAC ARCHITECTURE The four MSBs of the 16-bit data word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of the 15 matched resistors to either AGNDx or IOUT. The remaining 12 bits of the data-word drive Switch S0 to Switch S11 of the 12-bit R-2R ladder network. R 2R 2R E15 E14 2R E1 R 2R S11 R 2R S10 2R S0 2R Standalone Operation R/8 IOUT VOUTx 05303-060 AGNDx 4 MSBs DECODED INTO 15 EQUAL SEGMENTS Input Shift Register Upon power-up, the data register is loaded with zero code (0x0000), and the outputs are clamped to 0 V via a low impedance path. The outputs can be updated with the zero code value at this time by asserting either LDAC or CLR. The corresponding output voltage depends on the state of the BIN/2sCOMP pin. If the BIN/2sCOMP pin is tied to DGND, the data coding is twos complement, and the outputs update to 0 V. If the BIN/2sCOMP pin is tied to DVCC, the data coding is offset binary, and the outputs update to negative full scale. To power up the outputs with zero code loaded to the outputs, hold the CLR pin low during power-up. The DAC architecture of the AD5764 consists of a 16-bit, current mode, segmented R-2R DAC. The simplified circuit diagram for the DAC section is shown in Figure 32. VREF The AD5764 is controlled over a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with SPI, QSPI™, MICROWIRE™, and DSP standards. 12-BIT, R-2R LADDER Figure 32. DAC Ladder Structure REFERENCE BUFFERS The AD5764 operates with an external reference. The reference inputs (REFAB and REFCD) have an input range up to 7 V. This input voltage is used to provide a buffered positive and negative reference for the DAC cores. The positive reference is given by +VREF = 2 × VREF The negative reference to the DAC cores is given by −VREF = −2 × VREF These positive and negative reference voltages (along with the gain register values) define the output ranges of the DACs. The serial interface works with both a continuous and noncontinuous serial clock. A continuous SCLK source can only be used if SYNC is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used and SYNC must be taken high after the final clock to latch the data. The first falling edge of SYNC starts the write cycle. Exactly 24 falling clock edges must be applied to SCLK before SYNC is brought high again. If SYNC is brought high before the 24th falling SCLK edge, the data written is invalid. If more than 24 falling SCLK edges are applied before SYNC is brought high, the input data is also invalid. The input shift register addressed is updated on the rising edge of SYNC. For another serial transfer to take place, SYNC must be brought low again. After the end of the serial data transfer, data is automatically transferred from the input shift register to the addressed register. When the data has been transferred into the chosen register of the addressed DAC, the data register and outputs can be updated by taking LDAC low. Rev. F | Page 18 of 28 Data Sheet AD5764 Daisy-Chain Operation disable bit; this bit is cleared by default. Readback mode is invoked by setting the R/W bit = 1 in the serial input shift register write. With R/W = 1, Bit A2 to Bit A0, in association with Bit REG2, Bit REG1, and Bit REG0, select the register to be read. The remaining data bits in the write sequence are don’t cares. During the next SPI write, the data appearing on the SDO output contain the data from the previously addressed register. For a read of a single register, the NOP command can be used in clocking out the data from the selected register on SDO. The readback diagram in Figure 4 shows the readback sequence. For example, to read back the fine gain register of Channel A on the AD5764, implement the following: AD57641 MOSI SDIN SCK SCLK PC7 SYNC PC6 LDAC MISO SDO SDIN AD57641 SCLK 1. SYNC LDAC SDO 2. SDIN AD57641 SCLK SYNC LDAC SIMULTANEOUS UPDATING VIA LDAC 05303-061 SDO 1ADDITIONAL PINS OMITTED FOR CLARITY Write 0xA0XXXX to the AD5764 input shift register. This configures the AD5764 for read mode with the fine gain register of Channel A selected. Note that all the data bits, DB15 to DB0, are don’t cares. Follow this with a second write, an NOP condition, 0x00XXXX. During this write, the data from the fine gain register is clocked out on the SDO line, that is, data clocked out contain the data from the fine gain register in Bit DB5 to Bit DB0. Figure 33. Daisy-Chaining the AD5764 For systems that contain several devices, the SDO pin can be used to daisy-chain several devices together. This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. The first falling edge of SYNC starts the write cycle. The SCLK is continuously applied to the input shift register when SYNC is low. If more than 24 clock pulses are applied, the data ripples out of the input shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting the SDO of the first device to the SDIN input of the next device in the chain, a multidevice interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24N, where N is the total number of AD5764 devices in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register. The serial clock can be a continuous or a gated clock. Depending on the status of both SYNC and LDAC, and after data has been transferred into the input register of the DACs, there are two ways in which the data register and DAC outputs can be updated. Individual DAC Updating In this mode, LDAC is held low while data is being clocked into the input shift register. The addressed DAC output is updated on the rising edge of SYNC. Simultaneous Updating of All DACs In this mode, LDAC is held high while data is being clocked into the input shift register. All DAC outputs are updated by taking LDAC low any time after SYNC has been taken high. The update now occurs on the falling edge of LDAC. A continuous SCLK source can only be used if SYNC is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and SYNC must be taken high after the final clock to latch the data. Readback Operation Before a readback operation is initiated, the SDO pin must be enabled by writing to the function register and clearing the SDO Rev. F | Page 19 of 28 OUTPUT I/V AMPLIFIER VREFIN LDAC 16-BIT DAC VOUTx DATA REGISTER INPUT REGISTER SCLK SYNC SDIN INTERFACE LOGIC SDO 05303-062 68HC11 1 Figure 34. Simplified Serial Interface of Input Loading Circuitry for One DAC Channel AD5764 Data Sheet The output voltage expression for the AD5764 is given by TRANSFER FUNCTION Table 7 and Table 8 show the ideal input code to output voltage relationship for the AD5764 for both offset binary and twos complement data coding, respectively. Table 7. Ideal Output Voltage to Input Code Relationship— Offset Binary Data Coding Digital Input MSB 1111 1000 1000 0111 0000 1111 0000 0000 1111 0000 1111 0000 0000 1111 0000 LSB 1111 0001 0000 1111 0000 Analog Output VOUTx +2 VREF × (32,767/32,768) +2 VREF × (1/32,768) 0V −2 VREF × (1/32,768) −2 VREF × (32,767/32,768) Digital Input 1111 0000 0000 1111 0000 1111 0000 0000 1111 0000 LSB 1111 0001 0000 1111 0000 where: D is the decimal equivalent of the code loaded to the DAC. VREFIN is the reference voltage applied at the REFAB/REFCD pins. ASYNCHRONOUS CLEAR (CLR) Table 8. Ideal Output Voltage to Input Code Relationship— Twos Complement Data Coding MSB 0111 0000 0000 1111 1000 ⎡ D ⎤ VOUT = −2 × V REFIN + 4 × V REFIN ⎢ ⎥ ⎣ 65,536 ⎦ Analog Output VOUTx +2 VREF × (32,767/32,768) +2 VREF × (1/32,768) 0V −2 VREF × (1/32,768) −2 VREF × (32,767/32,768) CLR is a negative edge triggered clear that allows the outputs to be cleared to either 0 V (twos complement coding) or negative full scale (offset binary coding). It is necessary to maintain CLR low for a minimum amount of time (see Figure 2) for the operation to complete. When the CLR signal is returned high, the output remains at the cleared value until a new value is programmed. If at power-on, CLR is at 0 V, then all DAC outputs are updated with the clear value. A clear can also be initiated through software by writing Command 0x04XXXX to the AD5764. Table 9. Input Shift Register Bit Map MSB DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 0 REG2 REG1 REG0 A2 A1 A0 R/W LSB DB15:DB0 Data Table 10. Input Shift Register Bit Functions Bit R/W Description Indicates a read from or a write to the addressed register. REG2, REG1, REG0 Used in association with the address bits to determine if a read or write operation is to the data register, offset register, coarse gain register, fine gain register, or function register. REG2 REG1 REG0 Function 0 0 0 Function register 0 1 0 Data register 0 1 1 Coarse gain register 1 0 0 Fine gain register 1 0 1 Offset register These bits are used to decode the DAC channels. A2 A1 A0 Channel Address 0 0 0 DAC A 0 0 1 DAC B 0 1 0 DAC C 0 1 1 DAC D 1 0 0 All DACs Data bits. A2, A1, A0 Data Rev. F | Page 20 of 28 Data Sheet AD5764 FUNCTION REGISTER The function register is addressed by setting the three REG bits to 000. The values written to the address bits and the data bits determine the function addressed. The functions available via the function register are outlined in Table 11 and Table 12. Table 11. Function Register Options REG2 0 0 REG1 0 0 REG0 0 0 A2 0 0 A1 0 0 A0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 DB15:DB6 DB5 DB4 Don’t care Local ground offset adjust DB3 DB2 NOP, data = don’t care D1 direction D1 value D0 direction DB1 DB0 D0 value SDO disable Clear, data = don’t care Load, data = don’t care Table 12. Explanation of Function Register Options Option NOP Local Ground Offset Adjust D0/D1 Direction D0/D1 Value SDO Disable Clear Load Description No operation instruction used in readback operations. Set by the user to enable the local ground offset adjust function. Cleared by the user to disable the local ground offset adjust function (default). Refer to the Design Features section for further details. Set by the user to enable D0/D1 as outputs. Cleared by the user to enable D0/D1 as inputs (default). Refer to the Design Features section for further details. I/O port status bits. Logic values written to these locations determine the logic outputs on the D0 and D1 pins when configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is active as an input. When enabled as inputs, these bits are don’t cares during a write operation. Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default). Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary mode. Addressing this function updates the data register and consequently the analog outputs. DATA REGISTER The data register is addressed by setting the three REG bits to 010. The DAC address bits select with which DAC channel the data transfer is to take place (see Table 10). The data bits are in Position DB15 to Position DB0, as shown in Table 13. Table 13. Programming the Data Register Bit Map REG2 0 REG1 1 REG0 0 A2 A1 A0 DAC address DB15:DB0 16-bit DAC data COARSE GAIN REGISTER The coarse gain register is addressed by setting the three REG bits to 011. The DAC address bits select with which DAC channel the data transfer is to take place (see Table 10). The coarse gain register is a 2-bit register and allows the user to select the output range of each DAC, as shown in Table 14 and Table 15. Table 14. Programming the Coarse Gain Register Bit Map REG2 0 REG1 1 REG0 1 A2 A1 A0 DAC address DB15: DB2 Don’t care DB1 CG1 Table 15. Output Range Selection Output Range ±10 V (Default) ±10.2564 V ±10.5263 V CG1 0 0 1 Rev. F | Page 21 of 28 CG0 0 1 0 DB0 CG0 AD5764 Data Sheet FINE GAIN REGISTER OFFSET REGISTER The fine gain register is addressed by setting the three REG bits to 100. The DAC address bits select with which DAC channel the data transfer is to take place (see Table 10). The fine gain register is a 6-bit register and allows the user to adjust the gain of each DAC channel by −32 LSBs to +31 LSBs in 1 LSB increments, as shown in Table 16 and Table 17. The adjustment is made to both the positive full-scale points and the negative full-scale points simultaneously, each point being adjusted by ½ of one step. The fine gain register coding is twos complement. The offset register is addressed by setting the three REG bits to 101. The DAC address bits select with which DAC channel the data transfer is to take place (see Table 10). The AD5764 offset register is an 8-bit register and allows the user to adjust the offset of each channel by −16 LSBs to +15.875 LSBs in increments of ⅛ LSB, as shown in Table 18 and Table 19. The offset register coding is twos complement. Table 16. Programming the Fine Gain Register Bit Map REG2 1 REG1 0 REG0 0 A2 A1 A0 DAC address DB15:DB6 Don’t care DB5 FG5 DB4 FG4 DB3 FG3 DB2 FG2 DB1 FG1 DB0 FG0 Table 17. Fine Gain Register Options Gain Adjustment +31 LSBs +30 LSBs … +2 LSBs +1 LSB No Adjustment (Default) −1 LSB −2 LSBs … −31 LSBs −32 LSBs FG5 0 0 … 0 0 0 1 1 … 1 1 FG4 1 1 … 0 0 0 1 1 … 0 0 FG3 1 1 … 0 0 0 1 1 … 0 0 FG2 1 1 … 0 0 0 1 1 … 0 0 FG1 1 1 … 1 0 0 1 1 … 0 0 FG0 1 0 … 0 1 0 1 0 … 1 0 Table 18. Programming the Offset Register Bit Map REG2 1 REG1 0 REG0 1 A2 A1 A0 DAC address DB15:DB8 Don’t care DB7 OF7 OF6 1 1 … 0 0 0 1 1 … 0 0 OF5 1 1 … 0 0 0 1 1 … 0 0 DB6 OF6 DB5 OF5 DB4 OF4 DB3 OF3 DB2 OF2 DB1 OF1 Table 19. AD5764 Offset Register Options Offset Adjustment +15.875 LSBs +15.75 LSBs … +0.25 LSBs +0.125 LSBs No Adjustment (Default) −0.125 LSBs −0.25 LSBs … −15.875 LSBs −16 LSBs OF7 0 0 … 0 0 0 1 1 … 1 1 Rev. F | Page 22 of 28 OF4 1 1 … 0 0 0 1 1 … 0 0 OF3 1 1 … 0 0 0 1 1 … 0 0 OF2 1 1 … 0 0 0 1 1 … 0 0 OF1 1 1 … 1 0 0 1 1 … 0 0 OF0 1 0 … 0 1 0 1 0 … 1 0 DB0 OF0 Data Sheet AD5764 OFFSET AND GAIN ADJUSTMENT WORKED EXAMPLE Using the information provided in the Fine Gain Register and Offset Register sections, the following worked example demonstrates how the AD5764 functions can be used to eliminate both offset and gain errors. Because the AD5764 is factory calibrated, offset and gain errors should be negligible. However, errors can be introduced by the system that the AD5764 is operating within; for example, a voltage reference value that is not equal to 5 V introduces a gain error. An output range of ±10 V and twos complement data coding is assumed. Removing Offset Error Convert this to a negative twos complement number by inverting all bits and adding 1 to obtain 11110000, the value that should be programmed to the offset register. Note that this twos complement conversion is not necessary in the case of a positive offset adjustment. The value to be programmed to the offset register is simply the binary representation of the adjustment value. Removing Gain Error The AD5764 can eliminate a gain error at negative full-scale output in the range of −9.77 mV to +9.46 mV with a step size of ½ of a 16-bit LSB. Calculate the step size of the gain adjustment. The AD5764 can eliminate an offset error in the range of −4.88 mV to +4.84 mV with a step size of ⅛ of a 16-bit LSB. Gain Adjust Step Size = Calculate the step size of the offset adjustment. 20 Offset Adjust Step Size = 16 = 38.14 μV 2 ×8 Measure the offset error by programming 0x0000 to the data register and measuring the resulting output voltage. For this example, the measured value is 614 μV. Measure the gain error by programming 0x8000 to the data register and measuring the resulting output voltage. The gain error is the difference between this value and −10 V. For this example, the gain error is −1.2 mV. Calculate how many gain adjustment steps this value represents. Number of Steps = Calculate the number of offset adjustment steps that this value represents. Number of Steps = 614 μV 38.14 μV Measured Offset Value Offset Step Size 1.2 mV = 152.59 μV = 16 Steps The offset error measured is positive, therefore, a negative adjustment of 16 steps is required. The offset register is eight bits wide and the coding is twos complement. The required offset register value can be calculated as follows: 20 = 152.59 μV 2 ×2 16 Measured Gain Value Gain Step Size = = 8 Steps The gain error measured is negative (in terms of magnitude); therefore, a positive adjustment of eight steps is required. The gain register is 6 bits wide and the coding is twos complement, the required gain register value can be determined as follows: Convert the adjustment value to binary: 001000. The value to be programmed to the gain register is simply this binary number. Convert the adjustment value to binary: 00010000. Rev. F | Page 23 of 28 AD5764 Data Sheet DESIGN FEATURES ANALOG OUTPUT CONTROL PROGRAMMABLE SHORT-CIRCUIT PROTECTION In many industrial process control applications, it is vital that the output voltage be controlled during power-up and during brownout conditions. When the supply voltages are changing, the VOUTx pins are clamped to 0 V via a low impedance path. To prevent the output amp being shorted to 0 V during this time, Transmission Gate G1 is also opened (see Figure 35). These conditions are maintained until the power supplies stabilize and a valid word is written to the data register. At this time, G2 opens and G1 closes. Both transmission gates are also externally controllable via the reset logic (RSTIN) control input. For instance, if RSTIN is driven from a battery supervisor chip, the RSTIN input is driven low to open G1 and close G2 upon power-down or during a brownout. Conversely, the on-chip voltage detector output (RSTOUT) is also available to the user to control other parts of the system. The basic transmission gate functionality is shown in Figure 35. The short-circuit current of the output amplifiers can be programmed by inserting an external resistor between the ISCC pin and PGND. The programmable range for the current is 500 μA to 10 mA, corresponding to a resistor range of 120 kΩ to 6 kΩ. The resistor value is calculated as follows: RSTOUT RSTIN VOLTAGE MONITOR AND CONTROL G1 VOUTA AGNDA 05303-063 G2 R= 60 I SC If the ISCC pin is left unconnected, the short-circuit current limit defaults to 5 mA. Note that limiting the short-circuit current to a small value can affect the slew rate of the output when driving into a capacitive load; therefore, the value of the programmed short circuit should take into account the size of the capacitive load being driven. DIGITAL I/O PORT The AD5764 contains a 2-bit digital I/O port (D1 and D0). These bits can be configured as inputs or outputs independently, and can be driven or have their values read back via the serial interface. The I/O port signals are referenced to DVCC and DGND. When configured as outputs, they can be used as control signals to multiplexers or can be used to control calibration circuitry elsewhere in the system. When configured as inputs, the logic signals from limit switches can, for example, be applied to D0 and D1 and can be read back via the digital interface. LOCAL GROUND OFFSET ADJUST Figure 35. Analog Output Control Circuitry DIGITAL OFFSET AND GAIN CONTROL The AD5764 incorporates a digital offset adjust function with a ±16 LSB adjust range and 0.125 LSB resolution. The coarse gain register allows the user to adjust the AD5764 full-scale output range. The full-scale output can be programmed to achieve fullscale ranges of ±10 V, ±10.2564 V, and ±10.5263 V. A fine gain trim is also provided. The AD5764 incorporates a local ground offset adjust feature that, when enabled in the function register, adjusts the DAC outputs for voltage differences between the individual DAC ground pins, AGNDx, and the REFGND pin, ensuring that the DAC output voltages are always with respect to the local DAC ground pin. For instance, if Pin AGNDA is at +5 mV with respect to the REFGND pin and VOUTA is measured with respect to AGNDA, a −5 mV error results, enabling the local ground offset adjust feature to adjust VOUTA by +5 mV, eliminating the error. Rev. F | Page 24 of 28 Data Sheet AD5764 APPLICATIONS INFORMATION reference and associated buffers. This leads to an overall savings in both cost and board space. TYPICAL OPERATING CIRCUIT Figure 36 shows the typical operating circuit for the AD5764. The only external components needed for this precision 16-bit DAC are a reference voltage source, decoupling capacitors on the supply pins and reference inputs, and an optional shortcircuit current setting resistor. Because the device incorporates reference buffers, it eliminates the need for an external bipolar In Figure 36, AVDD is connected to +15 V and AVSS is connected to −15 V. However, AVDD can operate with supplies from +11.4 V to +16.5 V and AVSS can operate with supplies from −11.4 V to −16.5 V. +15V ADR02 2 VIN VOUT 6 GND 4 +15V –15V 10µF 10µF 100nF 100nF 100nF BIN/2sCOMP 1 SYNC SCLK 2 SCLK SDIN 3 SDIN SDO 4 SDO REFAB NC REFCD NC AVSS AVDD REFGND SYNC BIN/2sCOMP 32 31 30 29 28 27 26 25 +5V AGNDA 24 VOUTA 23 VOUTA VOUTB 22 VOUTB AGNDB 21 AD5764 AGNDC 20 8 D1 AGNDD 17 NC = NO CONNECT +5V 100nF 10µF +15V –15V Figure 36. Typical Operating Circuit Rev. F | Page 25 of 28 05303-064 10µF 10µF RSTIN 100nF 10 11 12 13 14 15 16 100nF 9 RSTOUT ISCC VOUTD D1 AVSS VOUTD 18 PGND D0 AVDD VOUTC 7 DVCC VOUTC 19 D0 DGND LDAC RSTIN CLR 6 RSTOUT 5 LDAC AD5764 Data Sheet Precision Voltage Reference Selection To achieve the optimum performance from the AD5764 over its full operating temperature range, a precision voltage reference must be used. Consideration should be given to the selection of a precision voltage reference. The AD5764 has two reference inputs, REFAB and REFCD. The voltages applied to the reference inputs are used to provide a buffered positive and negative reference for the DAC cores. Therefore, any error in the voltage reference is reflected in the outputs of the device. There are four possible sources of error to consider when choosing a voltage reference for high accuracy applications: initial accuracy, temperature coefficient of the output voltage, long-term drift, and output voltage noise. Initial accuracy error on the output voltage of an external reference can lead to a full-scale error in the DAC. Therefore, to minimize these errors, a reference with low initial accuracy error specification is preferred. Choosing a reference with an output trim adjustment, such as the ADR425, allows a system designer to trim system errors out by setting the reference voltage to a voltage other than the nominal. The trim adjustment can also be used at temperature to trim out any error. Long-term drift is a measure of how much the reference output voltage drifts over time. A reference with a tight long-term drift specification ensures that the overall solution remains relatively stable over its entire lifetime. The temperature coefficient of a reference output voltage affects INL, DNL, and TUE. Choose a reference with a tight temperature coefficient specification to reduce the dependence of the DAC output voltage on ambient conditions. In high accuracy applications, which have a relatively low noise budget, reference output voltage noise needs to be considered. Choosing a reference with as low an output noise voltage as practical for the system resolution required is important. Precision voltage references such as the ADR435 (XFET® design) produce low output noise in the 0.1 Hz to 10 Hz region. However, as the circuit bandwidth increases, filtering the output of the reference may be required to minimize the output noise. Table 20. Some Precision References Recommended for Use with the AD5764 Part No. ADR435 ADR425 ADR02 ADR395 Initial Accuracy (mV Max) ±2 ±2 ±5 ±5 Long-Term Drift (ppm Typ) 40 50 50 50 Temp Drift (ppm/°C Max) 3 3 3 9 Rev. F | Page 26 of 28 0.1 Hz to 10 Hz Noise (μV p-p Typ) 8 3.4 10 8 Data Sheet AD5764 LAYOUT GUIDELINES The power supply lines of the AD5764 must be as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, such as clocks, must be shielded with digital ground to avoid radiating noise to other parts of the board, and must never be run near the reference inputs. A ground line routed between the SDIN and SCLK lines helps reduce crosstalk between them (not required on a multilayer board, which has a separate ground plane; however, it is helpful to separate the lines). It is essential to minimize noise on the reference inputs because it couples through to the DAC output. Avoid crossover of digital and analog signals. Traces on opposite sides of the board must run at right angles to each other. This reduces the effects of feedthrough on the board. A microstrip technique is recommended, but not always possible with a doublesided board. In this technique, the component side of the board is dedicated to the ground plane, and signal traces are placed on the solder side. GALVANICALLY ISOLATED INTERFACE In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. Isocouplers provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5764 makes it ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 37 shows a 4-channel isolated interface to the AD5764 using an ADuM1400. For more information, go to www.analog.com. MICROCONTROLLER SERIAL CLOCK OUT SERIAL DATA OUT SYNC OUT CONTROL OUT ADuM1400* VIA VIB VIC VID ENCODE ENCODE ENCODE ENCODE DECODE DECODE DECODE DECODE *ADDITIONAL PINS OMITTED FOR CLARITY. VOA VOB VOC VOD TO SCLK TO SDIN TO SYNC TO LDAC 05303-065 In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The PCB on which the AD5764 is mounted must be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5764 is in a system where multiple devices require an AGND-to-DGND connection, the connection is to be made at one point only. The star ground point is established as close as possible to the device. The AD5764 must have ample supply bypassing of 10 μF in parallel with 0.1 μF on each supply, located as close to the package as possible, ideally right up against the device. The 10 μF capacitors are the tantalum bead type. The 0.1 μF capacitor must have low effective series resistance (ESR) and low effective series inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Figure 37. Isolated Interface MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5764 is via a serial bus that uses a standard protocol that is compatible with microcontrollers and DSP processors. The communications channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a synchronization signal. The AD5764 requires a 24-bit data-word with data valid on the falling edge of SCLK. For all the interfaces, the DAC output update can be performed automatically when all the data is clocked in, or it can be done under the control of LDAC. The contents of the data register can be read using the readback function. EVALUATION BOARD The AD5764 comes with a full evaluation board to aid designers in evaluating the high performance of the part with minimum effort. All that is required with the evaluation board is a power supply and a PC. The AD5764 evaluation kit includes a populated, tested AD5764 PCB. The evaluation board interfaces to the USB port of the PC. Software is available with the evaluation board, which allows the user to easily program the AD5764. The software runs on any PC that has Microsoft® Windows® 2000/NT/XP installed. The EVAL-AD5764EB data sheet is available, which gives full details on the operation of the evaluation board. Rev. F | Page 27 of 28 AD5764 Data Sheet OUTLINE DIMENSIONS 0.75 0.60 0.45 1.20 MAX 9.00 BSC SQ 25 32 24 1 PIN 1 7.00 BSC SQ TOP VIEW 0° MIN 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY SEATING PLANE 17 8 9 VIEW A VIEW A 16 0.80 BSC LEAD PITCH ROTATED 90° CCW 0.45 0.37 0.30 COMPLIANT TO JEDEC STANDARDS MS-026-AB A 020607-A 1.05 1.00 0.95 0.15 0.05 (PINS DOWN) Figure 38. 32-Lead Thin Plastic Quad Flat Package [TQFP] (SU-32-2) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5764ASUZ AD5764ASUZ-REEL7 AD5764BSUZ AD5764BSUZ-REEL7 AD5764CSUZ AD5764CSUZ-REEL7 EVAL-AD5764EBZ 1 INL ±4 LSB max ±4 LSB max ±2 LSB max ±2 LSB max ±1 LSB max ±1 LSB max Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Z = RoHS Compliant Part. ©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05303-0-9/11(F) Rev. F | Page 28 of 28 Package Description 32-Lead TQFP 32-Lead TQFP 32-Lead TQFP 32-Lead TQFP 32-Lead TQFP 32-Lead TQFP Evaluation Board Package Option SU-32-2 SU-32-2 SU-32-2 SU-32-2 SU-32-2 SU-32-2