Complete Dual, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC AD5762R FEATURES GENERAL DESCRIPTION Complete dual, 16-bit digital-to-analog converter (DAC) Programmable output range: ±10 V, ±10.2564 V, or ±10.5263 V ±1 LSB maximum INL error, ±1 LSB maximum DNL error Low noise: 60 nV/√Hz Settling time: 10 μs maximum Integrated reference buffers Internal reference: 10 ppm/°C maximum On-chip die temperature sensor Output control during power-up/brownout Programmable short-circuit protection Simultaneous updating via LDAC Asynchronous CLR to zero code Digital offset and gain adjust Logic output control pins DSP-/microcontroller-compatible serial interface Temperature range: −40°C to +85°C iCMOS process technology The AD5762R is a dual, 16-bit, serial input, bipolar voltage output DAC that operates from supply voltages of ±11.4 V to ±16.5 V. Nominal full-scale output range is ±10 V. The AD5762R provides integrated output amplifiers, reference buffers, and proprietary power-up/power-down control circuitry. The part also features a digital I/O port, programmed via the serial interface, and an analog temperature sensor. The part incorporates digital offset and gain adjust registers per channel. APPLICATIONS Industrial automation Open-loop/closed-loop servo control Process control Data acquisition systems Automatic test equipment Automotive test and measurement High accuracy instrumentation The AD5762R is a high performance converter that provides guaranteed monotonicity, integral nonlinearity (INL) of ±1 LSB, low noise, and 10 μs settling time. The AD5762R includes an on-chip 5 V reference with a reference temperature coefficient of 10 ppm/°C maximum. During power-up when the supply voltages are changing, VOUTx is clamped to 0 V via a low impedance path. The AD5764R is based on the iCMOS® technology platform, which is designed for analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels. iCMOS enables the development of analog ICs capable of 30 V and operation at ±15 V supplies, while allowing reductions in power consumption and package size, coupled with increased ac and dc performance. The AD5762R uses a serial interface that operates at clock rates of up to 30 MHz and is compatible with DSP and microcontroller interface standards. Double buffering allows the simultaneous updating of all DACs. The input coding is programmable to either twos complement or offset binary formats. The asynchronous clear function clears all DAC registers to either bipolar zero or zero scale, depending on the coding used. The AD5762R is ideal for both closed-loop servo control and open-loop control applications. The AD5762R is available in a 32-lead TQFP and offers guaranteed specifications over the −40°C to +85°C industrial temperature range (see Figure 1 for the functional block diagram). Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. AD5762R TABLE OF CONTENTS Features .............................................................................................. 1 Function Register ....................................................................... 24 Applications ....................................................................................... 1 Data Register ............................................................................... 25 General Description ......................................................................... 1 Coarse Gain Register ................................................................. 25 Revision History ............................................................................... 2 Fine Gain Register ...................................................................... 25 Functional Block Diagram .............................................................. 3 Offset Register ............................................................................ 26 Specifications..................................................................................... 4 Offset and Gain Adjustment Worked Example ......................... 26 AC Performance Characteristics ................................................ 6 Design Features ............................................................................... 27 Timing Characteristics ................................................................ 7 Analog Output Control ............................................................. 27 Absolute Maximum Ratings.......................................................... 10 Digital Offset and Gain Control ............................................... 27 Thermal Resistance .................................................................... 10 Programmable Short-Circuit Protection ................................ 27 ESD Caution ................................................................................ 10 Digital I/O Port ........................................................................... 27 Pin Configuration and Function Descriptions ........................... 11 Die Temperature Sensor ............................................................ 27 Typical Performance Characteristics ........................................... 13 Local Ground Offset Adjust ...................................................... 27 Terminology .................................................................................... 19 Applications Information .............................................................. 28 Theory of Operation ...................................................................... 21 Typical Operating Circuit ......................................................... 28 DAC Architecture ....................................................................... 21 Layout Guidelines ........................................................................... 30 Reference Buffers ........................................................................ 21 Galvanically Isolated Interface ................................................. 30 Serial Interface ............................................................................ 21 Microprocessor Interfacing ....................................................... 30 Simultaneous Updating via LDAC ........................................... 22 Evaluation Board ........................................................................ 31 Transfer Function ....................................................................... 23 Outline Dimensions ....................................................................... 32 Asynchronous Clear (CLR) ....................................................... 23 Ordering Guide .......................................................................... 32 Registers ........................................................................................... 24 REVISION HISTORY 12/08—Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD5762R FUNCTIONAL BLOCK DIAGRAM AVDD AVSS AVDD AVSS DVCC DGND AD5762R SCLK SYNC SDO INPUT SHIFT REGISTER AND CONTROL LOGIC REFGND 5V REFERENCE 16 SDIN REFOUT INPUT REG A REFERENCE BUFFERS DAC REG A RSTOUT REFA VOLTAGE MONITOR AND CONTROL 16 ISCC G1 DAC A VOUTA G2 GAIN REG A AGNDA OFFSET REG A INPUT REG B DAC REG B 16 G1 DAC B VOUTB D0 D1 RSTIN G2 GAIN REG B AGNDB OFFSET REG B BIN/2sCOMP REFERENCE BUFFERS TEMP SENSOR REFB TEMP CLR LDAC Figure 1. Rev. 0 | Page 3 of 32 07248-001 PGND AD5762R SPECIFICATIONS AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFA = REFB = 5 V external; DVCC 1 = 2.7 V to 5.25 V, RLOAD = 10 kΩ, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter ACCURACY Resolution Relative Accuracy (INL) Differential Nonlinearity (DNL) Bipolar Zero Error Bipolar Zero Tempco 3 Zero-Scale Error Zero-Scale Tempco3 Gain Error Gain Tempco3 DC Crosstalk3 REFERENCE INPUT/OUTPUT Reference Input3 Reference Input Voltage DC Input Impedance Input Current Reference Range Reference Output Output Voltage Reference Tempco3 RLOAD3 Power Supply Sensitivity3 Output Noise3 Noise Spectral Density3 Output Voltage Drift vs. Time3 Min Unit 16 −1 −1 −2 +1 +1 +2 Bits LSB LSB mV −3 −2 −2 +3 +2 +2 mV ppm FSR/°C mV −2.5 −2 −0.02 −2 +2.5 +2 +0.02 +2 0.5 mV ppm FSR/°C % FSR ppm FSR/°C LSB ±1% for specified performance +10 7 V MΩ μA V V ppm/°C MΩ μV/V μV p-p nV/√Hz ppm/500 hr ppm/1000 hr ppm ppm 25°C, AVDD/AVSS = ±13.5 V 4.995 −10 1 5 100 ±0.03 5 ±1.7 5.005 +10 300 18 75 ±40 ±50 70 30 Thermal Hysteresis3 OUTPUT CHARACTERISTICS3 Output Voltage Range 4 −10.5263 −14.7368 Output Voltage Drift vs. Time +10.5263 +14.7368 +1 V V ppm FSR/ 500 hr ppm FSR/ 1000 hr mA mA 200 1000 0.3 pF pF Ω ±13 ±15 Short-Circuit Current Load Current Capacitive Load Stability RLOAD = ∞ RLOAD = 10 kΩ DC Output Impedance Test Conditions/Comments 2 Outputs unloaded Max 1 −10 1 Typ 10 −1 Rev. 0 | Page 4 of 32 Guaranteed monotonic 25°C; error at other temperatures obtained using bipolar zero tempco 25°C; error at other temperatures obtained using zero-scale tempco 0.1 Hz to 10 Hz 10 kHz First temperature cycle Subsequent temperature cycles AVDD/AVSS = ±11.4 V, REFA = REFB = 5 V AVDD/AVSS = ±16.5 V, REFA = REFB = 7 V RISCC = 6 kΩ, see Figure 31 For specified performance AD5762R Parameter DIGITAL INPUTS3 Input High Voltage, VIH Input Low Voltage, VIL Input Current Pin Capacitance DIGITAL OUTPUTS (D0, D1, SDO)1,3 Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance DIE TEMPERATURE SENSOR3 Output Voltage at 25°C Output Voltage Scale Factor Output Voltage Range Output Load Current Power-On Time POWER REQUIREMENTS AVDD AVSS DVCC1 Power Supply Sensitivity3 ∆VOUT/∆ΑVDD AIDD AISS DICC Power Dissipation Min Typ Unit 0.8 +1.2 10 V V μA pF Per pin Per pin V V V V μA pF DVCC = 5 V ± 5%, sinking 200 μA DVCC = 5 V ± 5%, sourcing 200 μA DVCC = 2.7 V to 3.6 V, sinking 200 μA DVCC = 2.7 V to 3.6 V, sourcing 200 μA SDO only SDO only V mV/°C V μA ms Die temperature 2.4 −1.2 0.4 DVCC − 1 0.4 DVCC − 0.5 −1 +1 5 1.47 5 1.175 1.9 200 80 +11.4 −16.5 2.7 Test Conditions/Comments 2 DVCC = 2.7 V to 5.25 V Max +16.5 −11.4 5.25 −85 4.25 3.9 1.2 180 1 −40°C to +105°C Current source only V V dB mA/channel mA/channel mA mW Outputs unloaded Outputs unloaded VIH = DVCC, VIL = DGND, 750 μA typ ±12 V operation output unloaded To guarantee a successful readback operation over the full operating temperature range, DVCC must be restricted to within a range of 2.7 V to 3.63 V. Temperature range: −40°C to +85°C; typical at +25°C. Device functionality is guaranteed to +105°C with degraded performance. 3 Guaranteed by design and characterization; not production tested. 4 Output amplifier headroom requirement is 1.4 V minimum. 2 Rev. 0 | Page 5 of 32 AD5762R AC PERFORMANCE CHARACTERISTICS AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFA, REFB= 5 V external; DVCC 1 = 2.7 V to 5.25 V, RLOAD = 10 kΩ, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE 2 Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Channel-to-Channel Isolation DAC-to-DAC Crosstalk Digital Crosstalk Digital Feedthrough Output Noise (0.1 Hz to 10 Hz) Output Noise (0.1 Hz to 100 kHz) 1/f Corner Frequency Output Noise Spectral Density Complete System Output Noise Spectral Density 3 Min Typ Max Unit Test Conditions/Comments 8 2 5 8 10 μs μs V/μs nV-sec mV dB nV-sec nV-sec nV-sec Full-scale step to ±1 LSB 512 LSB step settling 25 80 8 2 2 0.1 45 1 60 80 1 LSB p-p μV rms kHz nV/√Hz nV/√Hz Effect of input bus activity on DAC outputs Measured at 10 kHz Measured at 10 kHz To guarantee a successful readback operation over the full operating temperature range, DVCC must be restricted to within a range of 2.7 V to 3.63 V. Guaranteed by design and characterization; not production tested. 3 Includes noise contributions from integrated reference buffers,16-bit DAC, and output amplifier. 2 Rev. 0 | Page 6 of 32 AD5762R TIMING CHARACTERISTICS AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFA = REFB = 5 V external; DVCC 1 = 2.7 V to 5.25 V, RLOAD = 10 kΩ, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter 2, 3, 4 t1 t2 t3 t4 t5 5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 6, 7 t16 t17 t18 Limit at TMIN, TMAX 33 13 13 13 13 40 2 5 1.7 480 10 500 10 10 2 25 13 2 170 Unit ns min ns min ns min ns min ns min ns min ns min ns min μs min ns min ns min ns max μs max ns min μs max ns max ns min μs max ns min Description SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time 24th SCLK falling edge to SYNC rising edge Minimum SYNC high time Data setup time Data hold time SYNC rising edge to LDAC falling edge (all DACs updated) SYNC rising edge to LDAC falling edge (single DAC updated) LDAC pulse width low LDAC falling edge to DAC output response time DAC output settling time CLR pulse width low CLR pulse activation time SCLK rising edge to SDO valid SYNC rising edge to SCLK falling edge SYNC rising edge to DAC output response time (LDAC = 0) LDAC falling edge to SYNC rising edge 1 To guarantee a successful readback operation over the full operating temperature range, DVCC must be restricted to within a range of 2.7 V to 3.63 V. Guaranteed by design and characterization; not production tested. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 4 See Figure 2, Figure 3, and Figure 4. 5 Standalone mode only. 6 Measured with the load circuit of Figure 5. 7 Daisy-chain mode only. 2 3 Rev. 0 | Page 7 of 32 AD5762R Timing Diagrams t1 SCLK 1 2 24 t3 t6 t2 t4 t5 SYNC t8 t7 SDIN DB23 DB0 t10 t9 LDAC t10 t18 t12 t11 VOUTA/ VOUTB LDAC = 0 t12 t17 VOUTA/ VOUTB t13 CLR t14 07248-002 VOUTA/ VOUTB Figure 2. Serial Interface Timing Diagram t1 SCLK 24 t3 t6 48 t2 t5 t16 t4 SYNC t7 SDIN t8 DB23 DB0 INPUT WORD FOR DAC N DB23 DB0 t15 INPUT WORD FOR DAC N – 1 DB23 SDO UNDEFINED DB0 INPUT WORD FOR DAC N t9 t10 07248-003 LDAC Figure 3. Daisy-Chain Timing Diagram Rev. 0 | Page 8 of 32 AD5762R SCLK 24 48 SYNC DB0 DB23 DB0 NOP CONDITION INPUT WORD SPECIFIES REGISTER TO BE READ DB23 SDO UNDEFINED DB0 SELECTED REGISTER DATA CLOCKED OUT Figure 4. Readback Timing Diagram 200µA TO OUTPUT PIN IOL VOH (MIN) OR VOL (MAX) CL 50pF 200µA IOH Figure 5. Load Circuit for SDO Timing Diagram Rev. 0 | Page 9 of 32 07248-004 DB23 07248-005 SDIN AD5762R ABSOLUTE MAXIMUM RATINGS TA = 25°C unless, otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 4. Parameter AVDD to AGND, DGND AVSS to AGND, DGND DVCC to DGND Digital Inputs to DGND Digital Outputs to DGND REFx to AGND, PGND REFOUT to AGND TEMP VOUTx to AGND AGND to DGND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) Lead Temperature (Soldering) Rating −0.3 V to +17 V +0.3 V to −17 V −0.3 V to +7 V −0.3 V to (DVCC + 0.3 V) or +7 V, whichever is less −0.3 V to DVCC + 0.3 V −0.3 V to AVDD + 0.3 V AVSS to AVDD AVSS to AVDD AVSS to AVDD −0.3 V to +0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance Package Type 32-Lead TQFP ESD CAUTION −40°C to +85°C −65°C to +150°C 150°C JEDEC Industry Standard J-STD-020 Rev. 0 | Page 10 of 32 θJA 65 θJC 12 Unit °C/W AD5762R REFA REFB REFOUT REFGND TEMP AVSS AVDD BIN/2sCOMP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 32 31 30 29 28 27 26 25 24 NC 23 NC 22 VOUTA 21 AGNDA 20 AGNDB LDAC 6 19 VOUTB D0 7 18 NC D1 8 17 NC SYNC 1 PIN 1 SDIN 3 AD5762R SDO 4 TOP VIEW (Not to Scale) CLR 5 ISCC AVSS PGND AVDD DVCC DGND 10 11 12 13 14 15 16 RSTIN RSTOUT 9 NC = NO CONNECT 07248-006 SCLK 2 Figure 6. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 Mnemonic SYNC 2 SCLK 3 4 5 6 SDIN SDO CLR LDAC 7, 8 D0, D1 9 RSTOUT 10 RSTIN 11 12 13, 31 14 15, 30 16 DGND DVCC AVDD PGND AVSS ISCC 17 18 19 NC NC VOUTB 20 21 AGNDB AGNDA Description Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in on the falling edge of SCLK. Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds of up to 30 MHz. Serial Data Input. Data must be valid on the falling edge of SCLK. Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Negative Edge Triggered Input. 1 Asserting this pin sets the DAC registers to 0x0000. Load DAC. This logic input is used to update the DAC registers and, consequently, the analog outputs. When tied permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the DAC input register is updated, but the output update is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. The LDAC pin must not be left unconnected. Digital I/O Port. D0 and D1 form a digital I/O port. The user can set up these pins as inputs or outputs that are configurable and readable over the serial interface. When configured as inputs, these pins have weak internal pull-ups to DVCC. When programmed as outputs, D0 and D1 are referenced by DVCC and DGND. Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. If desired, it can be used to control other system components. Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to this input clamps the DAC outputs to 0 V. In normal operation, RSTIN should be tied to Logic 1. Register values remain unchanged. Digital Ground Pin. Digital Supply Pin. Voltage ranges from 2.7 V to 5.25 V. Positive Analog Supply Pins. Voltage ranges from 11.4 V to 16.5 V. Ground Reference Point for Analog Circuitry. Negative Analog Supply Pins. Voltage ranges from –11.4 V to –16.5 V. This pin is used in association with an optional external resistor to AGND to program the short-circuit current of the output amplifiers. Refer to the Design Features section for more information. Do not connect to this pin. Do not connect to this pin. Analog Output Voltage of DAC B. Buffered output with a nominal full-scale output range of ±10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load. Ground Reference Pin for DAC B Output Amplifier. Ground Reference Pin for DAC A Output Amplifier. Rev. 0 | Page 11 of 32 AD5762R Pin No. 22 Mnemonic VOUTA 23 24 25 NC NC REFA 26 REFB 27 REFOUT 28 29 REFGND TEMP 32 BIN/2sCOMP 1 Description Analog Output Voltage of DAC A. Buffered output with a nominal full-scale output range of ±10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load. Do not connect to this pin. Do not connect to this pin. External Reference Voltage. The reference input range is 1 V to 7 V, and it programs the full-scale output voltage. REFA = 5 V for specified performance. External Reference Voltage. The reference input range is 1 V to 7 V, and it programs the full-scale output voltage. REFB = 5 V for specified performance. Reference Output. This is the reference output from the internal voltage reference. The internal reference is 5 V ± 3 mV at 25°C, with a reference temperature coefficient of 10 ppm/°C. Reference Ground Return for the Reference Generator and Buffers. This pin provides an output voltage proportional to temperature. The output voltage is 1.47 V typical at 25°C die temperature; variation with temperature is 5 mV/°C. This pin determines the DAC coding. This pin should be hardwired to either DVCC or DGND. When hardwired to DVCC, input coding is offset binary (see Table 7). When hardwired to DGND, input coding is twos complement (see Table 8). Internal pull-up device on this logic input. Therefore, it can be left floating and defaults to a logic high condition. Rev. 0 | Page 12 of 32 AD5762R TYPICAL PERFORMANCE CHARACTERISTICS 0.8 0.6 0.4 0.4 DNL ERROR (LSB) 0.6 0.2 0 –0.2 –0.4 0 –0.2 –0.4 –0.6 –0.8 –0.8 0 10,000 20,000 30,000 40,000 50,000 60,000 DAC CODE –1.0 0 10,000 20,000 30,000 40,000 50,000 60,000 DAC CODE Figure 7. Integral Nonlinearity Error vs. DAC Code, VDD/VSS = ±15 V Figure 10. Differential Nonlinearity Error vs. DAC Code, VDD/VSS = ±12 V 0.5 1.0 TA = 25°C 0.8 VDD/VSS = ±12V REFIN = 5V 0.6 0.4 0.4 0.3 INL ERROR (LSB) INL ERROR (LSB) 0.2 –0.6 –1.0 TA = 25°C VDD/VSS = ±12V REFIN = 5V 0.8 07248-007 INL ERROR (LSB) 1.0 TA = 25°C VDD/VSS = ±15V REFIN = 5V 07248-012 1.0 0.2 0 –0.2 –0.4 VDD/VSS = ±15V REFIN = 5V 0.2 0.1 0 –0.6 –0.1 0 10,000 20,000 30,000 40,000 50,000 60,000 DAC CODE –0.2 –40 07248-008 –1.0 40 60 80 100 0.5 VDD/VSS = ±12V REFIN = 5V 0.4 0.6 INL ERROR (LSB) 0.4 0.2 0 –0.2 –0.4 –0.6 0.3 0.2 0.1 0 –1.0 0 10,000 20,000 30,000 40,000 50,000 60,000 DAC CODE Figure 9. Differential Nonlinearity Error vs. DAC Code, VDD/VSS = ±15 V –0.1 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 12. Integral Nonlinearity Error vs. Temperature, VDD/VSS = ±12 V Rev. 0 | Page 13 of 32 100 07248-016 –0.8 07248-011 DNL ERROR (LSB) 20 Figure 11. Integral Nonlinearity Error vs. Temperature, VDD/VSS = ±15 V TA = 25°C VDD/VSS = ±15V REFIN = 5V 0.8 0 TEMPERATURE (°C) Figure 8. Integral Nonlinearity Error vs. DAC Code, VDD/VSS = ±12 V 1.0 –20 07248-015 –0.8 0.15 0.15 0.10 0.10 0.05 0.05 DNL ERROR (LSB) 0 –0.05 –0.10 –0.15 0 –0.05 –0.10 –0.15 –0.20 –0.20 VDD/VSS = ±15V REFIN = 5V –20 0 20 40 60 80 100 TEMPERATURE (°C) –0.25 11.4 07248-019 –0.25 –40 TA = 25°C REFIN = 5V 12.4 13.4 14.4 15.4 16.4 SUPPLY VOLTAGE (V) Figure 13. Differential Nonlinearity Error vs. Temperature, VDD/VSS = ±15 V 07248-025 DNL ERROR (LSB) AD5762R Figure 16. Differential Nonlinearity Error vs. Supply Voltage 0.15 0.8 0.10 0.6 TA = 25°C 0.4 INL ERROR (LSB) 0 –0.05 –0.10 –0.15 –0.4 20 40 60 80 100 –1.0 1 2 3 4 5 6 7 REFERENCE VOLTAGE (V) 07248-027 0 07248-020 –20 Figure 14. Differential Nonlinearity Error vs. Temperature, VDD/VSS = ±12 V Figure 17. Integral Nonlinearity Error vs. Reference Voltage, VDD/VSS = ±16.5 V 0.4 0.5 TA = 25°C REFIN = 5V TA = 25°C 0.3 0.4 0.2 DNL ERROR (LSB) 0.3 0.2 0.1 0 0.1 0 –0.1 –0.2 –0.1 –0.3 12.4 13.4 14.4 15.4 SUPPLY VOLTAGE (V) 16.4 07248-023 INL ERROR (LSB) –0.2 –0.8 VDD/VSS = ±12V REFIN = 5V TEMPERATURE (°C) –0.2 11.4 0 –0.6 –0.20 –0.25 –40 0.2 –0.4 1 2 3 4 5 6 7 REFERENCE VOLTAGE (V) Figure 18. Differential Nonlinearity Error vs. Reference Voltage, VDD/VSS = ±16.5 V Figure 15. Integral Nonlinearity Error vs. Supply Voltage Rev. 0 | Page 14 of 32 07248-031 DNL ERROR (LSB) 0.05 AD5762R 0.6 0.8 TA = 25°C 0.4 REFIN = 5V BIPOLAR ZERO ERROR (mV) 0 –0.2 TUE (mV) VDD/VSS = ±15V 0.6 0.2 –0.4 –0.6 –0.8 –1.0 –1.2 0.4 VDD/VSS = ±12V 0.2 0 –0.2 1 2 3 4 5 6 7 REFERENCE VOLTAGE (V) –0.4 –40 07248-035 –1.6 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 19. Total Unadjusted Error vs. Reference Voltage, VDD/VSS = ±16.5 V 07248-039 –1.4 Figure 22. Bipolar Zero Error vs. Temperature 1.4 9.0 REFIN = 5V 8.5 1.2 8.0 GAIN ERROR (mV) 7.0 6.5 6.0 |ISS| 5.5 VDD/VSS = ±12V 0.8 0.6 0.4 VDD/VSS = ±15V 0.2 5.0 12.4 13.4 14.4 15.4 16.4 VDD/VSS (V) –0.2 –40 07248-037 4.0 11.4 –20 100 5V 0.0012 VDD/VSS = ±12V 0.10 0.0011 DICC (mA) 0.05 0 –0.05 –0.10 0.0010 0.0009 0.0008 –0.15 3V 0.0007 –0.20 –20 0 20 40 60 80 TEMPERATURE (°C) 100 07248-038 ZERO-SCALE ERROR (mV) 80 0.0013 0.15 –0.25 –40 60 TA = 25°C VDD/VSS = ±15V 0.20 40 Figure 23. Gain Error vs. Temperature 0.0014 REFIN = 5V 20 TEMPERATURE (°C) Figure 20. IDD/ISS vs. VDD/VSS 0.25 0 07248-040 0 4.5 0.0006 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VLOGIC (V) Figure 24. DICC vs. Logic Input Voltage Figure 21. Zero-Scale Error vs. Temperature Rev. 0 | Page 15 of 32 4.5 5.0 07248-041 IDD/ISS (mA) 1.0 |IDD| 7.5 AD5762R –6 5000 VDD/VSS = ±15V –8 VDD/VSS = ±12V –10 –12 4000 VOUT (mV) 3000 2000 –14 –16 –18 –20 1000 0 –5 0 5 07248-042 –24 –1000 –10 10 SOURCE/SINK CURRENT (mA) Figure 25. Source and Sink Capability of Output Amplifier with Positive Full Scale Loaded –26 –2.0–1.5–1.0–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 TIME (µs) Figure 28. Major Code Transition Glitch Energy, VDD/VSS = ±12 V 10,000 VDD/VSS = ±15V MIDSCALE LOADED REFIN = 0V TA = 25°C 9000 REFIN = 5V 8000 VDD/VSS = ±15V 7000 6000 VDD/VSS = ±12V 5000 4 4000 3000 2000 0 50µV/DIV –7 –2 3 CH4 50.0µV 07248-043 –1000 –12 8 SOURCE/SINK CURRENT (mA) M1.00s CH4 26µV 07248-048 1000 Figure 29. Peak-to-Peak Noise (100 kHz Bandwidth) Figure 26. Source and Sink Capability of Output Amplifier with Negative Full Scale Loaded T VDD/VSS = ±15V TA = 25°C REFIN = 5V VDD/VSS = ±12V, REFIN = 5V, TA = 25°C, RAMP TIME = 100µs, LOAD = 200pF||10kΩ 1 2 3 1 1µs/DIV CH1 3.00V M1.00µs CH1 –120mV 07248-044 OUTPUT VOLTAGE DELTA (µV) VDD/VSS = ±12V, REFIN = 5V, TA = 25°C, 0x8000 TO 0x7FFF, 500ns/DIV –22 Figure 27. Full-Scale Settling Time CH1 10.0V BW CH2 10.0V M100µs CH3 10.0mV BW T 29.60% A CH1 Figure 30. VOUTx vs. VDD/VSS on Power-Up Rev. 0 | Page 16 of 32 7.80mV 07248-055 OUTPUT VOLTAGE DELTA (µV) 6000 –4 TA = 25°C REFIN = 5V 07248-047 7000 AD5762R 10 VDD/VSS = ±12V TA = 25°C VDD/VSS = ±15V TA = 25°C REFIN = 5V 9 SHORT-CIRCUIT CURRENT (mA) 8 7 6 1 5 4 3 1 5µV/DIV 40 60 80 100 120 RISCC (kΩ) M1.00s Figure 31. Short-Circuit Current vs. RISCC T 6 REFERENCE OUTPUT VOLTAGE (V) TA = 25°C VDD/VSS = ±15V 1 2 3 T 29.60% A CH1 7.80mV 5 4 3 2 1 0 07248-054 M400µs CH3 5.00V BW 0 40 60 80 100 120 140 1.9 TEMPERATURE OUTPUT VOLTAGE (V) 50µV/DIV 15µV 07248-052 1 A CH1 160 180 200 Figure 35. REFOUT Load Regulation VDD/VSS = ±12V TA = 25°C, 10µF CAPACITOR ON REFOUT M1.00s 20 LOAD CURRENT (µA) Figure 32. REFOUT Turn-On Transient CH1 50.0µV 18mV Figure 34. REFOUT Output Noise, 0.1 Hz to 10 Hz VDD/VSS = ±12V TA = 25°C CH1 10.0V BW CH2 10.0V A CH1 07248-032 20 TA = 25°C VDD/VSS = ±15V 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 33. REFOUT Output Noise, 100 kHz Bandwidth Figure 36. Temperature Output Voltage vs. Temperature Rev. 0 | Page 17 of 32 07248-033 0 07248-050 0 07248-053 2 AD5762R 40 20 DEVICES SHOWN MAX: 10ppm/°C TYP: 1.7ppm/°C 35 5.002 30 POPULATION (%) 5.001 5.000 4.999 25 20 15 10 4.998 4.997 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 Figure 37. Reference Output Voltage vs. Temperature 0 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 TEMPERATURE DRIFT (ppm/°C) Figure 38. Reference Output Temperature Drift (−40°C to +85°C) Rev. 0 | Page 18 of 32 07248-072 5 07248-070 REFERENCE OUTPUT VOLTAGE (V) 5.003 AD5762R TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Total Unadjusted Error (TUE) A measure of the output error, considering all the various errors. Figure 19 shows a plot of total unadjusted error vs. reference voltage. Differential Nonlinearity (DNL) The difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic. Zero-Scale Error Temperature Coefficient A measure of the change in zero-scale error with a change in temperature. It is expressed as parts per million of full-scale range per degree Celsius (ppm FSR/°C). Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5744R is monotonic over its full operating temperature range. Bipolar Zero Error The deviation of the analog output from the ideal half-scale output of 0 V when the DAC register is loaded with 0x8000 (offset binary coding) or 0x0000 (twos complement coding). Figure 22 shows a plot of bipolar zero error vs. temperature. Bipolar Zero Temperature Coefficient The measure of the change in the bipolar zero error with a change in temperature. It is expressed as parts per million of full-scale range per degree Celsius (ppm FSR/°C). Full-Scale Error The measure of the output error when full-scale code is loaded to the DAC register. Ideally, the output voltage should be 2 × VREFIN − 1 LSB. Full-scale error is expressed as a percentage of full-scale range (% FSR). Gain Error Temperature Coefficient A measure of the change in gain error with changes in temperature. It is expressed as parts per million of full-scale range per degree Celsius (ppm FSR/°C). Digital-to-Analog Glitch Energy The impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nanovolt-seconds (nV-sec) and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000), as seen in Figure 28. Digital Feedthrough A measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nanovolt-seconds (nV-sec) and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s, and vice versa. Power Supply Sensitivity Indicates how the output of the DAC is affected by changes in the power supply voltage. Negative Full-Scale Error/Zero-Scale Error The error in the DAC output voltage when 0x0000 (offset binary coding) or 0x8000 (twos complement coding) is loaded to the DAC register. Ideally, the output voltage should be −2 × VREFIN. Figure 21 shows a plot of zero-scale error vs. temperature. DC Crosstalk The dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a fullscale output change on one DAC while monitoring another DAC, and is expressed in least significant bits (LSBs). Output Voltage Settling Time The amount of time it takes for the output to settle to a specified level for a full-scale input change. DAC-to-DAC Crosstalk The glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (from all 0s to all 1s, and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nanovolt-seconds (nV-sec). Slew Rate A limitation in the rate of change of the output voltage. The output slewing speed of a voltage-output DAC is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is given in volts per microsecond (V/μs). Gain Error A measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed as a percentage of the full-scale range (% FSR). Figure 23 shows a plot of gain error vs. temperature. Channel-to-Channel Isolation The ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of another DAC. It is measured in decibels (dB). Reference Temperature Coefficient A measure of the change in the reference output voltage with a change in temperature. It is expressed in parts per million per degree Celsius (ppm/°C). Rev. 0 | Page 19 of 32 AD5762R Digital Crosstalk A measure of the impulse injected into the analog output of one DAC from the digital inputs of another DAC but is measured when the DAC output is not updated. It is specified in nanovoltseconds (nV-sec) and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s, and vice versa. Thermal Hysteresis The change of reference output voltage after the device is cycled through temperatures from −40°C to +85°C and back to −40°C. This is a typical value from a sample of parts put through such a cycle. Rev. 0 | Page 20 of 32 AD5762R THEORY OF OPERATION The AD5762R is a dual, 16-bit, serial input, bipolar voltage output DAC that operates from supply voltages of ±11.4 V to ±16.5 V and has a buffered output voltage of up to ±10.5263 V. Data is written to the AD5762R in a 24-bit word format via a 3-wire serial interface. The AD5762R also offers an SDO pin that is available for daisy chaining or readback. SERIAL INTERFACE The AD5762R incorporates a power-on reset circuit that ensures that the DAC registers are loaded with 0x0000 on power-up. The AD5762R features a digital I/O port that can be programmed via the serial interface, an analog die temperature sensor, on-chip 10 ppm/°C voltage reference, on-chip reference buffers, and per channel digital gain and offset registers. The input shift register is 24 bits wide. Data is loaded into the device, MSB first, as a 24-bit word under the control of a serial clock input, SCLK. The input register consists of a read/write bit, a reserved bit that must be set to 0, three register select bits, three DAC address bits, and 16 data bits, as shown in Table 9. The timing diagram for this operation is shown in Figure 2. DAC ARCHITECTURE Upon power-up, the DAC registers are loaded with zero code (0x0000), and the outputs are clamped to 0 V via a low impedance path. The outputs can be updated with the zero code value by asserting either LDAC or CLR. The corresponding output voltage depends on the state of the BIN/2sCOMP pin. If the BIN/2sCOMP pin is tied to DGND, the data coding is twos complement and the outputs update to 0 V. If the BIN/2sCOMP pin is tied to DVCC, the data coding is offset binary and the outputs update to negative full scale. To have the outputs power-up with zero code loaded to the outputs, the CLR pin should be held low during power-up. The DAC architecture of the AD5762R consists of a 16-bit current mode segmented R-2R DAC. The simplified circuit diagram for the DAC section is shown in Figure 39. R VREF 2R E15 E14 2R 2R E1 R 2R S11 R 2R S10 2R 2R R/8 S0 IOUT Input Shift Register Standalone Operation VOUTx 07248-060 AGNDx 4 MSBs DECODED INTO 15 EQUAL SEGMENTS The AD5762R is controlled over a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with SPI, QSPI™, MICROWIRE™, and DSP standards. 12-BIT, R-2R LADDER Figure 39. DAC Ladder Structure The four MSBs of the 16-bit data-word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of the 15 matched resistors to either AGNDx or IOUT. The remaining 12 bits of the data-word drive Switch S0 to Switch S11 of the 12-bit R-2R ladder network. REFERENCE BUFFERS The AD5762R can operate with either an external or an internal reference. The reference inputs (REFA and REFB) have an input range up to 7 V. This input voltage is then used to provide a buffered positive and negative reference for the DAC cores. The positive reference is given by The serial interface works with both a continuous and noncontinuous serial clock. A continuous SCLK source can be used only if SYNC is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used and SYNC must be taken high after the final clock to latch the data. The first falling edge of SYNC starts the write cycle. Exactly 24 falling clock edges must be applied to SCLK before SYNC is brought high again. If SYNC is brought high before the 24th falling SCLK edge, the data written is invalid. If more than 24 falling SCLK edges are applied before SYNC is brought high, the input data is also invalid. The input register addressed is updated on the rising edge of SYNC. For another serial transfer to take place, SYNC must be brought low again. After the end of the serial data transfer, data is automatically transferred from the input shift register to the addressed register. When the data has been transferred into the chosen register of the addressed DAC, all DAC registers and outputs can be updated by taking LDAC low. +VREF = 2 × VREFIN The negative reference to the DAC cores is given by −VREF = −2 × VREFIN These positive and negative reference voltages (along with the gain register values) define the output ranges of the DACs. Rev. 0 | Page 21 of 32 AD5762R A continuous SCLK source can be used only if SYNC is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and SYNC must be taken high after the final clock to latch the data. AD5762R* 68HC11* MOSI SDIN SCK SCLK PC7 SYNC PC6 LDAC MISO Readback Operation SDO Before a readback operation is initiated, the SDO pin must be enabled by writing to the function register and clearing the SDO disable bit; this bit is cleared by default. Readback mode is invoked by setting the R/W bit = 1 in the serial input register write. With R/W = 1, Bit A2 to Bit A0, in association with Bit REG2, Bit REG1, and Bit REG0, select the register to be read. The remaining data bits in the write sequence are don’t care. During the next SPI write, the data appearing on the SDO output contains the data from the previously addressed register. For a read of a single register, the NOP command can be used in clocking out the data from the selected register on SDO. The readback diagram in Figure 4 shows the readback sequence. For example, to read back the fine gain register of Channel A on the AD5762R, implement the following sequence: SDIN AD5762R* SCLK SYNC LDAC SDO SDIN AD5762R* SCLK SYNC LDAC 1. *ADDITIONAL PINS OMITTED FOR CLARITY. 07248-061 SDO Figure 40. Daisy-Chaining the AD5762R 2. Daisy-Chain Operation For systems that contain several devices, the SDO pin can be used to daisy-chain several devices together. This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. The first falling edge of SYNC starts the write cycle. The SCLK is continuously applied to the input shift register when SYNC is low. If more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting the SDO of the first device to the SDIN input of the next device in the chain, a multidevice interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24n, where n is the total number of AD5762R devices in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register. The serial clock can be a continuous or a gated clock. Write 0xA0XXXX to the input register. This write configures the AD5762R for read mode with the fine gain register of Channel A selected. Note that all of the data bits, DB15 to DB0, are don’t care. Follow with a second write: an NOP condition, 0x00XXXX. During this write, the data from the fine gain register is clocked out on the SDO line; that is, data clocked out contains the data from the fine gain register in Bit DB5 to Bit DB0. SIMULTANEOUS UPDATING VIA LDAC Depending on the status of both SYNC and LDAC, and after data has been transferred into the input register of the DACs, there are two ways to update the DAC registers and DAC outputs. Individual DAC Updating In this mode, LDAC is held low while data is being clocked into the input shift register. The addressed DAC output is updated on the rising edge of SYNC. Simultaneous Updating of All DACs In this mode, LDAC is held high while data is being clocked into the input shift register. All DAC outputs are updated by taking LDAC low any time after SYNC has been taken high. The update then occurs on the falling edge of LDAC. Rev. 0 | Page 22 of 32 AD5762R See Figure 41 for a simplified block diagram of the DAC load circuitry. The output voltage expression for the AD5762R is given by ⎡ D ⎤ VOUT = −2 × VREFIN + 4 × VREFIN ⎢ ⎥ ⎣ 65,536 ⎦ OUTPUT I/V AMPLIFIER 16-BIT DAC REFA, REFB VOUTx where: D is the decimal equivalent of the code loaded to the DAC. VREFIN is the reference voltage applied at the REFA, REFB pins. DAC REGISTER LDAC ASYNCHRONOUS CLEAR (CLR) SCLK SYNC SDIN INTERFACE LOGIC SDO 07248-062 INPUT REGISTER Figure 41. Simplified Serial Interface of Input Loading Circuitry for One DAC Channel TRANSFER FUNCTION Table 7 and Table 8 show the ideal input code to output voltage relationship for both offset binary data coding and twos complement data coding, respectively. CLR is a negative edge triggered clear that allows the outputs to be cleared to either 0 V (twos complement coding) or negative full scale (offset binary coding). It is necessary to maintain CLR low for a minimum amount of time (see Figure 2) for the operation to complete. When the CLR signal is returned high, the output remains at the cleared value until a new value is programmed. If CLR is at 0 V at power-on, all DAC outputs are updated with the clear value. A clear can also be initiated through software by writing the command of 0x04XXXX to the AD5762R. Table 7. Ideal Output Voltage to Input Code Relationship—Offset Binary Data Coding Digital Input MSB 1111 1000 1000 0111 0000 1111 0000 0000 1111 0000 1111 0000 0000 1111 0000 LSB 1111 0001 0000 1111 0000 Analog Output VOUT +2 VREFIN × (32,767/32,768) +2 VREFIN × (1/32,768) 0V −2 VREFIN × (1/32,768) −2 VREFIN × (32,767/32,768) Table 8. Ideal Output Voltage to Input Code Relationship—Twos Complement Data Coding Digital Input MSB 0111 0000 0000 1111 1000 1111 0000 0000 1111 0000 1111 0000 0000 1111 0000 LSB 1111 0001 0000 1111 0000 Analog Output VOUT +2 VREFIN × (32,767/32,768) +2 VREFIN × (1/32,768) 0V −2 VREFIN × (1/32,768) −2 VREFIN × (32,767/32,768) Rev. 0 | Page 23 of 32 AD5762R REGISTERS Table 9. Input Shift Register Format MSB DB23 R/W LSB DB22 0 DB21 REG2 DB20 REG1 DB19 REG0 DB18 A2 DB17 A1 DB16 A0 DB15 to DB0 Data Table 10. Input Shift Register Bit Function Descriptions Register Bit R/W Descriptions Indicates a read from or a write to the addressed register REG2, REG1, REG0 Used in association with the address bits, determines if a read or write operation is to the data register, offset register, gain register, or function register REG2 REG1 REG0 Function 0 0 0 Function register 0 1 0 Data register 0 1 1 Coarse gain register 1 0 0 Fine gain register 1 0 1 Offset register Decodes the DAC channels A2 A1 A0 Channel Address 0 0 0 DAC A 0 0 1 DAC B 1 0 0 Both DACs Data bits A2, A1, A0 Data FUNCTION REGISTER The function register is addressed by setting the three REG bits to 000. The values written to the address bits and the data bits determine the function addressed. The functions available via the function register are outlined in Table 11 and Table 12. Table 11. Function Register Options REG2 0 0 REG1 0 0 REG0 0 0 A2 0 0 A1 0 0 A0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 DB15 to DB6 DB5 Don’t care Local ground offset adjust DB4 DB3 DB2 NOP, data = don’t care D1 D1 D0 direction value direction DB1 DB0 D0 value SDO disable Clear, data = don’t care Load, data = don’t care Table 12. Explanation of Function Register Options Option NOP Local Ground Offset Adjust D0, D1 Direction D0, D1 Value SDO Disable Clear Load Description No operation instruction used in readback operations. Set by the user to enable the local ground offset adjust function. Cleared by the user to disable the local ground offset adjust function (default). See the Design Features section for more information. Set by the user to enable the D0 and D1 pins as outputs. Cleared by the user to enable the D0 and D1 pins as inputs (default). See the Design Features section for more information. I/O port status bits. Logic values written to these locations determine the logic outputs on the D0 and D1 pins when configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is active as an input. When enabled as inputs, these bits are don’t cares during a write operation. Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default). Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary mode. Addressing this function updates the DAC registers and, consequently, the analog outputs. Rev. 0 | Page 24 of 32 AD5762R DATA REGISTER The data register is addressed by setting the three REG bits to 010. The DAC address bits select the DAC channel with which the data transfer takes place (see Table 10). The data bits are positioned in DB15 to DB0, as shown in Table 13. Table 13. Programming the Data Register REG2 0 REG1 1 REG0 0 A2 A1 A0 DAC address DB15 to DB0 16-bit DAC data COARSE GAIN REGISTER The coarse gain register is addressed by setting the three REG bits to 011. The DAC address bits select the DAC channel with which the data transfer takes place (see Table 10). The coarse gain register is a 2-bit register that allows the user to select the output range of each DAC, as shown in Table 15. Table 14. Programming the Coarse Gain Register REG2 0 REG1 1 REG0 1 A2 A1 DAC address A0 DB15 to DB2 Don’t care DB1 CG1 DB0 CG0 Table 15. Output Range Selection Output Range ±10 V (Default) ±10.2564 V ±10.5263 V CG1 0 0 1 CG0 0 1 0 FINE GAIN REGISTER The fine gain register is addressed by setting the three REG bits to 100. The DAC address bits select the DAC channel with which the data transfer takes place (see Table 10). The AD5762R fine gain register is a 6-bit register that allows the user to adjust the gain of each DAC channel by −32 LSBs to +31 LSBs in 1 LSB steps, as shown in Table 16 and Table 17. The adjustment is made to both the positive full-scale points and the negative full-scale points simultaneously, with each point adjusted by one-half of one step. The fine gain register coding is twos complement. Table 16. Programming the Fine Gain Register REG2 1 REG1 0 REG0 0 A2 A1 A0 DAC address DB15 to DB6 Don’t care DB5 FG5 DB4 FG4 DB3 FG3 DB2 FG2 DB1 FG1 Table 17. Fine Gain Register Options Gain Adjustment +31 LSBs +30 LSBs No Adjustment (Default) −31 LSBs −32 LSBs FG5 0 0 0 1 1 FG4 1 1 0 0 0 FG3 1 1 0 0 0 Rev. 0 | Page 25 of 32 FG2 1 1 0 0 0 FG1 1 1 0 0 0 FG0 1 0 0 1 0 DB0 FG0 AD5762R OFFSET REGISTER The offset register is addressed by setting the three REG bits to 101. The DAC address bits select the DAC channel with which the data transfer is to take place (see Table 10). The AD5762R offset register is an 8-bit register and allows the user to adjust the offset of each channel by −16 LSBs to +15.875 LSBs in steps of ⅛ LSB, as shown in Table 18 and Table 19. The offset register coding is twos complement. Table 18. Programming the Offset Register REG2 1 REG1 0 REG0 1 A2 A1 A0 DAC address DB15:DB8 Don’t care DB7 OF7 DB6 OF6 DB5 OF5 DB4 OF4 DB3 OF3 DB2 OF2 DB1 OF1 DB0 OF0 Table 19. Offset Register Options Offset Adjustment +15.875 LSBs +15.75 LSBs No Adjustment (Default) −15.875 LSBs −16 LSBs OF7 0 0 0 1 1 OF6 1 1 0 0 0 OF5 1 1 0 0 0 Using the information provided in the previous section, the following worked example demonstrates how the AD5762R functions can be used to eliminate both offset and gain errors. As the AD5762R is factory calibrated, offset and gain errors should be negligible. However, errors can be introduced by the system that the AD5762R is operating within, for example, a voltage reference value that is not equal to +5 V introduces a gain error. An output range of ±10 V and twos complement data coding is assumed. The AD5762R can eliminate an offset error in the range of −4.88 mV to +4.84 mV with a step size of ⅛ of a 16-bit LSB. 2. 3. Offset Step Size = 614 μV 38.14 μV OF1 1 1 0 0 0 OF0 1 0 0 1 0 Convert adjustment value to binary: 00010000. Convert this to a negative twos complement number by inverting all bits and adding 1: 11110000. Program 11110000 to the offset register. 3. Note that this twos complement conversion is not necessary in the case of a positive offset adjustment. The value to be programmed to the offset register is simply the binary representation of the adjustment value. Removing Gain Error Calculate the step size of the gain adjustment using the following equation: 20 = 38.14 μV 2 16 × 8 Gain Adjust Step Size = Measure the offset error by programming 0x0000 to the data register and measuring the resulting output voltage. For this example, the measured value is +614 μV. Determine the number of offset adjustment steps this value represents, using the following equation: Number Steps = 1. 2. 1. Calculate the step size of the offset adjustment Measured Offset Value OF2 1 1 0 0 0 The AD5762R can eliminate a gain error at negative full-scale output in the range of −9.77 mV to +9.46 mV with a step size of ½ of a 16-bit LSB. Removing Offset Error Offset Adjust Step Size = OF3 1 1 0 0 0 The required offset register value can be calculated as follows: OFFSET AND GAIN ADJUSTMENT WORKED EXAMPLE 1. OF4 1 1 0 0 0 2. Measure the gain error by programming 0x8000 to the data register and measuring the resulting output voltage. The gain error is the difference between this value and −10 V. For this example, the gain error is −1.2 mV. Determine how many gain adjustment steps this value represents by using the following equation: 3. = 16 Steps Number of Steps = The offset error measured is positive; therefore, a negative adjustment of 16 steps is required. The offset register is 8 bits wide, and the coding is twos complement. 20 = 152.59 μV 216 × 2 Measured GainValue Gain Step Size = 1.2 mV 152.59 μV = 8 Steps The gain error measured is negative (in terms of magnitude); therefore, a positive adjustment of eight steps is required. The gain register is 6 bits wide, and the coding is twos complement. The required gain register value can be determined as follows: 1. 2. Rev. 0 | Page 26 of 32 Convert the adjustment value to binary: 001000. 001000 is the value to be programmed to the gain register. AD5762R DESIGN FEATURES ANALOG OUTPUT CONTROL In many industrial process control applications, it is vital that the output voltage be controlled during power-up and during brownout conditions. When the supply voltages are changing, the VOUTx pins are clamped to 0 V via a low impedance path. To prevent the output amp from being shorted to 0 V during this time, Transmission Gate G1 is also opened (see Figure 42). RSTOUT VOLTAGE MONITOR AND CONTROL G1 VOUTA 07248-063 G2 DIE TEMPERATURE SENSOR Figure 42. Analog Output Control Circuitry These conditions are maintained until the power supplies stabilize and a valid word is written to the DAC register. G2 then opens, and G1 closes. Both transmission gates are also externally controllable via the reset in (RSTIN) control input. For example, if RSTIN is driven from a battery supervisor chip, the RSTIN input is driven low to open G1 and close G2 on power-off or during a brownout. Conversely, the on-chip voltage detector output (RSTOUT) is also available to the user to control other parts of the system. The basic transmission gate functionality is shown in Figure 42. DIGITAL OFFSET AND GAIN CONTROL The AD5762R incorporates a digital offset adjust function with a ±16 LSB adjust range and 0.125 LSB resolution. The gain register allows the user to adjust the AD5762R full-scale output range. The full-scale output can be programmed to achieve full-scale ranges of ±10 V, ±10.25 V, and ±10.5 V. A fine gain trim is also available. PROGRAMMABLE SHORT-CIRCUIT PROTECTION The short-circuit current (ISC) of the output amplifiers can be programmed by inserting an external resistor between the ISCC pin and PGND. The programmable range for the current is 500 μA to 10 mA, corresponding to a resistor range of 120 kΩ to 6 kΩ. The resistor value is calculated as follows: R≈ DIGITAL I/O PORT The AD5762R contains a 2-bit digital I/O port (D1 and D0). These bits can be configured independently as inputs or outputs and can be driven or have their values read back via the serial interface. The I/O port signals are referenced to DVCC and DGND. When configured as outputs, they can be used as control signals to multiplexers or can be used to control calibration circuitry elsewhere in the system. When configured as inputs, the logic signals from limit switches, for example, can be applied to D0 and D1 and can be read back using the digital interface. RSTIN AGNDA If the ISCC pin is left unconnected, the short-circuit current limit defaults to 5 mA. It should be noted that limiting the short-circuit current to a small value can affect the slew rate of the output when driving into a capacitive load. Therefore, the value of the short-circuit current that is programmed should take into account the size of the capacitive load being driven. The on-chip die temperature sensor provides a voltage output that is linearly proportional to the Celsius temperature scale. Its nominal output voltage is 1.47 V at 25°C die temperature, varying at 5 mV/°C, giving a typical output range of 1.175 V to 1.9 V over the full temperature range. Its low output impedance and linear output simplify interfacing to temperature control circuitry and analog-to-digital converters (ADCs). The temperature sensor is provided as more of a convenience than as a precise feature; it is intended for indicating a die temperature change for recalibration purposes. LOCAL GROUND OFFSET ADJUST The AD5762R incorporates a local ground offset adjust feature that, when enabled in the function register, adjusts the DAC outputs for voltage differences between the individual DAC ground pins and the REFGND pin, ensuring that the DAC output voltages are always referenced to the local DAC ground pin. For example, if the AGNDA pin is at +5 mV with respect to the REFGND pin and VOUTA is measured with respect to AGNDA, a −5 mV error results, enabling the local ground offset adjust feature to adjust VOUTA by +5 mV, thereby eliminating the error. 60 I SC Rev. 0 | Page 27 of 32 AD5762R APPLICATIONS INFORMATION TYPICAL OPERATING CIRCUIT Figure 43 shows the typical operating circuit for the AD5762R. The only external components needed for this precision 16-bit DAC are decoupling capacitors on the supply pins and reference inputs, and an optional short-circuit current setting resistor. Because the AD5762R incorporates a voltage reference and reference buffers, it eliminates the need for an external bipolar reference and associated buffers, resulting in an overall savings in both cost and board space. In Figure 43, AVDD and AVSS are both connected to ±15 V, but AVDD and AVSS can operate with supplies from ±11.4 V to ±16.5 V. In Figure 43, AGNDA and AGNDB are connected to REFGND. Precision Voltage Reference Selection To achieve the optimum performance from the AD5762R over its full operating temperature range, an external voltage reference must be used. Care must be taken in the selection of a precision voltage reference. The voltage applied to the reference input is used to provide a buffered positive and negative reference for the DAC cores. Therefore, any error in the voltage reference is reflected in the outputs of the device. There are four possible sources of error to consider when choosing a voltage reference for high accuracy applications: initial accuracy, temperature coefficient of the output voltage, long term drift, and output voltage noise. Initial accuracy error on the output voltage of an external reference could lead to a full-scale error in the DAC. Therefore, to minimize these errors, a reference with low initial accuracy error specification is preferred. Choosing a reference with an output trim adjustment, such as the ADR425, allows a system designer to trim system errors out by setting the reference voltage to a voltage other than the nominal. The trim adjustment can also be used at temperature to trim out any error. Long-term drift is a measure of how much the reference output voltage drifts over time. A reference with a tight long-term drift specification ensures that the overall solution remains relatively stable over its entire lifetime. The temperature coefficient of a reference output voltage affects INL, DNL, and TUE. A reference with a tight temperature coefficient specification should be chosen to reduce the dependence of the DAC output voltage on ambient conditions. In high accuracy applications, which have a relatively low noise budget, reference output voltage noise must be considered. It is important to choose a reference with as low an output noise voltage as practical for the system resolution that is required. Precision voltage references such as the ADR435 (XFET® design) produce low output noise in the 0.1 Hz to 10 Hz region. However, as the circuit bandwidth increases, filtering the output of the reference may be required to minimize the output noise. Table 20. Some Precision References Recommended for Use with the AD5762R Part No. ADR435 ADR425 ADR02 ADR395 AD586 Initial Accuracy (mV Maximum) ±6 ±6 ±5 ±6 ±2.5 Long-Term Drift (ppm Typical) 30 50 50 50 15 Temperature Drift (ppm/°C Maximum) 3 3 3 25 10 Rev. 0 | Page 28 of 32 0.1 Hz to 10 Hz Noise (μV p-p Typical) 3.5 3.4 10 5 4 AD5762R +15V –15V 10µF 10µF 100nF 10µF 100nF TEMP BIN/2sCOMP SCLK SDIN 3 SDIN SDO 4 SDO REFA AVSS TEMP AVDD REFB NC 24 NC 23 VOUTA 22 AGNDB 20 5 CLR LDAC 6 LDAC D0 7 D0 NC 18 D1 8 D1 NC 17 ISCC AVSS PGND AVDD DVCC DGND VOUTB 10µF 10µF 100nF 10 11 12 13 14 15 16 100nF RSTIN RSTIN RSTOUT VOUTB 19 9 RSTOUT VOUTA AGNDA 21 AD5762R +5V 100nF 10µF +15V –15V Figure 43. Typical Operating Circuit Rev. 0 | Page 29 of 32 07248-064 SYNC 2 REFOUT 1 SCLK REFGND SYNC BIN/2sCOMP 32 31 30 29 28 27 26 25 +5V AD5762R LAYOUT GUIDELINES In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. Design the PCB on which the AD5762R is mounted such that the analog and digital sections are separated and confined to certain areas of the board. If the AD5762R is in a system where multiple devices require an AGNDx-to-DGND connection, establish the connection at one point only. Establish the star ground point as close as possible to the device. The AD5762R should have ample supply bypassing of 10 μF in parallel with 0.1 μF on each supply located as close to the package as possible, ideally right up against the device. The 10 μF capacitors are of the tantalum bead type. The 0.1 μF capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI), such as the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. The power supply lines of the AD5762R should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Shield fast-switching signals, such as clocks, with digital ground to avoid radiating noise to other parts of the board; they should never be run near the reference inputs. A ground line routed between the SDIN and SCLK lines helps reduce cross talk between them. (A ground line is not required on a multilayer board because it has a separate ground plane; however, it is helpful to separate the lines.) It is essential to minimize noise on the reference inputs because it couples through to the DAC output. Avoid crossover of digital and analog signals. Run traces on opposite sides of the board at right angles SERIAL CLOCK OUT SERIAL DATA OUT SYNC OUT CONTROL OUT GALVANICALLY ISOLATED INTERFACE In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. Isocouplers provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5762R makes it ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 44 shows a 4-channel isolated interface to the AD5762R using an ADuM1400 iCoupler® product. For more information on iCoupler products, go to www.analog.com. MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5762R is accomplished using a serial bus that uses standard protocol that is compatible with microcontrollers and DSP processors. The communication channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a synchronization signal. The AD5762R requires a 24-bit data-word with data valid on the falling edge of SCLK. For all the interfaces, a DAC output update can be performed automatically when all the data is clocked in, or it can be done under the control of LDAC. The contents of the DAC register can be read using the readback function. ADuM1400* VIA VIB VIC VID ENCODE DECODE ENCODE DECODE ENCODE DECODE ENCODE DECODE *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 44. Isolated Interface Rev. 0 | Page 30 of 32 VOA VOB VOC VOD TO SCLK TO SDIN TO SYNC TO LDAC 07248-065 MICROCONTROLLER to each other to reduce the effects of feedthrough on the board. A microstrip technique is recommended, but not always possible, with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane, and signal traces are placed on the solder side. AD5762R EVALUATION BOARD Performance of the AD5762R can be evaluated using the AD5764R evaluation board. The evaluation board aids designers in evaluating the high performance of the part with a minimum of effort. All that is required with the evaluation board is a power supply and a PC. The AD5764R evaluation kit includes a populated, tested AD5764R PCB. The evaluation board interfaces to the USB interface of the PC. Software is available with the evaluation board that allows the user to easily program the AD5764R. The software runs on any PC that has Microsoft Windows® 2000/XP installed. An application note is available that gives full details on operating the evaluation board. Rev. 0 | Page 31 of 32 AD5762R OUTLINE DIMENSIONS 0.75 0.60 0.45 1.20 MAX 9.00 BSC SQ 25 32 24 1 PIN 1 7.00 BSC SQ TOP VIEW 0° MIN 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY SEATING PLANE VIEW A 17 8 9 VIEW A 0.80 BSC LEAD PITCH ROTATED 90° CCW 16 0.45 0.37 0.30 020607-A 1.05 1.00 0.95 0.15 0.05 (PINS DOWN) COMPLIANT TO JEDEC STANDARDS MS-026-AB A Figure 45. 32-Lead Thin Plastic Dual Flat Package [TQFP] (SU-32-2) Dimensions shown in millimeters ORDERING GUIDE Model AD5762RCSUZ 1 AD5762RCSUZ-REEL71 1 Function Dual 16-Bit DAC Dual 16-Bit DAC INL ±1 LSB Max ±1 LSB Max Temperature Range −40°C to +85°C −40°C to +85°C Z = RoHS Compliant Part. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07248-0-12/08(0) Rev. 0 | Page 32 of 32 Internal Reference +5 V +5 V Package Description 32-Lead TQFP 32-Lead TQFP Package Option SU-32-2 SU-32-2