34.807IRELESS IMPORTANT NOTICE Dear customer, As from August 2nd 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless. As a result, the following changes are applicable to the attached document. ● Company name - NXP B.V. is replaced with ST-NXP Wireless. ● Copyright - the copyright notice at the bottom of each page “© NXP B.V. 200x. All rights reserved”, shall now read: “© ST-NXP Wireless 200x - All rights reserved”. ● Web site - http://www.nxp.com is replaced with http://www.stnwireless.com ● Contact information - the list of sales offices previously obtained by sending an email to [email protected] , is now found at http://www.stnwireless.com under Contacts. If you have any questions related to the document, please contact our nearest sales office. Thank you for your cooperation and understanding. ST-NXP Wireless 34.807IRELESS www.stnwireless.com TEA5760UK Single chip FM stereo radio Rev. 01 — 14 December 2006 Product data sheet 1. General description The TEA5760UK is a single chip electronically tuned FM stereo radio for low voltage applications with fully integrated Intermediate Frequency (IF) selectivity and demodulation. The radio is completely adjustment free and only requires a minimum of small and low cost external components. The TEA5760UK does not meet all of the requirements from EN55020, a trade off was done to make possible the previously stated features. The TEA5760UK application software is compatible to the TEA5761UK software to enable easy design in for customers. 2. Features n High sensitivity due to integrated low noise Radio Frequency (RF) input amplifier n FM mixer for conversion of the US/Europe (87.5 MHz to 108 MHz) and Japanese FM band (76 MHz to 90 MHz) to IF n Preset tuning to receive Japanese TV audio up to 108 MHz and raster 100 kHz n Autonomous search tuning, 100 kHz grid n RF Automatic Gain Control (AGC) circuit n LC tuner oscillator operating with one low cost chip inductor (external varicap not required) n Fully integrated FM IF selectivity n Fully integrated FM demodulator n 32.768 kHz external reference frequency n Phase-Locked Loop (PLL) synthesizer tuning system n IF counter; 7-bit output via control interface n Level detector, 4-bit level information output via the control interface n Soft mute, signal level dependent mute function n Signal level dependent mono/stereo blend, Stereo Noise Cancelling (SNC) n Soft mute and SNC can be switched off via control interface n Adjustment free stereo decoder n I2C-bus interface n Standby mode n One software programmable port n Interrupt flag TEA5760UK NXP Semiconductors Single chip FM stereo radio 3. Ordering information Table 1. Ordering information Type number TEA5760UK Package Name Description Version WLCSP25 wafer level chip-size package; 25 bumps; die 3 × 2.8 × 0.6 mm TEA5760UK TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 2 of 36 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x VCCA C1 E4 B5 A6 AUTO ALIGN POWER SUPPLY IF FILTER LIMITER Rev. 01 — 14 December 2006 ÷2 N1 I/Q MIXER 1st FM GND(RF) TMUTE E6 D6 E5 TEA5760UK SOFT MUTE DEMODULATOR IF COUNT MPX DECODER RFIN2 VAFR REFERENCE BUFFER IF AGC RFIN1 VAFL B6 SDS LEVEL ADC RF AGC C6 NXP Semiconductors D5 FREQIN MPXOUT GND(A1) 4. Block diagram TEA5760UK_1 Product data sheet GND(A2) C5 mono B2 pilot prog. div out ref. div out I2C-BUS INTERFACE TUNING SYSTEM D3 GND(D2) D1 MUX A1 3 of 36 © NXP B.V. 2006. All rights reserved. LOOPSW CPOUT A3 LO1 SW PORT A4 LO2 A5 VCC(VCO) B1 SWPORT C2 BUSEN E3 E2 CLOCK VREFDIG Fig 1. Block diagram E1 D2 GND(D1) DATA 001aaf260 TEA5760UK A2 VCCD Single chip FM stereo radio VCO INTX TEA5760UK NXP Semiconductors Single chip FM stereo radio 5. Pinning information 5.1 Pinning bump A1 index area TEA5760UK 1 2 3 4 5 6 A B C D E 001aaf252 Transparent top view Fig 2. Ball configuration TEA5760UK 5.2 Pin description Table 2. Pin description Symbol Pin Description CPOUT A1 charge pump output of synthesizer PLL LOOPSW A2 switch output of synthesizer PLL loop filter LO1 A3 local oscillator coil connection LO2 A4 local oscillator coil connection VCC(VCO) A5 Voltage Controlled Oscillator (VCO) supply voltage VCCA A6 analog supply voltage SWPORT B1 software programmable port INTX B2 interrupt GND(A1) B5 analog ground 1 RFIN1 B6 RF input 1 FREQIN C1 input for 32.768 kHz reference frequency BUSEN C2 bus enable input for control interface GND(RF) C5 RF ground RFIN2 C6 RF input 2 VCCD D1 digital supply voltage GND(D1) D2 digital ground 1 GND(D2) D3 digital ground 2 GND(A2) D5 analog ground 2 TMUTE D6 time constant for soft mute DATA E1 control interface data line input/output CLOCK E2 control interface clock line input VREFDIG E3 digital reference voltage for control interface TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 4 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio Table 2. Pin description …continued Symbol Pin Description MPXOUT E4 multiplex signal (MPX) output pin VAFL E5 left audio output VAFR E6 right audio output 6. Functional description 6.1 Low noise RF amplifier The Low Noise Amplifier (LNA) input impedance together with the LC RF input circuit defines an FM band filter. The gain of the LNA is controlled by the RF AGC circuit to prevent overdrive of the subsequent circuits. 6.2 FM mixer The FM quadrature mixer converts the received RF (76 MHz to 108 MHz) to an IF of 225 kHz. Downconversion is achieved by multiplying the RF with the Local Oscillator (LO) frequency. Image frequency suppression is achieved by using quadrature signal processing. 6.3 VCO The LC tuned VCO provides the LO signal for the FM quadrature mixer. The VCO frequency range is 150 MHz to 217 MHz. No external varactor is required. 6.4 Reference frequency An external 32.768 kHz reference frequency is used as the system clock. The reference frequency specifications are given in Section 10. The reference frequency is used for: • • • • Synthesizer PLL reference frequency Timing for the IF counter Adjustment of the frequency of the stereo decoder VCO Auto alignment of the selectivity as well as the demodulator filters 6.5 PLL tuning system The PLL synthesizer tuning system is designed to operate with a 32.768 kHz reference frequency. A 14-bit word is used to tune the radio (see Table 11 and Table 12). Calculation of this 14-bit word is as follows. [ 4 × ( f RF + f IF ) ] Formula for high-side injection: N DEC = -----------------------------------------f ref [ 4 × ( f RF – f IF ) ] Formula for low-side injection: N DEC = -----------------------------------------f ref TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 5 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio where: NDEC = decimal value of PLL word fRF = wanted tuning frequency (Hz) fIF = intermediate frequency (Hz): 225 kHz fref = reference frequency (Hz): 32.768 kHz Example for receiving a channel at 100.1 MHz: [ 4 × ( 100.e6 + 225e3 ) ] N DEC = --------------------------------------------------------- = 12246.704 32768 The result must always be rounded to the lowest integer value. If rounded down to the lowest integer value of NDEC = 12246, the PLL word becomes 2FD6h. Via the control interface this value can be written to register FRQSET and the TEA5760UK will then start an autonomous search beginning at this frequency or go to a preset channel at this frequency. When the application is built according the application diagram (see Figure 11) and with the preferred components, the tuning system will settle to the new frequency within 40 ms. The PLL is triggered by writing one of the following bytes: FRQSETMSB, FRQSETLSB, TNCTRL1, TNCTRL2, TESTBITS and TESTMODE. Accurate validation of the PLL locking onto the new frequency can take 40 ms. Bit LD in register TUNCHK (see Table 18) is set when a lock is detected. 6.6 Band limits The TEA5760UK can be switched to the Japanese FM band or the US/Europe FM band. With bit BLIM in register TNCTRL (see Table 13) set to logic 0 it enables the US/European FM band (87.5 MHz to 108 MHz), while setting bit BLIM to logic 1 enables the Japanese FM band (76 MHz to 90 MHz). 6.7 RF AGC The RF AGC prevents overloading and limits the amount of intermodulation products created by strong adjacent channels. The default setting for the RF AGC is on and it can be turned off via the control interface. The TEA5760UK also has an inband AGC to prevent overloading by the wanted channel itself. The inband AGC is always on. 6.8 IF filter Fully integrated IF filter with a center frequency of 225 kHz. 6.9 FM demodulator Fully integrated FM quadrature demodulator. TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 6 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio 6.10 IF counter The received RF signal is converted down to a 225 kHz IF. The IF is measured by means of a frequency counter. A correct IF frequency measurement result indicates that the radio is tuned to a valid channel and not to an image or a channel with high interference. The 7-bit IF counter output can be read via the control interface. The IF counter is active when the tuning algorithm is active (see Figure 3) and the outcome can be read via the control interface. It activates a flag if the IF count result lies outside a predefined window. The IF count period can be set to 1.953 ms or 15.625 ms with bit IFCTC in register TNCTRL (see Table 13). 6.11 Level voltage generator and analog-to-digital converter The level voltage reflects the received field strength at the antenna. The analog level voltage is digitized to 4 bits by the level Analog-to-Digital Converter (ADC). During a search or preset tuning cycle the level ADC is activated and the recorded level ADC information is stored in the registers. The level ADC information is used during search as well as preset tuning to compare the received signal strength with a search stop level (see Section 7.1.4.3). A flag will be set to indicate that the level voltage is below the predefined search stop level (see Figure 3). When the tuning algorithm is finished the level ADC is deactivated. 6.12 Mute 6.12.1 Soft mute The low-pass filtered level voltage drives the soft mute attenuator. At low RF input levels, the audio output is faded and hence also the noise. The soft mute function can be disabled with bit SMUTE in register TNCTRL (see Table 13). 6.12.2 Hard mute With bit MU in register TNCTRL (see Table 14) the audio outputs VAFL and VAFR can be hard muted, this means they are put in high ohmic mode. The same can be done by setting bits LHM (Left Hard Mute) or RHM (Right Hard Mute) in register TESTREG (see Table 19), which mutes only one output at a time (or both when both set). When one output is muted, the stereo decoder switches to mono. If the TEA5760UK is in Standby mode the audio outputs are in high impedance mode, see Table 3. Table 3. Type Specification of mute modes Description Left Impedance Mode Impedance Mode AFM Audio Frequency Mute 350 Ω muted 350 Ω muted MU Hard Mute 500 kΩ muted 500 kΩ muted LHM Left Hard Mute 500 kΩ muted 350 Ω mono audio RHM Right Hard Mute 350 Ω mono audio 500 kΩ muted Standby Standby 1 MΩ muted 1 MΩ muted SMUTE Soft Mute RF level sensitive audio level. Has no influence on mute or pin impedance. TEA5760UK_1 Product data sheet Right © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 7 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio 6.12.3 Audio Frequency Mute (AFM) With bit AFM in register TNCTRL (see Table 13), the audio signal can be muted. The audio pins maintain their functional impedance and DC-biasing level while the audio signal is muted. The audio frequency mute is automatically activated during preset as well as search tuning modes as shown in the flowchart of Figure 3. 6.13 MPX decoder The PLL stereo decoder is adjustment free. The stereo decoder can be switched to mono via the control interface. 6.14 Signal depending mono/stereo blend (stereo noise cancellation) With decreasing RF input level the MPX decoder blends from stereo to mono to limit the output noise. The continuous mono-to-stereo blend can also be programmed via the control interface to an RF level depending on the switched mono-to stereo transition. Stereo Noise Cancellation (SNC) can be switched on/off via the control interface using bit SNC in register TNCTRL (see Table 13). The RF input voltage where blending starts can be switched with bit SNCLEV in register TESTREG (see Table 20). 6.15 Software programmable port One software programmable port (CMOS output) is available and can be controlled via the control interface. • Bit SWPM = 1; the software port (SWPORT) functions as the output for bit FRRFLAG • Bit SWPM = 0; the software port outputs bit SWP of the registers In software test mode the software port outputs signals according to Table 21. Software test mode is selected setting bit TM of register TESTREG. The software port is not disabled by bit PUPD (see Section 6.16). 6.16 Standby With the Power-Up/Power-Down (PUPD) bit the radio can be put in Standby mode. Standby mode is defined as where the TEA5760UK has all supply voltages available but the circuits are powered down via software or after power-on reset. The TEA5760UK is still accessible via the control interface, but takes only a very limited amount of power from the supply. The software programmable port remains active to allow peripheral devices to be controlled. The audio outputs are hard muted. When pin BUSEN is HIGH and the circuits are powered down via software (PUPD) the TEA5760UK is in Sleep mode. In Sleep mode the TEA5760UK is accessible via the I2C-bus, but the radio part is not active. The digital supply current (ICCD) is higher than in Standby mode. When the supply voltage VCCA and VCCD are at 0 V and pin VREFDIG is HIGH, all I/Os, the audio outputs and the reference clock input are high-ohmic. The power supplies can be switched on in any order. TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 8 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio 6.17 Power-on reset After start-up of VCCA and VCCD, a power-on-reset circuit will generate a reset pulse and the registers will be set to their default values as shown in Table 8. The power-on reset is effectively generated by VCCD. To prevent any uncontrolled control interface response, before power is switched on, pin BUSEN must be LOW. The audio output pins are high-ohmic (hard mute), all other bits are set default according to Table 8. 6.18 Control interface The I2C-bus operates with a maximum clock frequency of 400 kHz. 6.19 Auto search and preset mode 6.19.1 Search mode In Search mode the TEA5760UK can search channels automatically. When the INTX signal is used as an interrupt to the host processor to indicate a search stop, the INTMSK register must be reset and only the FRRMSK must be set. In this way the host processor will only be interrupted when the search/preset algorithm is ready. Search mode is initiated by setting the SM bit to logic 1 in the FRQSET register. When bit SUD = 0 then it searches down, when SUD = 1 it searches up. The tuner starts searching at the frequency where it is or at a new start frequency programmed to the tuner. In the case the programmed frequency is a valid channel and auto search is initiated, the radio will stay tuned to programmed frequency. To continue the auto search tune algorithm under such conditions, an offset frequency relative to the tuned frequency has to be programmed (for example 100 kHz) to search for subsequent channels. With the Search Stop Level (SSL) bits the minimum field strength of channels to be found can be set. The tuner will stop on a channel with a field strength equal to or higher than this reference level and then will check the IF frequency. When both are valid the Search mode terminates. If the level check or the IF count fails, it keeps on searching. When no channels are found the TEA5760UK stops searching when it has reached the band limit and the BLFLAG goes HIGH. A search always stops with the FRRFLAG being set and a hardware interrupt. Figure 3 describes this procedure. After this interrupt the TEA5760UK will keep its status and will not update the INTREG, FRQCHK and TUNCHK tuner registers for a period of 15.625 ms. The state of the TEA5760UK can be checked by reading tuning registers INTREG, FRQCHK and TUNCHK. Table 4 shows the possible states after an auto search or a preset. TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 9 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio start mute the audio outputs reset flags set PLL frequency wait for PLL to settle false level OK set LEVFLAG true false IF OK true set IFFLAG false AHLSI true false search mode true false search up true increment current_pll by 100 kHz decrement current_pll by 100 kHz band limit false true BLFLAG = 0 FRRFLAG = 1 no mute BLFLAG = 0 FRRFLAG = 1 mute BLFLAG = 1 FRRFLAG = 1 no mute 001aaf262 Fig 3. Flowchart auto search or preset (IF statement down = true) 6.19.2 Preset mode A preset is done by setting bit SM to logic 0 and writing a frequency to register FRQSET. The tuner jumps to the selected frequency and sets the FRRFLAG when it is ready. After this interrupt the TEA5760UK will not update the tuner registers for a period of 15.625 ms. The state of the TEA5760UK can be checked by reading registers INTREG, FRQCHK and TUNCHK. Table 4 shows the possible states after an auto search or preset. TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 10 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio Table 4. Tuner truth table Bit Comment IFFLAG BLFLAG FRRFLAG 0 0 0 if INTX has gone low and IFMSK, LEVMSK, FRRMSK and BLMSK were set then this cannot occur 0 0 1 channel found during search, BLMSK and FRRMSK set 0 1 0 not a valid combination 0 1 1 no channel found and the band limit has been reached during a search, BLMSK and FRRMSK set 1 0 0 not possible during a preset or a search 1 0 1 A preset or search has been done, but the wanted channel has a valid RSSI level but fails the IF count. When AHLSI was set HLSI must be toggled and a new PLL value must be programmed. 1 1 0 not a valid combination 1 1 1 band limit is reached during search, no valid channel found 6.19.3 Auto high-side and low-side injection stop switch The channel quality can sometimes be improved in case of image frequency interference. This can be achieved if the LO injection is positioned at the opposite side of the wanted channel (see Figure 4). Indication for image frequency interference can be derived from the IF frequency counter. To enable this feature bit AHLSI has to be set to logic 1. The search/preset algorithm will stop and generate an interrupt event after detection of a valid RSSI level in combination with a frequency outside the IF frequency window. The host processor can detect this state by reading the interrupt register. Swap of the LO injection is achieved by inversion of bit HLSI in combination with a new tuning word for the changed oscillator frequency (see Section 6.5). image on low-side wanted channel image on high-side switch LO from high-side to low-side 001aab460 Fig 4. Switch from high-side injection of LO to low-side injection using the HLSI bit TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 11 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio 6.19.4 Muting during search or preset During a preset and search tuning the tuner is always muted, this is done by the algorithm itself. When bit AHLSI is set and the tuner stopped during a preset or a search because of a wrong IF count, the tuner stays muted and generates an interrupt event. In this way the host processor can switch the Hi-Lo setting quietly and wait for the new result. All these mute actions are done by blocking the audio signal inside the soft mute attenuator, so the audio output will keep its DC level and stay low-ohmic i.e. 350 Ω (a hard mute with bit MU will cause a plop) (see Table 3). 7. Interrupt handling 7.1 Interrupt register The first two bytes of the I2C-bus register contain the interrupt masks and the interrupt flags. A flag is set when it is 1. Table 5. INTREG byte0R Bit 7 6 5 4 3 2 1 0 Symbol - - - IFFLAG LEVFLAG - FRRFLAG BLFLAG Table 6. INTREG byte0W Bit 7 6 5 4 3 2 1 0 Symbol - - - IFMSK LEVMSK - FRRMSK BLMSK The interrupt flag register contains the flags set according to the behavior outlined in Section 7.1.4. When these are set they can also cause the INTX to go active [HardWare (HW) interrupt line] depending on the status of the corresponding mask bit in Table 6. A logic 1 in the mask register enables the HW interrupt for that flag. Hence it is conceivable that, with all the mask bits cleared, the SoftWare (SW) could operate in a polling mode by continuous read operation of the interrupt flag register to look for bits being set. Interrupt mask bits are always cleared after reading the interrupt register of the first two I2C-bus bytes. This is to control multiple HW interrupts (see Figure 5). TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 12 of 36 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx data S device address R ack 0R data INTMSK ack 1R data write access ack data ack S device address INTMSK W ack 0W data ack FRQSETMSB FRQSETLSB 1W data 2W data ack ack NXP Semiconductors TEA5760UK_1 Product data sheet INTFLAG read access P (2) interrupt event (1) A Rev. 01 — 14 December 2006 interrupt flag bit B1 B2 (3) interrupt mask bit (4) (5) (6) (5) INTX 001aab464 B1 is when only the INTFLAG is read and a stop condition is received (only INTFLAG is read so only this will be cleared). 13 of 36 © NXP B.V. 2006. All rights reserved. B2 is when both registers are read and hence cleared and this is terminated by either an acknowledge or stop bit. (3) Interrupt events that occur between A and B set their respective flags after the mask bits are cleared. Which means that in this diagram an interrupt event occurred in period A-B, so after A-B the flag goes to logic 1. (4) All interrupt mask bits are cleared after the interrupt flag and mask bytes are read. (5) Software writes to the mask byte and enables the required mask bits. Any flags currently set will then trigger a hardware interrupt. (6) INTX is set HIGH (inactive) after the interrupt mask bytes are read. Fig 5. I2C-bus interrupt sequence, read and write operation TEA5760UK (2) The blocking of interrupts is marked by the region A-B1 / B2 depending on the actual read cycle. Single chip FM stereo radio (1) Interrupt events that occur outside of the region A-B set their respective flag bits in the normal way immediately and can thus trigger a hardware interrupt if the mask bits are set. TEA5760UK NXP Semiconductors Single chip FM stereo radio 7.1.1 Interrupt clearing The interrupt flag and mask bits are always cleared after: • They have been read via the control interface • A power-on reset 7.1.2 Timing The timing sequence for the general operation interrupts is shown in Figure 5 shows a read access of the interrupt register INTREG and a subsequent (though not necessarily immediate) write to the mask register. It also indicates two key timing points A and B. If an interrupt event occurs while the register is being read (after point A) it must be held until after the mask register is cleared at the end of the read operation (point B). Point A is defined as: the R/W bit has been decoded. Point B is where the acknowledge has been received from the master after the first two bytes have been sent. The low time for the INTX line (tp) has a maximum value specified in Section 11. It can be shorter when a read action of the INTREG registers occurs within tp. 7.1.3 Reset A reset can be performed (at any time) by a simple read of the interrupt register (byte0R and byte1R), which automatically clears the interrupt flags and masks. 7.1.4 Interrupt flags and behavior 7.1.4.1 Multiple interrupt events If the interrupt mask register bit is set then the setting of an interrupt flag for that bit causes a HW interrupt (INTX goes LOW). If the event occurs again, before the flag is cleared, then this does not trigger any further HW interrupts until that specific flag is cleared. However two different events can occur in sequence and generate a sequence of HW interrupts. Only when read, followed by a write of the INTMSK byte has been done, can a second interrupt can be generated, as the first interrupt blocks the input of the INTX oneshot generator. If subsequent interrupts occur within the INTX LOW period then these do not cause the INTX period to extend beyond its specified maximum period (see Section 7.2). 7.1.4.2 IF frequency: IFFLAG During automatic frequency search or preset, the FM part of the TEA5760UK performs a check on the received IF frequency. If an incorrect IF frequency is received then this indicates the presence of strong interference or tuning to the image frequency. In case of preset tuning or search tuning with the AHLSI bit set the IFFLAG will be set and the algorithm will stop. When a search or preset is finished the FRRFLAG will be set and an interrupt is generated if the corresponding mask bit is set. The host processor can now read the outcome of the registers which will contain the IF count value and the IFFLAG status of the channel it is tuned to. TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 14 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio 7.1.4.3 RSSI threshold: LEVFLAG The level voltage reflects the field strength received by the antenna. The level voltage is analog-to-digital converted with 4 bits and output via the control interface. This 4-bit level value can be compared to a threshold level set by the SSL bits (see Table 14). The level ADC (which converts the analog value to digital) is triggered by a search or preset cycle. During a tuning step, which can be a search or a preset it is triggered by these algorithms and compares the level with the threshold set by the SSL bits. The LEVFLAG bit is set if the RSSI level drops below the threshold level set by the SSL bits (see Table 14), the HW interrupt is only generated if the corresponding mask bit is set. 7.1.4.4 Frequency ready flag: FRRFLAG The frequency ready flag bit FRRFLAG is set to logic 1 when the automatic tuning has finished a search or preset. The description of this bit is given in Table 9. This bit is cleared by a read of the flag register. 7.1.4.5 Band limit: BLFLAG The band limit bit BLFLAG is set to logic 1 when the automatic tuning has detected the end of the tuning band. This bit is described in Table 9. This bit is cleared by a read of the flag register. 7.2 Interrupt line The interrupt line driver is a MOS transistor with a nominal sink current of 900 µA. It is pulled HIGH by an 18 kΩ resistor connected to pin VREFDIG. The interrupt line can be connected to one other similar device with an interrupt output and an 18 kΩ pull-up resistor, providing a wired-OR function. This allows any of the drivers to pull the interrupt line LOW by sinking the current (see Section 11). When a flag is set and not masked it generates an interrupt. VCCA flag(1) INTX 10 ms <10 ms read clears INTX 10 ms <10 ms read INTMSK(2) write INTMSK(3) 001aab489 (1) When Flag is set next interrupts are blocked until Read/Write INTMSK. (2) Read INTMSK clears Flag, INTMSK and INTX. (3) Write INTMSK enables INTX. Fig 6. Interrupt line behavior TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 15 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio 8. I2C-bus interface The I2C-bus interface is based on The I2C-bus specification, version 2.1 January 2000, expanded by the following definitions. 8.1 Write and read mode S BYTE 1 A BYTE 2 A BYTE n A BYTE 8 chip address R/W byte0W ..... byte6W 0010 0000 0 xxxx xxxx xxxx xxxx xxxx xxxx NAK P 001aac341 Fig 7. Write mode S BYTE 1 A BYTE 2 A BYTE n A BYTE 17 chip address R/W byte0R ..... byte15R 0010 0000 1 xxxx xxxx xxxx xxxx xxxx xxxx A P 001aac342 Fig 8. Read mode Table 7. I2C-bus transfer description Code Description S START condition Byte 1 I2C-bus chip address (7 bits) R/W = 0 for write action and R/W = 1 for read action A acknowledge (SDA = LOW) Byte 2, etc. data byte (8 bits) NAK non acknowledge (SDA = HIGH) P STOP condition 8.2 Data transfer Structure of the I2C-bus: • Slave transceiver • Subaddresses not used Remark: The I2C-bus operates at a maximum clock rate of 400 kHz. It is not allowed to connect the TEA5760UK to an I2C-bus operating at a higher clock rate. Data transfer to the TEA5760UK: • Bit 7 of each byte is considered the MSB and has to be transferred as the first bit of the byte. • The LSB indicates the write or read action. TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 16 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio • The data becomes valid byte-wise at the appropriate falling edge of the SCL clock. • A STOP condition after any byte can shorten transmission times. When writing to the receiver by using the STOP condition before completion of the whole transfer: – The remaining bytes will contain the old information. – If the transfer of a byte is not completed the new bits will be used, but a new tuning cycle will not be started. I2C-bus activity: • With bit PUPD the TEA5760UK can be switched in a low current Standby mode. The I2C-bus is then still active. • When the I2C-bus interface is de activated, by making pin BUSENABLE LOW and without programmed Standby mode, the TEA5760UK keeps its normal operation, but is isolated from the I2C-bus lines. • Bus traffic can be started 10 µs after activating the bus again by making pin BUSENABLE HIGH. SDA tf t BUF tr SCL P S P Sr t SU;STO t HD;STA t SU;DAT t HD;DAT t HIGH t LOW t SU;STA t h(BUSEN) t su(BUSEN) BUSEN 001aaf518 tf = fall time of both SDA and SCL signals: 20 + 0.1 Cb < tf < 300 ns, where Cb = total capacitance on bus line in pF. tr = rise time of both SDA and SCL signals: 20 + 0.1 Cb < tr < 300 ns, where Cb = total capacitance on bus line in pF. tHD;STA = hold time (repeated) START condition. After this period, the first clock pulse is generated: > 600 ns. tHIGH = HIGH period of the SCL clock: > 600 ns. tSU;STA = set-up time for a repeated START condition: > 600 ns. tHD;DAT = data hold time: 300 < tHD;DAT < 900 ns. Remark: 300 ns lower limit is added because the ASIC has no internal hold time for the SDA signal. tSU;DAT = data set-up time: tSU;DAT > 100 ns. If ASIC is used in a standard mode I2C-bus system, tSU;DAT > 250 ns. tSU;STO = set-up time for STOP condition: > 600 ns. tBUF = bus free time between a STOP and a START condition: > 600 ns. Cb = capacitive load of one bus line: < 400 pF. tsu(BUSEN) = set-up time on pin BUSEN: tsu(BUSEN) > 10 µs. th(BUSEN) = hold time on pin BUSEN: th(BUSEN) > 10 µs. Fig 9. Bus timing diagram TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 17 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio 8.3 Register map Table 8. Register overview Register name I2C-bus byte number Read INTREG TNCTRL FRQCHK TUNCHK MANID CHIPID Reference R 00h Table 9 1R 0W R/W 00h Table 10 2R 1W R/W 80h Table 11 3R 2W R/W 00h Table 12 4R 3W R/W 08h Table 13 5R 4W R/W D2h Table 14 6R R - Table 15 7R R - Table 16 8R R - Table 17 R - Table 18 10R 5W R/W 00h Table 19 11R 6W R/W 00h Table 20 12R R 20h Table 22 13R R 2Bh Table 23 14R R 57h Table 24 15R R 60h Table 25 9R TESTREG Reset value Write 0R FRQSET Access 8.4 Register description 8.4.1 Register INTREG Table 9. Register INTREG - byte0R Legend: * reset value Bit Symbol Access Value Description 7 to 5 - - - not used 4 IFFLAG R 0* IF count is correct 1 IF count is not correct 3 LEVFLAG R 0* RSSI level is above VSSL[1:0] 1 RSSI level has dropped below VSSL[1:0] - not used 2 - - 1 FRRFLAG R 0 BLFLAG R 0* tuner state machine is not ready 1 tuner state machine is ready 0* during a search the band limit has not been reached or no time-out 1 during a search the band limit has been reached or time-out TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 18 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio Table 10. Register INTREG - byte1R/byte0W description Legend: * reset value Bit Symbol Access Value Description 7 to 5 - - - not used 4 IFMSK R/W 0* does not mask bit IFFLAG 1 masks bit IFFLAG 0* does not mask bit LEVFLAG 3 LEVMSK R/W 1 masks bit LEVFLAG 2 - - - restricted for RDS usage 1 FRRMSK R/W 0* does not mask bit FRRFLAG 1 masks bit FRRFLAG 0 BLMSK R/W 0* does not mask bit BLFLAG 1 masks bit BLFLAG 8.4.2 Register FRQSET Table 11. Register FRQSET - byte2R/byte1W description Legend: * reset value Bit Symbol Access Value Description 7 SUD R/W 0 search down 1* search up 6 5 to 0 SM FR_[13:08] R/W R/W 0* Preset mode 1 Search mode 00 0000* frequency set; FR_13 is MSB Table 12. Register FRQSET - byte3R/byte2W description Legend: * reset value Bit Symbol Access Value Description 7 to 0 FR_[07:00] R/W 00*h frequency set; FR_00 is LSB 8.4.3 Register TNCTRL Table 13. Register TNCTRL - byte4R/byte3W Legend: * reset value Bit Symbol Access Value Description 7 - R/W - not used 6 PUPD R/W 5 BLIM R/W 4 SWPM R/W 3 IFCTC R/W power-up power-down MSB 0* FM off 1 FM on 0* US/Europe FM band 87.5 MHz to 108 MHz 1 Japan FM band 76 MHz to 90 MHz 0* software port is output of bit SWP 1 software port is output of bit FRRFLAG 0 IF count time = 1.953 ms 1* IF count time = 15.625 ms TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 19 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio Table 13. Register TNCTRL - byte4R/byte3W …continued Legend: * reset value Bit Symbol Access Value Description 2 AFM R/W 0* audio not muted 1 left and right audio muted 1 0 SMUTE R/W SNC R/W 0* soft mute off 1 soft mute on 0* stereo noise cancellation off 1 stereo noise cancellation on Table 14. Register TNCTRL - byte5R/byte4W description Legend: * reset value Bit Symbol Access Value Description 7 MU R/W 1 1 = L- and R- audio hard muted; 0 = no hard mute 6 and 5 SSL_[1:0] R/W 4 3 2 1 0 HLSI R/W MST R/W SWP R/W DTC R/W AHLSI R/W search stop level 00 ADC3 01 ADC5 10* ADC7 11 ADC10 0 low-side injection 1* high-side injection 0* stereo on 1 forced mono 0* SWPORT = LOW 1 SWPORT = HIGH 0 de-emphasis time constant = 75 µs 1* de-emphasis time constant = 50 µs 0* tuner will search continuously 1 tuner will stop during search on failed IF count and correct level 8.4.4 Register FRQCHK Table 15. Register FRQCHK - byte6R description Bit Symbol Access Value Description 7 and 6 - - - not used 5 to 0 PLL_[13:08] R - frequency found; PLL_13 is MSB Table 16. Register FRQCHK - byte7R description Bit Symbol Access Value Description 7 to 0 PLL_[07:00] R - frequency found; PLL_00 is LSB TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 20 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio 8.4.5 Register TUNCHK Table 17. Register TUNCHK - byte8R description Bit Symbol Access Value Description 7 to 1 IF_[6:0] R - IF count; IF_6 is MSB, IF_0 is LSB 0 TUNTO R 0 PLL has settled 1 PLL tuning time-out Table 18. Register TUNCHK - byte9R description Bit Symbol Access Value Description 7 to 4 LEV_[3:0] R - level count; LEV_3 is MSB, LEV_0 is LSB 3 LD R 0 PLL is not locked 1 PLL is locked 0 mono 1 stereo - not used 2 STEREO R 1 and 0 - - 8.4.6 Register TESTREG Table 19. Register TESTREG - byte10R/byte5W description Legend: * reset value Bit Symbol Access Value Description 7 LHM R/W 0* left audio output is not muted 1 left audio output is hard muted 6 RHM R/W 0* right audio output is not muted 1 right audio output is hard muted 5 to 3 - R/W - not used 2 TUN R/W 0 no tuning programming error 1 tuning programming error 1 RFAGC R/W 0* RFAGC on 1 RFAGC off 0* no interrupt generated on INTX 1 when INTCTRL is set to 1 and TM = 1; generates an interrupt on INTX 0 INTCTRL R/W Table 20. Register TESTREG - byte11R/byte6W description Legend: * reset value Bit Symbol Access Value Description 7 and 6 - R/W - not used 5 SNCLEV R/W 1* starting point mono/stereo blending, this is a write only bit 0 30 µV (EMF value) 1* 15 µV (EMF value) TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 21 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio Table 20. Register TESTREG - byte11R/byte6W description …continued Legend: * reset value Bit Symbol Access Value Description 4 TM R/W 0* normal operation 1 TEA5760UK in Test mode and software port outputs according to Table 21 0*h test bits, Table 21 describes selection of output signals available at the SWPORT 3 to 0 TB_[3:0] Table 21. SWPORT R/W Bit Output signal Output pin TM TB_3 TB_2 TB_1 TB_0 0/1 0 0 0 0 bit SWP of byte4W (SWPM = 0) or FRRFLAG (SWPM = 1) SWPORT 1 0 0 0 1 oscillator output 32.768 kHz SWPORT 1 0 0 1 0 lock detect bit LD SWPORT 1 0 0 1 1 stereo bit STEREO SWPORT 1 0 1 0 0 programmable divider SWPORT 1 0 1 0 1 programmable divider INTX 8.4.7 Register MANID Table 22. Register MANID - byte12R description Legend: * reset value Bit Symbol Access Value Description 7 to 4 VERSION[3:0] R 0010* version code 3 to 0 MAN_ID[10:07} R 0000* manufacturer ID code Table 23. Register MANID - byte13R description Legend: * reset value Bit Symbol Access Value Description 7 to 1 MAN_ID[06:00] R 000 0101* manufacturer ID code 0 IDAV R 0 chip has no manufacturer ID 1* chip has manufacturer ID (available in IIC mode) 8.4.8 Register CHIPID Table 24. Register CHIPID - byte14R description Legend: * reset value Bit Symbol Access Value Description 7 to 0 CHIP_ID[15:08] R 57*h TEA5760UK chip identification code Table 25. Register CHIPID - byte15R description Legend: * reset value Bit Symbol Access Value Description 7 to 0 CHIP ID[07:00] R 60*h TEA5760UK chip identification code TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 22 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio 9. Limiting values Table 26. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). The quality requirements are derived from the GQS - General Quality Specification. Symbol Parameter Conditions Min Max Unit VLO1 voltage on pin LO1 −0.6 +3.6 V VLO2 voltage on pin LO2 −0.6 +3.6 V VCCD digital supply voltage −0.6 +3.6 V VCCA analog supply voltage −0.6 +3.6 V VI input voltage with respect to ground −0.6 +3.6 V VO output voltage with respect to ground −0.6 +3.6 V Tstg storage temperature −40 +125 °C Tamb ambient temperature TEA5760UK functional, specification not guaranteed −35 +85 °C Vesd electrostatic discharge voltage MM [1] −200 +200 V HBM [2] −2000 +2000 V −1750 +1750 V −500 +500 V all pins, except pin FREQIN pin FREQIN [3] CDM [1] MM: Machine Model; R = 0 Ω and C = 200 pF. [2] HBM: Human Body Model; R = 1.5 kΩ and C = 100 pF. [3] CDM: Charged Device Model; JEDEC Standard JESD22-C101. 10. Recommended operating conditions Table 27. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit Reference clock 32.768 kHz f frequency Tamb = 25 °C - 32.768 - ∆f/f relative frequency difference Tamb = 25 °C −20 × 10-6 - Tamb = −20 °C to +85 °C −150 × 10-6 - +150 × 10-6 δ duty cycle square wave 30 - 70 % tr rise time - - 50 ns tf fall time - - 50 ns VIH HIGH-level input voltage 1.0 - VCCD V VIL LOW-level input square wave voltage 0 - 0.7 V square wave TEA5760UK_1 Product data sheet kHz +20 × 10-6 © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 23 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio 11. Characteristics The IEC filter as mentioned in the characteristics is defined in IEC60315-4. The audio bandwidth of this filter is between 200 Hz and 15 kHz. The characteristics are valid under restriction of the reference clock as specified in Section 10. Table 28. General characteristics Symbol Parameter VCCA VCC(VCO) Min Typ Max Unit analog supply voltage 2.6 2.7 3.6 V VCO supply voltage 2.6 2.7 3.6 V VCCD digital supply voltage 2.6 2.7 3.6 V ICCA analog supply current - 8.7 10 mA ICC(VCO) VCO supply current ICCD digital supply current Conditions operational Standby mode - 1 3 µA operational - 5 7 mA Standby mode - 0.8 2 µA operational - 350 450 µA Standby mode - 5 10 µA Sleep mode; BUSEN = HIGH - 16 25 µA VVREFDIG voltage on pin VREFDIG VVREFDIG ≤ VCCD 1.65 1.8 3.6 V IVREFDIG current on pin VREFDIG operational - 1 10 µA Standby mode - 1 1 µA 76 - 108 MHz −20 - +85 °C fi(FM) Tamb FM input frequency [1] ambient temperature [2] [1] Fulfill specifications. [2] Functional, indication required for reduced performance. Table 29. Characteristics All AC values are given in RMS unless otherwise specified. The minimum and maximum values include spread due to: voltage between 2.6 V and 3.6 V; Tamb = −20 °C to +85 °C; reference frequency offset plus deviation and process spread. VVREFDIG = 1.65 V to 3.6 V. Symbol Parameter Conditions Min Typ Max Unit Antenna input including matching circuit Zi input impedance fRF = 76 MHz to 108 MHz - 50 - Ω |s11|2 input return loss fRF = 76 MHz to 108 MHz −5 - - dB 150 - 217 MHz 0.925 1.0 V Voltage controlled oscillator fVCO VCO frequency Reference frequency input: pin FREQIN VFREQIN voltage on pin FREQIN switching level 0.7 Ri input resistance 500 - - kΩ Ci input capacitance - - 7 pF TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 24 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio Table 29. Characteristics …continued All AC values are given in RMS unless otherwise specified. The minimum and maximum values include spread due to: voltage between 2.6 V and 3.6 V; Tamb = −20 °C to +85 °C; reference frequency offset plus deviation and process spread. VVREFDIG = 1.65 V to 3.6 V. Symbol Parameter Conditions Min Typ Max Unit ms Synthesizer Programmable divider ts settling time single frequency jump in any direction to a frequency within the frequency band (87.5 MHz to 108 MHz or 76 MHz to 90 MHz); settling limit is ±5 kHz of target frequency - - 40 Dprog programmable divider maximum; FRQSET[15:8] = XX01 1111; FRQSET[7:0] = 1111 1111 - - 8191 minimum; FRQSET[15:8] = XX00 1000; FRQSET[7:0] = 0000 0000 2048 - - - 1 - - 100 - kHz - 7 - bit - - 3[1] µV - 3C hex Dprog(step) programmable divider step fstep step frequency synthesizer auto search frequency IF counter NIFc IF counter length Vsens sensitivity voltage NIFc(result) IF counter result for search stop; stop level 3 V < VRF[1] < 2 V 31 49 - 60 dec T period IFCTC = 1 - 15625 - µs IFCTC = 0 - 1953 - µs - 4096 - Hz MΩ NIFc(res) IF counter resolution Logic pins: pins BUSEN, CLOCK and DATA RI input resistance 10 - - VIH HIGH-level input voltage 0.7 × VVREFDIG - VVREFDIG + V 0.3 VIL LOW-level input voltage −0.3 - 0.3 × VVREFDIG V VVREFDIG V Software multi functional port pin: SWPORT VO(max) maximum output voltage Iload = 150 µA VVREFDIG − 0.25 VO(min) minimum output voltage Iload = 150 µA 0 0.2 0.45 V Isink sink current VSWPORT = 1.8 V 500 - - µA Isource source current VSWPORT = 0 V 500 - - µA Pin INTX VO(max) maximum output voltage VO(min) minimum output voltage 1.65 V ≤ VVREFDIG; pull-up resistor of second device connected to INTX 18 kΩ ± 20 % TEA5760UK_1 Product data sheet VVREFDIG − 0.2 VVREFDIG + V 0.2 0 0.22 × VVREFDIG - V © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 25 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio Table 29. Characteristics …continued All AC values are given in RMS unless otherwise specified. The minimum and maximum values include spread due to: voltage between 2.6 V and 3.6 V; Tamb = −20 °C to +85 °C; reference frequency offset plus deviation and process spread. VVREFDIG = 1.65 V to 3.6 V. Symbol Parameter Conditions Min Typ Max Unit Isink sink current including internal Rpu(int) 600 900 1100 µA Rpu(int) internal pull-up resistance 14.4 18 24 kΩ tp pulse duration 9 - 10 ms 2[1] 3.0[1] µV - dBa FM signal channel FM RF input Vsens sensitivity voltage fRF = 76 MHz to 108 MHz; ∆f = 22.5 kHz; fmod = 1 kHz; S+N/N = 26 dB; τdeemp = 50 µs; L = R; IEC filter + A-weighting filter - S/N signal-to-noise ratio fRF = 76 MHz to 108 MHz; ∆f = 22.5 kHz; fmod = 1 kHz; L = R; τdeemp = 50 µs; VRF = 10 µV (EMF value); IEC filter + A-weighting filter 45 IP3ib in-band third-order intercept point ∆f1 = 200 kHz; ∆f2 = 400 kHz; fRF = 76 MHz to 108 MHz; RF AGC is off 82[1] 95[1] - dBµV IP3ob out-band third-order intercept point ∆f1 = 4 MHz; ∆f2 = 8 MHz; fRF = 76 MHz to 108 MHz; RF AGC is off 88[1] 100[1] - dBµV 220 225 230 kHz IF filter fc center frequency S200 200 kHz selectivity ∆f = ±200 kHz; fRF = 76 MHz to 108 MHz;measured according to EN55020; τdeemp = 50 µs 16 - - dB SFM FM selectivity ∆fmin = 300 kHz; fRF = 76 MHz to 108 MHz; except image frequency band measured according to EN55020; τdeemp = 50 µs 35 - - dB αf(image) image frequency rejection ∆f = 450 kHz; measured according to EN55020; image rejection defined as difference between image and co-channel response; τdeemp = 50 µs 25 - - dB FM IF level detector and mute voltage; see Figure 10 ∆G deviation from average curve −2 +2 dB VADC(start) start ADC voltage extrapolated 0.75[1] 1.6[1] 2.5[1] µV GADC(step) step of ADC gain average 2.5 2.8 3 dB SMUTE = 1 3[1] 3.8[1] 5[1] µV 5 5.8 8 dB gain deviation Soft mute Vmute(start) start mute voltage αmute mute attenuation µV[1], VRF = 1.26 L = R; ∆f = 22.5 kHz; fmod = 1 kHz; τdeemp = 75 µs; IEC filter; SMUTE = 1 TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 26 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio Table 29. Characteristics …continued All AC values are given in RMS unless otherwise specified. The minimum and maximum values include spread due to: voltage between 2.6 V and 3.6 V; Tamb = −20 °C to +85 °C; reference frequency offset plus deviation and process spread. VVREFDIG = 1.65 V to 3.6 V. Symbol Parameter Conditions Min Typ Max Unit Stereo decoder; pins VAFL and VAFR VO output voltage VRF = 2 mV[1]; L = R; ∆f = 22.5 kHz; fmod = 1 kHz; τdeemp = 75 µs 60 75 90 mV RO output resistance MU = LHM = RHM = 0; AFM = 0 or AFM = 1 250 350 400 Ω hard mute; MU = LHM = RHM = 1; AFM = 0 or AFM = 1 500 - - kΩ Standby mode; PUPD = 0 1 - - MΩ 80 100 120 µA −0.5 - +0.5 dB SNCLEV = 1 or SNC = 0 30 40 - dB SNCLEV = 0 IO output current |∆Gv| voltage gain difference VRF = 2 mV[1]; L = R; ∆f = 75 kHz; fmod = 1 kHz; IEC filter; τdeemp = 75 µs minimum load resistance = 10 kΩ αcs(stereo) stereo channel separation VRF = 2 mV[1]; ∆f = 75 kHz including 9 % pilot; R = 0 and L = 1 or R = 1 and L = 0; fmod = 1 kHz; IEC filter; MST = 0; SNC = 1 27 36 - dB f−3dB(l) low frequency −3 dB point audio band; VRF = 2 mV[1]; ∆f = 22.5 kHz, L = R, pre-emphasis = 75 µs; τdeemp = 75 µs - - 20 Hz f−3dB(h) high frequency −3 dB point audio band; VRF = 2 mV[1]; ∆f = 22.5 kHz, L = R, pre-emphasis = 75 µs; τdeemp = 75 µs 15 - - kHz (S+N)/N signal plus noise-to-noise ratio VRF = 2 mV[1]; ∆f = 22.5 kHz; L = R; fmod = 1 kHz; τdeemp = 50 µs; IEC filter + A-weighting filter mono 53 57 - dBA stereo; ∆fpilot = 6.75 kHz 49 53 - dBA - - −60 dBA ∆f = 75 kHz; fmod = 400 Hz - 0.4 0.8 % ∆f = 75 kHz; fmod = 1 kHz - 0.4 0.8 % ∆f = 75 kHz; fmod = 3 kHz - 0.4 0.8 % ∆f = 100 kHz; fmod = 1 kHz - 0.5 1 % αresp(sp) spurious response relative to ∆f = 22.5 kHz; fm = 1 kHz (mono); VRF = 2 mV[1]; τdeemp = 50 µs; IEC filter + A-weighting filter THD total harmonic distortion mono; VRF = 2 mV[1]; L = R; τdeemp = 75 µs stereo; VRF = 2 mV[1]; ∆f = 75 kHz; L = R including 9 % pilot; τdeemp = 75 µs fmod = 1 kHz - 0.5 1.5 % fmod = 3 kHz - 0.5 1.5 % TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 27 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio Table 29. Characteristics …continued All AC values are given in RMS unless otherwise specified. The minimum and maximum values include spread due to: voltage between 2.6 V and 3.6 V; Tamb = −20 °C to +85 °C; reference frequency offset plus deviation and process spread. VVREFDIG = 1.65 V to 3.6 V. Symbol Parameter Conditions αAM AM suppression L = R; ∆f = 22.5 kHz; fmod = 1 kHz; m = 0.3; τdeemp = 75 µs, IEC filter Min Typ Max Unit VRF = 20 µV [1] 40 - - dB VRF = 200 µV to 20 mV [1] 45 - - dB 40 50 - dB αpilot pilot suppression related to ∆f = 75 kHz; including 9 % pilot; L = 0 and R = 1 or L = 1 and R = 0; fmod = 1 kHz; τdeemp = 75 µs ∆fpilot pilot frequency deviation stereo; required for pilot detection; VRF = 2 mV [1] 1.8 3.6 5.8 kHz αhys(pilot) pilot hysteresis switch of pilot; VRF = 2 mV [1] 2 2.5 5 dB τdeemp de-emphasis time constant DTC = 1 40 50 60 µs DTC = 0 60 75 90 µs SNCLEV = 0 20[1] 30[1] 40[1] µV SNCLEV = 1 10[1] 15[1] 20[1] µV VRF = 80 µV (EMF value); ∆f = 75 kHz; R = 0 + L = 1 or R = 1 + L = 0; including 9 % pilot; fmod = 1 kHz; MST = 0; SNC = 1 + SNCLEV = 1 or SNC = 0 4 10 16 dB ∆f = 75 kHz, including 9 % pilot; fmod = 1 kHz; SNC = 0 60[1] 80[1] 110[1] µV ∆f = 75 kHz, including 9 % pilot; fmod = 1 kHz; SNC = 0 2 3 4 dB AFM = 1 or RHM = 1 - - −60 dB AFM = 1 or LHM = 1 - - −60 dB MU = 1 - - −80 dB Mono/stereo blend Vstart(blend) blend start voltage αcs(stereo) stereo channel separation stereo channel separation = 1 dB; SNC = 1 Mono/stereo switching switch voltage Vsw |∆Vsw/Vsw| switch voltage deviation over switch voltage ratio Bus driven mute functions Tuning mute αmute [1] mute attenuation ∆f = 75 kHz; mono, IEC filter EMF value. TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 28 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio 15 ADC level 10 5 0 1 Vstart(ADC) 10 G ∆G 102 Vsens (µV) 103 001aaf263 VADC(start) is the starting point of the curve. Taking the starting point the curve shows a monotone increase, increasing with the average step size GADC(step). The maximum deviation from the average curve is ∆G Fig 10. FM IF level detector and mute voltage 12. Application information Table 30. List of components Symbol Value Type L1 120 nH Murata LQW15ANR12J00 or equivalent, minimum Q = 20 (f = 100 MHz), tolerance = ±5 % L2 47 nH Murata LQW15AN47NJ00 or equivalent, minimum Q = 25 (f = 250 MHz), tolerance = ±5 % R 10 kΩ, 100 kΩ tolerance = ±10 % (max). C 27 pF, 47 pF, 100 pF, 10 nF, 100 nF (2 ×) tolerance = ±10 % (max). TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 29 of 36 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx MPXOUT VAFL VAFR NXP Semiconductors TEA5760UK_1 Product data sheet GND(A1) GND(A2) TMUTE 100 nF B5 D5 FREQIN VCCA C1 A6 IF AGC FM antenna Rev. 01 — 14 December 2006 L1 120 nH 47 pF AUTO ALIGN POWER SUPPLY IF FILTER LIMITER ÷2 N1 I/Q MIXER 1st FM 100 pF 27 pF E4 E5 E6 D6 REFERENCE BUFFER TEA5760UK SOFT MUTE DEMODULATOR IF COUNT MPX DECODER RFIN1 B6 RFIN2 C6 SDS LEVEL ADC RF AGC GND(RF) C5 mono B2 pilot prog. div out ref. div out I2C-BUS INTERFACE TUNING SYSTEM D3 GND(D2) D1 MUX VCO A2 LOOPSW A3 A4 CPOUT LO1 LO2 A5 SWPORT C2 BUSEN E3 E2 CLOCK VREFDIG 30 of 36 © NXP B.V. 2006. All rights reserved. 100 kΩ VCC(VCO) E1 D2 GND(D1) DATA 001aaf261 TEA5760UK 47 nH 10 kΩ Fig 11. Application diagram B1 Single chip FM stereo radio 100 nF VCCD SW PORT A1 L2 10 nF INTX TEA5760UK NXP Semiconductors Single chip FM stereo radio 13. Package outline WLCSP25: wafer level chip-size package; 25 bumps; 3 x 2.8 x 0.6 mm A B D TEA5760UK bump A1 index area A2 E A A1 detail X e1 1/2 e ∅v ∅w b e M M C C A B C y E e D e2 C e3 B A 1 2 3 4 5 6 X 0 1 2 3 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 A2 b D E e e1 e2 e3 v w y mm 0.64 0.26 0.22 0.38 0.34 0.34 0.30 3.1 3.0 2.9 2.8 0.5 2.5 2 0.028 0.01 0.04 0.02 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-12-09 06-07-06 TEA5760UK Fig 12. Package outline TEA5760UK (WLCSP25) TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 31 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio 14. Soldering 14.1 Introduction to soldering WLCSP packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in Application Note AN10439 “Wafer Level Chip Scale Package” and in Application Note AN10365 “Surface mount reflow soldering description”. Wave soldering is not suitable for this package. 14.2 Board mounting Board mounting of a WLCSP requires several steps: 1. Solder paste printing on the PCB 2. Component placement with a pick and place machine 3. The reflow soldering itself 14.3 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 13) than a PbSn process, thus reducing the process window • Solder paste printing issues, such as smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature), and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic) while being low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 31 and 32 Table 31. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 32. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 32 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 13. maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 13. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14.3.1 Stand off The stand off between the substrate and the chip is determined by: • The amount of printed solder on the substrate • The size of the solder land on the substrate • The bump height on the chip The higher the stand off, the better the stresses are released due to TEC (Thermal Expansion Coefficient) differences between substrate and chip. 14.3.2 Quality of solder joint A flip-chip joint is considered to be a good joint when the entire solder land has been wetted by the solder from the bump. The surface of the joint should be smooth and the shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps after reflow can occur during the reflow process in bumps with high ratio of bump diameter to bump height, i.e. low bumps with large diameter. No failures have been found to be related to these voids. Solder joint inspection after reflow can be done with X-ray to monitor defects such as bridging, open circuits and voids. TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 33 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio 14.3.3 Rework In general, rework is not recommended. By rework we mean the process of removing the chip from the substrate and replacing it with a new chip. If a chip is removed from the substrate, most solder balls of the chip will be damaged. In that case it is recommended not to re-use the chip again. Device removal can be done when the substrate is heated until it is certain that all solder joints are molten. The chip can then be carefully removed from the substrate without damaging the tracks and solder lands on the substrate. Removing the device must be done using plastic tweezers, because metal tweezers can damage the silicon. The surface of the substrate should be carefully cleaned and all solder and flux residues and/or underfill removed. When a new chip is placed on the substrate, use the flux process instead of solder on the solder lands. Apply flux on the bumps at the chip side as well as on the solder pads on the substrate. Place and align the new chip while viewing with a microscope. To reflow the solder, use the solder profile shown in Application Note AN10365 “Surface mount reflow soldering description”. 14.3.4 Cleaning Cleaning can be done after reflow soldering. 15. Revision history Table 33. Revision history Document ID Release date Data sheet status Change notice Supersedes TEA5760UK_1 20061214 Product data sheet - - TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 34 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 17. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] TEA5760UK_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 14 December 2006 35 of 36 TEA5760UK NXP Semiconductors Single chip FM stereo radio 18. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.12.1 6.12.2 6.12.3 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.19.1 6.19.2 6.19.3 6.19.4 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.4.1 7.1.4.2 7.1.4.3 7.1.4.4 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Low noise RF amplifier . . . . . . . . . . . . . . . . . . . 5 FM mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Reference frequency . . . . . . . . . . . . . . . . . . . . 5 PLL tuning system . . . . . . . . . . . . . . . . . . . . . . 5 Band limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 RF AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 IF filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 FM demodulator . . . . . . . . . . . . . . . . . . . . . . . . 6 IF counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Level voltage generator and analog-to-digital converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Hard mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Audio Frequency Mute (AFM). . . . . . . . . . . . . . 8 MPX decoder . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal depending mono/stereo blend (stereo noise cancellation) . . . . . . . . . . . . . . . . . . . . . . 8 Software programmable port . . . . . . . . . . . . . . 8 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9 Control interface . . . . . . . . . . . . . . . . . . . . . . . . 9 Auto search and preset mode. . . . . . . . . . . . . . 9 Search mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Preset mode . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Auto high-side and low-side injection stop switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Muting during search or preset . . . . . . . . . . . . 12 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . 12 Interrupt register . . . . . . . . . . . . . . . . . . . . . . . 12 Interrupt clearing. . . . . . . . . . . . . . . . . . . . . . . 14 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Interrupt flags and behavior . . . . . . . . . . . . . . 14 Multiple interrupt events . . . . . . . . . . . . . . . . . 14 IF frequency: IFFLAG . . . . . . . . . . . . . . . . . . . 14 RSSI threshold: LEVFLAG . . . . . . . . . . . . . . . 15 Frequency ready flag: FRRFLAG . . . . . . . . . . 15 7.1.4.5 7.2 8 8.1 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 8.4.8 9 10 11 12 13 14 14.1 14.2 14.3 14.3.1 14.3.2 14.3.3 14.3.4 15 16 16.1 16.2 16.3 16.4 17 18 Band limit: BLFLAG . . . . . . . . . . . . . . . . . . . . Interrupt line . . . . . . . . . . . . . . . . . . . . . . . . . . I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . Write and read mode . . . . . . . . . . . . . . . . . . . Data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . Register map . . . . . . . . . . . . . . . . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . . Register INTREG . . . . . . . . . . . . . . . . . . . . . . Register FRQSET . . . . . . . . . . . . . . . . . . . . . Register TNCTRL. . . . . . . . . . . . . . . . . . . . . . Register FRQCHK . . . . . . . . . . . . . . . . . . . . . Register TUNCHK . . . . . . . . . . . . . . . . . . . . . Register TESTREG . . . . . . . . . . . . . . . . . . . . Register MANID . . . . . . . . . . . . . . . . . . . . . . . Register CHIPID. . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Recommended operating conditions . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering WLCSP packages. . Board mounting . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Stand off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quality of solder joint . . . . . . . . . . . . . . . . . . . Rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 16 16 16 18 18 18 19 19 20 21 21 22 22 23 23 24 29 31 32 32 32 32 33 33 34 34 34 35 35 35 35 35 35 36 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2006. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 14 December 2006 Document identifier: TEA5760UK_1