UC1875-SP SLUSAQ9 – DECEMBER 2011 www.ti.com RAD-TOLERANT CLASS-V, PHASE SHIFT RESONANT CONTROLLER Check for Samples: UC1875-SP FEATURES DESCRIPTION • • • • The UC1875-SP implements control of a bridge power stage by phase-shifting the switching of one half-bridge with respect to the other, allowing constant frequency pulse-width modulation in combination with resonant, zero-voltage switching for high efficiency performance at high frequencies. This circuit may be configured to provide control in either voltage or current mode operation, with a separate overcurrent shutdown for fast fault protection 1 • • • • • • • • • QML-V Qualified, SMD 5962-94555 Zero to 100% Duty Cycle Control Programmable Output Turn-On Delay Compatible with Voltage or Current Mode Topologies Practical Operation at Switching Frequencies to 1 MHz Four 2-A Totem Pole Outputs 10 MHz Error Amplifier Undervoltage Lockout Low Startup Current – 150 µA Outputs Active Low During UVLO Soft-Start Control Latched Overcurrent Comparator With Full Cycle Restart Trimmed Reference APPLICATIONS • Power FPGAs A programmable time delay is provided to insert a dead-time at the turn-on of each output stage. This delay, providing time to allow the resonant switching action, is independently controllable for each output pair (A-B, C-D). With the oscillator capable of operation at frequencies in excess of 2 MHz, overall switching frequencies to 1 MHz are practical. In addition to the standard free running mode, with the CLOCKSYNC pin, the user may configure these devices to accept an external clock synchronization signal, or may lock together up to 5 units with the operational frequency determined by the fastest device spacer BLOCK DIAGRAM 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated UC1875-SP SLUSAQ9 – DECEMBER 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) Protective features include an undervoltage lockout which maintains all outputs in an active-low state until the supply reaches a 10.75 V threshold. 1.5 hysteresis is built in for reliable, boot-strapped chip supply. Overcurrent protection is provided, and will latch the outputs in the OFF state within 70 nsec of a fault. The current-fault circuitry implements full-cycle restart operation. Additional features include an error amplifier with bandwidth in excess of 7 MHz, a 5 V reference, provisions for soft-starting, and flexible ramp generation and slope compensation circuitry. This device is available in hermetically sealed cerdip, surface mount, and ceramic leadless chip carrier packages for –55°C to +125°C operation. ORDERING INFORMATION TA 55°C to 125°C PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING CDIP (J) 5962-9455501VRA 5962-9455501VRA LCCC (FK) 5962-9455501V3A 5962-9455501V3A CFP (W) 5962-9455502VKA 5962-9455502VKA ABSOLUTE MAXIMUM RATINGS (1) VALUE PARAMETER MIN Supply voltage (VC, VIN) UNIT MAX 20 V 0.5 A 3 A –0.3 5.3 V –65 150 Output current, source or sink DC Pulse (0.5 µs) Analog inputs (Pins 1, 2, 3, 4, 5, 6, 7, 15, 16, 17, 18, 19) Storage temperature range Maximum junction temperature, JTmax °C 150 Thermal Resistance TJC (1) J package 7 W package 5.4 FK package 5.6 °C/W Pin references are to 20-pin packages. All voltages are with respect to ground. Currents are positive into, negative out of the device terminals. DEVICE INFORMATION UCC1875-SP 2 UVLO Turn-On UVLO Turn-Off Delay Set 10.75V 9.25V Yes Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UC1875-SP UC1875-SP SLUSAQ9 – DECEMBER 2011 www.ti.com SPACE DIL - 20 Pin LCCC - 28 Pin J Package FK Package (TOP VIEW) (TOP VIEW) VIN VC PWRGND OUTC OUTB OUTA OUTD 4 3 2 1 28 27 26 N/C 5 25 N/C N/C 6 24 DELAYSET C-D DELAYSET A-B 7 23 SS FREQSET 8 22 CS+ CLOCKSYNC 9 21 EA+ 10 20 E/A- 19 11 12 13 14 15 16 17 18 N/C SLOPE RAMP N/C N/C GND N/C E/A OUT VREF N/C CFP - 24 Pin W Package (TOP VIEW) N/C N/C 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 GND VREF RAMP E / AOUT SLOPE EAEA+ CLOCKSYNC FRQSET CS+ SOFTSTART DELAYSET A-B DELAYSET C-D OUTA OUTD OUTB OUTC PWRGND VC VIN N/C N/C Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UC1875-SP 3 UC1875-SP SLUSAQ9 – DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS –55°C < TA < 125°C. VC = VIN = 12 V, R(FREQSET) = 12 kΩ, C(FREQSET) = 330 pF, R(SLOPE) = 12 kΩ, C(RAMP) = 200 pF, C(DELAYSET A-B) = C(DELAYSET C-D) = 0.01 µF, I(DELAYSET A-B) = I(DELAYSET C-D) = –500 µA, TA = TJ, unless otherwises stated. PARAMETER TEST CONDITIONS MIN TYP MAX 10.75 11.75 1.25 2 UNIT Undervoltage Lockout Start threshold UVLO hysteresis 0.5 V Supply Current IIN Startup VIN = 8 V, VC = 20 V, R(SLOPE) open, I(DELAY) = 0 150 600 IC Startup VIN = 8 V, VC = 20 V, R(SLOPE) open, I(DELAY) = 0 10 100 IIN 30 44 IC 15 30 5 5.08 μA mA Voltage Reference Output voltage TJ = 25°C 4.92 Line regulation 11 V < VIN < 20 V 1 10 Load regulation IVREF = –10 mA 5 20 Total variation Line, Load, Temperature Noise Voltage 10 Hz to 10 kHz 50 µVrms Long Term Stability TJ = 125°C, 1000 hours 2.5 mV Short circuit current VREF = 0 V, TJ = 25°C 60 mA 4.9 5.1 V mV V Error Amplifier Offset voltage Input bias current 5 15 mV 0.6 3 μA AVOL 1 V < V(E/AOUT) < 4 V 60 CMMR 1.5 V < VCM < 5.5 V PSRR 11 V < VIN < 20 V Output sink current V(E/AOUT) = 1 V Output source current I(E/AOUT) = 4 V –1.3 –0.5 Output voltage high I (E/AOUT) = –0.5 mA 4 4.7 5 V Output voltage low I(E/AOUT) = 1 mA 0 0.5 1 V 7 11 MHz 6 11 V/μsec 1.3 V Unity Gain BW See (1) Slew rate See (1) 90 dB 75 95 dB 85 100 dB 1 2.5 mA mA PWM Comparator TJ = 25°C (2) RAMP offset voltage Zero phase shift voltage PWM phase shift Output skew (4) (5) (1) (2) (3) (4) (5) (6) 4 V(E/AOUT) > (Ramp Peak + Ramp Offset) V(E/AOUT) < Zero Phase Shift Voltage (4) (5) Ramp to output delay See (3) V(E/AOUT) > 1 V (6) (1) 0.55 0.9 96% 99.5% 104% V 0% 0.5% 2% 5 ±20 65 125 nsec Not production tested. Ramp offset voltage has a temperature coefficient of about –4 mV/°C. The zero phase shift voltage has a temperature coefficient of about –2 mV/°C. 200 Phase shift percentage (0% = 0 , 100% = 180 ) is defined as q = T f % where is the phase shift, and and T are defined in Figure 1. At 0% phase shift, is the output skew. Not production tested at –55·C. Ramp delay to output time is defined in Figure 1 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UC1875-SP UC1875-SP SLUSAQ9 – DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) –55°C < TA < 125°C. VC = VIN = 12 V, R(FREQSET) = 12 kΩ, C(FREQSET) = 330 pF, R(SLOPE) = 12 kΩ, C(RAMP) = 200 pF, C(DELAYSET A-B) = C(DELAYSET C-D) = 0.01 µF, I(DELAYSET A-B) = I(DELAYSET C-D) = –500 µA, TA = TJ, unless otherwises stated. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1 1.19 MHz 0.2% 2% Oscillator Initial accuracy TA = 25°C Voltage stability 11 V < VIN < 20 V Total variation Line, Temperature Sync pin threshold TJ = 25°C 3.8 Clock out peak TJ = 25°C 4.3 Clock out low TJ = 25°C 3.3 R(CLOCKSYNC) = 3.9 kΩ 30 Clock out pulse width Maximum frequency (7) 0.85 0.8 R(FREQUEST) = 5 kΩ 1.2 MHz V 100 2 nsec MHz Ramp Generator/Slope Compensation Ramp current, minimum I(SLOPE) = 10 µA, V(FREQSET) = VREF Ramp current, maximum I(SLOPE) = 1 mA, V(FREQSET) = VREF –11 –0.8 Ramp valley –14 µA –0.95 mA 0 Ramp peak - clamping level R(FREQSET) = 100 kΩ 3.8 4.1 2.4 85 V 5 V 2 5 μA 2.5 2.6 V 150 nsec 2 10 μA 2 2.15 V 110 300 ns –3 Current Limit Input bias VCS+ = 3 V Threshold voltage Delay to output (8) Cycle-by-Cycle Current Limit Input bias VCS = 2.2 V Threshold voltage 1.85 Delay to output zero phase Soft Start/Reset Delay Charge current V(SOFTSTART) = 0.5 V –20 –9 Discharge current V(SOFTSTART) = 1 V 120 230 Restart threshold 4.3 Discharge level μA 4.7 V 300 mV Output Drivers Output low level IOUT = 50 mA 0.2 0.4 Output high level IOUT = –50 mA 1.5 2.5 V Delay Set I(DELAY) = –500 µA Delay set voltage Delay time (8) I(DELAY) = –250 µA (9) (7) (8) Not production tested at –55·C. Not production tested. (9) Delay time can be programmed via resistors from the delay set pins to ground. Delay time = Where I(DELAY) = 2.3 2.4 2.6 V 150 250 600 nsec 62.5 x 10-12 I(DELAY) . Delay set voltage . The Recommended range for I(DELAY) is 25 µA ≤ I(DELAY) ≤ 1 mA. R(DELAY) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UC1875-SP 5 UC1875-SP SLUSAQ9 – DECEMBER 2011 www.ti.com SPACER Duty Cycle = t/T, Period = T TDHL (A to C) = TDHL (B to D) = Φ Figure 1. Phase Shift, Output Skew and Delay Time Definitions Figure 2. Ramp to Delay Output 6 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UC1875-SP UC1875-SP SLUSAQ9 – DECEMBER 2011 www.ti.com PIN DESCRIPTIONS CLKSYNC (bi-directional clock and synchronization pin): Used as an output, this pin provides a clock signal. As an input, this pin provides a synchronization point. In its simplest usage, multiple devices, each with their own local oscillator frequency, may be connected together by the CLOCKSYNC pin and will synchronize on the fastest oscillator. This pin may also be used to synchronize the device to an external clock, provided the external signal is of higher frequency than the local oscillator. A resistor load may be needed on this pin to minimize the clock pulse width. E/AOUT (Error Amplifier Output): This is is the gain stage for overall feedback control. Error amplifier output voltage levels below 1 volt will force 0° phase shift. Since the error amplifier has a relatively low current drive capability, the output may be overridden by driving with a sufficiently low impedance source. CS+ (Current Sense): The non-inverting input to the current-fault comparator whose reference is set internally to a fixed 2.5 V (separate from VREF). When the voltage at this pin exceeds 2.5 V the current-fault latch is set, the outputs are forced OFF and a SOFT-START cycle is initiated. If a constant voltage above 2.5 V is applied to this pin the outputs are disabled from switching and held in a low state until the CS+ pin is brought below 2.5 V. The outputs may begin switching at 0 degrees phase shift before the SOFTSTART pin begins to rise -- this condition will not prematurely deliver power to the load. FREQSET (Oscillator Frequency Set pin): A resistor and a capacitor from FREQSET to GND will set the oscillator frequency. DELSETA-B, DELSETC-D (Output Delay Control): The user programmed current flowing from these pins to GND set the turn-on delay for the corresponding output pair. This delay is introduced between turn-off of one switch and turn-on of another in the same leg of the bridge to provide a dead time in which the resonant switching of the external power switches takes place. Separate delays are provided for the two half-bridges to accommodate differences in the resonant capacitor charging currents. EA– (Error Amplifier Inverting Input): This is normally connected to the voltage divider resistors which sense the power supply output voltage level. EA+ (Error Amplifier Non-Inverting Input): This is normally connected to a reference voltage used for comparison with the sensed power supply output voltage level at the EA+ pin. GND (Signal Ground): All voltages are measured with respect to GND. The timing capacitor, on the FREQSET pin, any bypass capacitor on the VREF pin, bypass capacitors on VIN and the ramp capacitor, on the RAMP pin, should be connected directly to the ground plane near the signal ground pin. OUTA – OUTD (Outputs A-D): The outputs are 2 A totem-pole drivers optimized for both MOSFET gates and level-shifting transformers. The outputs operate as pairs with a nominal 50% duty-cycle. The A-B pair is intended to drive one half-bridge in the external power stage and is syncronized with the clock waveform. The C-D pair will drive the other half-bridge with switching phase shifted with respect to the A-B outputs. PWRGND (Power Ground): VC should be bypassed with a ceramic capacitor from the VC pin to the section of the ground plane that is connected to PWRGND. Any required bulk reservoir capacitor should parallel this one. Power ground and signal ground may be joined at a single point to optimize noise rejection and minimize DC drops. RAMP (Voltage Ramp): This pin is the input to the PWM comparator. Connect a capacitor from here to GND. A voltage ramp is developed at this pin with a slope: dV Sense Voltage = dT R(SLOPE) x C(RAMP) Current mode control may be achieved with a minimum amount of external circuitry, in which case this pin provides slope compensation. Because of the 1.3 V offset between the ramp input and the PWM comparator, the error amplifier output voltage can not exceed the effective ramp peak voltage and duty cycle clamping is easily achievable with appropriate values of R(SLOPE) and C(RAMP). SLOPE (Set Ramp Slope/Slope Compensation): A resistor from this pin to VCC will set the current used to generate the ramp. Connecting this resistor to the DC input line voltage will provide voltage feed-forward. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UC1875-SP 7 UC1875-SP SLUSAQ9 – DECEMBER 2011 www.ti.com SOFTSTART:(soft start): SOFTSTART will remain at GND as long as VIN is below the UVLO threshold. SOFTSTART will be pulled up to about 4.8 V by an internal 9 µA current source when VIN becomes valid (assuming a non-fault condition). In the event of a current-fault (CS+ voltage exceeding 2.5 V), SOFTSTART will be pulled to GND and them ramp to 4.8 V. If a fault occurs during the SOFTSTART cycle, the outputs will be immediately disabled and SOFTSTART must charge fully prior to resetting the fault latch. For paralleled controllers, the SOFTSTART pins may be paralled to a single capacitor, but the charge currents will be additive. VC (Output Switch Supply Voltage): This pin supplies power to the output drivers and their associated bias circuitry. Connect VC to a stable source above 3 V for normal operation, above 12 V for best performance. This supply should be bypassed directly to the PWRGND pin with low ESR, low ESL capacitors VIN (Primary Chip Supply Voltage): This pin supplies power to the logic and analog circuitry on the integrated circuit that is not directly associated with driving the output stages. Connect VIN to a stable source above 12 V for normal operation. To ensure proper chip functionality, these devices will be inactive until VIN exceeds the upper undervoltage lockout threshold. This pin should by bypassed directly to the GND pin with low ESR, low ESL capacitors. NOTE When VIN exceeds the UVLO threshold the supply current (IIN) will jump from about 100 µA to a current in excess of 20 µA. If the UC1875-SP is not connected to a well bypassed supply, it may immediately enter UVLO again. VREF: This pin is an accurate 5 V voltage reference. This output is capable of delivering about 60 mA to peripheral circuitry and is internally short circuit current limited. VREF is disabled while VIN is low enough to force the chip into UVLO. The circuit is also in UVLO until VREF reaches approximately 4.75 V. For best results bypass VREF with a 0.1 µF, low ESR, low ESL, capacitor to the GND pin. 8 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UC1875-SP UC1875-SP SLUSAQ9 – DECEMBER 2011 www.ti.com APPLICATION INFORMATION Undervoltage Lockout Section When power is applied to the circuit and VIN is below the upper UVLO threshold, IIN will be below 600 µA, the reference generator will be off, the fault latch is reset, the soft-start pin is discharged, and the outputs are actively held low. When VIN exceeds the upper UVLO threshold, the reference generator turns on. All else remains in the shut-down mode until the output of the reference, VREF, exceeds 4.75 V. VIN 10.75V/9.25V GATE REFERENCE GENERATOR INTERNAL BIAS VREF TO SOFT START LOGIC GND 4.75V Figure 3. Undervoltage Circuit The high frequency oscillator may be either free-running or externally synchronized. For free-running operation, the frequency is set via an external resistor and capacitor to ground from the FREQSET pin. Figure 4. Simplified Oscillator Schematic Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UC1875-SP 9 UC1875-SP SLUSAQ9 – DECEMBER 2011 www.ti.com Synchronizing The Oscillator The CLOCKSYNC pin of the oscillator may be used to synchronize multiple UC1875-SP device by connecting the CLOCKSYNC of each UC1875-SP to the others: Figure 5. ALL ICs will sync to the chip with the fastest local oscillator. R1 and RN may be needed to keep sync pulse narrow due to capacitance on line. R1 and RN may also be needed to properly terminate R(SYNC) line. Syncing to External TTL/CMOS FREQSET FREQSET FREQSET IC1 IC2 ICN TTL LOGIC CLOCKSYNC CLOCKSYNC CLOCKSYNC RN R1 Figure 6. ICs will sync to the fastest chip or TTL clock if it is higher frequency. R1 and RN may be needed to keep sync pulse narrow due to capacitance on line. R1 and RN may also be needed to properly terminate R(SYNC) line. Although the UC1875-SP has a local oscillator frequency, the device will synchronize to the fastest oscillator driving the CLOCKSYNC pin. This arrangement allows the synchronizing connection between ICs to be broken without any local loss of functionality. Synchronizing the device to an external clock signal may be accomplished with a minimum of external circuitry, as shown in Figure 6. Capacitive loading on the CLOCKSYNC pin will increase the clock pulse width, and may adversely effect system performance. Therefore, a resistor to ground from the CLOCKSYNC pin is optional, but may be required to offset capacitive loading on this pin. These resistors are shown in the oscillator schematics as R1, RN. 10 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UC1875-SP UC1875-SP SLUSAQ9 – DECEMBER 2011 www.ti.com Delay Blocks and Output Stages In each of the output stages, transistors Q3 through Q6 form a high-speed totem-pole driver which will source or sink more than one amp peak with a total delay of approximately 30 nanoseconds. To ensure a low output level prior to turn-on, transistors Q7 through Q9 form a self-biased driver to hold Q6 on prior to the supply reaching its turn-on threshold. This circuit is operable when the chip supply is zero. Q6 is also turned on and held low with a signal from the fault logic portion of the chip. Figure 7. The delay providing the dead-time is accomplished with C1 which must discharge to VTH before the output can go high. The time is defined by the current sources, I1, which is programmed by an external resistor, RTD. The voltage on the Delay Set pins is internally regulated to 2.5 V and the range of dead time control is from 50 to 200 nanoseconds. NOTE There is no way to disable the delay circuitry, and the delay time must be programmed. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UC1875-SP 11 UC1875-SP SLUSAQ9 – DECEMBER 2011 www.ti.com Output Switch Orientation The four outputs of the UC1875-SP interfaces to the full bridge converter switches as shown in Figure 8 15 W UC1875 15 W QA QC T1 10t 10t OUTA 10t 15 W 15 W QB OUTB 10t QD 10t 10t OUTC OUTD Figure 8. 3 Winding Bifilar, AWG 30 Kynar Insulation Fault/SoftStart The fault control circuitry provides two forms of power shutdown: • Complete turn-off of all four output power stages. • Clamping the phase shift command to zero. Complete turn-off is ordered for an over-current fault or a low supply voltage. When the SOFTSTART pin reaches its low threshold, switching is allowed to proceed while the phase-shift is advanced from zero to its nominal value with the time constant of the SOFT-START capacitor. The fault logic insures that a continuous fault will institute a low frequency “hiccup” retry cycle by forcing the SOFT-START capacitor to charge through its full cycle between each restart attempt. 12 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UC1875-SP UC1875-SP SLUSAQ9 – DECEMBER 2011 www.ti.com Figure 9. Figure 10. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UC1875-SP 13 UC1875-SP SLUSAQ9 – DECEMBER 2011 www.ti.com Slope/Ramp Pins The ramp generator may be configured for the following control methods: • Voltage Mode • Voltage Feedforward • Current Mode • Current Mode with Slope Compensation Figure 11 shows a voltage-mode configuration. With R(SLOPE) tied to a stable voltage source, the waveform on C(RAMP) will be a constant-slope ramp, providing conventional voltage-mode control. If R(SLOPE) is connected to the power supply input voltage, a variable-slope ramp will provide voltage feedforward. SUPPLY VOLTAGE R(SLOPE) SLOPE VREF RAMP CLK IN C(RAMP) Q1 Figure 11. Voltage Mode Operation 1. Simple voltage mode operation achieved by placing R(SLOPE) between VIN and SLOPE 2. Voltage Feedforward achieved by placing R(SLOPE) between supply voltage and SLOPE pin of UC1875-SP. RAMP: VRslope dV = dT RSLOPE x CRAMP For current-mode control the ramp generator may be disabled by grounding the slope pin and using the ramp pin as a direct current sense input to the PWM comparator. 14 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): UC1875-SP PACKAGE OPTION ADDENDUM www.ti.com 29-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) 5962-9455501V3A ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type 5962-9455501VRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type 5962-9455502VKA ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UC1875-SP : • Catalog: UC1875 NOTE: Qualified Version Definitions: Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 29-Aug-2012 • Catalog - TI's standard catalog product Addendum-Page 2 MECHANICAL DATA MCFP007 – OCTOBER 1994 W (R-GDFP-F24) CERAMIC DUAL FLATPACK 0.375 (9,53) 0.340 (8,64) Base and Seating Plane 0.006 (0,15) 0.004 (0,10) 0.090 (2,29) 0.045 (1,14) 0.045 (1,14) 0.026 (0,66) 0.395 (10,03) 0.360 (9,14) 0.360 (9,14) 0.240 (6,10) 1 0.360 (9,14) 0.240 (6,10) 24 0.019 (0,48) 0.015 (0,38) 0.050 (1,27) 0.640 (16,26) 0.490 (12,45) 0.030 (0,76) 0.015 (0,38) 12 13 30° TYP 1.115 (28,32) 0.840 (21,34) 4040180-5 / B 03/95 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD Index point is provided on cap for terminal identification only. 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