PHILIPS SAA7111H

INTEGRATED CIRCUITS
DATA SHEET
SAA7111
Video Input Processor (VIP)
Product specification
Supersedes data of 1996 Oct 30
File under Integrated Circuits, IC22
1998 May 15
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
CONTENTS
1
FEATURES
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
QUICK REFERENCE DATA
5
ORDERING INFORMATION
6
BLOCK DIAGRAM
7
PINNING
8
FUNCTIONAL DESCRIPTION
8.1
8.2
8.2.1
8.2.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.11.1
Analog input processing
Analog control circuits
Clamping
Gain control
Chrominance processing
Luminance processing
RGB matrix
VPO-bus (digital outputs)
Synchronization
Clock generation circuit
Power-on reset and CE input
RTCO output
The Line-21 text slicer
Suggestions for I2C-bus interface of the display
software reading line-21 data
9
GAIN CHARTS
10
LIMITING VALUES
11
CHARACTERISTICS
12
TIMING DIAGRAMS
13
CLOCK SYSTEM
13.1
13.2
Clock generation circuit
Power-on control
14
OUTPUT FORMATS
15
APPLICATION INFORMATION
15.1
Layout hints
16
I2C-BUS DESCRIPTION
16.1
16.2
16.2.1
16.2.2
16.2.3
16.2.4
16.2.5
16.2.6
16.2.7
16.2.8
16.2.9
I2C-bus format
I2C-bus detail
Subaddress 00
Subaddress 02
Subaddress 03
Subaddress 04
Subaddress 05
Subaddress 06
Subaddress 07
Subaddress 08
Subaddress 09
1998 May 15
2
16.2.10
16.2.11
16.2.12
16.2.13
16.2.14
16.2.15
16.2.16
16.2.17
16.2.18
16.2.19
16.2.20
16.2.21
Subaddress 0A
Subaddress 0B
Subaddress 0C
Subaddress 0D
Subaddress 0E
Subaddress 10
Subaddress 11
Subaddress 12
Subaddress 1A (read-only register)
Subaddress 1B (read-only register)
Subaddress 1C (read-only register)
Subaddress 1F (read-only register)
17
FILTER CURVES
17.1
17.2
17.3
Anti-alias filter curve
Luminance filter curves
Chrominance filter curves
18
I2C START SET-UP
19
PACKAGE OUTLINE
20
SOLDERING
20.1
20.2
20.3
20.3.1
20.3.2
20.3.3
20.4
Introduction
Reflow soldering
Wave soldering
PLCC
QFP
Method (PLCC and QFP)
Repairing soldered joints
21
DEFINITIONS
22
LIFE SUPPORT APPLICATIONS
23
PURCHASE OF PHILIPS I2C COMPONENTS
Philips Semiconductors
Product specification
Video Input Processor (VIP)
1
SAA7111
FEATURES
• Four analog inputs, internal analog source selectors,
e.g. 4 × CVBS or 2 × Y/C or (1 × Y/C and 2 × CVBS)
• Two analog preprocessing channels
• Fully programmable static gain for the main channels or
automatic gain control for the selected CVBS or Y/C
channel
• Switchable white peak control
• Two switchable outputs for the digitized CVBS or Y/C
input signals AD1 (7 to 0) and AD2 (7 to 0) via the
I2C-bus
• Two built-in analog anti-aliasing filters
• Chip enable function (reset for the clock generator)
• Two 8-bit video CMOS analog-to-digital converters
(ADCs)
• Compatible with memory-based features (line-locked
clock)
• On-chip clock generator
• Boundary scan test circuit complies with the
IEEE Std. 1149.1 − 1990 (ID-Code = 0 7111 02 B)
• Line-locked system clock frequencies
• I2C-bus controlled (full read-back ability by an external
controller).
• Digital PLL for H-sync processing and clock generation
• Requires only one crystal (24.576 MHz) for all standards
• Horizontal and vertical sync detection
• Automatic detection of 50/60 Hz field frequency and
automatic switching between standards PAL and NTSC
2
• Luminance and chrominance signal processing for
PAL BGHI, PAL N, PAL M, NTSC M, NTSC N and
NTSC 4.43
• Multimedia
• Desktop video
• Digital television
• Image processing
• User programmable luminance peaking or aperture
correction
• Video phone.
• Cross-colour reduction for NTSC by chrominance comb
filtering
3
• PAL delay line for correcting PAL phase errors
GENERAL DESCRIPTION
The Video Input Processor (VIP) is a combination of a
two-channel analog preprocessing circuit including source
selection, anti-aliasing filter and ADC, an automatic clamp
and gain control, a Clock Generation Circuit (CGC), a
digital multi-standard decoder (PAL BGHI, PAL M, PAL N,
NTSC M and NTSC N), a brightness/contrast/saturation
control circuit and a colour space matrix (see Fig.1).
• Real time status information output (RTCO)
• Brightness Contrast Saturation (BCS) control on-chip
• The YUV (CCIR-601) bus supports a data rate of:
– 864 × fH = 13.5 MHz for 625 line sources
– 858 × fH = 13.5 MHz for 525 line sources.
The CMOS circuit SAA7111, analog front-end and digital
video decoder, is a highly integrated circuit for desktop
video applications. The decoder is based on the principle
of line-locked clock decoding and is able to decode the
colour of PAL and NTSC signals into CCIR-601
compatible colour component values. The SAA7111
accepts as analog inputs CVBS or S-video (Y/C) from
TV or VTR sources. The circuit is I2C-bus controlled.
• Data output streams for 16, 12 or 8-bit width with the
following formats:
– 411 YUV (12-bit)
– 422 YUV (16-bit)
– 422 YUV [CCIR-656] (8-bit)
– 565 RGB (16-bit) with dither
– 888 RGB (24-bit) with special application.
• 720 active samples per line on the YUV bus
• One user programmable general purpose switch on an
output pin
• Built in line-21 text slicer
• Power-on control
1998 May 15
APPLICATIONS
3
Philips Semiconductors
Product specification
Video Input Processor (VIP)
4
SAA7111
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VDDD
digital supply voltage
4.5
5.0
5.5
V
VDDA
analog supply voltage
4.75
5.0
5.25
V
Tamb
operating ambient temperature
0
25
70
°C
PA+D
analog and digital power
0.77
1.0
1.26
W
5
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SAA7111WP
SAA7111H
1998 May 15
DESCRIPTION
PLCC68 plastic leaded chip carrier; 68 leads
QFP64
plastic quad flat package; 64 leads (lead length 1.6 mm); body
14 × 14 × 2.7 mm
4
VERSION
SOT188-2
SOT393-1
Philips Semiconductors
Product specification
Video Input Processor (VIP)
6
SAA7111
BLOCK DIAGRAM
handbook, full pagewidth
BYPASS
AOUT
23 (14)
AI11
AI12
21 (12)
AI21
17 (8)
AI22
15 (6)
ANALOG
PROCESSING
AND
ANALOG-TODIGITAL
CONVERSION
19 (10)
AD2
n.c.
VSS
CHROMINANCE
CIRCUIT
AND
BRIGHTNESS
CONTRAST
SATURATION
CONTROL
C/CVBS
(52) 63
Y
(31) 42
AD1
FEI
HREF
22 (13)
10,36,
37
ANALOG
PROCESSING
CONTROL
2
Y
I C-BUS
CONTROL
(53) 64
GPSW
2
I C-BUS
INTERFACE
LUMINANCE
CIRCUIT
(61) 4
(62) 5
Y/CVBS
(63) 6
Y
VSSA1-2
VDDA1-2
VPO
(0 : 15)
7,8,9 (64)
CON
n.c.
UV
45 to 50
53 to 62
(34 to 39)
(42 to 51)
YUV-to-RGB
CONVERSION
AND
OUTPUT
FORMATTER
IICSA
SDA
SCL
18,14 (9,5)
SAA7111
20,16 (11,7)
CLOCKS
TDI
TCK
12 (3)
TMS
13 (4)
TRST
TDO
2 (59)
1 (58)
11 (2)
TEST
CONTROL
BLOCK
FOR
BOUNDARY
SCAN TEST
AND
SCAN TEST
(57,41,33,25,18)
68,52,44,34,27
(56,40,32,26,19)
67,51,43,35,28
(54) 65
CLOCK
GENERATION
CIRCUIT
SYNCHRONIZATION
CIRCUIT
(27)
38
(17)
26
(29)
40
(21) 30
(22) 31
LFCO
(30)
41
(55) 66
(28)
39
(60)
3
POWER-ON
CONTROL
(15)
24
(16)
25
(20) 29
(23) 32
(24)
33
MGC653
VDD1-5
VSS1-5
VS
HS
VREF RTS0 RTS1 RTCO
The pin numbers given in parenthesis refer to the 64-pin package.
Fig.1 Block diagram.
1998 May 15
5
VDDA0 VSSA0
CE
XTAL
XTALI
LLC2
CREF
LLC
RES
Philips Semiconductors
Product specification
Video Input Processor (VIP)
7
SAA7111
PINNING
PINS
SYMBOL
I/O
DESCRIPTION
PLCC68
QFP64
TRST
1
58
I
Test reset input not (active LOW), for boundary scan test;
notes 1, 2, 3 and 4.
TCK
2
59
I
Test clock input for boundary scan test; note 3.
RTCO
3
60
O
Real time control output: contains information about actual system
clock frequency, subcarrier frequency and phase and PAL sequence.
IICSA
4
61
I
I2C-bus slave address select input; 0 → 48H for write, 49H for read,
1 → 4AH for write, 4BH for read.
SDA
5
62
I/O
I2C-bus serial data input/output.
SCL
6
63
I/O
I2C-bus serial clock input/output.
n.c.
7
64
−
Not connected.
n.c.
8
−
−
Not connected.
n.c.
9
−
−
Not connected.
n.c.
10
1
−
Not connected.
TDO
11
2
O
Test data output for boundary scan test; note 3.
TDI
12
3
I
Test data input for boundary scan test; note 3.
TMS
13
4
I
Test mode select input for boundary scan test or scan test; note 3.
VSSA2
14
5
GND
AI22
15
6
I
Analog input 22.
VDDA2
16
7
P
Positive supply voltage (+5 V) for analog channel 2.
AI21
17
8
I
Analog input 21.
VSSA1
18
9
GND
AI12
19
10
I
Analog input 12.
VDDA1
20
11
P
Positive supply voltage (+5 V) for analog channel 1.
AI11
21
12
I
Analog input 11.
VSSS
22
13
GND
AOUT
23
14
O
Analog test output; for testing the analog input channels.
VDDA0
24
15
P
Positive supply voltage (+5 V) for internal CGC.
VSSA0
25
16
GND
VREF
26
17
O
Vertical reference output signal (I2C-bit COMPO = 0) or inverse
composite blank signal (I2C-bit COMPO = 1) (enabled via I2C-bit
OEHV).
VDD5
27
18
P
Positive digital supply voltage 5 (+5 V).
VSS5
28
19
GND
Digital ground for positive supply voltage 5.
LLC
29
20
O
Line-locked system clock output (27 MHz).
LLC2
30
21
O
Line-locked clock 1⁄2 output (13.5 MHz).
CREF
31
22
O
Clock reference output: this is a clock qualifier signal distributed by
the CGC for a data rate of LLC2. Using CREF all interfaces on the
VPO-bus are able to generate a bus timing with identical phase.
If CCIR-656 format is selected (OFTS0 = 1 and OFTS1 = 1) an
inverse composite blank signal (pixel qualifier) is provided on this pin.
1998 May 15
Ground for analog supply voltage channel 2.
Ground for analog supply voltage channel 1.
Substrate (connected to analog ground).
Ground for internal CGC.
6
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
PINS
SYMBOL
I/O
DESCRIPTION
PLCC68
QFP64
RES
32
23
O
Reset output (active LOW); sets the device into a defined state.
All data outputs are in high impedance state. The I2C-bus is reset
(waiting for start condition) note 4.
CE
33
24
I
Chip enable; connection to ground forces a reset.
VDD4
34
25
P
Positive digital supply voltage 4 (+5 V).
VSS4
35
26
GND
n.c.
36
−
−
Not connected.
n.c.
37
−
−
Not connected.
HS
38
27
O
Horizontal sync output signal (programmable); the positions of the
positive and negative slopes are programmable in 8 LLC increments
over a complete line (equals 64 µs) via I2C-bus bytes HSB and HSS.
Fine position adjustment in 2 LLC increments can be performed via
I2C-bits HDEL1 and HDEL0.
RTS1
39
28
O
Two functions output; controlled by I2C-bit RTSE1.
RTSE1 = 0: PAL line identifier (LOW = PAL line); indicates the
inverted and non-inverted R − Y component for PAL signals.
RTSE1 = 1: H-PLL locked indicator; a high state indicates that the
internal horizontal PLL has locked.
RTS0
40
29
O
Two functions output; controlled by I2C-bit RTSE0.
RTSE0 = 0: odd/even field identification (HIGH = odd field).
RTSE0 = 1: vertical locked indicator; a HIGH state indicates that the
internal VNL has locked.
VS
41
30
O
Vertical sync output signal (enabled via I2C-bit OEHV); this signal
indicates the vertical sync with respect to the YUV output. The HIGH
period of this signal is approximately six lines if the vertical noise
limiter (VNL) function is active. The positive slope contains the phase
information for a deflection controller.
HREF
42
31
O
Horizontal reference output signal (enabled via I2C-bit OEHV); this
signal is used to indicate data on the digital YUV bus. The positive
slope marks the beginning of a new active line. The HIGH period of
HREF is 720 Y samples long. HREF can be used to synchronize data
multiplexer/demultiplexers. HREF is also present during the vertical
blanking interval.
VSS3
43
32
GND
VDD3
Digital ground for positive supply voltage 4.
Digital ground for positive supply voltage 3.
44
33
P
Positive digital supply voltage 3 (+5 V).
45 to 50
34 to 39
O
Digital VPO-bus (Video Port Out) output signal; higher bits of the
16-bit YUV-bus or the 16-bit RGB-bus output signal. The output data
rate, the format and multiplexing scheme of the VPO-bus are
controlled via I2C-bits OFTS0 and OFTS1. With I2C-bit VIPB = 1 the
six MSBs of the digitized input signal (AD1 [7 to 2]) are connected to
these outputs.
VSS2
51
40
GND
VDD2
52
41
P
VPO (15 to 10)
1998 May 15
Digital ground for positive supply voltage 2.
Positive digital supply voltage 2 (+5 V).
7
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
PINS
SYMBOL
I/O
DESCRIPTION
42 to 51
O
Digital VPO-bus output signal; lower bits of the 16-bit YUV-bus or the
16-bit RGB-bus output signal. The output data rate, the format and
multiplexing schema of the VPO-bus are controlled via I2C-bits
OFTS0 and OFTS1. With I2C-bit VIPB = 1 the digitized input signals
(AD1 [1 and 0] and AD2 [7 to 0]) are connected to these outputs.
63
52
I
Fast enable input signal (active LOW); this signal is used to control
fast switching on the digital YUV-bus. A HIGH at this input forces the
IC to set its Y and UV outputs to the high impedance state; note 4.
GPSW
64
53
O
General purpose switch output; the state of this signal is set via
I2C-bus control and the levels are TTL compatible.
XTAL
65
54
O
Second output terminal of crystal oscillator; not connected if external
clock signal is used.
XTALI
66
55
I
Input terminal for 24.576 MHz crystal oscillator or connection of
external oscillator with CMOS compatible square wave clock signal.
VSS1
67
56
GND
VDD1
68
57
P
PLCC68
QFP64
53 to 62
FEI
VPO (9 to 0)
Digital ground for positive supply voltage 1.
Positive digital supply voltage 1 (+5 V).
Notes
1. For board design without boundary scan implementation (pin compatibility with the SAA7110) connect the TRST pin
to ground.
2. This pin provides easy initialization of BST circuit. TRST can be used to force the TAP (Test Access Port) controller
to the Test-Logic-Reset state (normal operation) at once.
3. In accordance with the IEEE1149.1 standard the pads TCK, TDI, TMS and TRST are input pads with an internal
pull-up transistor and TDO a 3-state output pad.
4. All pin names that carry an ‘overscore’ have been renamed due to Philips pin name conventions. In previous data
sheet versions these pins were marked by the suffix ‘N’, e.g. TRST = TRSTN.
1998 May 15
8
Philips Semiconductors
Product specification
TRST
1
61 VPO1
TCK
2
62 VPO0
RTCO
3
63 FEI
IICSA
4
64 GPSW
SDA
5
65 XTAL
SCL
6
66 XTALI
n.c.
7
67 V
SS1
n.c.
8
68 V
DD1
n.c.
handbook, full pagewidth
SAA7111
9
Video Input Processor (VIP)
n.c. 10
60 VPO3
TDO 11
59 VPO3
TDI 12
58 VPO4
TMS 13
57 VPO5
VSSA2 14
56 VPO6
AI22 15
55 VPO7
VDDA2 16
54 VPO8
AI21 17
53 VPO9
52 VDD2
SAA7111
VSSA1 18
AI12 19
51 V
SS2
Fig.2 Pin configuration (PLCC68).
1998 May 15
9
VSS3 43
HREF 42
VS 41
RTS0 40
44 VDD3
RTS1 39
VREF 26
HS 38
45 VPO15
n.c. 37
VSSA0 25
n.c. 36
46 VPO14
VSS4 35
VDDA0 24
VDD4 34
47 VPO13
CE 33
AOUT 23
RES 32
48 VPO12
CREF 31
VSS 22
LLC2 30
49 VPO11
LLC 29
AI11 21
VSS5 28
50 VPO10
VDD5 27
VDDA1 20
MGC636
Philips Semiconductors
Product specification
n.c.
SCL
SDA
IICSA
RTCO
TCK
TRST
VDD1
VSS1
XTALI
XTAL
GPSW
FEI
VPO0
VPO1
VPO2
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
SAA7111
64
Video Input Processor (VIP)
handbook, full pagewidth
n.c.
1
48 VPO3
TDO
2
47 VPO4
TDI
3
46 VPO5
TMS
4
45 VPO6
VSSA2
5
44 VPO7
AI22
6
43 VPO8
VDDA2
7
42 VPO9
AI21
8
VSSA1
41 VDD2
SAA7111
40 VSS2
9
Fig.3 Pin configuration (QFP64).
1998 May 15
10
VSS3 32
HREF 31
VS 30
33 VDD3
RTS0 29
VSSA0 16
RTS1 28
34 VPO15
HS 27
VDDA0 15
VSS4 26
35 VPO14
VDD4 25
AOUT 14
CE 24
36 VPO13
RES 23
VSS 13
CREF 22
37 VPO12
LLC2 21
AI11 12
LLC 20
38 VPO11
VSS5 19
VDDA1 11
VDD5 18
39 VPO10
VREF 17
AI12 10
MBH226
Philips Semiconductors
Product specification
Video Input Processor (VIP)
8
SAA7111
control (AGC) as part of the Analog Input Control (AICO).
The AGC (automatic gain control for luminance) is used to
amplify a CVBS or Y signal to the required signal
amplitude, matched to the ADCs input voltage range.
The AGC active time is the sync bottom of the video signal.
FUNCTIONAL DESCRIPTION
8.1
Analog input processing
The SAA7111 offers four analog signal inputs, two analog
main channels with clamp circuit, analog amplifier,
anti-alias filter and video CMOS ADC (see Fig.6).
8.2
Analog control circuits
The anti-alias filters are adapted to the line-locked clock
frequency with help from a filter control. During the vertical
blanking, time gain and clamping control are frozen.
handbook, halfpage
analog input level
8.2.1
CLAMPING
+4 dB
The clamp control circuit controls the correct clamping of
the analog input signals. The coupling capacitor is also
used to store and filter the clamping voltage. An internal
digital clamp comparator generates the information with
respect to clamp-up or clamp-down. The clamping levels
for the two ADC channels are fixed for luminance (60) and
chrominance (128). Clamping time in normal use is set
with the HCL pulse at the back porch of the video signal.
0 dB
(1 V(p-p) 75 Ω)
−6 dB
controlled
ADC input level
maximum
range 10 dB
0 dB
minimum
MGC660
Fig.5 Automatic gain range.
8.3
handbook, halfpage
The 8-bit chrominance signal is fed to the multiplication
inputs of a quadrature demodulator, where two subcarrier
signals from the local oscillator DTO1 are applied
(0 and 90° phase relationship to the demodulator axis).
The frequency is dependent on the present colour
standard. The output signals of the multipliers are
low-pass filtered (four programmable characteristics) to
achieve the desired bandwidth for the colour difference
signals.
TV line
analog line blanking
225
GAIN
CLAMP
60
1
HCL
HSY
Fig.4
8.2.2
MGC661
The colour difference signals are fed to the
Brightness/Contrast/Saturation block (BCS), which
includes the following five functions;
Analog line with clamp (HCL) and gain
range (HSY).
1. AGC (automatic gain control for chrominance)
2. Chroma amplitude matching [different gain factors for
(R−Y) and (B−Y) to achieve CCIR-601 levels
Cr and Cb]
GAIN CONTROL
Signal (white) peak control limits the gain at signal
overshoots. The flow charts (see Figs 10 and 11) show
more details of the AGC. The influence of supply voltage
variation within the specified range is automatically
eliminated by clamp and automatic gain control.
3. Chroma saturation control
4. Luminance contrast and brightness
5. Limiting YUV to the values 1 (min.) and 254 (max.) to
fulfil CCIR-601 requirements.
The gain control circuit receives (via the I2C-bus) the static
gain levels for the two analog amplifiers or controls one of
these amplifiers automatically via a built-in automatic gain
1998 May 15
Chrominance processing
11
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
The burst processing block provides the feedback loop of
the chroma PLL and contains;
8.5
RGB matrix
Y, Cr and Cb-data are converted after interpolation into
RGB data in accordance with CCIR-601 recommendation.
The realized matrix equations consider the digital
quantization:
Burst gate accumulator
Colour identification and killer
Comparison nominal/actual burst amplitude
R = Y + 1.371 Cr
Loop filter chroma gain control
Loop filter chroma PLL
G = Y − 0.336 Cb − 0.698 Cr
PAL sequence generation
B = Y + 1.732 Cb.
After dithering (noise shaping) the RGB data is fed to the
output interface within the VPO-bus output formatter.
Increment generation for DTO1 with divider to generate
stable subcarrier for non-standard signals.
The chroma comb filter block eliminates crosstalk between
the chrominance channels in accordance with the PAL
standard requirements. For NTSC colour standards the
chroma comb filter can be used to eliminate crosstalk from
luminance to chrominance (cross-colour) for vertical
structures. The comb filter can be switched off if desired.
8.6
The 16-bit VPO-bus transfers digital data from the output
interfaces to a feature box or a field memory, a digital
colour space converter (SAA7192 DCSC), a video
enhancement and digital-to-analog processor
(SAA7165 VEDA2) or a colour graphics board
(Targa-format) as a graphical user interface.
The resulting signals are fed to the variable Y-delay
compensation, RGB matrix, dithering circuit and output
interface, which contains the VPO output formatter and the
output control logic (see Fig.7).
8.4
The output data formats are controlled via the I2C-bus bits
OFTS0, OFTS1 and RGB888. Timing for the data stream
formats, 411 YUV (12-bit), 422 YUV (16-bit),
565 RGB (16-bit) and 888 RGB (24-bit) with an LLC2 data
rate, is achieved by marking each second positive rising
edge of the clock LLC in conjunction with CREF (clock
reference) (except RGB 888, see special application in
Fig.27). The higher output signals VPO15 to VPO8 in the
YUV format perform the digital luminance signal.
The lower output signals VPO7 to VPO0 in the YUV format
are the bits of the multiplexed colour difference signals
(B−Y) and (R−Y). The arrangement of the RGB 565 and
RGB 888 data stream bits on the VPO-bus is given in
Table 5.
Luminance processing
The 8-bit luminance signal, a digital CVBS format or a
luminance format (S-VHS, HI8), is fed through a
switchable prefilter. High frequency components are
emphasized to compensate for loss. The following
chrominance trap filter (f0 = 4.43 or 3.58 MHz centre
frequency selectable) eliminates most of the colour carrier
signal, therefore, it must be bypassed for S-video
(S-VHS, HI8) signals.
The high frequency components of the luminance signal
can be peaked (control for sharpness improvement via
I2C-bus) in two band-pass filters with selectable transfer
characteristic. This signal is then added to the original
(unpeaked) signal. A switchable amplifier achieves
common DC amplification, because the DC gains are
different in both chrominance trap modes. The improved
luminance signal is fed to the BCS control located in the
chrominance processing block (see Fig.8).
1998 May 15
VPO-bus (digital outputs)
The data stream format 422 YUV (the 8 higher output
signals VPO15 to VPO8) in LLC data rate fulfils the
CCIR-656 standard with its own timing reference code at
the start and end of each video data block.
A pixel in the format tables is the time required to transfer
a full set of samples. In the event of a 4 : 2 : 2 format two
luminance samples are transmitted in comparison to one
(B−Y) and one (R−Y) sample within a pixel. The time
frames are controlled by the HREF signal.
12
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
Fast enable is achieved by setting input FEI to LOW.
The signal is used to control fast switching on the digital
VPO-bus. HIGH on this pin forces the YUV outputs to a
high-impedance state (see Figs 15 and 17).
It is possible to force a reset by pulling the CE
(chip enable) to ground. After the rising edge of CE and
sufficient power supply voltage, the outputs LLC, LLC2,
CREF, RTCO, RTS0, RTS1, GPSW and SDA return from
3-state to active, while HREF, VREF, HS and VS remain in
3-state and have to be activated via I2C-bus programming
(see Table 4).
The digitized analog PAL or NTSC signals AD1 (7 to 0)
and AD2 (7 to 0) are connected directly to the VPO-bus
via I2C-bit VIPB = 1.
AD1 (7 to 0) → VPO (15 to 8) and
AD2 (7 to 0) → VPO (7 to 0)
8.10
The real time control and status output signal contains
serial information about the actual system clock
(increment of the HPLL), subcarrier frequency [increment
and phase (via reset) of the FSC-PLL] and PAL sequence
bit. The signal can be used for various applications in
external circuits, e.g. in a digital encoder to achieve clean
encoding (see Fig.16).
The selection of the analog input channels are controlled
via I2C-bus subaddress 02 MODE select.
8.7
Synchronization
The prefiltered luminance signal is fed to the
synchronization stage. Its bandwidth is reduced to 1 MHz
in a low-pass filter. The sync pulses are sliced and fed to
the phase detectors where they are compared with the
sub-divided clock frequency. The resulting output signal is
applied to the loop filter to accumulate all phase
deviations. Internal signals (e.g. HCL and HSY) are
generated in accordance with analog front-end
requirements. The output signals HS, VS, and PLIN are
locked to the timing reference, guaranteed between the
input signal and the HREF signal, as further improvements
to the circuit may change the total processing delay. It is
therefore not recommended to use them for applications
which require absolute timing accuracy on the input
signals. The loop filter signal drives an oscillator to
generate the line frequency control signal LFCO
(see Fig.8).
8.8
8.11
8.11.1
Clock generation circuit
SUGGESTIONS FOR I2C-BUS INTERFACE OF THE
DISPLAY SOFTWARE READING LINE-21 DATA
There are two methods by which the software can acquire
the data;
1. Synchronous reading once per frame (or once per
field): It can use either the rising edge (Line-21 Field 1)
or both edges (Line-21 Field 1 or 2) of the ODD signal
(pin RTSO) to initiate an I2C-bus read transfer of the
three registers 1A, 1B and 1C
2. Asynchronous reading: It can poll either the F1RDY bit
(Line-21 Field 1) or both F1RDY/F2RDY bits (Line-21
Field 1 or 2). After valid data has been read the
corresponding F*RDY bit is set to LOW until new data
has arrived. The polling frequency has to be slightly
higher than the frame or field frequency, respectively.
Power-on reset and CE input
A missing clock, insufficient digital or analog VDDA0 supply
voltages (below 3.5 V) will initiate the reset sequence; all
outputs are forced to 3-state. The indicator output RES is
LOW for approximately 128 LLC after the internal reset
and can be applied to reset other circuits of the digital TV
system.
1998 May 15
The Line-21 text slicer
The text slicer block detects and acquires Line-21 closed
captioning data from a 525-line CVBS signal. Extended
data services on Line-21 Field 2 are also supported.
If valid data is detected the two data bytes are stored in two
I2C-bus registers. A parity check is also performed and the
result is stored in the MSB of the corresponding byte.
A third I2C-bus register is provided for data valid and data
ready flags. The two bits F1VAL and F2VAL indicate that
the input signal carries valid Closed Captioning data on the
corresponding fields. The data ready bits F1RDY and
F2RDY have to be evaluated if asynchronous I2C-bus
reading is used.
The internal CGC generates all clock signals required for
the video input processor. The internal signal LFCO is a
digital-to-analog converted signal provided by the
horizontal PLL. It is the multiple of the line frequency
(6.75 MHz = 432 × fh). Internally the LFCO signal is
multiplied by a factor of 2 or 4 in the PLL circuit (including
phase detector, loop filtering, VCO and frequency divider)
to obtain the LLC and LLC2 output clock signals.
The rectangular output clocks have a 50% duty factor
(see Fig.22).
8.9
RTCO output
13
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AI22
AI21
VDDA1
VDDA2
AI12
AI11
9
14
5
AOSL (1 : 0)
6
8
SOURCE
SWITCH
CLAMP
CIRCUIT
ANALOG
AMPLIFIER
DAC9
ANTI-ALIAS
FILTER
BYPASS
SWITCH
ADC2
11
FUSE (1 : 0)
7
10
12
CLAMP
CIRCUIT
SOURCE
SWITCH
ANALOG
AMPLIFIER
DAC9
ANTI-ALIAS
FILTER
BYPASS
SWITCH
AOUT
Philips Semiconductors
VSSA1
VSSA2
64
Video Input Processor (VIP)
1998 May 15
n.c.
TEST
SELECTOR
AND
BUFFER
ADC1
14
FUSE (1 : 0)
MODE
CONTROL
HCL
GLIMB HSY
GLIMT
WIPA
SLTCA
ANALOG
CONTROL
VSSS
GAIN
CONTROL
13
ANTI-ALIAS
CONTROL
CROSS
CHR
The pin numbers given in parenthesis refer to the 64-pin package.
8
8
MULTIPLEXER
Fig.6 Analog input processing.
AD2BYP AD1BYP
SAA7111
LUM
VBLNK
SVREF
Product specification
MGC655
VERTICAL
BLANKING
CONTROL
VBSL
HOLDG
GAFIX
WPOFF
GUDL0-GUDL2
GAI20-GAI28
GAI10-GAI18
HLNRS
UPTCV
handbook, full pagewidth
MODE 0
MODE 1
MODE 2
CLAMP
CONTROL
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TRST
TCK
TDI
TMS
TDO
RES
10 (1)
1 (58)
2 (59)
12 (3)
13 (4)
QUADRATURE
DEMODULATOR
TEST
CONTROL
BLOCK
11 (2)
SUBCARRIER
GENERATION
(57,41,33,
25,18)
68,52,44,
34,27
32 (23)
POWER-ON
CONTROL
SUBCARRIER
INCREMENT
GENERATION
AND
DIVIDER
HUEC
PHASE
DEMOD.
AMPLITUDE
DETECTOR
BURST GATE
ACCUMULATOR
LOOP FILTER
CE CLOCKS
VSS1-5
LOW-PASS
CHBW0
CHBW1
CSTD 1
CSTD 0
INCS
(56,40,32,26,19)
67,51,43,35,28
FCTC CODE
(52) 63
BRIGHTNESS,
CONTRAST,
AND
SATURATION
CONTROL
Y
GAIN
CONTROL
AND Y-DELAY
COMPENSATION UV
RGB MATRIX RGB
interpolation
dithering
DIT CBR
(31) 42
COMB
FILTERS
DCCF
BRIG
CONT
SATN
(42 to 51),
53 to 62
OUTPUT
FORMATTER
AND
(34 to 39),
INTERFACE
45 to 50
OFTS0
OFTS1
RGB888
OEYC
OEHV
FECO
VRLN
GPSW
RTSE1
RTSE0
VIPB
VLOF
COLO
COMPO
(60) 3
FEI
VPO
(9 : 0)
VPO
(15 : 10)
HREF
RTCO
MGC645
Y
LUM
Product specification
Fig.7 Chrominance circuit.
SAA7111
The pin numbers given in parenthesis refer to the 64-pin package.
handbook, full pagewidth
15
VDD1-5
AD2BYP AD1BYP
CHR
Philips Semiconductors
n.c.
Video Input Processor (VIP)
1998 May 15
LUM
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LUMINANCE CIRCUIT
PREF
WEIGHTING
AND
ADDING
STAGE
VARIABLE
BAND-PASS
FILTER
CHROMINANCE
TRAP
PREFILTER
BYPS
VBLB
BPSS0
BPSS1
PREF
APER0
APER1
VBLB
MATCHING
AMPLIFIER
PREFILTER
SYNC
CLOCK CIRCUIT
CLOCKS
VBLB
16
LINE 21
TEXT
SLICER
SYNC SLICER
BYTE1
BYTE2
STATUS
SYNCHRONIZATION CIRCUIT
2
I C BUS CONTROL
GPSW
53
2
I C-BUS
INTERFACE
61
63
Philips Semiconductors
Video Input Processor (VIP)
1998 May 15
Y
LUM
VNOI0
VNOI1
VTRC
FIDT
VERTICAL
PROCESSOR
62
30
29
17
PHASE
DETECTOR
FINE
AUFD
HSB
HSS
FSEL
VTRC
PHASE
DETECTOR
COARSE
DAC6
HLCK
STTC
VTRC
LOOP FILTER
2
COUNTER
27
HPLL
VTRC
EXFIL
LINE-LOCKED
CLOCK
GENERATOR
22
20
21
CREF
LLC
LLC2
CLOCK
GENERATION
CIRCUIT
15
16
24
VDDA0
VSSA0
CE
INCS
DISCRETE
TIME
OSCILLATOR 2
CRYSTAL
CLOCK
GENERATOR
55
54
XTALI
XTAL
28
MGC654
HS
RTS1
Product specification
Fig.8 Luminance and sync processing.
SAA7111
The pin numbers given in parenthesis refer to the 64-pin package.
VS RTS0 VREF
handbook, full pagewidth
IICSA SCL SDA
Philips Semiconductors
Product specification
Video Input Processor (VIP)
9
SAA7111
GAIN CHARTS
MGC648
handbook, halfpage
factor dB = 20 x log 10 gain =
dB
5.5
(
512
768 − i
(
7.5
3.5
bit [8] = 1
i > 256
1.5
bit [8] = 0
i < 256
−0.5
factor dB = 20 x log 10 gain =
(
257 + i
512
(
−2.5
−4.5
0
256
512
gain value (i)
Fig.9 Amplifier curve.
handbook, full pagewidth
ANALOG INPUT
ADC
1
NO BLANKING ACTIVE
VBLK
0
<- CLAMP
1
1
+ CLAMP
CLL
HCL
GAIN ->
0
1
0
0
− CLAMP
NO CLAMP
+ GAIN
SBOT
HSY
1
− GAIN
0
1
fast − GAIN
WIPE
0
slow + GAIN
MGC647
WIPE = white peak level (254); SBOT = sync bottom level (1); CLL = clamp level [60 Y (128 C)];
HSY = horizontal sync pulse; HCL = horizontal clamp pulse.
Fig.10 Clamp and gain flow.
1998 May 15
17
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
handbook, full pagewidth
ANALOG INPUT
gain
AMPLIFIER
9
DAC
ANTI-ALIAS FILTER
ADC
8
1
NO ACTION
VBLK
1
LUMA/CHROMA DECODER
0
HOLDG
0
1
0
X
1
0
0
<4
>254
1
1
1
1
0
<1
+1/F
STOP
>248
>254
0
X=1
X=0
1
0
HSY
0
+1/L
−1/LLC2
+1/LLC2
+/− 0
−1/LLC2
GAIN ACCUMULATOR (18 BITS)
ACTUAL GAIN VALUE 9-BIT (AGV) [−6/+6 dB]
1
0
X
1
0
HSY
1
AGV
Y
UPDATE
0
FGV
GAIN VALUE 9-BIT
MGC652
X = system variable; Y = AGV − FGVI > GUDL; VBLK = vertical blanking pulse;
HSY = horizontal sync pulse; AGV = actual gain value; FGV = frozen gain value.
Fig.11 Gain flow chart.
1998 May 15
18
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
10 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDDD
digital supply voltage
−0.5
+6.5
V
VDDA
analog supply voltage
−0.5
+6.5
V
Vdiff
voltage difference between VSSAall and
VSSall
−
100
mV
Tstg
storage temperature
−65
+150
°C
Tamb
operating ambient temperature
0
70
°C
Tamb(bias)
operating ambient temperature under bias
−10
+80
°C
VESD
electrostatic discharge all pins
−2000
+2000
V
note 1
Note
1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor.
11 CHARACTERISTICS
VDDD = 4.5 to 5.5 V; VDDA = 4.75 to 5.25 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDD
digital supply voltage
4.5
5.0
5.5
V
IDDD
digital supply current
100
130
160
mA
PD
digital power
0.45
0.65
0.88
W
VDDA
analog supply voltage
4.75
5.0
5.25
V
IDDA
analog supply current
60
70
80
mA
PA
analog power
0.32
0.35
0.38
W
PA+D
analog and digital power
0.77
1.0
1.26
W
Analog part
Iclamp
clamping current
VI = 1.25 V DC
−
2
−
µA
Vi(p-p)
input voltage (peak-to-peak
value), AC coupling required
coupling
capacitor = 10 nF; note 1
0.55
1.0
1.5
V
clamping current off
|Zi|
input impedance
Ci
input capacitance
αcs
channel crosstalk
200
−
−
kΩ
−
−
10
pF
fi = 5 MHz
−
−50
−
dB
at −3 dB
−
15
−
MHz
Analog-to-digital converters
B
bandwidth
φdiff
differential phase (amplifier
plus anti-alias filter = bypass)
−
2
−
deg
Gdiff
differential gain (amplifier plus
anti-alias filter = bypass)
−
2
−
%
fADC
ADC clock frequency
11
−
16
MHz
DLE
DC differential linearity error
−
0.5
−
LSB
ILE
DC integral linearity error
−
1
−
LSB
1998 May 15
19
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SYMBOL
SAA7111
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital inputs
VIL
LOW-level input voltage pins
SDA and SCL
−0.5
VIH
HIGH-level input voltage pins
SDA and SCL
VIL(xtalI)
−
+1.5
V
0.7VDDD −
VDDD + 0.5
V
LOW-level CMOS input
voltage pin XTALI
−
0.3VDDD
V
VIH(xtalI)
HIGH-level CMOS input
voltage pin XTALI
0.7VDDD −
−
V
VILn
LOW-level input voltage all
other inputs
−0.5
−
+0.8
V
VIHn
HIGH-level input voltage all
other inputs
2.0
−
VDDD + 0.5
V
−
−
1
µA
−
−
8
pF
−
−
8
pF
ILI
input leakage current
Ci(I/O)
input capacitance
Ci(n)
input capacitance all other
inputs
inputs and outputs at
high-impedance
−
Digital outputs
VOL
LOW-level output voltage pins
SDA and SCL
SDA/SCL at 3 mA sink
current
−
−
0.4
V
VOL
LOW-level output voltage
note 2
0
−
0.6
V
VOH
HIGH-level output voltage
note 2
2.4
−
VDDD
V
VOL(clk)
LOW-level output voltage for
clocks
−0.5
−
+0.6
V
VOH(clk)
HIGH-level output voltage for
clocks
2.6
−
VDDD + 0.5
V
FEI input timing
tSU;DAT
input data set-up time
13
−
−
ns
tHD;DAT
input data hold time
3
−
−
ns
15
−
50
pF
Data and control output timing
CL
output load capacitance
tOHD;DAT
output hold time
CL = 15 pF
5
−
−
ns
tPD
propagation delay
CL = 40 pF
−
−
21
ns
tPDZ
propagation delay to 3-state
−
−
21
ns
1998 May 15
20
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SYMBOL
SAA7111
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Clock output timing (LLC and LLC2)
CL(LLC)
output load capacitance
Tcy
cycle time
15
−
40
pF
LLC
35
−
39
ns
LLC2
70
−
78
ns
δLLC
duty factors for tLLCH/tLLC and
tLLC2H/tLLC2
CL = 40 pF
40
−
60
%
tr
rise time
Vi = 0.6 to 2.6 V
−
−
5
ns
tf
fall time
Vi = 2.6 to 0.6 V
−
−
5
ns
tdLLC2
delay time LLC output to LLC2
output
Vi = 1.5 V;
LLC/LLC2 = 40 pF
−1
−
+1
ns
Data qualifier output timing (CREF)
tOHD;CREF
output hold time
CL = 15 pF
4
−
−
ns
tPD;CREF
propagation delay from
positive edge of LLC
CL = 40 pF
−
−
20
ns
nominal frequency
40
−
60
%
50 Hz field
−
15625
−
Hz
60 Hz field
−
15734
−
Hz
−
−
5.7
%
PAL BGHI and NTSC 443
−
4433619
−
Hz
NTSC M
−
3579545
−
Hz
PAL M
−
3575612
−
Hz
PAL N
−
3582056
−
Hz
±400
−
−
Hz
Clock input timing (XTALI)
δXTALI
duty factor for tXTALIH/tXTALI
Horizontal PLL
fHn
∆fH/fHn
nominal line frequency
permissible static deviation
Subcarrier PLL
fSCn
nominal subcarrier frequency
∆fSCH/fSCHn lock-in range
1998 May 15
21
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SYMBOL
PARAMETER
SAA7111
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Crystal oscillator
fn
nominal frequency
−
24.576
−
MHz
∆f/fn
permissible nominal
frequency deviation
−
−
±50
10−6
∆f/fn(T)
permissible nominal
frequency deviation with
temperature
−
−
±20
10−6
0
−
70
°C
3rd harmonic
CRYSTAL SPECIFICATION (X1)
TambX1
operating ambient
temperature
CL
load capacitance
8
−
−
pF
Rs
series resonance resistor
−
40
80
Ω
C1
motional capacitance
−
1.5 ±20%
−
fF
C0
parallel capacitance
−
3.5 ±20%
−
pF
Notes
1. The levels must be measured with load circuits; 1.2 kΩ at 3 V (TTL load); CL = 50 pF.
2. The effects of rise and fall times are included in the calculation of tOHD;DAT, tPD and tPDZ. Timings and levels refer to
drawings and conditions illustrated in Figs 12 and 13.
Table 1
Processing delay
FUNCTION
TYPICAL ANALOG DELAY
AI22 −> ADCIN (AOUT) (ns)
Without amplifier or anti-alias filter
14
With amplifier, without anti-alias filter
30
With amplifier plus anti-alias filter
72
1998 May 15
22
DIGITAL DELAY
ADCIN → VPO (LLC-CLOCKS)
[YDEL(2 to 0) = 000]
139
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
12 TIMING DIAGRAMS
tLLC
handbook, full pagewidth
tLLCL
2.6 V
1.5 V
0.6 V
CLOCK OUTPUT LLC
t
tr
f
t
LLCH
tPD
tOHD;DAT
2.4 V
0.6 V
OUTPUTS VPO, HREF,
VREF, VS, HS
MGC658
An explanation of the output formats is given in Table 5.
Fig.12 Clock/data timing (8-bit CCIR-656 format of the VPO-bus).
tLLC
tLLC
handbook, full pagewidth
tLLCL
2.6 V
1.5 V
0.6 V
CLOCK OUTPUT LLC
tf
tLLCH
tr
t
tPD
PD
2.4 V
0.6 V
OUTPUT CREF
tOHD;CREF
tOHD;CREF
tdLLC2
tdLLC2
2.6 V
1.5 V
0.6 V
CLOCK OUTPUT LLC2
tPD
tOHD;DAT
2.4 V
0.6 V
OUTPUTS VPO, HREF,
VREF, VS, HS
MGC659
An explanation of the output formats is given in Table 5. The FEI timing of the VPO-bus is illustrated in Figs 15 and 17.
Fig.13 Clock/data timing (12/16-bit CCIR-601 format of the VPO-bus).
1998 May 15
23
Philips Semiconductors
Product specification
Video Input Processor (VIP)
handbook, full pagewidth
SAA7111
tLLC
tLLC
tLLCL
2.4 V
1.5 V
0.6 V
CLOCK OUTPUT LLC
,,,,
,,,,,
,,,,,
,,,,
,,,,,
,,,,,
,,,, ,,,,, ,,,,,
tf
tr
tLLCH
tPD;CREF
OUTPUT CREF
tOHD;CREF
2.4 V
1.5 V
0.6 V
tOHD;CREF
tPD;CREF
RGB (8, 8, 8) data
VPO15 to VPO8
RGB (8, 8, 8) data
VPO7 to VPO0
tOHD;CREF
2.4 V
1.5 V
0.6 V
R(7 : 3)
G(7 : 5)
,,,
,,,
,,
,,
tOHD;DAT
R(2 : 0)
G(1 : 0)
B(2 : 0)
,,,
,,,
tOHD;DAT
G(4 : 2)
B(7 : 3)
tPD
An explanation of the output formats is given in Table 5.
Fig.14 Clock/data timing for RGB888 output format.
handbook, full pagewidth
LLC
CREF
HREF
tSU;DAT
tHD;DAT
FEI
t
PDZ
t
OHD;DAT
tPD
VPO
MGC656
to 3-state
from 3-state
I2C-bit FECO = 1.
Fig.15 FEI timing diagram (FEI sampling at CREF = HIGH).
1998 May 15
24
2.4 V
1.5 V
0.6 V
MBH227
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
transmitted once per line
handbook, full pagewidth
INCRHPLL
HIGH
16
128
BIT NO.:
TIME SLOT:
INCRFSCPLL
45
2
0
15
0 1
RESERVED
RESERVED
SEQUENCE
LOW
DTO RESET(1)
RESERVED
50 Hz fields: 235
60 Hz fields: 232
3 1
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
63 67 68
16 19
(1) Set to zero for one transmission, if a phase reset of the fsc - DTO is applied via I2C-bit CDTO. RTCO sequence is generated in LLC/4.
The HPLL increment represents the actual LFCO frequency (fLFCO × 4 = fLLC); 16 LSB from 20, upper four bits are fixed to 0100b
INCR HPLL × f XTAL
f LFCO = -----------------------------------------------word length DTO2
2
Where: fXTAL = 24.576 MHz, word length DTO2 = 20 bits.
The fsc increment represents the actual subcarrier frequency (related to the actual clock); 23 LSB from 24, MSB is 0b.
INCR FSCPLL × f XTAL INCR HPLL
f sc = ------------------------------------------------------ × --------------------------word length DTO1
19
2
2
Where: word length DTO1 = 24 bits.
Fig.16 Real time control output.
handbook, full pagewidth
LLC
CREF
HREF
tSU;DAT
FEI
tHD;DAT
t
PDZ
t
tPD
OHD;DAT
VPO
MGC657
from 3-state
to 3-state
Timing is compatible with SAA7110; I2C-bit FECO = 0.
Fig.17 FEI timing diagram (FEI sampling at CREF = LOW).
1998 May 15
25
MGC649
Philips Semiconductors
Product specification
Video Input Processor (VIP)
handbook, full pagewidth
SAA7111
LLC
CREF
LLC2
START OF ACTIVE LINE
HREF
Yn
0
1
2
3
4
UVn
U0
V0
U2
V2
U4
END OF ACTIVE LINE
HREF
Yn
715
716
717
718
719
UVn
V714
U716
V716
U718
V718
MGC646
Fig.18 HREF timing diagram.
1998 May 15
26
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
0
handbook, full pagewidth
50 x 2/LLC
burst
CVBS
139 x 1/LLC
processing delay CVBS->VPO(2)
Y - output
sync clipped
HREF (50 Hz)
12 x 2/LLC
144 x 2/LLC
720 x 2/LLC
113 x 2/LLC
7 x 2/LLC
RTS1 (PLIN)(1)
4/LLC
HS
HS (50 Hz)
108
programming range
(step size: 8/LLC)
−107
0
HREF (60 Hz)
3 x 2/LLC
16 x 2/LLC
138 x 2/LLC
720 x 2/LLC
HS (60 Hz)
HS (60 Hz)
programming range
(step size: 8/LLC)
107
0
MGC664
(1) PLIN is switched to output RTS1 via I2C-bit RTSE1 = 0.
(2) See Table 1.
Fig.19 Horizontal timing diagram.
1998 May 15
−106
27
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
handbook, full pagewidth
622
input CVBS
623
624
625
1
2
3
4
5
6
7
8
22
23
HREF
VREF VRLN = 1
VREF VRLN = 0
503 x 2/LLC
VS
RTS0 (ODD)(1)
a: 1st field
310
311
312
313
314
315
316
317
318
319
320
335
336
337
input CVBS
HREF
VREF
VRLN = 1
VREF
VRLN = 0
71 x 2/LLC
VS
RTS0 (ODD)(1)
MGC662
b: 2nd field
(1) ODD is switched to output RTS0 via I2C-bit RTSE0 = 0.
The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bit VBLB is set to logic 1.
The chrominance delay line (chroma-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.
Fig.20 Vertical timing diagram for 50 Hz [nominal input signal VNL in normal mode (VNOI = 00b)].
1998 May 15
28
Philips Semiconductors
Product specification
Video Input Processor (VIP)
handbook, full pagewidth
523
(1)
522
(525)
524
(2)
525
(3)
SAA7111
1
(4)
2
(5)
3
(6)
4
(7)
5
(8)
6
(9)
7
(10)
17
(20)
8
(11)
18
(21)
19
(22)
(2)
input CVBS
HREF
VRLN = 1
VREF
VRLN = 0
VREF
493 x 2/LLC
VS
RTS0 (ODD)(1)
a: 1st field
259
(262)
260
(263)
261
(264)
262
(265)
263
(266)
264
(267)
265
(268)
266
(269)
267
(270)
268
(271)
269
(272)
270
(273)
271
(274)
280
(283)
281
(284)
(2)
input CVBS
HREF
VRLN = 1
VREF
VRLN = 0
VREF
61 x 2/LLC
VS
RTS0 (ODD)(1)
b: 2nd field
MGC663
(1) ODD is switched to output RTS0 via I2C-bit RTSE0 = 0.
(2) Line numbers in parenthesis refer to CCIR line counting.
The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bit VBLB is set to logic 1.
The chrominance delay line (chroma-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.
Fig.21 Vertical timing diagram for 60 Hz [nominal input signal VNL in normal mode (VNOI = 00b)].
1998 May 15
282
(285)
29
Philips Semiconductors
Product specification
Video Input Processor (VIP)
Table 2
SAA7111
Digital output control
Table 3
VPO
OEYC
FEI
0
Clock frequencies
CLOCK
FREQUENCY (MHz)
15 to 0(1)
15 to 8(2)
7 to 0(2)
XTAL
24.576
0
Z
Z
Z
LLC
27
1
0
active
active
Z
LLC2
13.5
0
1
Z
Z
Z
LLC4
6.75
Z
LLC8
3.375
1
1
Z
active
Notes
1. OFTS(1 : 0) = 10 or 01 or 00.
2. OFTS(1 : 0) = 11.
13 CLOCK SYSTEM
13.1
Clock generation circuit
The internal CGC generates the system clocks LLC, LLC2
and the clock reference signal CREF. The internal
generated LFCO (triangular waveform) is multiplied by
2 or 4 via the analog PLL (including phase detector, loop
filter, VCO and frequency divider). The rectangular output
signals have a 50% duty factor.
handbook, full pagewidth
LFCO
BAND PASS
FC = LLC/4
ZERO
CROSS
DETECTION
PHASE
DETECTION
LOOP
FILTER
OSCILLATOR
LLC
DIVIDER
1/2
DIVIDER
1/2
LLC2
DELAY
CREF
MGC632
Fig.22 Block diagram of clock generation circuit.
1998 May 15
30
Philips Semiconductors
Product specification
Video Input Processor (VIP)
13.2
SAA7111
Power-on control
Power-on reset is activated at power-on, chip enable, PLL clock generation failure and if the supply voltage falls below
3.5 V. The RES signal can be applied to reset other circuits of the digital picture processing system.
andbook, full pagewidth
POC VDDA
POC VDDD
ANALOG
DIGITAL
POC
LOGIC
POC
DELAY
CLOCK
PLL
LLC
RES
CE
CLK0
CE
XTAL
LLCINT
RESINT
LLC
RES
some ms
20 to 200 µs
PLL-delay
896 LCC
digital delay
<1 ms
CE = chip enable input; XTAL = crystal oscillator output; LLCINT = internal system clock;
RESINT = internal reset; LLC = line-locked system clock output; RES = reset output (active LOW).
Fig.23 Power-on control circuit.
1998 May 15
31
128 LCC
MGC633
Philips Semiconductors
Product specification
Video Input Processor (VIP)
Table 4
SAA7111
Power-on control sequence
INTERNAL POWER-ON
CONTROL SEQUENCE
PIN OUTPUT STATUS
FUNCTION
Directly after power-on
asynchronous reset
VPO15 to VPO0, RTCO, RTS0, RTS1,
GPSW, HREF, VREF, HS, VS, LLC, LLC2
and CREF are in high-impedance state
direct switching to high impedance for
20 to 200 ms
Synchronous reset
sequence
LLC, LLC2, CREF, RTCO, RTS0, RTS1,
GPSW and SDA become active;
VPO15 to VPO0, HREF, VREF, HS and VS
are held in high-impedance state
internal reset sequence
Status after power-on
control sequence
VPO15 to VPO0, HREF, VREF, HS and VS
are held in high-impedance state
after power-on (reset sequence) a complete
I2C-bus transmission is required
14 OUTPUT FORMATS
Table 5
Output formats
BUS SIGNAL
VPO15
VPO14
VPO13
VPO12
VPO11
VPO10
VPO9
VPO8
VPO7
VPO6
VPO5
VPO4
VPO3
VPO2
VPO1
VPO0
Pixel order Y
Pixel order UV
Data rates
I2C-bus
control signals
422 (16-BIT)(1)
411 (12-BIT)
Y07
Y06
Y05
Y04
Y03
Y02
Y01
Y00
U07
U06
V07
V06
X
X
X
X
0
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
U05
U04
V05
V04
X
X
X
X
1
Y27
Y26
Y25
Y24
Y23
Y22
Y21
Y20
U03
U02
V03
V02
X
X
X
X
2
Y37
Y36
Y35
Y34
Y33
Y32
Y31
Y30
U01
U00
V01
V00
X
X
X
X
3
0
LLC2
OFTS0 = 0
OFTS1 = 1
RGB888 = X
Y07
Y06
Y05
Y04
Y03
Y02
Y01
Y00
U07
U06
U05
U04
U03
U02
U01
U00
0
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
V07
V06
V05
V04
V03
V02
V01
V00
1
CCIR-656 (8-BIT)(2)
U07
U06
U05
U04
U03
U02
U01
U00
X
X
X
X
X
X
X
X
Y07
Y06
Y05
Y04
Y03
Y02
Y01
Y00
X
X
X
X
X
X
X
X
0
0
LLC2
OFTS0 = 1
OFTS1 = 0
RGB888 = X
V07
V06
V05
V04
V03
V02
V01
V00
X
X
X
X
X
X
X
X
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
X
X
X
X
X
X
X
X
1
0
LLC
OFTS0 = 1
OFTS1 = 1
RGB888 = X
RGB (16-BIT)(3) RGB (24-BIT)(3)
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
−
−
LLC2
OFTS0 = 0
OFTS1 = 0
RGB888 = 0
Notes
1. Values in accordance with CCIR-601.
2. Before and after the video data, video timing codes are inserted in accordance with CCIR-656.
3. Values not defined during HREF = LOW.
4. CREF = 0 (see Fig.14).
5. CREF = 1 (see Fig.14).
1998 May 15
32
R7
R6
R5
R4
R3
G7
G6
G5
G4
G3
G2
B7
B6
B5
B4
B3
note 4
R7
R6
R5
R4
R3
G7
G6
G5
R2
R1
R0
G1
G0
B2
B1
B0
note 5
−
LLC
OFTS0 = 0
OFTS1 = 0
RGB888 = 1
Philips Semiconductors
Product specification
Video Input Processor (VIP)
+255
handbook, full pagewidth
+235
+128
white
LUMINANCE 100%
SAA7111
+255
+240
blue 100%
+255
+240
red 100%
+212
blue 75%
+212
red 75%
+128
colourless
+128
colourless
U-COMPONENT
+16
black
V-COMPONENT
+44
yellow 75%
+44
cyan 75%
+16
yellow 100%
+16
cyan 100%
0
0
0
MGC634
a. Y output range.
b. U output range (Cb).
c. V output range (Cr).
CCIR Rec. 602 digital levels.
Equations for modification to the YUV levels via BCS control I2C bytes BRIG, CONT and SATN.
Luminance:
CONT
Y OUT = Int ------------------ × ( Y – 128 ) + BRIG
71
Chrominance:
SATN
UV OUT = Int ----------------- × ( Cr, Cb – 128 ) + 128
64
It should be noted that the resulting levels are limited to 1 to 254 in accordance with CCIR-601/656 standard.
Fig.24 VPO output signal range with default BCS settings.
handbook, full pagewidth
quartz (3rd harmonic)
24.576 MHz
XTAL
C=
10 pF
XTAL
65 (54)
SAA7111
XTALI
65 (54)
SAA7111
XTALI
66 (55)
66 (55)
L = 10 µH ±20%
C=
10 pF
C=
1 nF
MGC635
a. With quartz crystal.
b. With external clock.
The pin numbers given in parenthesis refer to the 64-pin package.
Fig.25 Oscillator application.
1998 May 15
33
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
15 APPLICATION INFORMATION
VDD
VDDA
C15
100 nF C14
C9
C8
C13 100 nF
100 nF
BST
1
12 11 2
(3) (2) (59) (58)
(35) 46
10 nF
(36) 47
VSSA 75 Ω
(37) 48
(38) 49
C3
17 (8)
AI21
(39) 50
10 nF
R3
(42) 53
VSSA 75 Ω
(43) 54
(44) 55
C2
AI12
(45) 56
19 (10)
10 nF
R2
(46) 57
(47) 58
VSSA 75 Ω
(48) 59
C1
(49) 60
AI11
21 (12)
SAA7111
(50) 61
10 nF
R1
VSS
100 nF
(34) 45
15 (6)
R4
C11 100 nF
68 52 44 34 27
(57) (41) (33) (25) (18)
C4
AI22
VDD5
VDD4
VDD3
TCK
TDO
TDI
TMS
24 20 16 13
(15) (11) (7) (4)
n.c.
TRST
n.c.
VDDA2
VDDA1
VDDA0
100 nF
VSSA
100 nF C12
VSS
n.c.
VDD2
C7
100 nF
VDD1
handbook, full pagewidth
(51) 62
15
14
13
12
11
10
9
8
VPO(15 : 0)
7
6
5
4
3
2
1
0
VSSA 75 Ω
R5
VDDD
(31) 42
33 (24)
1 kΩ
6 (63)
(27) 38
HS
SDA
5 (62)
(30) 41
VS
63 (52)
R6
1 kΩ
VSS
XTAL
65 (54)
Q1(24.576 MHz)
VSS
VSS
VSSA
IICSA
VSS5
VSS4
VSS3
(5) (13) (56) (40) (32) (26) (19) (61) (64)
8
14 22 67 51 43 35 28 4
7
VSS2
10 pF 10 pF
(16) (9)
25 18
VSS1
1 nF
C18
VSS
C17
VSSA2
C16
VSSA1
10
µH
66 (55)
VSSA0
XTALI
VSS
Fig.26 Application diagram.
34
(60) 3
RTCO
(28) 39
RTS1
(29) 40
RTS0
(53) 64
GPSW
(14) 23
AOUT
(20) 29
LLC
(21) 30
LLC2
(22) 31
CREF
(23) 32
RES
9 10 36 37
n.c.
n.c.
The pin numbers given in parenthesis refer to the QFP64 package.
1998 May 15
VREF
SCL
FEI
L1
HREF
(17) 26
n.c.
n.c.
n.c.
n.c.
MGC651
Philips Semiconductors
Product specification
Video Input Processor (VIP)
handbook, full pagewidth
(34) 45
(35) 46
(36) 47
VPO
(15 : 8)
(37) 48
(38) 49
(39) 50
(42) 53
(43) 54
SAA7111
VPO (15 : 11)
15
R (7 : 3)
3
14
13
G (7 : 5)
VPO (10 : 8)
12
3
11
VPO (7 : 5)
10
G (4 : 2)
3
9
8
VSS
VDD
OEN
(44) 55
(45) 56
(46) 57
VPO
(7 : 0)
(47) 58
(48) 59
(49) 60
(50) 61
(51) 62
7
6
5
D7
O7
D6
O6
O5
D5
4
D4
3
e.g.
O4
D3 74HCT574 O3
2
1
0
D2
O2
D1
O1
VDD
R (2 : 0)
3
8
2
8
3
8
G (1 : 0)
B (2 : 0)
R (7 : 0)
G (7 : 0)
B (7 : 0)
00
D0
VSS
CLK
VSS
SAA7111
VPO (4 : 0)
B (7 : 3)
5
(31) 42
HREF
(17) 26
VREF
(27) 38
HS
(30) 41
VS
(60) 3
RTCO
(28) 39
RTS1
(29) 40
RTS0
(53) 64
GPSW
(14) 23
AOUT
(20) 29
LLC
(21) 30
(32) 31
CREF
(23) 32
RES
e.g. 74F240
LLC2
LLC2N
MGD137
The pin numbers given in parenthesis refer to the QFP64 package.
I2C-bus control bits:
OFTS(1 : 0) = 00 (subaddress 10h, bits D7 and D6).
RGB888 = 1 (subaddress 12h, bit D3).
Fig.27 Application diagram for RGB 24-bit output format.
15.1
Place the coupling (clamp) capacitors close to the analog
input pins. Place the termination resistors close to the
coupling capacitors. Care should be exercised concerning
the hidden layout capacitors around the crystal
application. To avoid reflection effects use serial resistors
in the clock, sync and data lines.
Layout hints
Use separate ground planes for analog and digital ground.
Connect these planes at one point directly under the
device, by using a zero Ω resistor. Use separate supply
lines for analog and digital supply. Place the supply
decoupling capacitors nearby the supply pins.
1998 May 15
35
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
16 I2C-BUS DESCRIPTION
16.1
I2C-bus format
Table 6
S
Write procedure
SLAVE ADDRESS W
Table 7
ACK(s)
SUBADDRESS
ACK(s)
DATA (N BYTES)
P
Read procedure (combined format)
S
SLAVE ADDRESS W
ACK(s)
SUBADDRESS
Sr
SLAVE ADDRESS R
ACK(s)
DATA (N BYTES)
Table 8
ACK(s)
ACK(s)
ACK(m)
P
Description of I2C-bus format
CODE
DESCRIPTION
S
START condition
Sr
repeated START condition
Slave address W
0100 1000b (IICSA = LOW) or 0100 1010b (IICSA = HIGH)
Slave address R
0100 1001b (IICSA = LOW) or 0100 1011b (IICSA = HIGH)
ACK(s)
acknowledge generated by the slave
ACK(m)
acknowledge generated by the master
Subaddress
subaddress byte; see Table 9
Data
data byte, see; note 1 and Table 9
P
STOP condition
X = LSB slave
address
read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read
(the circuit is slave transmitter)
Slave address
read = 49H or 4BH; note 2
write = 48H or 4AH
IICSA = 0 or 1
Subaddress
00H chip version
read and write; note 3
01H reserved
−
02H to 05H front-end part
read and write
06H to 12H decoder part
read and write
13H to 19H reserved
−
1AH to 1CH Line-21 text slicer part
read only
1DH to 1EH reserved
−
1FH status byte
read only
Notes
1. If more than one byte DATA is transmitted then the auto-increment of the subaddress is performed.
2. During slave transmitter mode the SCL-LOW period may be extended by pulling SCL to LOW (in accordance with
the I2C-bus specification).
3. The I2C-bus subaddress 00 has to be initialized with 0 before being read.
1998 May 15
36
Philips Semiconductors
Product specification
Video Input Processor (VIP)
Table 9
SAA7111
I2C-bus receiver/transmitter overview
READ
WRITE
IICSA
49H and 4BH
48H and 4AH
0 and 1
SUBADDR.
D7
D6
D5
D4
D3
D2
D1
D0
Chip version
00
ID07
ID06
ID05
ID04
ID03
ID02
ID01
ID00
Reserved
01
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Analog input control 1
02
FUSE1
FUSE0
GUDL2
GUDL1
GUDL0
MODE2
MODE1
MODE0
Analog input control 2
03
(1)
HLNRS
VBSL
WPOFF
HOLDG
GAFIX
GAI28
GAI18
Analog input control 3
04
GAI17
GAI16
GAI15
GAI14
GAI13
GAI12
GAI11
GAI10
Analog input control 4
05
GAI27
GAI26
GAI25
GAI24
GAI23
GAI22
GAI21
GAI20
Horizontal sync start
06
HSB7
HSB6
HSB5
HSB4
HSB3
HSB2
HSB1
HSB0
Horizontal sync stop
07
HSS7
HSS6
HSS5
HSS4
HSS3
HSS2
HSS1
HSS0
VTRC
HPLL
VNOI1
VNOI0
SLAVE ADDRESS
REGISTER
FUNCTION
Sync control
08
AUFD
FSEL
EXFIL
(1)
Luminance control
09
BYPS
PREF
BPSS1
BPSS0
VBLB
UPTCV
APER1
APER0
Luminance brightness
0A
BRIG7
BRIG6
BRIG5
BRIG4
BRIG3
BRIG2
BRIG1
BRIG0
Luminance contrast
0B
CONT7
CONT6
CONT5
CONT4
CONT3
CONT2
CONT1
CONT0
Chroma saturation
0C
SATN7
SATN6
SATN5
SATN4
SATN3
SATN2
SATN1
SATN0
Chroma Hue control
0D
HUEC7
HUEC6
HUEC5
HUEC4
HUEC3
HUEC2
HUEC1
HUEC0
Chroma control
0E
CDTO
CM99
CSTD1
CSTD0
DCCF
FCTC
CHBW1
CHBW0
Reserved
0F
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Format/delay control
10
OFTS1
OFTS0
HDEL1
HDEL0
VRLN
YDEL2
YDEL1
YDEL0
Output control 1
11
GPSW
(1)
FECO
COMPO
OEYC
OEHV
VIPB
COLO
Output control 2
12
RTSE1
RTSE0
(1)
CBR
RGB888
DIT
AOSL1
AOSL0
13-19
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Text slicer status
1A
(1)
(1)
(1)
(1)
F2VAL
F2RDY
F1VAL
F1RDY
Decoded bytes of the
text slicer
1B
P1
BYTE16 BYTE15 BYTE14
BYTE13
BYTE12
BYTE11
BYTE10
1C
P2
BYTE26 BYTE25 BYTE24
BYTE23
BYTE22
BYTE21
BYTE20
1D-1E
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
1F
STTC
HLCK
FIDT
GLIMT
GLIMB
WIPA
SLTCA
CODE
Reserved
Reserved
Status byte
Note
1. All unused control bits must be programmed with 0.
16.2
I2C-bus detail
The I2C-bus receiver slave address is 48H/49H. Subaddresses 0F, 1D, 1E and 13 to 19 are reserved; subaddress 01 is
reserved for chip version.
1998 May 15
37
Philips Semiconductors
Product specification
Video Input Processor (VIP)
16.2.1
SAA7111
SUBADDRESS 00
Table 10 Chip version SA 00, D7 to D0
CONTROL BITS
FUNCTION
Chip version in read mode(1)
ID07
ID06
ID05
ID04
ID03
ID02
ID01
ID00
0
0
0
0
X
X
X
X
chip version number
reserved for chip name
Note
1. The I2C-bus subaddress 00 has to be initialized with 0 prior to reading it.
16.2.2
SUBADDRESS 02
Table 11 Analog control 1 (mode select; see Figs 28 to 35) SA 02, D2 to D0; note 1
CONTROL BITS D2 TO D0
FUNCTION
MODE 2
MODE 1
MODE 0
Mode 0: CVBS (automatic gain)
0
0
0
Mode 1: CVBS (automatic gain)
0
0
1
Mode 2: CVBS (automatic gain)
0
1
0
Mode 3: CVBS (automatic gain)
0
1
1
Mode 4: Y (automatic gain) + C (gain channel 2 fixed to GAI2 level)
1
0
0
Mode 5: Y (automatic gain) + C (gain channel 2 fixed to GAI2 level)
1
0
1
Mode 6: Y (automatic gain) + C (gain channel 2 adapted to Y gain)
1
1
0
Mode 7: Y (automatic gain) + C (gain channel 2 adapted to Y gain)
1
1
1
Note
1. For modes 0 to 3 use BYPS (SA 09, D7) = 0 (chrominance trap active) and for modes 4 to 7 use BYPS = 1
(chrominance trap bypassed).
Table 12 Analog control 1 SA 02, D5 to D3 (see Fig.11)
CONTROL BITS D5 TO D3
DECIMAL VALUE
UPDATE HYSTERESIS FOR 9-BIT GAIN
GUDL 2
GUDL 1
GUDL 0
0....
off
0
0
0
....7
±7 LSB
1
1
1
Table 13 Analog control 1 SA 02, D7 and D6
CONTROL BITS D7 AND D6
ANALOG FUNCTION SELECT FUSE
Amplifier plus anti-alias filter bypassed
FUSE 1
FUSE 0
0
0
0
1
Amplifier active
1
0
Amplifier plus anti-alias filter active
1
1
1998 May 15
38
Philips Semiconductors
Product specification
Video Input Processor (VIP)
handbook,AI22
halfpage
AI21
AI12
AI11
AD2
AD1
SAA7111
handbook,AI22
halfpage
CHROMA
AI21
LUMA
AI12
AI11
MGC637
AI21
AI12
AI11
AD2
AD1
AD1
handbook,AI22
halfpage
CHROMA
AI21
LUMA
AI12
AI11
AD2
AD1
AI12
AI11
AD2
AD1
handbook,AI22
halfpage
CHROMA
AI21
LUMA
AI12
AI11
AD2
AD1
AI12
AI11
AD2
AD1
LUMA
Fig.33 Mode 5 Y (automatic gain) + C
(gain channel 2 fixed to GAI1 level).
handbook,AI22
halfpage
CHROMA
AI21
LUMA
AI12
AI11
MGC643
AD2
AD1
CHROMA
LUMA
MGC644
Fig.34 Mode 6 Y (automatic gain) + C
(gain channel 2 adapted to Y gain).
1998 May 15
CHROMA
MGC642
Fig.32 Mode 4 Y (automatic gain) + C
(gain channel 2 fixed to GAI1 level).
AI21
LUMA
Fig.31 Mode 3; CVBS (automatic gain).
MGC641
handbook,AI22
halfpage
CHROMA
MGC640
Fig.30 Mode 2; CVBS (automatic gain).
AI21
LUMA
MGC638
MGC639
handbook,AI22
halfpage
CHROMA
Fig.29 Mode 1; CVBS (automatic gain).
Fig.28 Mode 0; CVBS (automatic gain).
handbook,AI22
halfpage
AD2
Fig.35 Mode 7 Y (automatic gain) + C
(gain channel 2 adapted to Y gain).
39
Philips Semiconductors
Product specification
Video Input Processor (VIP)
16.2.3
SAA7111
SUBADDRESS 03
Table 14 Analog control 2 (AICO2)
FUNCTION
BIT NAME
LOGIC LEVEL
CONTROL BIT
GAI18
see Table 15
D0
GAI28
see Table 16
D1
Automatic gain controlled by MODE 1 and MODE 0
GAFIX
0
D2
Gain control is user programmable via GAI1 + GAI2
GAFIX
1
D2
AGC active
HOLDG
0
D3
AGC integration hold (freeze)
HOLDG
1
D3
White peak control active
WPOFF
0
D4
White peak off
WPOFF
1
D4
Long vertical blanking
VBSL
0
D5
Short vertical blanking
VBSL
1
D5
Normal clamping by HL not
HLNRS
0
D6
Reference select by HL not
HLNRS
1
D6
Static gain control channel 1 (GAI18)
Sign bit of gain control
Static gain control channel 2 (GAI28)
Sign bit of gain control
Gain control fix (GAFIX)
Automatic gain control integration (HOLDG)
White peak off (WPOFF)
Vertical blanking select (VBSL)
HL not reference select (HLNRS)
16.2.4
SUBADDRESS 04
Table 15 Gain control analog (AIC03); static gain control channel 1 GAI1 SA 04, D7 to D0
DECIMAL
VALUE
GAIN (dB)
SIGN
BIT
CONTROL BITS D7 TO D0
GAI18
GAI17
GAI16
GAI15
GAI14
GAI13
GAI12
GAI11
GAI10
0....
−5.98
0
0
0
0
0
0
0
0
0
....255
0
0
1
1
1
1
1
1
1
1
256....
0
1
0
0
0
0
0
0
0
0
....511
5.98
1
1
1
1
1
1
1
1
1
1998 May 15
40
Philips Semiconductors
Product specification
Video Input Processor (VIP)
16.2.5
SAA7111
SUBADDRESS 05
Table 16 Gain control analog (AIC04); static gain control channel 2 GAI2 SA 05
\DECIMAL
VALUE
GAIN
(dB)
SIGN BIT
(SA 03, D1)
CONTROL BITS D7 to D0
GAI28
GAI27
GAI26
GAI25
GAI24
GAI23
GAI22
GAI21
GAI20
0....
−5.98
0
0
0
0
0
0
0
0
0
....255
0
0
1
1
1
1
1
1
1
1
256....
0
1
0
0
0
0
0
0
0
0
....511
5.98
1
1
1
1
1
1
1
1
1
16.2.6
SUBADDRESS 06
Table 17 Horizontal sync begin SA 06, D7 to D0
DELAY TIME
(STEP SIZE = 8/LLC)
CONTROL BITS D7 to D0
HSB7
HSB6
−107...
1
0
0
1
0
...108 (50 Hz)
0
1
1
0
...107 (60 Hz)
0
1
1
0
−128...−108
HSB4
HSB3
HSB2
HSB1
HSB0
1
0
1
1
1
0
0
1
0
1
1
forbidden (outside available central counter range)
109...127 (50 Hz)
forbidden (outside available central counter range)
108...127 (60 Hz)
16.2.7
HSB5
SUBADDRESS 07
Table 18 Horizontal sync stop SA 07
DELAY TIME
(STEP SIZE = 8/LLC)
CONTROL BITS D7 to D0
HSS7
HSS6
−128...−108
HSS5
HSS4
HSS3
HSS2
HSS1
HSS0
forbidden (outside available central counter range)
−107...
1
0
0
1
0
1
0
1
...108 (50 Hz)
0
1
1
0
1
1
0
0
...107 (60 Hz)
0
1
1
0
1
0
1
1
109...127 (50 Hz)
108...127 (60 Hz)
1998 May 15
forbidden (outside available central counter range)
41
Philips Semiconductors
Product specification
Video Input Processor (VIP)
16.2.8
SAA7111
SUBADDRESS 08
Table 19 Sync control SA 08, D7 to D5, D3 to D0
FUNCTION
BIT NAME
LOGIC LEVEL
CONTROL BIT
VNOI1
0
D1
VNOI0
0
D0
Searching mode
VNOI1
0
D1
VNOI0
1
D0
Free running mode
VNOI1
1
D1
VNOI0
0
D0
Vertical noise reduction (VNOI)
Normal mode
Vertical noise reduction bypassed
VNOI1
1
D1
VNOI0
1
D0
PLL closed
HPLL
0
D2
PLL open, horizontal frequency fixed
HPLL
1
D2
TV mode
(recommended for poor quality TV signals only)
VTRC
0
D3
VTR mode (recommended as default setting)
VTRC
1
D3
Word width of the loop filter (LF2) amplification = 16-bit
EXFIL
0
D5
Word width of the loop filter (LF2) amplification = 14-bit
EXFIL
1
D5
50 Hz and 625 lines
FSEL
0
D6
60 Hz and 525 lines
FSEL
1
D6
Field state directly controlled via FSEL
AUFD
0
D7
Automatic field detection
AUFD
1
D7
Horizontal PLL (HPLL)
TV/VTR mode select (VTRC)
Extended loop filter (EXFIL)
Field selection (FSEL)
Automatic field detection (AUFD)
1998 May 15
42
Philips Semiconductors
Product specification
Video Input Processor (VIP)
16.2.9
SAA7111
SUBADDRESS 09
Table 20 Luminance control
FUNCTION
BIT NAME
LOGIC LEVEL
CONTROL BIT
Aperture factor (APER)
Aperture factor = 0
Aperture factor = 0.25
Aperture factor = 0.5
Aperture factor = 1.0
APER1
0
D1
APER0
0
D0
APER1
0
D1
APER0
1
D0
APER1
1
D1
APER0
0
D0
APER1
1
D1
APER0
1
D0
Update time interval for AGC value (UPTCV)
Horizontal update (once per line)
UPTCV
0
D2
Vertical update (once per field)
UPTCV
1
D2
Active luminance processing
VBLB
0
D3
Luminance bypass during vertical blanking
VBLB
1
D3
Vertical blanking luminance bypass (VBLB
Aperture band-pass (centre frequency) (BPSS) D5 and D4
Centre frequency = 4.1 MHz
Centre frequency = 3.8 MHz; note 1
Centre frequency = 2.6 MHz; note 1
BPSS1
0
D5
BPSS0
0
D4
BPSS1
0
D5
BPSS0
1
D4
BPSS1
1
D5
BPSS0
0
D4
BPSS1
1
D5
BPSS0
1
D4
Bypassed
PREF
0
D6
Active
PREF
1
D6
Chrominance trap active; default for CVBS mode
BYPS
0
D7
Chrominance trap bypassed; default for S-Video mode
BYPS
1
D7
Centre frequency = 2.9 MHz; note 1
Prefilter active (PREF)
Chrominance trap bypass (BYPS)
Note
1. Not to be used with bypassed chrominance trap.
1998 May 15
43
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
16.2.10 SUBADDRESS 0A
Table 21 Luminance brightness control BRIG7 to BRIG0 SA 0A
CONTROL BITS D7 to D0
OFFSET
BRIG7
BRIG6
BRIG5
BRIG4
BRIG3
BRIG2
BRIG1
BRIG0
255 (bright)
1
1
1
1
1
1
1
1
128 (CCIR level)
1
0
0
0
0
0
0
0
0 (dark)
0
0
0
0
0
0
0
0
16.2.11 SUBADDRESS 0B
Table 22 Luminance contrast control CONT7 to CONT0 SA 0B
CONTROL BITS D7 to D0
GAIN
CONT7
CONT6
CONT5
CONT4
CONT3
CONT2
CONT1
CONT0
1.999 (maximum)
0
1
1
1
1
1
1
1
1.109 (CCIR level)
0
1
0
0
0
1
1
1
1.0
0
1
0
0
0
0
0
0
0 (luminance off)
0
0
0
0
0
0
0
0
−1 (inverse luminance)
1
1
0
0
0
0
0
0
−2 (inverse luminance)
1
0
0
0
0
0
0
0
16.2.12 SUBADDRESS 0C
Table 23 Chrominance saturation control SATN7 to SATN0 SA 0C
CONTROL BITS D7 to D0
GAIN
SATN7
SATN6
SATN5
SATN4
SATN3
SATN2
SATN1
SATN0
1.999 (maximum)
0
1
1
1
1
1
1
1
1.0 (CCIR level)
0
1
0
0
0
0
0
0
0 (colour off)
0
0
0
0
0
0
0
0
−1 (inverse chroma)
1
1
0
0
0
0
0
0
−2 (inverse chroma)
1
0
0
0
0
0
0
0
16.2.13 SUBADDRESS 0D
Table 24 Chrominance hue control HUEC7 to HUEC0 SA 0D
CONTROL BITS D7 to D0
HUE PHASE (DEG)
HUEC7
HUEC6
HUEC5
HUEC4
HUEC3
HUEC2
HUEC1
HUEC0
+178.6....
0
1
1
1
1
1
1
1
....0....
0
0
0
0
0
0
0
0
....−180
1
0
0
0
0
0
0
0
1998 May 15
44
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
16.2.14 SUBADDRESS 0E
Table 25 Chrominance control SA 0E
FUNCTION
BIT NAME
LOGIC LEVEL
CONTROL BIT
CHBW1
0
D1
CHBW0
0
D0
Nominal bandwidth (≈ 800 kHz)
CHBW1
0
D1
CHBW0
1
D0
Medium bandwidth (≈ 920 kHz)
CHBW1
1
D1
CHBW0
0
D0
CHBW1
1
D1
CHBW0
1
D0
Nominal time constant
FCTC
0
D2
Fast time constant
FCTC
1
D2
Chroma comb filter on (during VREF = 1)
(see Figures 20 and 21)
DCCF
0
D3
Chroma comb filter off
DCCF
1
D3
Colour standard control automatic switching between
PAL BGHI and NTSC M
CSTD1
0
D5
CSTD0
0
D4
Colour standard control automatic switching between
NTSC 4.43 (50 Hz) and PAL 4.43 (60 Hz)
CSTD1
0
D5
CSTD0
1
D4
Colour standard control automatic switching between
PAL N and NTSC 4.43 (60 Hz)
CSTD1
1
D5
CSTD0
0
D4
Colour standard control automatic switching between
NTSC N and PAL M
CSTD1
1
D5
CSTD0
1
D4
Default value
CM99
0
D6
To be set if SAA7199 (digital encoder) is used for
re-encoding in conjunction with RTCO
CM99
1
D6
Disabled
CDTO
0
D7
Every time CDTO is set, the internal subcarrier DTO
phase is reset to 0° and the RTCO output generates a
logic 0 at time slot 68 (see RTCO description Fig.16). So
an identical subcarrier phase can be generated by an
external device (e.g. an encoder).
CDTO
1
D7
Chroma bandwidth (CHBW0 and CHBW1)
Small bandwidth (≈ 620 kHz)
Wide bandwidth (≈ 1000 kHz)
Fast colour time constant (FCTC)
Disable chroma comb filter (DCCF)
Colour standard (CSTD0 and CSTD1)
Compatibility to SAA7199 (CM99)
Clear DTO (CDTO)
1998 May 15
45
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
16.2.15 SUBADDRESS 10
Table 26 Format/delay control SA 10
CONTROL BITS D2 to D0
LUMINANCE DELAY COMPENSATION
(STEPS IN 2/LLC)
YDEL2
YDEL1
YDEL0
−4...
1
0
0
...0...
0
0
0
...3
0
1
1
Table 27 VREF pulse position and length VRLN SA 10 (D3)
VREF at 60 HZ 525 LINES(1)
VREF at 50 HZ 625 LINES
VRLN
Length
Line number
0
1
0
1
240
242
286
288
first
last
first
last
first
last
first
last
Field 1
19 (22)
258 (261)
18 (21)
259 (262)
24
309
23
310
Field 2
282 (285)
521 (524)
281 (284)
522 (525)
337
622
336
623
Note
1. The numbers given in parenthesis refer to CCIR line counting.
Table 28 Fine position of HS HDEL0 and HDEL1 SA 10
CONTROL BITS D5 and D4
FINE POSITION OF HS WITH A STEP SIZE
OF 2/LLC
HDEL1
HDEL0
0
0
0
1
0
1
2
1
0
3
1
1
Table 29 Output format selection OFTS0 and OFTS1 SA 10
CONTROL BITS D7 and D6
FORMATS
OFTS1
OFTS0
RGB 565, RGB 888 (dependent on control
bit RGB888) see Table 31
0
0
YUV 422 16 bits
0
1
YUV 411 12 bits
1
0
YUV CCIR-656 8 bits
1
1
1998 May 15
46
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
16.2.16 SUBADDRESS 11
Table 30 Output control 1 SA 11
FUNCTION
BIT NAME
LOGIC LEVEL
CONTROL BIT
Colour on (COLO)
Automatic colour killer
COLO
0
D0
Colour forced on
COLO
1
D0
DMSD data to YUV output
VIPB
0
D1
ADC data to YUV output; dependent on mode settings
VIPB
1
D1
HS, HREF, VREF and VS high impedance inputs
OEHV
0
D2
Outputs HS, HREF, VREF and VS active
OEHV
1
D2
VPO-bus high-impedance inputs
OEYC
0
D3
Output VPO-bus active
OEYC
1
D3
Decoder VIP bypassed (VIPB)
Output enable horizontal/vertical sync (OEHV)
Output enable YUV data (OEYC)
Inverse composite blank (COMPO)
VREF is vertical reference
COMPO
0
D4
VREF is inverse composite blank
COMPO
1
D4
FEI sampling at CREF = LOW
(SAA7110 compatible; see Fig.17)
FECO
0
D5
FEI sampling at CREF = HIGH
FECO
1
D5
FEI control (FECO)
General purpose switch (GPSW)
Switches directly pin 64 (53) GPSW; note 1
GPSW
0
D7
GPSW
1
D7
Note
1. The pin number given in parenthesis refers to the 64-pin package.
1998 May 15
47
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
16.2.17 SUBADDRESS 12
Table 31 Output control 2 SA 12
FUNCTION
BIT NAME
LOGIC LEVEL
CONTROL BIT
Analog test select (AOSL)
AOUT connected to internal test point 1
AOUT connected to input AD1
AOUT connected to input AD2
AOUT connected to internal test point 2
AOSL1
0
D1
AOSL0
0
D0
AOSL1
0
D1
AOSL0
1
D0
AOSL1
1
D1
AOSL0
0
D0
AOSL1
1
D1
AOSL0
1
D0
Dithering off
DIT
0
D2
Dithering on
DIT
1
D2
RGB565
RGB888
0
D3
RGB888
RGB888
1
D3
Cubic interpolation (default)
CBR
0
D4
Linear interpolation (lower bandwidth)
CBR
1
D4
ODD switched to output pin 40 (29); note 1
RTSE0
0
D6
VL switched to output pin 40 (29); note 1
RTSE0
1
D6
PLIN switched to output pin 39 (28); note 1
RTSE1
0
D7
HL switched to output pin 39 (28); note 1
RTSE1
1
D7
Dithering (noise shaping) control (DIT)
RGB output format selection (RGB888)
Chroma interpolation filter function (CBR)
Real time outputs mode select (RTSE0)
Real time outputs mode select (RTSE1)
Note
1. The pin number given in parenthesis refers to the 64-pin package.
1998 May 15
48
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
16.2.18 SUBADDRESS 1A (READ-ONLY REGISTER)
Table 32 Line-21 text slicer status SA 1A
I2C-BUS
STATUS BIT
NAME
FUNCTION
STATUS BIT
F1RDY
new data on field 1 has been acquired (for asynchronous reading); active HIGH
D0
F1VAL
Line-21 of field 1 carries valid data; active HIGH
D1
F2RDY
new data on field 2 has been acquired (for asynchronous reading); active HIGH
D2
F2VAL
Line-21 of field 2 carries valid data; active HIGH
D3
16.2.19 SUBADDRESS 1B (READ-ONLY REGISTER)
Table 33 First decoded data byte of the text slicer SA 1B
I2C-BUS
TEXT DATA
BITS
BYTE1 (6 to 0)
P1
FUNCTION
data bit 6 to 0 of first data byte
DATA BITS
D6 to D0
parity error flag bit; bit goes HIGH when a parity error has occurred
D7
16.2.20 SUBADDRESS 1C (READ-ONLY REGISTER)
Table 34 Second decoded data byte of the text slicer SA 1C
I2C-BUS
TEXT DATA
BITS
BYTE2 (6 to 0)
P2
FUNCTION
data bit 6 to 0 of second data byte
DATA BITS
D6 to D0
parity error flag bit; bit goes HIGH when a parity error has occurred
D7
16.2.21 SUBADDRESS 1F (READ-ONLY REGISTER)
Table 35 Status byte SA 1F
I2C-BUS
STATUS BIT
NAME
FUNCTION
STATUS BIT
CODE
colour signal according to selected standard has been detected; active HIGH
SLTCA
slow time constant active in WIPA-mode; active HIGH
D1
white peak loop is activated; active HIGH
D2
GLIMB
gain value for active luminance channel is limited [min (bottom)]; active HIGH
D3
GLIMT
gain value for active luminance channel is limited [max (top)]; active HIGH
D4
WIPA
D0
FIDT
identification bit for detected field frequency; LOW = 50 Hz and HIGH = 60 Hz
D5
HLCK
status bit for locked horizontal frequency; LOW = locked and HIGH = unlocked
D6
STTC
status bit for horizontal phase loop; LOW = TV time-constant and
HIGH = VTR time-constant
D7
1998 May 15
49
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
17 FILTER CURVES
17.1
Anti-alias filter curve
MGD138
6
handbook, full pagewidth
V
(dB)
0
−6
−12
−18
−24
−30
−36
−42
0
2
4
6
8
10
12
f (MHz)
14
Fig.36 Anti-alias filter.
17.2
Luminance filter curves
MGD139
18
handbook, full pagewidth
VY
(dB)
(1)
(2)
(4)
(3)
6
−6
(1)
(2)
(4)
(3)
−18
−30
0
2
4
6
fY (MHz)
8
(1) = 43H; (2) = 53H; (3) = 63H; (4) = 73H.
Fig.37 Luminance control SA 09H, 4.43 MHz Trap/CVBS mode, prefilter on and different aperture band-pass
centre frequencies.
1998 May 15
50
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
MGD140
18
handbook, full pagewidth
VY
(dB)
6
(1)
(2)
(3)
(4)
−6
(4)
(3)
(2)
(1)
−18
−30
0
2
4
6
fY (MHz)
8
(1) = 40H; (2) = 41H; (3) = 42H; (4) = 43H.
Fig.38 Luminance control SA 09H, 4.43 MHz Trap/CVBS mode, prefilter on and different aperture factors.
MGD141
18
handbook, full pagewidth
VY
(dB)
6
(1)
(2)
(4)
(3)
−6
(1)
(2)
(4)
(3)
−18
−30
0
2
4
6
fY (MHz)
8
(1) = 03H; (2) = 13H; (3) = 23H; (4) = 33H.
Fig.39 Luminance control SA 09H, 4.43 MHz Trap/CVBS mode, prefilter off and different aperture band-pass
centre frequencies.
1998 May 15
51
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
MGD142
18
handbook, full pagewidth
VY
(dB)
(1)
(2)
(3)
(4)
6
−6
−18
−30
0
2
4
6
fY (MHz)
8
(1) = C0H; (2) = C1H; (3) = C2H; (4) = C3H.
Fig.40 Luminance control SA 09H, Y/C mode, prefilter on and different aperture factors.
MGD143
18
handbook, full pagewidth
VY
(dB)
6
(1)
(2)
(3)
(4)
−6
−18
−30
0
2
4
6
fY (MHz)
(1) = 80H; (2) = 81H; (3) = 82H; (4) = 83H.
Fig.41 Luminance control SA 09H, Y/C mode, prefilter off and different aperture factors.
1998 May 15
52
8
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
MGD144
18
handbook, full pagewidth
VY
(dB)
(1)
(2)
(4)
(3)
6
(1)
(2)
(4)
(3)
−6
−18
−30
0
2
4
6
fY (MHz)
8
(1) = 43H; (2) = 53H; (3) = 63H; (4) = 73H.
Fig.42 Luminance control SA 09H, 3.58 MHz Trap/CVBS mode, prefilter on and different aperture band-pass
centre frequencies.
MGD145
18
handbook, full pagewidth
VY
(dB)
6
(1)
(2)
(3)
(4)
(4)
(3)
(2)
(1)
−6
−18
−30
0
2
4
6
fY (MHz)
8
(1) = 40H; (2) = 41H; (3) = 42H; (4) = 43H.
Fig.43 Luminance control SA 09H, 3.58 MHz Trap/CVBS mode, prefilter on and different aperture factors.
1998 May 15
53
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
MGD146
18
handbook, full pagewidth
VY
(dB)
6
(1)
(2)
(4)
(3)
−6
(1)
(2)
(4)
(3)
−18
−30
0
2
4
6
fY (MHz)
8
(1) = 03H; (2) = 13H; (3) = 23H; (4) = 33H.
Fig.44 Luminance control SA 09H, 3.58 MHz Trap/CVBS mode, prefilter off and different aperture band-pass
centre frequencies.
1998 May 15
54
Philips Semiconductors
Product specification
Video Input Processor (VIP)
17.3
SAA7111
Chrominance filter curves
MGD147
6
handbook,
V full pagewidth
(dB)
0
−6
(1)
(2)
(3)
(4)
−12
−18
−24
−30
(4)
(1)
(3)
(2)
−36
−42
−48
−54
0
0.54
1.08
1.62
Transfer characteristics of the chroma low-pass dependent on CHBW[1:0] settings.
(1) CHBW [1 : 0] = 00; (2) CHBW [1 : 0] = 01; (3) CHBW [1 : 0] = 10; (4) CHBW [1 : 0] = 11.
Fig.45 Chrominance filter.
18 I2C-BUS START SET-UP
• The given values force the following behaviour of the SAA7111:
– The analog input AI11 expects a signal in CVBS format; analog anti-alias filter active
– Automatic field detection
– YUV 422/16-bit output format enabled
– Outputs HS, HREF, VREF and VS active
– Contrast, brightness and saturation control in accordance with CCIR standards
– Chrominance processing with nominal bandwidth (800 kHz).
1998 May 15
55
2,16
f(MHz)
2.7
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
Table 36 I2C-bus start set-up values
SUB
(HEX)
VALUES (BIN)
NAME(1)
FUNCTION
7
6
5
4
3
2
1
0
START
0
0
0
0
0
0
0
0
00
0
0
0
0
0
0
0
0
00
00
chip version
01
reserved
02
analog input control 1
FUSE(1 : 0), GUDL(2 : 0) and
MODE(2 : 0)
1
1
0
0
0
0
0
0
C0
03
analog input control 2
X, HLNRS, VBSL, WPOFF, HOLDG,
GAFIX, GAI2 and GAI18
0
0
1
0
0
0
1
1
33
04
analog input control 3
GAI(17 : 10)
0
0
0
0
0
0
0
0
00
05
analog input control 4
GAI(27 : 20)
0
0
0
0
0
0
0
0
00
06
horizontal sync start
HSB(7 : 0)
1
1
1
0
1
0
1
1
EB
07
horizontal sync stop
HSS(7 : 0)
1
1
1
0
0
0
0
0
E0
08
sync control
AUFD, FSEL, EXFIL, X, VTRC and HPLL 1
and VNOI(1 : 0)
0
0
0
1
0
0
0
88
09
luminance control
BYPS, PREF, BPSS(1 : 0), VBLB,
UPTCV and APER(1 : 0)
0
0
0
0
0
0
0
1
01
0A
luminance brightness
BRIG(7 : 0)
1
0
0
0
0
0
0
0
80
0B
luminance contrast
CONT(7 : 0)
0
1
0
0
0
1
1
1
47
0C
chrominance saturation SATN(7 : 0)
0
1
0
0
0
0
0
0
40
0D
chroma hue control
HUEC(7 : 0)
0
0
0
0
0
0
0
0
00
0E
chrominance control
CDTO, CM99, CSTD(1 : 0), DCCF, FCTC 0
and CHBW(1 : 0)
0
0
0
0
0
0
1
01
0F
reserved
0
0
0
0
0
0
0
0
00
10
format/delay control
OFTS(1 : 0), HDEL(1 : 0), VRLN and
YDEL(2 : 0)
0
1
0
0
0
0
0
0
40
11
output control 1
GPSW, X, FECO, COMPO, OEYC,
OEHV, VIPB and COLO
0
0
0
1
1
1
0
0
1C
12
output control 2
RTSE(1 : 0), X, CBR, RGB888, DIT and
AOSL(1 : 0)
0
0
0
0
0
0
0
1
03
13 to
19
reserved
0
0
0
0
0
0
0
0
00
1A
text slicer status
0, 0, 0, 0, F2VAL, F2RDY, F1VAL and
F1RDY
1B
decoded bytes of the
text slicer
P1 and BYTE1(6 : 0)
0
0
0
00
1C
1D to
1E
reserved
1F
status byte
ID0(7 : 0); note 2
(HEX)
P2 and BYTE2(6 : 0)
0
STTC, HLCK, FIDT, GLIMT, GLIMB,
WIPA and SLTCA and CODE
Notes
1. All X values must be set to LOW.
2. The I2C-bus subaddress 00 has to be initialized with 0 prior to reading.
1998 May 15
read only register
56
0
0
0
0
read only register
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
19 PACKAGE OUTLINES
PLCC68: plastic leaded chip carrier; 68 leads
SOT188-2
eD
eE
y
X
60
A
44
43 Z E
61
bp
b1
w M
68
1
HE
E
pin 1 index
A
e
A4 A1
(A 3)
β
9
k1
27
Lp
k
detail X
10
26
e
v M A
ZD
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
k1
max.
Lp
v
w
y
0.51
1.44
1.02
0.18
0.18
0.10
Z D(1) Z E (1)
max. max.
UNIT
A
A1
min.
A3
A4
max.
bp
b1
mm
4.57
4.19
0.51
0.25
3.30
0.53
0.33
0.81
0.66
0.180
0.020 0.01
0.165
0.13
0.930 0.930 0.995 0.995 0.048
0.057
0.021 0.032 0.958 0.958
0.020
0.05
0.007 0.007 0.004 0.085 0.085
0.890 0.890 0.985 0.985 0.042
0.040
0.013 0.026 0.950 0.950
inches
D (1)
E (1)
e
eD
eE
HD
HE
k
24.33 24.33
23.62 23.62 25.27 25.27 1.22
1.27
24.13 24.13
22.61 22.61 25.02 25.02 1.07
2.16
β
2.16
45 o
Note
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT188-2
112E10
MO-047AC
1998 May 15
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-03-11
57
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm
SOT393-1
c
y
X
A
48
33
49
32
ZE
e
E HE
A
A2
(A 3)
A1
θ
wM
Lp
bp
pin 1 index
L
17
64
detail X
16
1
w M
bp
e
v M A
ZD
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
3.00
0.25
0.10
2.75
2.55
0.25
0.45
0.30
0.23
0.13
14.1
13.9
14.1
13.9
0.8
HD
HE
L
17.45 17.45
1.60
16.95 16.95
Lp
v
w
y
1.03
0.73
0.16
0.16
0.10
Z D (1) Z E (1)
1.2
0.8
1.2
0.8
θ
o
7
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT393-1
1998 May 15
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
96-05-21
97-08-04
MS-022
58
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
20 SOLDERING
20.3.2
20.1
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
CAUTION
Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
20.2
If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
Reflow soldering
Reflow soldering techniques are suitable for all PLCC and
QFP packages.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
The choice of heating method may be influenced by larger
PLCC or QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
20.3.3
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.
20.3.1
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
20.4
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Wave soldering
PLCC
Wave soldering techniques can be used for all PLCC
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream corners.
1998 May 15
METHOD (PLCC AND QFP)
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
20.3
QFP
59
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
21 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
22 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
23 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1998 May 15
60
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
NOTES
1998 May 15
61
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
NOTES
1998 May 15
62
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
NOTES
1998 May 15
63
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1998
SCA60
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Date of release: 1998 May 15
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9397 750 03116