PHILIPS SAA8110G

INTEGRATED CIRCUITS
DATA SHEET
SAA8110G
Digital Signal Processor (DSP) for
cameras
Preliminary specification
File under Integrated Circuits, IC02
1997 Jun 13
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
FEATURES
• High precision digital processing with 9 or 10 bit input
• Different types of CCDs (PAL, NTSC and CIF)
(progressive, interlaced and non-interlaced)
• Black offset preprocessing (including optical black offset
control)
• RGB-separation (with contour and white clip signals
generation)
GENERAL DESCRIPTION
The SAA8110G is designed for desktop video applications
(teleconferencing, video grabbing), surveillance and
video-phone systems.
• RGB-processing (colour space matrix, black control,
knee and gamma)
• RGB-to-YUV conversion (including down-sampling
filters)
The SAA8110G may be applied together with an analog
front-end (TDA8786 including CDS/AGC/ADC), a timing
generator and a microcontroller as shown in
Figs 18 and 19. Other configurations are also possible.
• White balance control
• Y-processing (contour processing, false colour detector,
filters and noise reduction)
The CCD-sensor can be of PAL, NTSC or CIF type (with
complementary mosaic colour filter). The maximum
number of active pixels is limited to 800 samples/line.
The 10-bits digital input may have a pixel frequency of up
to 14.318 MHz.
• UV-processing (false colour correction and noise
reduction)
• Digital output formatter (including CIF-formatter, DTV2,
D1)
The SAA8110G output data is available in a digital and an
analog output format. Two digital output formats are
selectable: DTV2 (CCIR-601 at the input pixel frequency)
and D1 (CCIR-656 at twice the input pixel frequency). It is
also possible to generate the CIF and QCIF formats as
subsets from the processed CCD-image. The analog
output is available in one of four formats: RGB, YUV, YC
or CVBS. The SAA8110G includes a digital
PAL/NTSC-encoder and 3 DACs for this purpose.
• Analog output preprocessing (including
PAL/NTSC-encoder and DACs)
• Measurement engine (prepared for auto-exposure and
auto-white balance features)
• Miscellaneous functions (e.g. switched mode power
supply pulse generator, control DAC)
• VH-reference and window timing
• Serial interface (selectable I2C-bus or 80C51 UART
interface)
Two types of serial interface are selectable: a fast 400 kHz
I2C-bus interface or a 80C51 UART interface (with bit rates
from 1 Mbit/s up to 3.75 Mbit/s depending on the system
clock used). The power dissipation of the SAA8110G can
be optimized for each application using the built-in power
management function.
• Mode control (including power management).
APPLICATIONS
• Desktop video applications
• Surveillance systems
• Video-phone systems.
ORDERING INFORMATION
TYPE
NUMBER
SAA8110G
1997 Jun 13
PACKAGE
NAME
LQFP80
DESCRIPTION
plastic low profile quad flat package; 80 leads; body 12 × 12 × 1.4 mm
2
VERSION
SOT315-1
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDD
digital supply voltage
3
5
5.25
V
VDDA
analog supply voltage
3
5
5.25
V
VIL
LOW level digital input voltage
0
−
0.3VDDD
V
VIH
HIGH level digital input voltage
0.6VDDD
−
VDDD
V
VOL
LOW level digital output voltage IOL = −20 µA
−
−
0.5
V
VOH
HIGH level digital output voltage IOH = 20 µA
VDDD − 0.1 −
−
V
IDDD(tot)
total digital supply current
−
200
mA
IDDA(tot)
total analog supply current
Tamb
operating ambient temperature
IDMD
supply current in digital output
mode
fclk = 14.3 MHz; VDDD = 5 V
fclk = 14.3 MHz; VDDD = 3.3 V −
80
100
mA
−
30
40
mA
fclk = 14.3 MHz; VDDA = 3.3 V −
22
35
mA
fclk = 14.3 MHz; VDDA = 5 V
fclk = 14.3 MHz; VDDD = 5 V;
note 1
0
−
75
°C
−
185
−
mA
85
−
mA
fclk = 14.3 MHz; VDDD = 3.3 V −
Note
1. When digital mode is selected, VDDA supply pins can be connected to ground.
1997 Jun 13
180
3
1997 Jun 13
4
RESET
T2, T1, T0
CLK2
CLK1
CCD9
to
CCD0
30
31 to 33
47
2
7 to 16
MODE
CONTROL
20
P0, P1
18
SCLK
24
UVPROCESSING
YPROCESSING
4
HSYNCIN
FIIN
5
77
74
61 to 54
70 to 63
MGK158
28
51
52
48
50
49
80
79
44
43
35, 37, 39
A0/SNDA
75
SNERT/
I2C
SELECT
SDA
SCL/SNCL
A1/SNRES
73
SNERT/I2C
INTERFACE
ANALOG
OUTPUT
PREPROCESSING
PAL/NTSCENCODER
V DACs
DIGITAL
OUTPUT
FORMATTER
SIS
CREF/PXQ
LLC
FIOUT
HREF
VSYNCOUT
XIN
XOUT
RBIAS
DECOUPL
OUT3 to OUT1
UV0 to UV7
Y0 to Y7
Digital Signal Processor (DSP) for
cameras
Fig.1 Block diagram.
VSYNCIN
3
VH-REFERENCE WINDOW
TIMING AND CONTROL
SAA8110G
STROBE
SDATA
SMP
CDACRBIAS
26,
27 23
25
21
RGB
TO
YUV
MEASUREMENT ENGINE
RGB
PROCESSING
MISCELLANEOUS
FUNCTIONS
RGB
SEPARATION
(INCL. LINE
MEMORIES)
CDACOUT
OFFSET
PREPROCESSING
19, 34,
42
VSSA(CD)
VSSA(OB)
VSSA(BG)
45, 41, 22,
40, 38, 36
VDDA(BG)
VDDA(DC)
VDDA(CD)
VDDA(O1)
VDDA(O2)
VDDA(O3)
6, 17, 76,
78, 53, 71
VSSD(C1)
VSSD(C2)
VSSD(C3)
VSSD(C4)
VSSD(P1)
VSSD(P2)
full pagewidth
1, 29,72,
46, 62
VDDD(C1)
VDDD(C2)
VDDD(C3)
VDDD(P1)
VDDD(P2)
Philips Semiconductors
Preliminary specification
SAA8110G
BLOCK DIAGRAM
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
PINNING
SYMBOL
PIN
I/O
DESCRIPTION
VDDD(C1)
1
I
digital supply 1 for digital core and CLK1 related peripherals
CLK1
2
I
system- or pixel clock
VSYNCIN
3
I
vertical synchronization input
HSYNCIN
4
I
horizontal synchronization input
FIIN
5
I
field identification signal input
VSSD(C1)
6
I
digital ground 1 for digital core and CLK1 related peripherals
CCD9
7
I
(preprocessed) AD-converted CDD-signal bit 9 (MSB)
CCD8
8
I
(preprocessed) AD-converted CDD-signal bit 8
CCD7
9
I
(preprocessed) AD-converted CDD-signal bit 7
CCD6
10
I
(preprocessed) AD-converted CDD-signal bit 6
CCD5
11
I
(preprocessed) AD-converted CDD-signal bit 5
CCD4
12
I
(preprocessed) AD-converted CDD-signal bit 4
CCD3
13
I
(preprocessed) AD-converted CDD-signal bit 3
CCD2
14
I
(preprocessed) AD-converted CDD-signal bit 2
CCD1
15
I
(preprocessed) AD-converted CDD-signal bit 1
CCD0
16
I
(preprocessed) AD-converted CDD-signal bit 0 (LSB)
VSSD(C2)
17
I
digital ground 2 for digital core and CLK1 related peripherals
SCLK
18
O
serial clock to TDA8786
VSSA(CD)
19
I
analog ground for control DAC
CDACOUT
20
O
output control DAC
CDACRBIAS
21
I
pin to connect external bias resistor for control DAC
VDDA(CD)
22
I
analog supply for control DAC
SDATA
23
O
serial data to TDA8786
STROBE
24
O
strobe to TDA8786
SMP
25
O
switch mode pulse for DC-DC
P0
26
O
quasi-static control output pin 0
P1
27
O
quasi-static control output pin 1
SIS
28
I
SNERT/I2C-bus select input signal
VDDD(C2)
29
I
digital supply 2 for digital core and CLK1 related peripherals
RESET
30
I
reset input
T2
31
I
test mode control signal bit 2
T1
32
I
test mode control signal bit 1
T0
33
I
test mode control signal bit 0
VSSA(OB)
34
I
analog ground for the three output buffers
OUT3
35
O
output buffer 3 (R, V or CVBS)
VDDA(O3)
36
I
analog supply for output buffer OUT3
OUT2
37
O
output buffer 2 (B, U or C)
VDDA(O2)
38
I
analog supply for output buffer OUT2
OUT1
39
O
output buffer 1 (G or Y)
VDDA(O1)
40
I
analog supply for output buffer OUT1
1997 Jun 13
5
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SYMBOL
SAA8110G
PIN
I/O
VDDA(DC)
41
I
analog supply for analog core of triple DAC
VSSA(BG)
42
I
analog ground for to band gap
DECOUPL
43
O
pin to be used for external decoupling of band gap
RBIAS
44
O
external bias resistor connection for band gap
VDDA(BG)
45
I
analog supply for band gap
VDDD(P1)
46
I
digital supply 1 for CLK2 related peripherals
CLK2
47
I
output clock (CLK2 frequency is 2 × CLK1 frequency)
FIOUT
48
O
field identification output pulse
VSYNCOUT
49
O
vertical synchronization output
HREF
50
O
horizontal reference output for YUV-port
CREF/PXQ
51
O
clock/pixel qualifier output for YUV-port
LLC
52
O
line-locked system clock output
VSSD(P1)
53
I
digital ground 1 for CLK2 related peripherals
UV7
54
O
multiplex chrominance UV bit 7 (MSB)
UV6
55
O
multiplex chrominance UV bit 6
UV5
56
O
multiplex chrominance UV bit 5
UV4
57
O
multiplex chrominance UV bit 4
UV3
58
O
multiplex chrominance UV bit 3
UV2
59
O
multiplex chrominance UV bit 2
UV1
60
O
multiplex chrominance UV bit 1
UV0
61
O
multiplex chrominance UV bit 0 (LSB)
VDDD(P2)
62
I
digital supply for CLK2 related peripherals
Y7
63
O
luminance Y or multiplexed YUV bit 7 (MSB)
Y6
64
O
luminance Y or multiplexed YUV bit 6
Y5
65
O
luminance Y or multiplexed YUV bit 5
Y4
66
O
luminance Y or multiplexed YUV bit 4
Y3
67
O
luminance Y or multiplexed YUV bit 3
Y2
68
O
luminance Y or multiplexed YUV bit 2
Y1
69
O
luminance Y or multiplexed YUV bit 1
Y0
70
O
luminance Y or multiplexed YUV bit 0 (LSB)
VSSD(P2)
71
I
digital ground 2 for to CLK2 related peripherals
VDDD(C3)
72
I
digital supply 3 for digital core and CLK1 related peripherals
A1/SNRES
73
I
I2C-bus address select pin A1 or SNERT reset input
A0/SNDA
74
I
I2C-bus address select pin A0 or SNERT data input/output
SDA
75
I
I2C-bus data input/output
VSSD(C3)
76
I
digital ground 3 for digital core and CLK1 related peripherals
SCL/SNCL
77
I
I2C-bus clock/SNERT clock input
VSSD(C4)
78
I
digital ground 4 for digital core and CLK1 related peripherals
XIN
79
I
input crystal oscillator for subcarrier lock applications
XOUT
80
O
output crystal oscillator for subcarrier lock applications
1997 Jun 13
DESCRIPTION
6
Philips Semiconductors
Preliminary specification
61 UV0
62 VDDD(P2)
63 Y7
64 Y6
65 Y5
66 Y4
67 Y3
68 Y2
69 Y1
70 Y0
71 VSSD(P2)
SAA8110G
72 VDDD(C3)
73 A1/SNRES
74 A0/SNDA
75 SDA
76 VSSD(C3)
77 SCL/SNCL
79 XIN
80 XOUT
handbook, full pagewidth
78 VSSD(C4)
Digital Signal Processor (DSP) for
cameras
VDDD(C1)
1
60 UV1
CLK1
2
59 UV2
VSYNCIN
3
58 UV3
HSYNCIN
4
57 UV4
FIIN
5
56 UV5
VSSD(C1)
6
55 UV6
CCD9
7
54 UV7
CCD8
8
53 VSSD(P1)
CCD7
9
52 LLC
CCD6 10
51 CREF/PXQ
SAA8110G
CCD5 11
50 HREF
CCD4 12
49 VSYNCOUT
CCD3 13
48 FIOUT
CCD2 14
47 CLK2
CCD1 15
46 VDDD(P1)
CCD0 16
45 VDDA(BG)
VSSD(C2) 17
44 RBIAS
Fig.2 Pin configuration.
1997 Jun 13
7
VDDA(O1) 40
OUT1 39
VDDA(O2) 38
OUT2 37
VDDA(O3) 36
OUT3 35
VSSA(OB) 34
T0 33
T1 32
T2 31
RESET 30
VDDD(C2) 29
SIS 28
P1 27
P0 26
41 VDDA(DC)
SMP 25
CDACOUT 20
STROBE 24
42 VSSA(BG)
SDATA 23
VSSA(CD) 19
VDDA(CD) 22
43 DECOUPL
CDACRBIAS 21
SCLK 18
MGK151
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
FUNCTIONAL DESCRIPTION
RGB processing
Black offset preprocessing
The RGB processing includes several features:
• Colour space matrix depending on CCD type to be
suitable with different sensor colour filters
The input data is clamped within the optical black pixel
area of the CCD. The size of the digital clamp window is
16 pixels by 128 lines (i.e. TDA8786). It is possible to
differentiate black levels for odd/even lines, pixels and
fields. This comes in addition to the analog preprocessing
clamp which is active on the clamp pulse generated by the
external timing circuit. The analog clamp is included in the
TDA8786.
• Gain correction for R and B signals for white balance
control
• Black offset
• Adjustable knee
• Adjustable gamma function.
The knee function is applied to all three RGB signals.
Its shape is continuously adjustable by changing the slope
and the knee offset point.
RGB separation
PAL/NTSC sensors generate interlaced data adding offset
in the complementary colour pixels. The RGB separation
block with its two line memories generates the three
components Y, 2R − G, and 2B − G for each input data
corresponding to a pixel value of the CCD. Then the
triplet R, G, B is derived. This block also delivers some
contour and white clip information.
handbook, full pagewidth
To compensate for the non-linear response of display
devices, a gamma correction is applied to R, G and B
signals. It may be adjustable from linear to a 0.35 power
coefficient.
LINE
MEMORY
R
G
RGB
COLOUR
SEPARATION
LINE
MEMORY
10
B
white clip
CCD inputs
vertical contour
MGK153
Fig.3 RGB separation diagram.
Rgain
handbook, full pagewidth
×
R
Rblack
+
R
3×
KNEE
Gblack
G
+
COLOUR
MATRIX
Bgain
B
×
3×
GAMMA
G
Bblack
+
B
MGK154
Fig.4 RGB processing.
1997 Jun 13
8
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
• Contour correction allowing an increase of the
luminance transitions for a sharper picture
RGB-to-YUV block
After RGB processing, the channels are separated in a
luminance and two colour difference path:
Y = 0.299 R + 0.597 G + 0.114 B, U = 0.49 (B − Y) and
V = 0.88 (R − Y) . It also contains two down-sampling
filters for U and V signals.
• Black stretch function for contrast enhancement in dark
scenes
• False colour detector used by the UV-processing block
to enable the colour killer
• Filters and noise reduction by coring (only in the high
frequency part of the signal).
Y-processing
The luminance component includes several features:
9
handbook, full pagewidth
R
CONVERSION
MATRIX
G
B
DOWNSAMPLING
& MUX
8
Y
(0 to 511)
UV
(−128 to 127)
MGK155
Fig.5 RGB-to-YUV conversion.
vertical contour
(−512 to 511)
(from RGB-separation)
handbook, full pagewidth
Y
(0, 0.5 to 255.5)
10
false colour
CONTOUR PROCESSING
AND
FALSE COLOUR DETECTION
9
BLACK STRETCH
+
NOISE
REDUCTION
8
Y
MGK156
Fig.6 Y processing.
1997 Jun 13
9
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
handbook, full pagewidth
UV
(−127 to 128)
8
SAA8110G
NOISE
REDUCTION
FALSE COLOUR
CORRECTION
UV GAIN
CONTROL
false colour
(from Y-processing)
white clip
(from RGB-separation)
8
UV
(−127 to 128)
MGK157
Fig.7 UV-processing.
Moreover, using a high resolution PAL and NTSC CCDs,
it is possible to generate the following formats by means of
cutting or down-sampling.
UV-processing
The chrominance component includes several features:
• Noise reduction for high frequencies
• CIF 352 × 288 at 25 frame/second and CIF 352 × 240 at
30 frame/second
• False colour correction: a colour killer cuts the false
colour components in the UV signals
• QCIF 176 × 144 at 25 frame/second and QCIF
176 × 120 at 30 frame/second.
• UV-gain control used to set the correct UV levels for
PAL/NTSC encoding.
Table 1
As the colour filter saturation levels may be different in the
CCD, the white clip is used in the UV-processing to
suppress colour errors in case of high exposure.
INPUT FORMAT
PAL/NTSC-sensor
Digital output formatter
This block contains several features:
• Generation of a synchronous clock LLC (twice the clock
frequency)
• Generation of three synchronization signals (HREF,
CREF and VS)
CIF
• Synchronization of the output data to the output clock
LLC
• Generation of a CIF/QCIF output format for several type
of sensors (see Table 1)
• Selection of the required digital output format (8-bit
multiplexed YUV standard D1/CCIR 656, including the
generator of SAV/EAV codes or 16-bit multiplexed YUV
4 : 2 : 2 standard DTV2/CCIR601).
Note that the D1 frequency data rate is twice the DTV2
frequency data rate.
1997 Jun 13
CIF/QCIF output format for different sensor
types
10
OUTPUT FORMAT
CIF
‘full screen’
CIF
‘zoom-by-2’
QCIF
‘full screen’
QCIF
‘zoom-by-2’
QCIF
‘zoom-by-4’
QCIF
‘full screen’
QCIF
‘zoom-by-2’
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
handbook, full pagewidth 521 522 523 524 525 1
2
3
4
5
6
SAA8110G
7
8
9
10
11
12
13
14
15
18
19
20
21
22
23
HSYNCIN
VSYNCIN
FIIN
VSYNCOUT
FIOUT
CSYNC
BLANK
BURST
MGK159
Fig.8 Vertical timing NTSC odd field.
handbook, full pagewidth 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 280 281 282 283 284 285
HSYNCIN
VSYNCIN
FIIN
VSYNCOUT
FIOUT
CSYNC
BLANK
BURST
MGK160
Fig.9 Vertical timing NTSC even field.
1997 Jun 13
11
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
handbook, full pagewidth 621 622 623 624 625 1
2
3
4
5
SAA8110G
6
7
8
9
10
11
12
13
14
15
20
2 1 22
23
24
25
HSYNCIN
VSYNCIN
FIIN
VSYNCOUT
FIOUT
CSYNC
BLANK
BURST(1)
−
+ even frame
+
odd frame
odd frame
even frame
+
+
−
+
−
+
−
+
−
+
−
+
−
+
−
+
−
+
−
+
−
+
−
+
−
+
−
+
−
+
−
MGK161
(1) +: burst phase = +135°.
−: burst phase = −135°.
Fig.10 Vertical timing PAL odd field.
handbook, full pagewidth 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327
332 333 334 335 336 337
HSYNCIN
VSYNCIN
FIIN
VSYNCOUT
FIOUT
CSYNC
BLANK
BURST(1)
−
+
+
−
odd frame
+
+
even frame
−
+
−
+
−
+
−
+
−
+
−
+
−
+
+
−
+
−
+
−
+
−
+
−
+
−
+
−
MGK162
(1) +: burst phase = +135°.
−: burst phase = −135°.
Fig.11 Vertical timing PAL even field.
1997 Jun 13
12
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
handbook, full pagewidth
SAA8110G
0
NPIX
HSYNCIN
BLANK
BURST
HREF
MGK163
Fig.12 Horizontal timing for non-CIF processing.
Y(UV)7
to
Y(UV)0
handbook, full pagewidth
SAA8110G
(OUTPUTS
CLOCKED
AT
CLK2)
YUV
HOST
LLC
PXQ
HREF
VSYNCOUT
Y(UV)
FF
00
00
SAV
U0
Y0
V0
Y2
U4
Y4
V4
Y6
LLC
PXQ
HREF
sample moment
MGK164
Fig.13 8-bits multiplexed format (D1, CCIR656); example: CIF down-sampling.
1997 Jun 13
13
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
Y(UV)7
to
Y(UV)0
handbook, full pagewidth
SAA8110G
(OUTPUTS
CLOCKED
AT
CLK2)
YUV
HOST
LLC
PXQ
HREF
VSYNCOUT
YUV
FF
00
00
SAV
U0
Y0
V0
Y1
U2
Y2
V2
UN−1 YN−1
FF
00
00
EAV
LLC
PXQ
HREF
sample moment
MGK165
Fig.14 8-bits multiplexed format (D1, CCIR656); SAV/EAV included.
Y7 to Y0
handbook, full pagewidth
Y(UV)
UV7 to UV0
UV
SAA8110G
(OUTPUTS
CLOCKED
AT
CLK2)
HOST
LLC
CREF
HREF
VSYNCOUT
FIOUT
Y(UV)
Y0
Y1
Y2
Y3
Y4
Y5
Y6
UV
U0
V0
U2
V2
U4
V4
U6
LLC
CREF
HREF
MGK166
sample moment
Fig.15 16-bits multiplexed format (DTV2, CCIR601).
1997 Jun 13
14
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
Analog output preprocessing
Serial interface
This block contains several features:
The serial interface can either be an I2C-bus or a 80C51
UART (SNERT) (selectable with the SIS pin). Via the serial
interface the external microcontroller can control the
internal settings of the SAA8110G and read/write from/to
the internal RAM work-space linked to the measurement
engine (see list of parameter settings in
Chapter “Programming”). Some of the registers are
double-buffered to prevent that the change of control data
becomes visible on the output display.
• Delay compensation for the luminance signal
• Up-sampling of the UV signal
• PAL/NTSC encoding
• YUV to RGB conversion
• Selection of the required analog output format (RGB,
YUV, YC or CVBS).
The analog outputs are given by three voltage DACs in
RGB or YUV or CVBS or YC format. Channels Y and G
include the sync information. Over-sampling at twice fclk is
made so that external filtering becomes easier. It is also
possible to have an adjustment of the subcarrier via the
serial interface. When CVBS output is used, chrominance
range is halved compared to luminance.
Miscellaneous functions
A three wire bus is used to send 10-bit settings from a
microcontroller to the TDA8786 via the SAA8110G
registers.The SAA8110G supplies picture parameters and
needs some configuration parameters. Those values are
contained in registers and are updated during every
vertical synchronization pulse.
Measurement engine
The measurement engine performs measurements on
some selectable internal signals on frame/field basis and
prepares data for auto exposure, auto focus and auto
white balance processing. It uses an internal RAM
work-space for its control and data handling operations.
The contents of the work-space can be accessed via the
serial interface.
Mode control
This block controls the operation mode of the SAA8110G.
As described in Table 2, four modes may be selected:
depending on power reduction and I2C-bus timing.
Power dissipation management
The power dissipation of the SAA8110G will depend on the
required activity for a certain application. It is possible to
switch off via the serial interface unconcerned parts for a
given application. When an analog output is not used, the
power voltage pin of the DAC can be connected to ground
to limit the power consumption.
Vertical/horizontal reference and window timing and
control
The SAA8110G uses two vertical and horizontal
synchronization input signals (VSYNCIN and HSYNCIN) to
derive internal vertical and horizontal reference signals.
Besides a Field Identification input (FIIN) signal is required.
The timing of the vertical and horizontal input signals
should be such that:
Clock configurations
Following conditions must be fulfilled:
• CLK1 should be generated as divide-by-two from CLK2
1. The pixel frequency (CLK1) must be line-locked to the
line frequency of HSYNCIN: the number of clock
periods between two HSYNCIN pulses must be a fixed
integer number. The HSYNCIN should be at least one
clock period active HIGH.
• The RESET pin should not go LOW before CLK1 and
CLK2 are both HIGH or LOW.
Table 2
2. The VSYNCIN signal indicates the start of a field
(or frame in case of progressive scanning); this
signal is also required for non-interlaced applications.
The VSYNCIN should be at least one clock period
HIGH.
T2
3. The FIIN pulse indicates the phase of the field in case
of interlaced applications (FIIN = 0 means odd field).
1997 Jun 13
15
T1
SAA8110G mode control
T0
MODE
application
mode
POWER
REDUCTION
to(h)
I2C-BUS
on
short
on
long
0
0
0
0
0
1
0
1
0
off
short
0
1
1
off
long
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
Table 3
SAA8110G
Sensor and output formats covered by the SAA8110G
CCD-formats
STANDARD
RESOLUTION
FRAME SCANNING AND
FREQUENCY (Hz)
ACTIVE
H/V
PIXEL
FREQUENCY
(MHz)
OUTPUT FORMATS
DIGITAL
TOTAL
H/V
ANALOG
DTV2/D1 CIF
CIF
non-interlaced
60
352/243
429/262
6.75
no
yes
yes
CIF
non-interlaced
50
352/288
432/312
6.75
no
yes
yes
NTSC
high resolution
non-interlaced
60.054
768/243
910/262
interlaced
29.997
768/494
910/525
14.3181
yes
yes
yes
PAL
high resolution
non-interlaced
50
752/288
908/312
interlaced
25
752/582
908/625
14.1875
yes
yes
yes
yes
no
yes
yes
no
yes
NTSC
non-interlaced
medium resolution interlaced
60
512/243
606/262
30
512/492
606/525
PAL
non-interlaced
medium resolution interlaced
50
512/288
618/312
25
512/582
618/625
9.53495
9.65625
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDDD
digital supply voltage
−0.3
+7.0
V
VDDA
analog supply voltage
−0.3
+7.0
V
∆VDDD-DDA
supply voltage difference between the digital and the analog
supply voltages
−0.1
+0.1
V
VI
input voltage
−0.3
VDD + 0.3
V
VO
output voltage
−0.3
VDD + 0.3
V
Ptot
total allowed power dissipation at Tamb = 75 °C
−
1
W
Tstg
storage temperature
−55
+150
°C
Tj
junction temperature
−
125
°C
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
1997 Jun 13
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
16
in free air
VALUE
50
UNIT
K/W
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDACs specification
OUTPUTS PINS OUT1 TO OUT3 (IN CASE OF SCALE FACTOR = 1)
Vo
output voltage (see note 1)
Voffset
amplitude offset voltage between
DACs
code 0
code 511
0
0.2
1.3
1.5
−60
0.3
V
1.6
V
+60
mV
INPUTS
Rbias
Rext
Cdecoup
bias resistor
external anti-reflection resistor
note 2
14
15
16
kΩ
note 3
44
47
50
kΩ
note 2
−
21
−
Ω
note 3
−
70.6
−
Ω
10
−
100
nF
decoupling capacitor
TRANSFER FUNCTION
RES
resolution
−
9
−
bit
NLdiff
differential non-linearity
−
−
1.5
LSB
NLint
integral non-linearity
−
−
1.5
LSB
THD60
total harmonic distortion at 60%
of full-scale
fclk = 30 MHz, fi = 1 MHz,
VDDA = 5 V
−
55
45
dB
S/N
signal-to-noise ratio
fclk = 30 MHz, fo = 1 MHz,
VDDA = 5 V
−
45
38
dB
4.5
5.0
5.5
V
APPLICATION1: PAL/NTSC HIGH RESOLUTION
VDD1
supply voltage
VDD2
supply voltage
3.0
3.3
3.6
V
CR
conversion rate
−
28.6
−
MHz
fclk
clock frequency
−
28.6
−
MHz
Ba
analog bandwidth
−
7.6
−
MHz
4.5
5.0
5.5
V
APPLICATION 2: PAL/NTSC MEDIUM RESOLUTION
VDD1
supply voltage
VDD2
supply voltage
3.0
3.3
3.6
V
fclk
clock frequency
−
19
−
MHz
Ba
analog bandwidth
−
6.5
−
MHz
SWITCHING CHARACTERISTICS ON RISING FULL-SCALE STEP (see Fig.16)
tPD
propagation delay time
to 50% value
−
9
13
ns
tst(10-90)
settling time
10% to 90% full-scale
−
9
11
ns
tst(LSB)
setting time (to ±1 LSB)
−
25
30
ns
1997 Jun 13
17
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SYMBOL
PARAMETER
SAA8110G
CONDITIONS
MIN.
TYP.
MAX.
UNIT
CDAC specification (VDD = 5 V)
Lint
−
integral linearity
Ldiff
differential linearity
Vo(CDAC)
output voltage at pin CDAC
−
1
LSB
−
−
1⁄
2
LSB
code 0
−
10
300
mV
code 61, VDDA = 5 V
−4.6
4.95
−
V
3
3.25
−
V
Ro(CDAC)
output resistance at pin CDAC
−
13
−
Ω
fclk
clock frequency
−
28.6
−
MHz
RL
load resistance
−
10
−
kΩ
CL
load capacitance
−
−
10
pF
tPD
propagation delay time
to 50% value (see Fig.17),
VDDA = 5 V
−
−
104
ns
tst(10-90)
settling time
10% to 90% full-scale (see
Fig.16)
−
9
−
ns
tst(LSB)
setting time
to ±1 LSB (see Fig.16)
−
25
−
ns
code 61, VDDA = 3.3 V
INPUTS RELATED TO CLK1: CCD0 TO CCD9, VSYNCIN, HSYNCIN, FIIN
tsu(i)(D)1
data input set-up time CCD
inputs, HSYNCIN, VSYNCIN, FIIN
0
3
5
ns
tsu(i)(D)2
data input set-up time SNRES and
SNDA
0
1
2
ns
th(i)(CCD)
data hold time CCD inputs
−1
−
+1
ns
th(i)(D)
data input hold time
0
1
3
ns
VSYNCIN, HSYNCIN, FIIN
OUTPUTS RELATED TO CLK2: Y7 TO Y0, UV7 TO UV0, CREF, HREF, VSYNCOUT, FIOUT AND LLC
th(o)(D)
data output hold time
−
8
22
ns
td(o)(D)
data output delay time
−
25
31
ns
OUTPUTS RELATED TO CLK1: SDATA, STROBE, SMP, P0, P1 AND SCLK
th(o)(D)
data output hold time
−
13
21
ns
td(o)(D)
data output delay time
−
15
24
ns
δclk
clock duty cycle
40
−
60
%
Notes
1. When CVBS output is used the chrominance range is halved compared to luminance.
2. Monitor load of 75 Ω with Rext = 21 Ω and Rbias = 15 kΩ at 3.3 V application.
3. Monitor load of 75 Ω with Rext = 70.6 Ω and Rbias = 47 kΩ at 5.0 V application.
1997 Jun 13
18
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
handbook, full pagewidth
SAA8110G
CLK2
code FS
code 0
input code
(example of a full-scale
input data transmission)
1 LSB
(code FS)
10%
50%
90%
(code 0)
1 LSB
tst(10−90)
tPD
MGK167
tst(LSB)
Fig.16 Switching characteristics.
handbook, full pagewidth
CLK1
tsu
th(i)(D)
DATA IN
tPD
DATA OUT
MGK168
Fig.17 Data input/output timing.
1997 Jun 13
19
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
PROGRAMMING
Overview available write
ADDRESS
0
SYMBOL
CONTROL0
FUNCTION
miscellaneous; see Table 4
5(1)
FORMAT
RANGE/VALUE
byte
n.a.
byte
n.a.
1
CONTROL1
miscellaneous; see Table
2
CONTROL2
miscellaneous; see Table 6
byte
n.a.
4
OB_STARTL_F0
first line optical black window in field 0
byte
0 to 255
5
OB_STARTL_F1
first line optical black window in field 1/frame
byte
0 to 255
7
OB_STARTP
first pixel optical black window
byte
0 to 255
8
OB_PE_F0
fixed optical black level for even pixel in field 0
byte
0
9
OB_PO_F0
fixed optical black level for odd pixel in field 0
byte
0
10
OB_PE_F1
fixed optical black level for even pixel in
field 1/frame
byte
0
11
OB_PO_F1
fixed optical black level for odd pixel in
field 1/frame
byte
0
12
OB_OFFSET_LE
optical black offset for even line
byte
0
13
OB_OFFSET_LO
optical black offset for odd line
byte
0
14
MOSAIC_SEP_S1
multiplication-factor for Yn at even line and even
pixel
byte
0 to 255
15
MOSAIC_SEP_S2
multiplication-factor for Yn at even line and odd
pixel
byte
0 to 255
16
MOSAIC_SEP_S3
multiplication-factor for Yn at odd line and even
pixel
byte
0 to 255
17
MOSAIC_SEP_S4
multiplication-factor for Yn at odd line and odd
pixel
byte
0 to 255
18
WHITE_CLIP_THR
threshold for white clip
byte
768 to 1023
19
COL_MAT_P11
colour matrix coefficient p11
byte
−128 to 127
20
COL_MAT_P12
colour matrix coefficient p12
byte
−128 to 127
21
COL_MAT_P13
colour matrix coefficient p13
byte
−128 to 127
22
COL_MAT_P21
colour matrix coefficient p21
byte
−128 to 127
23
COL_MAT_P22
colour matrix coefficient p22
byte
−128 to 127
24
COL_MAT_P23
colour matrix coefficient p23
byte
−128 to 127
25
COL_MAT_P31
colour matrix coefficient p31
byte
−128 to 127
26
COL_MAT_P32
colour matrix coefficient p32
byte
−128 to 127
27
COL_MAT_P33
colour matrix coefficient p33
byte
−128 to 127
colour matrix R-gain
factor(1)
byte
0 to 255
factor(1)
28
COL_MAT_RGAIN
29
COL_MAT_BGAIN
colour matrix B-gain
byte
0 to 255
34
BLACK_LEVEL_R
fixed R-black level offset(1)
byte
−128 to 127
35
BLACK_LEVEL_G
fixed G-black level offset(1)
byte
−128 to 127
36
BLACK_LEVEL_B
offset(1)
byte
−128 to 127
37
RGB_KNEE_OFFSET offset for RGB-knee(1)
byte
0 to 255
6 bits
0 to 63
38
1997 Jun 13
GAMMA_BALANCE
fixed B-black level
gamma multiplication factor
20
(LS)(1)
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
ADDRESS
SAA8110G
SYMBOL
FUNCTION
FORMAT
RANGE/VALUE
0 to 255
39
NPIX_LSB
number of pixels on a line
byte
40
NPIX_MSB
number of pixels on a line
2 bits
0 to 3
41
FPIX_ACT
number of first active pixel on a line
byte
0 to 255
42
LPIX_ACT_LSB
number of last active pixel on a line
byte
0 to 255
43
FLINE_ACT_F0
number of first active line in field 0
byte
0 to 255
44
LLINE_ACT_F0_LSB
number of last active line in field 0
byte
0 to 255
45
FLINE_ACT_F1_LSB
number of first active line in field 1/frame
byte
0 to 255
46
LLINE_ACT_F1_LSB
number of last active line in field 1/frame
byte
0 to 255
47
ACT_LINES_MSB
MSBs of active line numbers
byte
see Table 7
48
CTR_UPD_LINE
number of line for double buffered update control
registers
byte
0 to 255
49
KCOMB
vertical contour comb filter coefficient (MS)
3 bits
0 to 7
VCGAIN
vertical contour gain (LS)
4 bits
0 to 15
50
CLDLEV
contour level dependancy level(1)
byte
0 to 255
51
HCHGAIN
horizontal contour band pass filter high gain (MS)
4 bits
0 to 15
HCLGAIN
horizontal contour band pass filter low gain (LS)
4 bits
0 to 15
52
CNCLEV
contour noise coring level(1)
6 bits
0 to 63
53
CONGAIN
contour gain factor
byte
0 to 63
54
FCDLEV
false colour detect level
byte
0 to 255
55
YNCLEV
Y (luminance) noise coring level
byte
0 to 127
byte
0
factor(1)
56
YGAIN
Y (luminance) gain
57
YCMPDEL
Y (luminance) compensation delay
4 bits
−3 to 4
see Table 8
58
UVNCLEV
UV (chrominance) noise coring level
byte
0 to 255
UGAIN
U(B − Y) gain
factor(1)
byte
0
60
VGAIN
V(R − Y) gain
factor(1)
byte
0
61
DTO_FREQ_LSB
DTO frequency (MSB)(1)
byte
0 to 255
62
DTO_FREQ_ISB
DTO frequency(1)
byte
0 to 255
byte
0 to 255
59
63
DTO_FREQ_MSB
64
PHASESHIFT
PHASE_SHIFT colour subcarrier
byte
0 to 255
65
BURST_LEVEL
BURST_LEVEL colour burst
byte
0 to 255
66
A
AWB_A (ME)
byte
−98
pole_thresh #A (DPD)
byte
0 to 255
67
B
AWB_B (ME); pole_thresh #B (DPD)
byte
−104
68
C
AWB_C (ME); pole_thresh #A (DPD)
byte
−68
69
D
AWB_D (ME); pole_thresh #B (DPD)
byte
126
70
E
AWB_E (ME)
6 bits
63
pole_thresh #A (DPD)
byte
63
71
72
1997 Jun 13
F
HIGHLIGHTTHR
DTO frequency
(LSB)(1)
AWB_F (ME)
6 bits
0
pole_thresh #B (DPD)
byte
0
highlight-threshold (ME); pole_thresh #A(DPD)
byte
60
21
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
ADDRESS
SYMBOL
SAA8110G
FUNCTION
ME_sync + ME_Resultscale (ME)
FORMAT
RANGE/VALUE
4 bits
0, 1
see Table 9
73
ME_RESSCALE
pole_thresh #B (DPD)
byte
0 to 255
74
MWHVGRID
measurement horizontal and vertical grid
6 bits
see Table 10
78
WHITECLIP
white clip limiter level for analog outputs
byte
256 + (0 to 255)
79
AUTO_BLACK
auto black attack slope control
2 bits
see Table 20
82
DOP_CNTRL0
digital output processing control
byte
see Table 11
byte
see Table 12
control(1)
83
DOP_CNTRL1
digital output processing
84
CIF_WSTRT
CIF-window start pixel (LSBs)
byte
0 to 255
85
CIF_WSTRT
CIF-window start line (LSBs)
byte
0 to 255
86
PRE_SI_LSB
control data for analog preprocessing
byte
0 to 255
87
PRE_SI_MSB
control data/address for analog preprocessing
5 bits
see Table 13
88
SMP_CNTRL
control for switched mode power supply
byte
0
89
PRE_CNTRL
preprocessing/timing control
byte
see Table 14
90
DIG_SETUP
set-up in digital output
byte
0.255
91
BLANKLEV
blanking level in analog output
byte
0 to 255
92
BL-SETUP
set-up level in analog output
byte
0 to 255
byte
see Table 15
control(1)
93
AOF_CNTRL
analog output format
94
PRE_PROC_DEL
control compensation delay W.I.L preprocessing
4 bits
0 to 15
126
RAMWRPTR
write pointer for RAM work-space
byte
0 to 223
127
RAMWRDATA
write data for RAM work-space
byte
0 to 255
Note
1. Double buffered write register.
1997 Jun 13
22
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
Register details
Table 4
CONTROL0
NAME.BITNR
NAME
FUNCTION
CONTROL0.0
AUTO_OPT_BLACK
Auto Optical Black ON/OFF
CONTROL0.1
SENS_VGA
RGB-bayer/complementary mosaic colour filter
CONTROL0.2
MOSAIC_FIL_TYPE
complementary mosaic colour filter
CONTROL0.3
PIX_PHASE
toggle phase for pixel in colour separation
CONTROL0.4
LINE_PHASE
toggle phase for line in colour separation
CONTROL0.5
FIELD_PHASE
toggle phase for field in colour separation
Table 5
CONTROL1
NAME.BITNR
NAME
FUNCTION
CONTROL1.2
RGB_KNEE_K
compression factor for RGB-knee (see Table 16)(1)
CONTROL1.3
RGB_KNEE_K
compression factor for RGB-knee (see Table 16)(1)
CONTROL1.4
MED_RES
medium resolution for PAL/NTSC encoder
CONTROL1.5
PAL_NTSC
choose between PAL/NTSC
CONTROL1.6
BSSCALE
black stretch scaling factor (see Table 17)(1)
CONTROL1.7
BSSCALE
black stretch scaling factor (see Table 17)(1)
Note
1. Double buffered write register.
Table 6
CONTROL2
NAME.BITNR
NAME
FUNCTION
CONTROL2.0
FCC_FILTER+
false colour low-pass filter ON/OFF
CONTROL2.1
NI
non-interlaced/interlaced
CONTROL2.2
DTOMWL_LSB
DTO measurement window length(1)
CONTROL2.3
DTOMWL_MSB
DTO measurement window length(1)
CONTROL2.4
WH_CL_MAP
white clip mapping on UV-grid (see Table 18)
CONTROL2.5
WH_CL_MAP
white clip mapping on UV-grid (see Table 18)
CONTROL2.6
FC_MAP
false colour mapping on UV-grid (see Table 19)
CONTROL2.7
FC_MAP
false colour mapping on UV-grid (see Table 19)
Note
1. Double buffered write register.
Table 7
ACT_LINES_MSB
NAME.BITNR
FUNCTION
ACT_LINES_MSB.0 and ACT_LINES_MSB.1
bits 8 and 9 for last active pixel number on a line
ACT_LINES_MSB.2 and ACT_LINES_MSB.3
bits 8 and 9 for last active line number in field 0
ACT_LINES_MSB.4 and ACT_LINES_MSB.5
bits 8 and 9 for first active line number in field 1/frame
ACT_LINES_MSB.6 and ACT_LINES_MSB.7
bits 8 and 9 for last active line number in field 1/frame
1997 Jun 13
23
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
Table 8
Table 9
SAA8110G
YCMPDEL
CONTENT
FUNCTION
(1 + 4 × B3 + B2 + 2 × B1 + 1 × B0) × td
0000
1td
0001
2td
0010
3td
0011
4td
0100
5td
0101
6td
0110
7td
0111
8td
1000
5td
1001
6td
1010
7td
1011
8td
1100
9td
1101
10td
1110
11td
1111
12td
MECNTRL
NAME.BITNR
FUNCTION
DEFAULT
MECNRTL.0, MECNRTL.1,
MECNRTL.2
ME_Resultscaler selection (0, 2, 4, 8, 16, 32)
1
MECNRTL.3
ME_Sync (synchronize field/frame toggle of measurement engine)
0
Table 10 MWHVGRID
NAME.BITNR
FUNCTION
DEFAULT
MWHVGRID.0, MWHVGRID.1,
MWHVGRID.2 and MWHVGRID.3
horizontal ME-window pixel size selection
4
MWHVGRID.4 and MWHVGRID.5
vertical ME-window pixel size selection
4
Table 11 DOP_CNTRL0
NAME.BITNR
FUNCTION
DOP_CNTRL0.0 and
DOP_CNTRL0.1
horizontal CIF-processing control bits HCIF.0 and HCIF.1 (see Table 21)
DOP_CNTRL0.2 and
DOP_CNTRL0.3
vertical CIF-processing control bits VCIF.0 and VCIF.1 (see Table 22)
DOP_CNTRL0.4 and
DOP_CNTRL0.5
temporal CIF-processing control bits TCIF.0 and TCIF.1 (see Table 23)
DOP_CNTRL0.6
CIF-processing enabled/disabled (by-pass)
DOP_CNTRL0.7
CIF-format/QCIF format
1997 Jun 13
24
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
Table 12 DOP_CNTRL1
NAME.BITNR
FUNCTION
DEFAULT
DOP_CNTRL1.0 and DOP_CNTRL1.1
horizontal pixel start MSBs for CIF-window
−
DOP_CNTRL1.2 and DOP_CNTRL1,3
vertical line start MSBs for CIF-window
−
DOP_CNTRL1.4
PXQ-output/CREF-output
−
DOP_CNTRL1.5
CIF-sensor applied/non CIF-sensor applied
−
DOP_CNTRL1.6
d1/d2 output format
−
DOP_CNTRL1.7
DOP-processing active/disabled
1
Table 13 PRE_SI_MSB
NAME.BITNR
FUNCTION
PRE_SI_MSB.0 and PRE_SI_MSB.1
control data bits d8 and d9
PRE_SI_MSB.2 to PRE_SI_MSB.4
control address bits a0 to a2
Table 14 PRE_CNTRL
NAME.BITNR
FUNCTION
PRE_CNTRL.0 to PRE_CNTRL.5
control DAC-data bits 0 to 5
PRE_CNTRL.6 and PRE_CNTRL.7
static control outputs P0 and P1
Table 15 AOF_CNTRL
NAME.BITNR
FUNCTION
DEFAULT
AOF_CNTRL.0 and AOF_CNTRL.1
analog output format selection (see Table 24)
1
AOF_CNTRL.2 and AOF_CNTRL.3
scale factor #1 for GY-multiplex (see Table 25)
−
AOF_CNTRL.4 and AOF_CNTRL.5
scale factor #2 for BU-, C- and RV-multiplex (see Table 26)
−
AOF_CNTRL.6
analog output processing active/disabled
1
AOF_CNTRL.7
triple DAC output range control large/small
−
Table 16 Knee compression factors
Table 17 Black stretch scaling factors
W 1.n
W 1.n
COMPRESSION FACTOR
n=3
n=2
0
0
0
1
1
0
1
1
1997 Jun 13
SCALING FACTOR
1⁄
8
1⁄
4
3⁄
8
1⁄
2
25
n=7
n=6
0
0
0
0
1
1
0
1
1
1⁄
4
1⁄
2
3⁄
4
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
Table 18 White-clip detection spreading
Table 23 TCIF-control
W 82.n
W 2.n
PROCESSING
SPREADING FILTER
n=5
n=4
[0 0 1 0 0]
0
0
one-to-one copy
1
[0 1 1 1 0]
0
1
down-sample by 2
X
[1 1 1 1 1]
1
0
down-sample by 4
1
1
down-sample by 8
n=5
n=4
0
0
0
1
Table 19 False colour detection spreading
Table 24 Analog output format selection
W 2.n
SPREADING FILTER
n=7
n=6
0
0
W 93.n
FORMAT
[0 0 1 0 0]
n=1
n=0
0
1
[0 1 1 1 0]
0
0
RGB
1
X
[1 1 1 1 1]
0
1
YUV
1
0
YC
1
1
CVBS
Table 20 Auto black attack slope control
W 79.n
n=7
n=6
0
0
0
1
1
0
1
1
SLOPE FACTOR
Table 25 Scale #1 selection
1⁄
4
1⁄
8
1⁄
16
1⁄
32
W 93.n
SCALE FACTOR
n=3
n=2
0
X
1
0
2
1
3⁄
2
1
1
Table 21 HCIF-control
Table 26 Scale #2 selection
W 82.n
SLOPE FACTOR
W 93.n
n=1
n=0
0
0
down-sample by 4
n=5
n=4
0
1
down-sample by 2
0
X
1
X
one-to-one copy
1
0
2
1
3⁄
2
SCALE FACTOR
1
Table 22 VCIF-control
W 82.n
PROCESSING
n=3
n=2
0
0
down-sample by 4
0
1
down-sample by 2
1
0
one-to-one copy
1
1
up-sample by 2
1997 Jun 13
26
1
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
APPLICATION INFORMATION
TDA8786 and SAA8110G can be used with Sharp CCDs. TDA8786A and SAA8110G can be used with Sony CCDs.
Table 27 gives as an example some references of ICs which may be used with Philips TDA8786(A)/SAA8110G. This
overview is not restrictive, both devices are compatible with other CCD/V-driver/PPG combinations including the more
recent ones.
Table 27 Possible components for the application of Figs 18 and 19.
NTSC
CCD TYPE
SONY CCDs
COMPONENT TYPE
CCD
MEDIUM
RESOLUTION
LZ2313H5
PAL
HIGH
RESOLUTION
LZ2353A
V-driver
SHARP CCDs
MEDIUM
RESOLUTION
LZ2323H5
HIGH
RESOLUTION
LZ2363
LR36683N
timing generator
LZ95G55
LZ95G71
LZ95G55
LZ95G71
CCD
ICX056AK
ICX068AK
ICX057AK
ICX069AK
V-driver
timing generator
CXD1250MN; CXD1267N
CXD1257AR
CXD1265R
CXD1257AR
CXD1265R
Notes to the application diagram
• In the configuration of Figs 18 and 19, the microcontroller reads and writes data from/to the DSP using the SNERT-bus
(UART-mode 0). Optional external control is available through the I2C-bus.
• Free I/O pins of the microcontroller can be used to control PGG, or for other purposes.
• 83Cxxx processing is synchronized by VD interruption. Depending on VD polarity, it can be necessary to invert VD.
• A customized 83Cxxx is available for this application. Please contact your nearest Philips sales office.
1997 Jun 13
27
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
handbook, full pagewidth
P0
P0 (optional, PPG setting)
P1
P1 (optional, PPG settings)
CDACOUT (optional, can be used for frequency tuning)
CDACOUT
CLK1 (to ADC and DSP)
CLK2
CLK2 (to DSP, CLK2 = 2 × CLK1)
CDSPULSE1
CDSPULSE1
CDSPULSE2
CDSPULSE2
VERTICAL DRIVER
(PPG)
analog ground
CLAMPCDS
CLAMPCDS (CLAMP CDS, OPB, ADC can be the same)
CLAMPOPB
CLAMPOPB
CLAMPADC
CLAMPADC
PreBlank (optional)
PreBlank
Horizontal Drive
HD (to DSP and µC)
Vertical Drive
VD (to DSP and µC)
V1
H1
H2
CDSPULSE1
CDSPULSE2
OEN (optional)
(from microcontroller)
VDDD
CLPOPB
VCCA1
AGCOUT
PBIN
220 nF
VDDA3
PBOUT
ADCIN
CLPADC
Vref
220 nF
VDDD
P1.0
10 kΩ
P1.1
P1.2
P1.3
OEN (optional)
(to ADC)
P1.4
P1.5
P1.6/SCL
VDDD
P1.7/SDA
JB
JB
P3.0/RxD
P3.1/TxD
1
JB
RST
P3.2/INT0
SDA
2
SCL
3
4
+5 V
GND
JB
4.7 µF
VDDD
P3.3/INT1
A0/SNDA
P3.4/T0
SCL/SNCL
P3.5/T1
HD (opt.)
P3.6/WR
FIIN
P3.7/RD
A1/SNRES
XTAL2
18 pF
12 MHz
XTAL1
VSS
2
44
3
43
4
5
VDD
40
39
CLAMPADC
(from PPG)
8
38
9
37
10
36
11
13
14
SDA
4.7
kΩ
P0.4/AD4
P0.6/AD6
5
4
VSS
EPROM
A2
6 PCF8598 3
NC
VDDD PTC
7 PCF8594 2
4.7
VDD
WP
kΩ
8 PCF8582 1
SCL
P0.3/AD3
P0.5/AD5
DGND2
VCCD2
CLK
CLPCDS
CDSP1
31
7
30
TDA8786G
or
TDA8786AG
8
9
29
28
10
27
11
26
12
25
31
30
17
29
VDDD VDDD
18
28
19
27
20
26
21
25
22
24
1
nF
2.2
nF
200
nF
RESET_DSP
(to DSP)
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
MGK393
18 pF
Fig.18 SAA8110G system configuration for camera application (continued in Fig.19).
1997 Jun 13
D5
D4
D3
D2
D1
D0
DGND1
B
C
D
E
F
G
H
I
J
K
L
1
nF
100 nF
P2.7/A15
P2.5/A13
D6
A
100
nF
P0.7/AD7
P2.6/A14
D7
VDDD
32
16
D8
100 nF
83C54/ 35 EA
VDDD
83C654
ALE
(OM-XXX) 33 PSEN
15
D9
VDDA1
41
7
32
6
VDDD
P0.0/AD0
33
5
1 nF
P0.1/AD1
MICRO42
CONTROLLER
P0.2/AD2
6
ANALOG TO DIGITAL INTERFACE
4
DACOUT
VD (from PPG)
10 µF
34
OGND1
13 14 15 16 17 18 19 20 21 22 23 24
10 kΩ
BC848C
3
SEN
100 nF
VDDD
35
SCLK
5V
AGND1
36
2
SDATA
VDDA2
AMPOUT
AMPOUT
48 47 46 45 44 43 42 41 40 39 38 37
STGE
5V
OFDOUT
SMP_CLK
(from DSP)
VDDA1
100 nF
1
DEC1
SWITCH MODE
POWER SUPPLIES
(optional)
VDDA1
PBK
100 nF
VRB
VRT
+xxV
CDSP2
PreBlank
VCCA3
CLAMPOPB
IN1
OFD level
(optional)
IN2
1 µF
Reset
CCDout
VCCA2
Shutter
AGND3
H2
AGND2
H1
CCD
5V
VDDA1
100 nF
V4 V3 V2 V1
−xxV
100 nF
VDDA1
VERTICAL
DRIVER BUFFER
VCCO
V2
OE
V3
CLAMPCDS
Electrical Reset
Shutter Pulse
STBY
V4
CLK1
FI (to DSP and µC)
Field Id
VCCD1
digital ground
CLK1
28
M
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
handbook, full pagewidth
25
24
23
DIGITAL OUTPUT CONNECTOR
26
22
A1/SNRES
20
A0/SNDA
18
SDA
16
14
SCL/SNCL
VDDD
12
10
100
nF
8
VDDD
6
optional
4
CLK1
VD
HD
FI
VSYNCIN
HSYNCIN
FIIN
VSSD(C1)
CCD9
A
CCD8
B
CCD7
C
CCD6
D
CCD5
E
CCD4
F
CCD3
G
CCD2
H
CCD1
I
CCD0
J
VSSD(C2)
60
2
59
3
58
4
57
5
56
DIGITAL SIGNAL PROCESSOR
6
55
7
54
8
53
9
52
10
51
SAA8110G
11
VDDD
50
12
49
13
48
14
47
15
46
16
45
OUT1
VDDA(O1)
OUT2
VDDA(O2)
OUT3
VDDA(O3)
T0
VSSA(OB)
T1
T2
RESET
SIS
VDDD(C2)
P1
P0
SMP
SDATA
43
STROBE
44
18
VDDA(CD)
17
150 kΩ
VDDA3
VDDA2
L
M
SMP_CLK (to power supply)
9
7
5
3
1
VDDD
UV4
UV5
UV6
UV7
VSSD(P1)
LLC
CREF/PXQ
HREF
VSYNCOUT
FIOUT
CLK2
VDDD(P1)
VDDA(BG)
RBIAS
CLK2 (from PPG)
VDDD
VDDA3
47 kΩ
100 nF
3
1 6
5
4
2 7
SVHS
L(1)
68 Ω
Y
L(1)
Green
6
11
7
100 nF
2
L(1)
RESET_DSP
(from µC)
11
UV3
VDDA3
VDDD
13
2
1
100 nF
15
UV2
L(1)
100
nF
100 nF
17
UV1
100 nF
DECOUPL
VSSA(BG) 100 nF
19
42
VDDA(DC)
CDACOUT
VDDA3
41
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
CDACOUT
100 nF
10 nF
SCLK
VSSA(CD)
19
UV0
Y6
Y7
VDDD(P2)
Y4
Y5
Y2
Y3
Y0
Y1
A1/SNRES
VDDD(C3)
VSSD(P2)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
CDACRBIAS
K
CLK1
SDA
A0/SNDA
VDDD
100 nF V
DDD(C1)
SCL/SNCL
VSSD(C3)
XOUT
XIN
VSSD(C4)
100 nF
21
L(1)
68 Ω
C
12
8
3
13
9
14
4
L(1)
10
5
15
U, Blue
P0
P1
VDDD
L(1)
digital ground
L(1)
analog ground
68 Ω
V, Red
L(1)
CVBS
CVBS-RCA
MGK394
(1) Values depend on DSP output configuration.
Fig.19 SAA8110G system configuration for camera application (continued from Fig.18).
1997 Jun 13
29
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
PACKAGE OUTLINE
LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
SOT315-1
c
y
X
A
60
41
40 Z E
61
e
Q
E HE
A A2
(A 3)
A1
w M
θ
bp
L
pin 1 index
80
Lp
21
detail X
20
1
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.16
0.04
1.5
1.3
0.25
0.25
0.13
0.18
0.12
12.1
11.9
12.1
11.9
0.5
HD
HE
14.15 14.15
13.85 13.85
L
Lp
Q
v
w
y
1.0
0.7
0.3
0.70
0.58
0.2
0.15
0.1
Z D (1) Z E (1)
θ
1.45
1.05
4
0o
1.45
1.05
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-03-24
95-12-19
SOT315-1
1997 Jun 13
EUROPEAN
PROJECTION
30
o
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
If wave soldering cannot be avoided, the following
conditions must be observed:
SOLDERING
Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all LQFP
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Wave soldering
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1997 Jun 13
31
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Jun 13
32
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
NOTES
1997 Jun 13
33
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
NOTES
1997 Jun 13
34
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
NOTES
1997 Jun 13
35
Philips Semiconductors – a worldwide company
Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101, Fax. +43 1 60 101 1210
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773
Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 0044
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580920
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Hungary: see Austria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.
Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722
Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 829 1849
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 3 301 6312, Fax. +34 3 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 632 2000, Fax. +46 8 632 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2686, Fax. +41 1 481 7730
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1997
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/1200/01/pp36
Date of release: 1997 Jun 13
Document order number:
9397 750 01576