CXA1616N/S Sync Discriminator for CRT Displays Description The CXA1616N/S automatically selects one of three types of sync signals – separate sync, composite sync, or sync-on video – to shape the waveform. It is ideally suited as a synchronous signal processor for auto tracking type displays. Features • Output of synchronous signal polarity information is obtainable • Supported polarities and amplitudes of input signals are as follows: — V. separate sync (positive/negative polarity, 1 to 5Vp-p For capacitor input 1.5 to 5Vp-p) — H. separate sync (positive/negative polarity, 1 to 5Vp-p) — Composite sync (positive/negative polarity, 1 to 5Vp-p) — Sync-on video (negative polarity sync level: 0.2 to 0.6Vp-p, picture level: 0 to 2.1Vp-p) CXA1616N 24 pin SSOP (Plastic) CXA1616S 22 pin SDIP (Plastic) Absolute Maximum Ratings (Ta = 25°C) • Supply voltage Vcc 14 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 900 mW Operating Condition Supply voltage Vcc 12 ± 0.5 V Applications CRT display monitors Pin Configuration (Top View) (SSOP) VS IN 1 (SDIP) 24 VCC VS IN 1 22 VCC 23 VD PVC 2 3 22 V IN EVC CS IN 4 21 V OUT PHC 5 20 HD EHC 6 19 PV VIDEO IN 7 18 PH HD SEL 8 17 EV TIMING 9 16 EH 15 IN/EXT CLAMP 10 13 IN/EXT 14 V REF GND 11 12 V REF PVC 2 EVC CLAMP 10 GND 11 NC 12 3 21 VD 20 V IN CS IN 4 19 V OUT PHC 5 18 EHC 6 17 PV VIDEO IN 7 16 PH HD SEL 8 15 EV TIMING 9 14 EH HD 13 NC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E92Y01C7Y-PS CXA1616N/S Block Diagram 1 EVC VS IN PVC (SSOP) 2 3 Polarity Check V. Ramp Generator Exist Check EV 20 HD PV Logic CS IN 4 PHC 5 Polarity Check Exist Check 8 PH HD SEL 23 VD 10 CLAMP 9 TIMING 18 HD EH EHC VIDEO IN 6 7 Clamp Pulse Generator Sync Sep V OUT V IN GND VCC V REF 24 IN/EXT 11 EV 22 14 EH 21 PH 19 18 17 16 15 PV Bias 1 EVC VS IN PVC (SDIP) 2 3 Polarity Check V. Ramp Generator Exist Check EV PV Logic CS IN Polarity Check 4 Exist Check 8 PH PHC 5 EHC 6 HD SEL 21 VD EH 20 12 11 22 GND VCC –2– V REF 19 V IN IN/EXT EV EH 17 16 15 14 13 V OUT Bias PH 7 Sync Sep PV VIDEO IN Clamp Pulse Generator 10 CLAMP 9 TIMING CXA1616N/S Pin Description Pin No. Symbol (Ta = 25°C, VCC = 12V) Pin voltage Description Equivalent circuit SDIP SSOP VCC Inputs the vertical separate sync. Inputs at TTL level and polarity is positive/negative. V Low ≤ 0.5V V High ≥ 4.5V Connect a pull-down resistance of 470kΩ or less to GND. 200k 1 1 VS IN — 1k 8k 1 20k 8k VCC 2 2 48k PVC 0.3, 3.4V 5 5 96k 2 1k 32k 8k PHC 32k VCC 5V 48k 2k 3 3 EVC 4.3 to 7.9V 3 8k 32k 17µA Connection pin of an integral capacitor for the polarity discriminator circuit (Polarity Check); connects a 0.22µF capacitor to GND. When the capacitor is connected at positive polarity: 3.4V; negative polarity: 0.3V. No input : 3.7V. Vertical ramp waveform generator. Generates a ramp waveform synchronized to the input separate sync frequency. Connects a 0.68µF capacitor to GND. The charging time constant (rising edge) of ramp waveform is determined by the 2kΩ resistance and the external 0.68µF capacitor, and the discharging time constant (falling edge) by the external 0.68µF capacitor and the internal 17µA current. When there is a verticai separate sync, the voltage at Pin 3 rises between 5.5 and 7.9V, existence discrimination (Exist Check) is performed, and an input signal is judged to exist. The voltage is 4.3V when no input signal exists. VCC 72k 4 4 CS IN 4.2V 2k 100µA Inputs the composite and horizontal separate sync (positive/negative polarity). Amplitude is 1 to 5Vp-p. Input through a capacitor. 200 4 400k 4V –3– CXA1616N/S Pin No. Symbol Pin voltage Description Equivalent circuit SDIP SSOP VCC 200 20k 6 6 6 EHC 3.0, 4.8V 1k 1k 3.8V 12k 30µA VCC 8k 16k 8.3V 5.8V 4k 7 7 VIDEO IN 4.5V 200 7 29µA 16k 72k Connects a quasi-peak hold circuit with a 33kΩ resistance and 0.22µF capacitor to discriminate input signal existence during composite sync input. When there is a composite sync, the voltage is held by the quasi-peak hold circuit at 4.2 to 4.8V. This voltage is then compared to a 3.8V reference voltage, and an input signal is judged to exist. The voltage is 3.0V when no input signal exists. Inputs the sync-on video (sync is negative polarity). Connect a 0.47µF capacitor and a 270Ω resistance in series between the pin and its signal source. The slice level is determined by the relationship between the sync frequency and Pulse width and the sum of the 200Ω internal resistance and the 270Ω external resistance multiplied by the 29µA current. ∆V ≈ 29µA × (T2/T1) × (200 + 270) ∆V T1 4.5V 200k 8 8 HD SEL — 70k 1k 8 T2 Selects whether or not to output the VD interval portion of HD (H Drive Pulse). Input is at TTL Ievel. V Low ≤ 0.5V V High ≥ 2.0V Low level: The VD interval HD is not output. High level or open: The VD interval HD is output as is. VCC 100 9 9 TIMING 10.5V 10k 9 1k 30µA –4– 17k Connect a desired capacitor and a 12kΩ resistance in parallel to GND. This capacitor changes the output pulse width of clamp pulse. (See Fig. 1) CXA1616N/S Pin No. Symbol Pin voltage Description Equivalent circuit SDIP SSOP VCC 56k 2.7V 10 10 CLAMP 0.15V 10k 10 Clamp pulse output. This is an open collector at positive polarity. 5k 11 11 GND — 0V GND VCC 12 1k 12 14 V REF — 1k 20 ( 14 ) ( 22 ) 30µA 16k 36k Reference for the vertical sync separator circuit. Connect an external resistance between Vcc and GND to apply the reference voltage. Based on 4.4V. (See Fig. 2) 4.5V 13 14 15 16 17 15 16 17 18 19 IN/EXT EH EV PH PV 20k 13 14 0.12, 4.5V 15 16 17 8k 15 16 17 18 19 VCC 18 20 HD 0.15V 8k Outputs the polarity and existence information of a sync signal. See "Description of Operation" for their l/O matrix. 8k 18 8k ( 20 ) HD (H Drive Pulse) output. This is an open collector at positive polarity. 10k VCC 45k 19 21 V OUT 2.3V 15k 19 ( 21 ) 2k 60k –5– Outputs the sync signal separated from the composite sync or sync-on video for the vertical sync separator. Positive polarity output at an amplitude of 2.3 to 6.0V. CXA1616N/S Pin No. SDIP SSOP Symbol Pin voltage Description Equivalent circuit VCC 12 1k 20 22 V IN — 1k 20 ( 14 ) ( 22 ) 30µA VCC 21 23 VD 0.15V 16k 36k 8k 21 Input for vertical sync separation comparator. Connect an integrator with a 3.9kΩ resistance and a 3300pF capacitor between Pins 19 and 20. The comparator operates when the voltage of the integrated sync signal at the vertical interval becomes higher than the voltage which lowers by VBE (approximately 0.7V) from the voltage at Pin 12. 8k 8k ( 23 ) VD (V Drive Pulse) output. This is an open collector at positive polarity. 10k 22 24 VCC 12V — –6– Power supply. CXA1616N/S Electrical Characteristics No. 1 Item VD output voltage (Ta = 25°C, VCC = 12V, See the Electrical Characteristics Test Circuit) Symbol Measurement description Measurement point Min. EVD Measures the height of the VD output wave for VS (vertical sparate sync) input. Input signal A (tw = 12.5µs). 5V output power supply, RL = 2.2kΩ. ( VD Pin 21 Pin 23 ( (H level) 4.85 (L level) 0 5.0 5.0 V 0.15 0.4 V ( VD Pin 21 Pin 23 ( 11.5 12.5 13.5 µs ( VD Pin 21 Pin 23 ( 6.5 10 12.5 µs ( VD Pin 21 Pin 23 ( 6.5 10 12.5 µs ( HD Pin 18 Pin 20 ( ( HD Pin 18 Pin 20 ( HD Pin 18 Pin 20 2 VD output pulse width 1 tV1 Measures the width of the VD output pulse for VS (vertical separate sync) input. Input signal A (tw = 12.5µs). 3 VD output pulse width 2 tV2 Measures the width of the VD output pulse for CS (composite sync) input. Input signal B (tw = 12.5µs) tV3 Measures the width of the VD output pulse for VIDEO IN (sync-on video) input. Input signal C (tw = 12.5µs). EHD Measures the height of the HD output wave for CS (composite sync) input. Input signal D (tw = 0.65µs). 5V output power supply, R4 = 2.2kΩ. 4 5 VD output pulse width 3 HD output voltage 6 HD output pulse width 1 7 HD output pulse width 2 8 9 10 th1 Measures the width of the HD output pulse for CS (composite sync) input. , Input signal B (tw = 0.65µs). th2 Measures the width of the HD output pulse for VIDIEO IN (sync-on video) input. Input signal C (tw = 0.65µs). Clamp pulse output pulse width 1 Clamp pulse output pulse width 2 5.0 5.0 V 0.15 0.4 V ( 0.5 0.65 0.8 µs ( 0.5 0.65 0.8 µs CLAMP (Pin 10) tC1 Measures the width of the clamp pulse output pulse for CS (composite sync) input. Input signal B. Connects Pin 9 to GND through a 560pF capacitor and a 12kΩ resistance in parallel. tC2 Measures the width of the clamp pulse output pulse for VIDEO IN (sync-on video) input. Input signal C. Connects Pin 9 to GND through a 10nF capacitor and a 12kΩ resistance in parallel. –7– Max. Unit (H level) 4.85 (L level) 0 Measures the hight of the clamp pulse output wave for CS (composite sync) input. Input signal B (tw = 0.65µs). 5V output power supply, R15 = 2.2kΩ. Clamp pulse ECP output voltage Typ. (H level) 4.85 (L level) 0 5.0 5.0 V 0.15 0.4 V CLAMP (Pin 10) — 0.25 — µs CLAMP (Pin 10) 3.7 4.1 4.5 µs CXA1616N/S (Ta = 25°C, VCC = 12V, See the Electrical Characteristics Test Circuit) No. 11 12 13 14 15 16 17 18 19 20 Measurement point Min. Typ. PVC voltage 1 VPV1 The voltage integral of the vertical polarity discrimination circuit for VS (vertical separate sync) input. Input signal F (negative logic). PVC (Pin 2) — 0.3 — V PVC voltage 2 VPV2 The voltage integral of the vertical polarity discrimination circuit for VS (vertical separate sync) input. Input signal G (positive Iogic). PVC (Pin 2) — 3.4 — V PHC voltage 1 VPH1 The voltage integral of the vertical polarity discrimination circuit for CS (composite sync) input. Input signal H (negative logic). PHC (Pin 5) — 0.4 — V PHC voltage 2 VPH2 The voltage integral of the vertical polarity discrimination circuit for CS (composite sync) input. Input signal I (positive logic). PHC (Pin 5) — 3.4 — V EVC voltage 1 VEV1 Measures the voltage of the vertical ramp waveform generator for VS (vertical separate sync) input. Input signal A. EVC (Pin 3) — 7.9 — V EVC voltage 2 VEV2 Measures the voltage of the vertical ramp waveform generator for VS (vertical separate sync) input. No input signal. EVC (Pin 3) — 4.3 — V EHC voltage 1 VEH1 Measurers the sync existence discrimination voltage for CS (composite sync) input. Input signal J. EHC (Pin 6) — 4.8 — V EHC voltage 2 VEH2 Measures the sync existence discrimination voltage for CS (composite sync) input. No input signal. EHC (Pin 6) — 3.0 — V td1 Measures the delay difference between CS and HD for CS (composite sync) Input. The time from the CS (negative polarity) fall time (50%) to the HD output rise time (50%). Input signal B. ( HD Pin 18 Pin 20 ( 120 190 250 ns td2 Measures the delay difference between CS and HD for CS (composite sync) input. The time from the CS (positive polarity) rise time (50%) to the HD output rise time (50%). Input signal D. ( HD Pin 18 Pin 20 ( 120 205 260 ns Item HD delay 1 HD delay 2 Symbol Measurement description –8– Max. Unit CXA1616N/S (Ta = 25°C, VCC = 12V, See the Electrical Characteristics Test Circuit) No. 21 22 23 24 Item HD delay 3 HD delay difference Clamp pulse delay 1 Clamp pulse delay 2 Measurement description Measurement point Min. Typ. Max. Unit td3 Measures the delay difference between the input signal sync and HD for VIDEO IN (sync-on video) input. The time from the input sync fall time (50%) to the HD output rise time (50%). Input signal C. ( HD Pin 18 Pin 20 ( 110 180 240 ns thd Compares the delay differences from both the VIDEO IN (sync-on video) input and the CS (composite sync) input to the HD output. (Compares Measurement No. 19 to 21). ( HD Pin 18 Pin 20 ( — 25 40 ns tcd1 Measures the delay difference between HD and the clamp pulse for CS (composite sync) input. The time from the HD output fall time (50%) to the clamp pulse output rise time (50%). Input signal B. CLAMP (Pin 10) 110 140 180 ns tcd2 Measures the delay difference between HD and the clamp pulse for CS (composite sync) input. The time from the HD output fall time (50%) to the clamp pulse output rise time (50%). Input signal D. CLAMP (Pin 10) 110 140 180 ns tcd3 Measures the delay difference between HD and the clamp pulse for VIDEO IN (sync-on video) input. The time from the HD output fall time (50%) to the clamp pulse output rise time (50%). Input signal C. CLAMP (Pin 10) 90 130 170 ns QH Polarity and existence information output of the sync signal. Measures the High level voltage under no load condition. Symbol 25 Clamp pulse delay 3 26 Logic output voltage High 27 Logic output voltage Low QL Polarity and existence information output of the sync signal. Measures the Low level voltage under no load condition. 28 Current consumption ICC Vcc = 12V, measures the current consumption for no input signal. –9– ( Q1 to Q4 Pin13 to17 Pin15 to19 ( 3.5 4.5 5.0 V ( Q1 to Q4 Pin13 to17 Pin15 to19 ( 0 0.12 0.4 V 18 27 35 mA ( VCC Pin 22 Pin 24 ( CXA1616N/S Signal Source Types Signal A Item V. SYNC IN (Pin 1) 1, 2, 15 tWV fV = 40Hz tWV = 12.5µs Negative logic 1Vp-p fV = 40Hz V B VIDEO IN (Pin 7) Composite SYNC IN (Pin 4) tWV = 12.5µs tWV 3, 6, 8, 9, 19, 23 H tWH Negative logic 1Vp-p fH = 130kHz tWH = 0.65µs Negative logic 1Vp-p V 0.7V 10H 12.5µs C 0.2V 3H fV = 40Hz tWV = 12.5µs 4, 7, 10, 21, 25 H 5.8µs 0.7V 1.5µs 0.2V 0.65µs fH = 130kHz tWH = 0.65µs fH = 130kHz D tWH = 0.65µs 5, 20, 24 Positive logic 1Vp-p F 11 fV = 200Hz tWV = 0.3ms Negative logic 5Vp-p fV = 200Hz tWV = 0.3ms Positive logic 5Vp-p G 12 H 13 fH = 130kHz tWV = 0.65µs Negative logic 5Vp-p I 14 fH = 130kHz tWV = 0.65µs Positive logic 5Vp-p J 17 fH = 15kHz tWV = 3.3µs Negative logic 1Vp-p – 10 – CXA1616N/S Electrical Characteristics Test Circuit (SSOP) VIDEO IN 75 CS IN 75 VS IN 75 C1 C2 470p 220µ 75 1 VS IN R18 75 VCC 24 VCC 12V R1 2.2k PVC VD 23 2 PVC C3 EVC 0.22µ VD 3 R3 75 75 V IN 22 EVC C4 0.22µ 4 CS IN C7 0.1µ R7 75 R5 33k C8 0.22µ C5 3300p R2 3.9k IN OUT V OUT 21 C6 4.7µ HD 5 PHC HD 20 R4 2.2k EHC 6 EHC PV 19 PV 7 VIDEO IN PH 18 PH R11 10k 8 HD SEL EV 17 EV C10 3.3µ TIMING R13 12k 9 TIMING EH 16 EH 75 R10 4.7k R6 C9 270 0.47µ 1SS119 S1 C11 560p CLAMP 10 CLAMP IN/EXT IN/EXT 15 R15 2.2k R16 68k 11 GND REF V REF 14 R17 39k NC 13 12 NC 5V Output power supply – 11 – CXA1616N/S Electrical Characteristics Test Circuit (SDIP) VIDEO IN 75 CS IN 75 VS IN 75 C1 C2 470p 220µ 75 1 VS IN R18 75 VCC 22 VCC 12V R1 2.2k PVC 2 PVC VD 21 C3 EVC 0.22µ VD 3 R3 75 75 V IN 20 EVC C4 0.22µ R7 75 R5 33k C8 0.22µ IN OUT V OUT 19 4 CS IN C7 0.1µ C5 3300p R2 3.9k C6 4.7µ HD HD 18 5 PHC R4 2.2k EHC 6 EHC PV 17 PV 7 VIDEO IN PH 16 PH R11 10k 8 HD SEL EV 15 EV C10 3.3µ TIMING R13 12k 9 TIMING EH 14 EH 75 R10 4.7k R6 C9 270 0.47µ 1SS119 S1 C11 560p CLAMP 10 CLAMP IN/EXT IN/EXT 13 R15 2.2k R16 68k 11 GND REF V REF 12 R17 39k 5V Output power supply – 12 – CXA1616N/S Description of Operation Input Signals • VS IN (Pin 1) fv: 40 to 200Hz Vs: 1 to 5Vp-p (positive/negative polarity) 1.5 to 5Vp-p (positive/negative polarity, for capacitor input) • CS IN (Pin 4) fH: 15k to 130kHz Vs: 1 to 5Vp-p (positive/negative polarity) • Video IN (Pin 7) fH: 15k to 130kHz fv: 40 to 200Hz V: 0 to 2.1Vp-p Vs: 0.2 to 0.6Vp-p Waveform of VS IN, CS IN Vs and Cs Waveform of Video IN V Vs Clamp Pulse Output • The clamp pulse (Pin 10) is output under the conditions described in 1 and 2 below. When output with Pin 10 operating as an open collector, its polarity is positive. td: 130 to 140ns delay to HD output tw: Clamp pulse width is variable from 200ns to 3µs depending on the capacitor value connected to Pin 9. HD Clamp pulse tw td <Conditions> 1) Clamp pulse is not output during the VD interval for CS IN or Video IN. Sync Clamp pulse VD interval 2) Clamp pulse is output during the VD intenal for HS and VS separate sync. l/O Delay Time Difference Video IN (Pin 7) sync waveform CS IN (Pin 4) separate sync waveform HD (Pin 18) waveform HD (Pin 18) waveform td1 td1: Delay time between Video IN (Pin 7) input and HD (Pin 18) output td2: Delay time between CS IN (Pin 4) input and HD (Pin 18) output td1, td2 = 200 to 260ns | td1 – td2 | = to 30ns to – 13 – td2 CXA1616N/S HD Selection Function HD SEL Low: The VD interval HD is not output. High: The VD interval HD is output as is. HD VD interval HD VD interval Mode Matrix of Sync Polarity Discrimination Signal CS IN (Pin 4) VS IN (Pin 1) EH out (Pin 14) EV out (Pin 15) PH out (Pin 16) PV out (Pin 17) Sync IN/EXT (Pin 13) HD, COMP (positive polarity) No signal VD (positive) VD (negative) H H H L H H L L L L L H H H H HD, COMP (negative polarity) No signal VD (positive) VD (negative) H H H L H H H H H L L H H H H No signal No signal VD (positive) VD (negative) L L L L H H L L L L L H L H H Low level: 0 to 0.2V, High level: 4.5 to 4.7V I/O Matrix VS IN CS IN VIDEO IN VD OUT HD OUT O O ∗ VS CS — O ∗ CS CS — — O VIDEO VIDEO — — — (VIDEO) (VIDEO) O: signal input —: no signal ∗ : unrelated to input signal – 14 – VV = 0 to 2.1Vp-p Vs = 0.2 to 0.6Vp-p VIDEO IN EHC PHC CS IN 7 6 5 4 Sync Sep PH Polarity Check 19 18 17 16 15 PV PV PH to 470k EV fH = 15k to 130kHz Vs = 1.0 to 5.0Vp-p V. Ramp Generator PVC Polarity Check EVC EH 1 IN/EXT VS IN EV 22 14 EH Exist Check Exist Check 21 V OUT 3 V IN 2 V REF fV = 40 to 200Hz Vs = 1.0 to 5.0Vp-p 1.5 to 5.0Vp-p (For capacitor input) Logic 24 Bias 9 10 23 8 20 12V TYP Clamp Pulse Generator 11 GND – 15 – VCC Operation and Waveforms (SSOP) 560p to 10000p TIMING CLAMP VD HD SEL HD 12kΩ tw = 200ns to 3µs CXA1616N/S VV = 0 to 2.1Vp-p Vs = 0.2 to 0.6Vp-p VIDEO IN EHC PHC CS IN 7 6 5 4 Sync Sep PH Polarity Check 17 16 15 14 13 PV PV EV to 470k PH fH = 15k to 130kHz Vs = 1.0 to 5.0Vp-p V. Ramp Generator PVC Polarity Check EVC EH 1 IN/EXT VS IN EV 20 12 EH Exist Check Exist Check 19 V OUT 3 V IN 2 V REF fV = 40 to 200Hz Vs = 1.0 to 5.0Vp-p 1.5 to 5.0Vp-p (For capacitor input) Logic 22 Bias 9 10 21 8 18 12V TYP Clamp Pulse Generator 11 GND – 16 – VCC Operation and Waveforms (SDIP) 560p to 10000p TIMING CLAMP VD HD SEL HD 12kΩ tw = 200ns to 3µs CXA1616N/S CXA1616N/S 4.0 VCC = 12V Ta = 25°C Pulse width [µs] 3.0 2.0 1.0 0 2000 4000 6000 8000 Pin 9 external capacitance [pF] 10000 Fig. 1. Clamp pulse output pulse width characteristics 13 For 12.5µs input width from composite sync or sync-on video. VCC = 12V, Ta = 25°C Pulse width [µs] 12 11 10 9 8 7 4.3 4.4 4.5 Pin12 reference voltagte [V] (Pin14) 4.6 Fig. 2. VD output pulse width characteristics – 17 – CXA1616N/S Application Circuit (SSOP) VIDEO IN 75 CS IN 75 VS IN 75 C1 C2 470p 220µ 75 1 VS IN R18 75 VCC 24 VD 23 2 PVC C3 0.22µ VD 3 R3 75 75 R7 75 75 R5 33k C8 0.22µ C5 3300p V IN 22 EVC C4 0.22µ R2 3.9k 4 CS IN C7 0.1µ VCC 12V R1 2.2k V OUT 21 C6 4.7µ HD 5 PHC HD 20 R4 2.2k 6 EHC PV 19 PV 7 VIDEO IN PH 18 PH 8 HD SEL EV 17 EV 9 TIMING EH 16 EH R6 C9 270 0.47µ HD SEL R13 12k C11 560p CLAMP 10 CLAMP IN/EXT IN/EXT 15 R15 2.2k R16 68k 11 GND V REF 14 R17 39k 12 NC NC 13 5V Note)Connect a resistance of 470k Ω or less between Pin 1 and GND when inputting to VS IN (Pin 1) through a capacitor. Consider sags in determining the constant setting. Make input signal amplitude 1.5 to 5.0Vp-p for capacitor input. C12 VS IN 1 VS IN R18 to 470k Application circuit with VS IN (Pin 1) capacitor input Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 18 – CXA1616N/S Application Circuit (SDIP) VIDEO IN 75 CS IN 75 VS IN 75 C1 C2 470p 220µ 75 1 VS IN R18 75 VCC 22 VCC 12V R1 2.2k PVC 2 PVC VD 21 C3 EVC 0.22µ VD 3 R3 75 75 V IN 20 EVC C4 0.22µ R7 75 R5 33k C8 0.22µ IN OUT V OUT 19 4 CS IN C7 0.1µ C5 3300p R2 3.9k C6 4.7µ HD HD 18 5 PHC R4 2.2k EHC 6 EHC PV 17 PV 7 VIDEO IN PH 16 PH R11 10k 8 HD SEL EV 15 EV C10 3.3µ TIMING R13 12k 9 TIMING EH 14 EH 75 R10 4.7k R6 C9 270 0.47µ 1SS119 S1 C11 560p CLAMP 10 CLAMP IN/EXT IN/EXT 13 R15 2.2k R16 68k 11 GND REF V REF 12 R17 39k 5V Output power supply Note)Connect a resistance of 470k Ω or less between Pin 1 and GND when inputting to VS IN (Pin 1) through a capacitor. Consider sags in determining the constant setting. Make input signal amplitude 1.5 to 5.0Vp-p for capacitor input. C12 VS IN 1 VS IN R18 to 470k Application circuit with VS IN (Pin 1) capacitor input Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 19 – CXA1616N/S Package Outline Unit: mm CXA1616N 24PIN SSOP(PLASTIC) + 0.2 1.25 – 0.1 ∗7.8 ± 0.1 0.1 24 13 ∗5.6 ± 0.1 7.6 ± 0.2 A 1 + 0.1 0.22 – 0.05 12 + 0.05 0.15 – 0.02 0.13 M 0.65 0.5 ± 0.2 0.1 ± 0.1 0° to 10° NOTE: Dimensions “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SSOP-24P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE SSOP024-P-0056 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.1g JEDEC CODE CXA1616S + 0.1 0.05 0.25 – 22PIN SDIP (PLASTIC) + 0.4 19.2 – 0.1 7.62 + 0.3 6.4 – 0.1 12 22 0° to 15° 11 1 0.5 ± 0.1 + 0.15 0.9 – 0.1 + 0.4 3.9 – 0.1 + 0.15 3.25 – 0.2 0.51 MIN 1.778 Two kinds of package surface: 1.All mat surface type. 2.All mirror surface type. PACKAGE STRUCTURE MOLDING COMPOUND EPOXY RESIN SONY CODE SDIP-22P-01 LEAD TREATMENT SOLDER PLATING EIAJ CODE SDIP022-P-0300 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 0.95g JEDEC CODE – 20 –