Freescale Semiconductor Advance Information Document Number: MC33907_08 Rev. 3.0, 2/2014 Power System Basis Chip with High Speed CAN transceiver 33907_08 The 33907_8 devices are multi-output, power supply, integrated circuit, including HSCAN transceiver, dedicated to the automotive market. Multiple switching and linear voltage regulators, including low power mode are available with various wake-up capabilities. An advanced power management scheme is implemented to maintain high efficiency over wide input voltages and output current ranges. The 33907_8 includes enhanced safety features, with multiple fail-safe outputs, becoming a full part of a safety oriented system partitioning, to reach a high integrity safety level. The built-in enhanced high speed CAN interface fulfills the ISO11898-2 and -5 standards. Local and bus failure diagnostics, protection, and failsafe operation mode are provided. This device is powered by SMARTMOS technology. Features • Highly flexible SMPS pre-regulator, allowing two topologies: noninverting buck-boost or standard buck • Switching mode power supply (SMPS) dedicated to MCU core supply, 1.2 V or 3.3 V delivering up to 1.5 A • Linear voltage regulator dedicated to MCU A/D reference voltage or I/ Os supply (VCCA). 5.0 V or 3.3 V • Linear voltage regulator dedicated to auxiliary functions, or to a sensor supply (VCCA tracker or independent 5.0 V / 3.3 V) • Multiple wake-up sources in low power mode: CAN and/or IOs • Battery voltage sensing & MUX output terminal • Enhanced safety block associated with fail-safe outputs • Six configurable I/Os POWER SYSTEM BASIS CHIP AE SUFFIX (PB-FREE) 98ASA00173D 48-PIN LQFP-EP Applications • Electrical power steering • Engine management • Battery management • Active suspension • Gear box • Transmission • Electrical Vehicle (EV), Hybrid Electrical Vehicle (HEV) • Advanced driver assistance systems +Battery (KL30) VDD 33907_08 BOOTS_CORE SW_CORE VPRE GATE_LS SW_PRE2 BOOTS_PRE SW_PRE1 VSUP2 VSUP1 VSUP3 VSENSE COMP_CORE VCCA_E VCCA_B VCCA VAUX_E VDDIO VAUX_B Vaux Vcca AD ref. voltage Vcore or Vcca MOSI MISO SCLK NCS MUX_OUT VAUX SELECT CAN-5V Ignition Key (KL15) MCU VCORE_SNS FB_CORE INTB IO_0 SPI ADC Input NMI VDDIO IO_1 RSTB IO_2 Reset VDDIO IO_3 IO_4 FS0B Vpre IO_5 CANH CAN BUS DEBUG CANL GNDA GND_COM DGND VDD TXD DEBUG mode RXD CAN Figure 1. Simplified Application Diagram - Buck Boost Configuration * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2013 - 2014. All rights reserved. FCCU +Battery (KL30) VDD 33907_08 BOOTS_CORE SW_CORE VPRE GATE_LS BOOTS_PRE SW_PRE2 SW_PRE1 VSUP2 VSUP1 VSUP3 MCU VCORE_SNS FB_CORE Vpre COMP_CORE VCCA_E VSENSE VCCA_B Vpre VCCA VAUX_E VDDIO Vcca AD ref. voltage Vcore or Vcca VAUX_B MOSI MISO SCLK NCS MUX_OUT VAUX SELECT CAN-5V Ignition Key (KL15) INTB IO_0 IO_1 SPI ADC Input NMI VDDIO Reset RSTB IO_2 VDDIO IO_3 FS0B IO_4 Vpre IO_5 CANH DEBUG CAN BUS CANL VDD GNDA GND_COM DGND TXD DEBUG mode RXD CAN FCCU Figure 2. Simplified Application Diagram - Buck Configuration, VAUX not used, VCCA = 100 mA 33907_8 2 Analog Integrated Circuit Device Data Freescale Semiconductor 1 Orderable Parts Table 1. Orderable Part Variations Part Number (1) MC33907AE MC33908AE VCORE Temperature (TA) VCORE Output Current Capability in Normal Mode Page 12 -40 to 125 °C Package 48-pin LQFP exposed pad Notes 1. To order parts in Tape & Reel, add the R2 suffix to the part number. 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 3 2 Internal Block Diagram COMP_CORE BOOTS_CORE VCORE_SNS FB_CORE SW_CORE DGND VPRE GATE_LS BOOTS_PRE SW_PRE2 SW_PRE1 VSUP2 VSUP1 Vpre VSUP3 TSD TSD Vpre SMPS Vcore SMPS TSD VAUX_E VAUX_B VAUX Vpre Vpre TSD Vaux Linear Regulator Vpre Vsense Vpre Vpre Vsup3 Vcan TSD Internal Linear Regulator CAN-5V VCCA_E VCCA_B VCCA Vcca Linear Regulator Analog Reference #1 Charge Pump Vref (2.5V) GNDA MUX Interface IO_0 SELECT Die Temp MUX_OUT IO_1 Select IO_0 IO_1 IO_2 6 I/Os Interface IO_3 V2p5 Logic Main OSC Main Power Management State Machine IO_4 IO_5 CAN-5V Vpre Vaux Voltage Regulator SUPERVISOR (Over & under voltage) Vsup1&2 CAN diag Vsense Debug INTB MOSI MISO SCLK NCS SPI Main VDDIO Vcca FB_core DEBUG MISO FS V2p5Logic FS 5 Analog Reference #2 FS Vpre SPI FS FAIL SAFE Machine VDDIO RSTB FS0B OSC FS Vsup3 Vsense CAN-5V CANH VDDIO Debug Select HSCAN Interface CANL VSENSE RXD TXD GND_COM Fail Safe Logic & supply Figure 3. MC33907_08 Simplified Internal Block Diagram 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 4 Table of Contents 1 Orderable Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 3 2 Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 4 3 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 6 3.1 Pinout Diagram for 33907_8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 6 3.2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 6 4 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 9 4.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 9 4.2 Static Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 11 4.3 Dynamic Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 20 5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 25 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 25 5.2 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 25 6 Functional Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 30 6.1 Mode and State Description of MAIN State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 30 6.2 Mode and State Description of Fail-safe State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 31 6.3 Functional State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 33 6.4 Fail-safe Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 34 6.5 Fail-safe Machine State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 34 6.6 Watchdog Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 35 6.7 Wrong Watchdog Refresh Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 37 6.8 Startup Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 48 7 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 50 7.1 High Level Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 50 7.2 Detail Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 51 7.3 Detail of Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 55 8 List of Interruptions and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 98 9 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 100 10 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 102 10.1 Package Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 102 11 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 106 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 5 VPRE VAUX VAUX_B VAUX_E VCCA_E VCCA_B VCCA GATE_LS DGND Pinout Diagram for 33907_8 BOOT_PRE 3.1 SW_PRE2 Pin connections SW_PRE1 3 Transparent top view VSUP1 BOOT_CORE VSUP2 SW_CORE VSENSE VCORE_SNS VSUP3 COMP_CORE NC FB_CORE GND_COM SELECT CAN_5V VDDIO NC RSTB NC RXD TXD IO_3 IO_2 MISO MUX_OUT MOSI IO_0 AGND SCLK IO_5 DEBUG NCS IO_4 IO_1 INTB CANL FS0B CANH Figure 4. 33907_8 Pinout 3.2 Pin Definitions A functional description of each pin can be found in the functional pin description section beginning on page 25. Table 2. 33907_8 Pin Definition Pin Pin Name Type Definition 1 VSUP1 A_IN Power supply of the device. An external reverse battery protection diode in series is mandatory 2 VSUP2 A_IN Second power supply. Also protected by the external reverse battery protection diode used for VSUP1 3 VSENSE A_IN Sensing of the battery voltage. Must be connected prior to the reverse battery protection diode. 4 VSUP3 A_IN Third power supply dedicated to the device supply. Also protected by the external reverse battery protection diode used for VSUP1. Shall be connected between the reverse protection diode and the input PI filter. 5, 22, 23 NC N/A Not connected. Pins must be left open. 33907_8 6 Analog Integrated Circuit Device Data Freescale Semiconductor Table 2. 33907_8 Pin Definition Pin Pin Name Type Definition 6 GND_COM GROUND 7 CAN_5V A_OUT 8 CANH A_IN/OUT HSCAN output High 9 CANL A_IN/OUT HSCAN output Low 10 11 IO_4:5 D_IN A_OUT Can be used as digital input (load dump proof) with wake-up capability or as an output gate driver Digital input: Pin status can be read through the SPI. Can be used to monitor error signals from another IC for safety purposes. Wake-up capability: Can be selectable to wake-up on a rising or falling edge, or on a transition Output gate driver: Can drive a logic level low side NMOS transistor. Controlled by the SPI. 12 13 IO_0:1 A_IN D_IN Can be used as analog or digital input (load dump proof) with wake-up capability (selectable) Analog input: Pin status can be read through the MUX output terminal Digital input: Pin status can be read through the SPI. Can be used to monitor error signals from another IC for safety purposes Wake-up capability: Can be selectable to wake-up on a rising or falling edge, or on a transition 14 FS0B D_OUT 15 DEBUG D_IN 16 AGND GROUND 17 MUX_OUT A_OUT 18 19 IO_2:3 D_IN Digital input pin with wake-up capability (logic level compatible) Digital INPUT: Pin status can be read through the SPI. Can be used to monitor error signals from MCU for safety purposes. Wake-up capability: Can be selectable to wake-up on a rising or falling edge, or on a transition. 20 TXD D_IN Transceiver input from the MCU which controls the state of the HSCAN bus 21 RXD D_OUT Receiver output which reports the state of the HSCAN bus to the MCU 24 RSTB D_OUT This output is asserted low when the safety block reports a failure. The main function is to reset the MCU. Reset input voltage is also monitored in order to detect external reset and fault condition. Open drain structure. 25 MISO D_OUT SPI bus. Master Input Slave Output 26 MOSI D_IN SPI bus. Master Output Slave Input 27 SCLK D_IN SPI Bus. Serial clock 28 NCS D_IN No Chip Select (Active low) 29 INTB D_OUT 30 VDDIO A_IN Input voltage for MISO output buffer. Allows voltage compatibility with MCU I/Os. 31 SELECT D_IN Hardware selection pin for VAUX and VCCA output voltages 32 FB_CORE A_IN VCORE voltage feedback. Input of the error amplifier. 33 COMP_CORE A_IN Compensation network. Output of the error amplifier. 34 VCORE_SNS A_IN Vcore output voltage sense 35 SW_CORE A_IN VCORE switching point 36 BOOT_CORE A_IN/OUT Dedicated ground for CAN Output voltage for the embedded CAN interface Output of the safety block (active low). The pin is asserted low at startup and when a fault condition is detected. Open drain structure. Debug mode entry input Analog ground connection Multiplexed output to be connected to a MCU ADC. Selection of the analog parameter is available at MUX-OUT through the SPI. This output pin generates a low pulse when an Interrupt condition occurs. Pulse duration is configurable Bootstrap capacitor for VCORE internal NMOS gate drive 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 7 Table 2. 33907_8 Pin Definition Pin Pin Name Type Definition 37 VPRE A_OUT VPRE output voltage 38 VAUX A_OUT VAUX output voltage. External PNP ballast transistor. Collector connection 39 VAUX_B A_OUT VAUX voltage regulator. External PNP ballast transistor. Base connection 40 VAUX_E A_OUT VAUX voltage regulator. External PNP ballast transistor. Emitter connection 41 VCCA_E A_OUT VCCA voltage regulator. External PNP ballast transistor. Emitter connection 42 VCCA_B A_OUT VCCA voltage regulator. External PNP ballast transistor. Base connection 43 VCCA A_OUT VCCA output voltage. External PNP ballast transistor. Collector connection 44 GATE_LS A_OUT Low side MOSFET gate drive for “Non-inverting Buck-boost” configuration 45 DGND GROUND Digital ground connection 46 BOOT_PRE A_IN/OUT Bootstrap capacitor for the VPRE internal NMOS gate drive 47 SW_PRE2 A_IN Second pre-regulator switching point 48 SW_PRE1 A_IN Pre-regulator switching point 33907_8 8 Analog Integrated Circuit Device Data Freescale Semiconductor 4 General Product Characteristics 4.1 Maximum Ratings Table 3. Maximum Ratings All voltages are with respect to ground, unless otherwise specified. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit DC Voltage at Power Supply Pins VSUP1/2/3 -1.0 to 40 V DC voltage between VSUP1, 2, and VSUP3 (VSUP1,2 > VSUP3) VSUP1/2/3 0.0 to 4.0 V DC Voltage at Battery Sense Pin VSENSE -14 to 40 V DC Voltage at SW_PRE1 and SW_PRE2 Pins VSW1, 2 -1.0 to 40 V VPRE -0.3 to 8 V VGATE_LS -0.3 to 8 V DC Voltage at BOOT_PRE pin VBOOT_PRE -1.0 to 50 V DC Voltage at SW_CORE pin VSW_CORE -1.0 to 8.0 V DC Voltage at VCORE_SNS pin VCORE_SNS 0.0 to 8.0 V DC Voltage at BOOT_CORE pin VBOOT_CORE 0.0 to 15 V VFB_CORE -0.3 to 2.5 V VCOMP_CORE -0.3 to 2.5 V VAUX_E,B -0.3 to 40 V VAUX -2.0 to 40 V VCCA_B,E -0.3 to 8.0 V DC Voltage at VCCA pin VCCA -0.3 to 8.0 V DC Voltage at VDDIO VDDIO -0.3 to 8.0 V DC Voltage at FS0B (with ext R mandatory) VFS0 -0.3 to 40 V VDEBUG -0.3 to 40 V VIO_0,1,4,5 -0.3 to 40 V VDIG -0.3 to VDDIO+0.3 V VSELECT -0.3 to 8.0 V VBUS_CAN -27 to 40 V VCAN_5V -0.3 to 8.0 V I_IO -5.0 to 5.0 mA Notes ELECTRICAL RATINGS DC Voltage at VPRE Pin DC Voltage at Gate_LS pin DC Voltage at FB_CORE pin DC Voltage at COMP_CORE pin DC Voltage at VAUX_E, VAUX_B pin DC Voltage at VAUX pin DC Voltage at VCCA_B, VCCA_E pin DC Voltage at DEBUG DC Voltage at IO_0:1; 4:5 (with ext R = 5.1 k in series mandatory) DC Voltage at INTB, RSTB, MISO, MOSI, NCS, SCLK, MUX_OUT, RXD, TXD, IO_2, IO_3 DC Voltage at SELECT DC Voltage on CANL, CANH DC voltage on CAN_5 V IOs maximum current capability 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 9 Table 3. Maximum Ratings (continued) All voltages are with respect to ground, unless otherwise specified. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit VESD-HBM1 VESD-HBM2 VESD-HBM3 VESD-HBM4 ±2.0 ±3.5 ±4.0 ±6.0 kV kV kV kV VESD-CDM1 VESD-CDM2 ±500 ±750 V V VESD-GUN1 VESD-GUN2 VESD-GUN3 VESD-GUN4 ±8.0 ±8.0 ±8.0 ±8.0 kV kV kV kV VESD-GUN5 VESD-GUN6 VESD-GUN7 VESD-GUN8 ±15 ±12 ±15 ±15 kV kV kV kV Ambient Temperature TA -40 to 125 °C Junction Temperature TJ -40 to 150 °C Storage Temperature TSTG -55 to 150 °C RJA 32 °C/W (2) RJCTOP 23 °C/W (3) RJCBOTTOM 1.3 °C/W (4) ESD Voltage Human Body Model (JESD22/A114) - 100 pF, 1.5 k • All pins • VSUP1, VSUP2, VSUP3, VSENSE, IO_0:1, IO_4:5, FS0B , DEBUG • VAUX versus AGND • CANH, CANL Charge Device Model (JESD22/C101): • All Pins • Corner Pins System level ESD (Gun Test) • VSUP1, VSUP2, VSUP3, VSENSE, VAUX, IO_0:1, IO_4:5, FS0B 330 Ω / 150 pF Unpowered According to IEC61000-4-2: 330 Ω / 150 pF Unpowered According to OEM LIN, CAN, FLexray Conformance 2.0 kΩ / 150 pF Unpowered According to ISO10605.2008 2.0 kΩ / 330 pF Powered According to ISO10605.2008 • CANH, CANL 330 Ω / 150 pF Unpowered According to IEC61000-4-2: 330 Ω / 150 pF Unpowered According to OEM LIN, CAN, FLexray Conformance 2.0 kΩ / 150 pF Unpowered According to ISO10605.2008 2.0 kΩ / 330 pF Powered According to ISO10605.2008 Notes THERMAL RATINGS THERMAL RESISTANCE Thermal resistance junction to ambient Thermal resistance junction to Case Top Thermal resistance junction to Case Bottom Notes 2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. 3. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC - 883 Method 1012.1). 4. Thermal resistance between the die and the solder par on the bottom of the packaged based on simulation without any interface resistance. 33907_8 10 Analog Integrated Circuit Device Data Freescale Semiconductor 4.2 Static Electrical Characteristics Table 4. Operating Range TCASE = -40 to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 22). Symbol Parameter Min Typ Max Unit 2.0 – 13.0 mA Notes POWER SUPPLY ISUP Power Supply Current in Normal Mode (Vsup > Vsup_uv_7) ISUP_LPOFF1 Power Supply Current in LPOFF (14 V, @ TA = 25 °C) – 32 – µA ISUP_LPOFF2 Power Supply Current in LPOFF (18 V, @ TA = 80 °C) – 42 60 µA Power Supply Undervoltage Warning – 8.5 – V Power Supply Undervoltage Hysteresis 0.1 – – V VSUP_UV_7 Power Supply Undervoltage Lockout (power-up) 7.0 – 8.2 V VSUP_UV_5 Power Supply Undervoltage Lockout (power-up) – – 5.6 V VSUP_UV_L Power Supply Undervoltage Lockout (falling - Boost config.) – – 2.7 V VSUP_UV_L_B Power Supply Undervoltage Lockout (falling - Buck config.) – – 4.6 V Power Supply Undervoltage Lockout Hysteresis – 0.1 – V 6.25 – 6.75 VPRE_UV_4P3 VSUP RDSON_PRE * IPRE – – VSNS_UV VSNS_UV_HYST VSUP_UV_HYST (5) VPRE VOLTAGE PRE-REGULATOR VPRE VPRE Output Voltage • Buck mode (VSUP > Vsup_uv_7) • Buck mode (VSUP_UV_7 VSUP 4.6 V) • Boost mode (VSUP 2.7 V) IPRE VPRE Maximum Output Current Capability • Buck or Boost with VSUP > VSUP_UV_7 • Buck with VSUP_UV_7 VSUP 4.6 V • Boost with VSUP_UV_7 VSUP 6.0 V • Boost with 6.0 V VSUP 4.0 V • Boost with 4.0 V VSUP 2.7 V IPRE_LPOFF VPRE Maximum Output Current Capability in LPOFF at low Vsup voltage • Buck with VSUP_UV_7 VSUP 4.6 V • Boost with VSUP_UV_7 VSUP 6.0 V • Boost with 6.0 V VSUP 4.0 V • Boost with 4.0 V VSUP 2.7 V V 6.0 2.0 0.5 2.0 1.0 0.3 – 2.0 – – – 7.0 A (5) A (5) – – – – – 0.050 2.0 1.0 0.3 – – – – – – – – IPRE_LIM VPRE Output Current Limitation with Vsup 28V 3.5 – – A IPRE_OC VPRE Overcurrent Detection Threshold (in buck mode only) with VSUP 28 V 5.0 – – A VPRE_UV VPRE Undervoltage Detection Threshold (Falling) 5.5 – 6.0 V VPRE Undervoltage Hysteresis 0.05 – 0.15 V VPRE Shut-off Threshold (Falling - buck mode) 4.2 – 4.5 V VPRE_UV_HYST VPRE_UV_4P3 (5) Notes 5. Guaranteed by design. 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 11 Table 4. Operating Range (continued) TCASE = -40 to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 22). Symbol Parameter Min Typ Max Unit Notes 0.05 – 0.15 V (6) VPRE Pass Transistor On Resistance with VSUP 28 V – – 200 m VPRE Line Regulation – 20 – mV (6) VPRE Load Regulation for COUT = 57 µF IPRE from 50 mA to 2.0 A - Buck mode – 100 – mV (6) LORVPRE_BOOST VPRE Load Regulation for COUT = 57 µF IPRE from 50 mA to 2.0 A - Boost mode – 500 – mV (6) VPRE VOLTAGE PRE-REGULATOR (CONTINUED) VPRE_UV_4P3_HY VPRE Shut-off Hysteresis ST RDSON_PRE LIR_VPRE LORVPRE_BUCK VPRE_LL_H VPRE_LL_L VPRE Pulse Skipping Thresholds – – 200 180 – – mV TWARN_PRE VPRE Thermal Warning Threshold – 125 – °C TSD_PRE VPRE Thermal Shutdown Threshold 160 – – °C TSD_PRE_HYST VPRE Thermal Shutdown Hysteresis – 10 – °C IPFF Input Voltage detection 18 – 24 V 0.2 – – V 1.7 – – A VPRE-1 – VPRE V – – 0.5 V 0.784 0.8 0.816 V – – – – 0.8 1.5 1.0 1.8 – – 2.0 3.5 – – 200 m VSUP_IPFF VSUP_IPFF_HYST IPFF Input Voltage hysteresis IPRE_IPFF_PK IPFF High Side Peak current detection with VSUP 28 V VG_LS_OH LS Gate driver High output voltage (IOUT = 50 mA) VG_LS_OL LS Gate driver Low Level (IOUT = 50 mA) (6) VCORE VOLTAGE REGULATOR VCORE_FB ICORE VCORE Feedback Input Voltage VCORE Output Current Capability in Normal Mode • MC33907 • MC33908 ICORE_LIM_10 ICORE_LIM_20 VCORE Output Current Limitation • MC33907 • MC33908 RDSON_CORE VCORE Pass Transistor On Resistance A A LORVCORE_1.2 VCORE Transient Load regulation - 1.2 V range -60 – 60 mV (6), (7) LORVCORE_3.3 VCORE Transient Load regulation - 3.3 V range -100 – 100 mV (6), (7) – 125 – °C 160 – – °C – 10 – °C TWARN_CORE TSD_CORE VCORE Thermal Warning Threshold VCORE Thermal Shutdown Threshold TSD_CORE_HYST VCORE Thermal Shutdown Hysteresis (6) Notes 6. 7. Guaranteed by design. COUT = 40 µF, ICORE = 10 mA to 1.5 A, dICORE/dt 2.0 A/µs 33907_8 12 Analog Integrated Circuit Device Data Freescale Semiconductor Table 4. Operating Range (continued) TCASE = -40 to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 22). Symbol Parameter Min Typ Max 4.95 4.9 4.85 3.2505 3.234 3.201 5.0 5.0 5.0 3.3 3.3 3.3 5.05 5.1 5.15 3.3495 3.366 3.399 Unit Notes VCCA VOLTAGE REGULATOR VCCA VCCA Output Voltage • 5.0 V config. with Internal ballast at 100 mA • 5.0 V config with external ballast at 200 mA • 5.0 V config with external ballast at 300 mA • 3.3 V config with Internal ballast at 100 mA • 3.3 V config with external ballast at 200 mA • 3.3 V config with external ballast at 300 mA V (8) (8) ICCA_IN VCCA Output Current (int. MOSFET) – – 100 mA ICCA_OUT VCCA Output Current (external PNP) – – 300 mA ICCA_LIM_INT VCCA Output Current Limitation (int. MOSFET) 100 – 675 mA ICCA_LIM_OUT VCCA Output Current Limitation (external PNP) 300 – 675 mA ICCA_LIM_FB VCCA Output Current Limitation Foldback 80 – 200 mA VCCA_LIM_FB VCCA Output Voltage Foldback Threshold 0.5 – 1.1 V VCCA_LIM_HYST VCCA Output Voltage Foldback Hysteresis 0.07 – 0.3 V ICCA_BASE_SC VCCA Base Current Capability (internal pull-up) – 20 30 mA ICCA_BASE_SK VCCA Base Current Capability (Current sink) 20 65 – mA VCCA Thermal Warning Threshold (int. ballast only) – 125 – °C 160 – – °C VCCA Thermal Shutdown Hysteresis – 10 – °C (9) VCCA Transient Load Regulation • ICCA = 10 mA to 100 mA (internal MOSFET) • ICCA = 10 mA to 300 mA (external ballast) – – 1.0 % (9) TWARN_CCA TSDCCA TSDCCA_HYST LORTVCCA VCCA Thermal Shutdown Threshold (int. ballast only) Notes 8. 9. External PNP gain within 150 to 450 Guaranteed by design. 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 13 Table 4. Operating Range (continued) TCASE = -40 to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 22). Symbol Parameter Min Typ Max Unit Notes VAUX VOLTAGE REGULATOR VAUX_5 VAUX Output Voltage (5.0 V configuration) 4.85 5.0 5.15 V VAUX_33 VAUX Output Voltage (3.3 V configuration) 3.2 3.3 3.4 V VAUX_TRK VAUX Tracking Error (VAUX_5 and VAUX_33) -15 – +15 mV IAUX_OUT VAUX Output Current – – 300 mA IAUX_LIM VAUX Output Current Limitation 300 – 700 mA IAUX_LIM_FB VAUX Output Current Limitation Foldback 100 – 530 mA VAUX_LIM_FB VAUX Output Voltage Foldback Threshold 0.5 – 1.1 V VAUX_LIM_HYST VAUX Output Voltage Foldback Hysteresis 0.05 – 0.3 V VAUX Base Current Capability – 7.0 – – -7.0 – mA TSDAUX VAUX Thermal Shutdown Threshold 160 – – °C TSDAUX_HYST VAUX Thermal Shutdown Hysteresis – 10 – °C (10) VAUX Static Load Regulation (IAUX_OUT = 10 to 300 mA) – 15 – mV (10) VAUX Transient Load Regulation • IAUX_OUT = 10 mA to 300 mA – – 1.0 % (10) 4.8 5.0 5.2 V – – 100 mA IAUX_BASE_SC IAUX_BASE_SK LORVAUX LORTVAUX 5V-CAN VOLTAGE REGULATOR VCAN VCAN Output Voltage VSUP > 6.0 V in Buck mode VSUP > VSUP_UV_L in Boost mode ICAN_OUT VCAN Output Current ICAN_LIM VCAN Output Current Limitation 100 – 250 mA TSDCAN VCAN Thermal Shutdown Threshold 160 – – °C TSDCAN_HYST VCAN Thermal Shutdown Hysteresis – 10 – °C VCAN Undervoltage Detection Threshold 4.25 – 4.8 V VCAN Undervoltage Hysteresis 0.07 – 0.22 V VCAN Overvoltage Detection Threshold 5.2 – 5.55 V VCAN Overvoltage Hysteresis 0.07 – 0.22 V – 100 – mV VCAN_UV VCAN_UV_HYST VCAN_OV VCAN_OV_HYST LORVCAN VCAN Load Regulation (from 0 to 50 mA) (10) (10) Notes 10. Guaranteed by design. 33907_8 14 Analog Integrated Circuit Device Data Freescale Semiconductor Table 4. Operating Range (continued) TCASE = -40 to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 22). Symbol Parameter Min Typ Max Unit 7.2 – 8.0 V – 0.1 – V Notes FAIL-SAFE MACHINE VOLTAGE SUPERVISOR VPRE_OV VPRE Overvoltage Detection Threshold VPRE_OV_HYST VPRE Overvoltage Hysteresis VCORE_FB_UV VCORE FB Undervoltage Detection Threshold 0.67 – 0.773 V VCORE_FB_UV_D VCORE FB Undervoltage Detection Threshold - Degraded mode 0.45 – 0.58 V 10 – 27 mV 0.84 – 0.905 V 10 – 30 mV VCORE Internal Pull-down Current 5.0 12 25 mA VCCA_UV_5 VCCA Undervoltage Detection Threshold (5.0 V config) 4.5 – 4.75 V VCCA_UV_5D VCCA Undervoltage Detection Threshold (Degraded 5.0 V) 3.0 – 3.2 V VCCA_UV_33 VCCA Undervoltage Detection Threshold (3.3 V config) 3.0 – 3.2 V – 0.07 – V VCORE_FB_UV_ VCORE FB Undervoltage Hysteresis (11) (11) HYST VCORE_FB_OV VCORE FB Overvoltage Detection Threshold VCORE_FB_OV_HY VCORE FB Overvoltage Hysteresis (11) ST IPD_CORE VCCA_UV_HYST VCCA Undervoltage Hysteresis VCCA_OV_5 VCCA Overvoltage Detection Threshold (5.0 V config) 5.25 – 5.5 V VCCA_OV_33 VCCA Overvoltage Detection Threshold (3.3 V config) 3.4 – 3.6 V VCCA Overvoltage Hysteresis – 0.15 – V VCCA Internal Pull-down Resistor (enabled when VCCA is switched off) 50 – 160 VAUX_UV_5 VAUX Undervoltage Detection Threshold (5.0 V config) 4.5 – 4.75 V VAUX_UV_5D VAUX Undervoltage Detection Threshold (Degraded 5.0 V) 3.0 – 3.2 V VAUX_UV_33 VAUX Undervoltage Detection Threshold (3.3 V config) 3.0 – 3.2 V – 0.07 – V VCCA_OV_HYST RPD_CCA VAUX_UV_HYST VAUX Undervoltage Hysteresis VAUX_OV_5 VAUX Overvoltage Detection Threshold (5.0 V config) 5.25 – 5.5 V VAUX_OV_33 VAUX Overvoltage Detection Threshold (3.3 V config) 3.4 – 3.6 V VAUX Overvoltage Hysteresis – 0.07 – V VAUX Internal Pull-down Resistor 50 – 170 VAUX_OV_HYST RPD_AUX (11) (11) (11) (11) Notes 11. Guaranteed by design. 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 15 Table 4. Operating Range (continued) TCASE = -40 to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 22). Symbol Parameter Min Typ Max Unit Notes (12) FAIL-SAFE OUTPUTS VRSTB_OL Reset Low Output Level (I_RSTB = 2.0 mA and 2.0 V < VSUP < 40 V) – – 0.5 V IRSTB_LIM Reset Output Current Limitation 12 – 25 mA VRSTB_IL External Reset Detection Threshold (falling) 1.0 – VRSTB_IH External Reset Detection Threshold (rising) – – 2.0 V 0.2 – – V VRSTB_IN_HYST External Reset Input Hysteresis V VFS0B_OL FS0B low Output Level (I_FS0b = 2.0 mA) – – 0.5 V IFS0B_LK FS0B Input Current Leakage (VFS0B = 28 V) – – 1.0 µA IFS0B_LIM FS0B Output Current Limitation 6.0 – 12 mA MULTI-PURPOSE IOS ANALOG INPUT VIO_ANA_WD Measurable Input Voltage (wide range) 3.0 – 19 V VIO_ANA_TG Measurable Input Voltage (tight range) 3.0 – 9.0 V – – 100 µA High Input Voltage Detection Threshold (IO_0:1, IO_4:5) • Min Limit = 2.7 V at VSUP = 40 V 2.6 – – V High Input Voltage Detection Threshold (IO_2, IO_3) 2.0 – – V Digital Low Input Level (IO_0:1; IO_4:5) – – 2.1 V VIO_HYST Input Voltage Hysteresis (IO_0:1, IO_4:5) 50 120 500 mV VIO23_IL Digital Low Input Level (IO_2, IO_3) – – 0.9 V Input Voltage Hysteresis (IO_2, IO_3) 200 450 700 mV IIO_IN_0:1 Input Current for IO_0:1 -5.0 – 100 µA IIO_IN_2:5 Input Current for IO_2:5 -5.0 – 5.0 µA Input Current for IO_0:5 in LPOFF -1.0 – 1.0 µA IIO_IN_ANA Input Current DIGITAL INPUT VIO_IH VIO23_IH VIO_IL VIO23_HYST IIO_IN_LPOFF (13) (13) OUTPUT GATE DRIVER VIO_OH High Output Level at IIO_OUT = -2.5 mA VPRE - 1.5 – VPRE V VIO_OL Low Output Level at IIO_OUT = +2.5 mA 0.0 – 1.0 V Output Current Capability 2.5 – – – – -2.5 mA VIO_OUT_SK VIO_OUT_SC Notes 12. For VSUP < 2.0 V, all supplies are already off and external pull-up on RSTB (e.g VCORE or VCCA) pulls the line down. 13. Guaranteed by design. 33907_8 16 Analog Integrated Circuit Device Data Freescale Semiconductor Table 4. Operating Range (continued) TCASE = -40 to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 22). Symbol Parameter Min Typ Max Unit Notes VAMUX_ACC Voltage Sense Accuracy (VSNS, IO_0, IO_1) using 5.1 kresistor -5.0 – 5.0 % (14) VAMUX_WD_5 Divider Ratio (wide input voltage range) at VDDIO = 5.0 V – 5.0 – VAMUX_WD_3P3 Divider Ratio (wide input voltage range) at VDDIO = 3.3 V – 7.0 – VAMUX_TG_5 Divider Ratio (tight input voltage range) at VDDIO = 5.0 V – 2.0 – VAMUX_TG_3P3 Divider Ratio (tight input voltage range) at VDDIO = 3.3 V – 3.0 – ANALOG MULTIPLEXER VAMUX_REF1 Internal Voltage Reference with 6.0 V < VSUP < 19 V 2.475 2.5 2.525 V VAMUX_REF2 Internal Voltage Reference with VSUP 6.0 V or VSUP 19 V 2.468 2.5 2.532 V – 9.9 – mV/°C 2.08 2.15 2.22 V VAMUX_TP_CO VAMUX_TP Internal Temperature Sensor Coefficient Temperature Sensor mux_output Voltage (at TJ = 165 °C) (15) INTERRUPT VINTB_OL Low output level (IINT = 2.5mA) – – 0.5 V RPU_INT Internal pull-up resistor (connected to VDDIO) – 10 – K IINT_LK Input leakage current – – 1 µA CAN TRANSCEIVER CAN LOGIC INPUT PIN (TXD) VTXD_IH TXD High Input Threshold 0.7 x VDDIO – – V VTXD_IL TXD Low Input Threshold – – 0.3 x VDDIO V TXDPULL-UP TXD Main Device Pull-up 20 33 50 K -1.0 – 1.0 µA TXDLK TXD Input Leakage Current, VTXD = VDDIO CAN LOGIC OUTPUT PIN (RXD) VRXD_OL1 Low Level Output Voltage (IRXD = 250 µA) – – 0.4 V VRXD_OL2 Low Level Output Voltage (IRXD = 1.5 mA) – – 0.9 V VOUTHIGH High Level Output Voltage (IRXD = -250 µA, VDDIO = 3.0 V to 5.5 V) VDDIO - 0.4V – – V Notes 14. If a higher resistor value than recommended is used, the accuracy degrades. 15. Guaranteed by design. 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 17 Table 4. Operating Range (continued) TCASE = -40 to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 22). Symbol Parameter Min Typ Max Unit -12 – 12 V Differential Input Voltage Threshold in Sleep Mode 0.5 – 0.9 V VIN_HYST Differential Input Hysteresis (in Tx, Rx mode) 50 – – mV RIN_CHCL CANH, CANL Input Resistance 5.0 – 50 k RIN_DIFF CAN Differential Input Resistance 10 – 100 k Input Resistance Matching -3.0 – 3.0 % VCANH CANH Output Voltage (45 < RBUS < 65 ) • TX dominant state • TX recessive state 2.75 2.0 – 2.5 4.5 3.0 VCANL CANL Output Voltage (45 < RBUS < 65 ) • TX dominant state • TX recessive state 0.5 2.0 – 2.5 2.25 3.0 VOH-VOL Differential Output Voltage • TX dominant state (45 < RBUS < 65 ) • TX recessive state 1.5 -50 2.0 0.0 3.0 50 V mV ICANL-SK CANL Sink Current Under Short-circuit Condition (VCANL 12 V, CANL driver ON, TXD low) 40 – 100 mA ICANH-SC CANH Source Current Under Short-circuit Condition (VCANH = -2.0 V, CANH driver ON, TXD low) -100 – -40 mA RINSLEEP CANH, CANL Input Resistance Device Supplied and in CAN Sleep Mode 5.0 – 50 k VCANLP CANL, CANH Output Voltage in Sleep Modes. No Termination load. -0.1 0.0 0.1 V ICAN CANH, CANL Input Current, Device Unsupplied, VSUP and VIO connected to GND • VCANH, VCANL = 5.0 V -10 – 10 TOT Overtemperature Detection 160 – – °C THYST Overtemperature Hysteresis -10 – +20 °C Notes CAN OUTPUT PINS (CANH, CANL) DIFF_COM_MODE Differential Input Comparator Common Mode Range VIN_DIFF_SLEEP RIN_MATCH V V µA DIGITAL INTERFACE MISOH High Output Level on MISO (IMISO = 1.5 mA) VDDIO - 0.4 – – V MISOL Low Output Level on MISO (IMISO = 2.0 mA) – – 0.4 V IMISO Tri-state Leakage Current (VDDIO = 5.0 V) -5.0 – 5.0 µA VDDIO Supply Voltage for MISO Output Buffer 3.0 – 5.5 V SPILK SCLK,NCS,MOSI Input Current -1.0 – 1.0 µA VSPI_IH SCLK,NCS,MOSI High Input Threshold 2.0 – – V VSPI_IL SCLK,NCS,MOSI Low Input Threshold – – 0.8 V 200 400 800 K RSPI NCS,MOSI Internal Pull-up (pull-up to VDDIO) 33907_8 18 Analog Integrated Circuit Device Data Freescale Semiconductor Table 4. Operating Range (continued) TCASE = -40 to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 22). Symbol Parameter Min Typ Max Unit Notes DEBUG VDEBUG_IL Low Input Voltage Threshold 2.1 2.35 2.6 V VDEBUG_IH High Input Voltage Threshold 4.35 4.6 4.97 V IDEBUG_LK Input Leakage Current -10 – 10 µA 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 19 4.3 Dynamic Electrical Characteristics Table 5. Dynamic Electrical Characteristics TCASE = -40 to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 22). Symbol Parameter Min Typ Max Unit 0.5 – 8.0 MHz 5.0 5.0 – – 30 50 Notes DIGITAL INTERFACE TIMING fSPI SPI Operation Frequency (50% DC) tMISO_TRANS MISO Transition Speed, 20 - 80% • VDDIO = 5.0 V, CLOAD = 50 pF • VDDIO = 5.0 V, CLOAD = 150 pF ns tCLH Minimum Time SCLK = HIGH 62 – - ns tCLL Minimum Time SCLK = LOW 62 – - ns tPCLD Propagation Delay (SCLK to data at 10% of MISO rising edge) – – 30 ns tCSDV NCS = LOW to Data at MISO Active – – 75 ns tSCLCH SCLK Low Before NCS Low (setup time SCLK to NCS change H/L) 75 – – ns tHCLCL SCLK Change L/H after NCS = low 75 – – ns tSCLD SDI Input Setup Time (SCLK change H/L after MOSI data valid) 40 – – ns tHCLD SDI Input Hold Time (MOSI data hold after SCLK change H/L) 40 – – ns tSCLCL SCLK Low Before NCS High 100 – – ns tHCLCH SCLK High After NCS High 100 – – ns tPCHD NCS L/H to MISO at High-impedance – – 75 ns NCS Min. High Time 500 – – ns NCS Filter Time 10 – 40 ns tONNCS tNCS_MIN 33907_8 20 Analog Integrated Circuit Device Data Freescale Semiconductor Table 5. Dynamic Electrical Characteristics (continued) TCASE = -40 to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 22). Symbol Parameter Min Typ NCS Max Unit Notes tONNCS tSCLCH tHCLCL tCLH tCLL tSCLCL tHCLCH SCLK MISO tPCLD tCSDV Tri-state tPCHD Not used LSB MSB tHCLD tSCLD MOSI LSB MSB Figure 5. SPI Timing Diagram 500 ns min NCS 3.5 µs min Any Fail Safe register acces Any Main register acces Any Fail Safe register acces Figure 6. Register Access Restriction 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 21 Table 5. Dynamic Electrical Characteristics (continued) TCASE = -40 to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 22). Symbol Parameter Min Typ Max Unit Notes CAN DYNAMIC CHARACTERISTICS tDOUT TXD Dominant State Timeout 0.8 – 5.0 ms tDOM Bus Dominant Clamping Detection 0.8 – 5.0 ms tLOOP Propagation Loop Delay TXD to RXD • RLOAD = 120 , C between CANH and CANL = 100 pF, C at RxD < 15 pF – – 255 t1PWU Single Pulse Wake-up Time 0.5 – 5.0 µs t3PWU Multiple Pulse Wake-up Time 0.5 – 1.0 µs t3PTO1 Multiple Pulse Wake-up Timeout (120 µs bit selection) 110 120 – µs t3PTO2 Multiple Pulse Wake-up Timeout (360µs bit selection) 350 360 – µs – – 100 µs tCAN_READY Delay to enable CAN by SPI Command (NCS rising edge) to CAN to Transmit (device in normal mode and CAN interface in TxRx mode) ns (16) FAIL-SAFE STATE MACHINE OSCFSSM Oscillator 400 – 500 kHz CLKFS_MIN Fail-safe Oscillator Monitoring 150 – – kHz tIC_ERR IO_0:5 Filter Time 4.0 – 20 µs tACK_FS Acknowledgement Counter (used for IC error handling IO_1 and IO_5) 7.0 – 9.7 ms 0.8 – 1.3 ms T_DFS_recovery IO_0 filter time to recover from deep reset and fail state FAIL-SAFE OUTPUT tRSTB_FB RSTB feedback filter time 8.0 – 15 µs tFSOB_FB FS0B feedback filter time 8.0 – 15 µs tRSTB_BLK RSTB feedback blanking time 180 – 320 µs tFSOB_BLK FS0B feedback blanking time 180 – 320 µs tRSTB_POR Reset delay time (after a Power On Reset or from LPOFF) 12 15.9 23.6 ms tRSTB_LG Reset duration (long pulse) 8.0 – 10 ms tRSTB_ST Reset duration (short pulse) 1.0 – 1.3 ms tRSTB_IN External Reset delay time 8.0 – 15 µs T_FS_FB RSTB, FS0B Feedback Filter Time 8.0 – 15 µs Fail-safe Output Diagnostic Counter (FS0B) 550 – 800 µs -2.0 – 2.0 V/µs T_DIAG_SC VSUP VOLTAGE SUPPLY DVSUP/DT Supply Voltage Slew Rate Notes 16. For proper CAN operation, TXD must be set to high level before CAN being enabled by SPI, and must remain high for at least TCAN_READY 33907_8 22 Analog Integrated Circuit Device Data Freescale Semiconductor Table 5. Dynamic Electrical Characteristics (continued) TCASE = -40 to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 22). Symbol Parameter Min Typ Max Unit 418 440 462 kHz – – 30 ns VPRE Soft Start Duration (COUT 100 µF) 500 – 700 µs VPRE Current Limitation Blanking Time 200 – 600 ns tIPRE_OC VPRE Overcurrent Filtering Time 30 – 120 ns tPRE_UV VPRE Undervoltage Filtering Time 20 – 40 µs Vpre Shut-off Filtering Time 3.0 – 6.0 µs VPRE Load Regulation Variation – – 25 A/ms tPRE_WARN VPRE Thermal Warning Filtering Time 30 – 40 µs tPRE_TSD VPRE Thermal Detection Filtering Time 1.3 – – µs tVSUP_IPFF IPFF Input Voltage Filtering Time 1.0 – 4.0 µs tIPRE_IPFF IPFF High Side Peak Current Filter Time 100 – 300 ns – – 50 ns 1.0 – 3.0 µs Notes VPRE VOLTAGE PRE-REGULATOR fSW_PRE VPRE Switching Frequency tSW_PRE VSW_PRE On and Off Switching Time tPRE_SOFT tPRE_BLK_LIM tPRE_UV_4p3 dIPRE/DT tLS_RISE/FALL LS Gate Voltage Switching Time (IOUT = 300 mA) (17) (17) (17) VSENSE VOLTAGE REGULATOR tVSNS_UV VSNS Undervoltage Filtering Time VCORE VOLTAGE REGULATOR tCORE_BLK_LIM VCORE Current Limitation Blanking Time 20 – 40 ns fSW_CORE VCORE Switching Frequency 2.28 2.4 2.52 MHz tSW_CORE VSW_CORE On and Off Switching Time 6.0 – 12 ns VCORE_SOFT VCORE Soft Start (COUT = 100 µF max) – – 10 V/ms tCORE_WARN VCORE Thermal Warning Filtering Time 30 – 40 µs tCORE_TSD VCORE Thermal Detection Filtering Time 0.5 – – µs VCCA Output Current Limitation Filter Time 1.0 – 3.0 µs VCCA Output Current Limitation Duration 10 50 – – – – ms VCCA Thermal Warning Filtering Time 30 – 40 µs tCCA_TSD VCCA Thermal Detection Filter Time (int. MOSFET) 1.5 – – µs dILOAD/dt VCCA Load Transient – 2.0 – A/ms VCCA Soft Start (5.0 V and 3.3 V) – – 50 V/ms VCCA VOLTAGE REGULATOR tCCA_LIM tCCA_LIM_OFF1 tCCA_LIM_OFF2 tCCA_WARN VCCA_SOFT (17) Notes 17. Guaranteed by characterization. 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 23 Table 5. Dynamic Electrical Characteristics (continued) TCASE = -40 to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 22). Symbol Parameter Min Typ Max Unit VAUX Output Current Limitation Filter Time 1.0 – 3.0 µs VAUX Output Current Limitation Duration 10 50 – – – – ms tAUX_TSD VAUX Thermal Detection Filter Time 1.5 – – µs dIAUX/dt VAUX Load Transient – 2.0 – A/ms VAUX Soft Start (5.0 V and 3.3 V) – – 50 V/ms Notes VAUX VOLTAGE REGULATOR tAUX_LIM tAUX_LIM_OFF1 tAUX_LIM_OFF2 VAUX_SOFT (18) 5V-CAN VOLTAGE REGULATOR tCAN_LIM Output Current Limitation Filter Time 2.0 – 4.0 µs tCAN_TSD VCAN Thermal Detection Filter Time 1.0 – – µs tCAN_UV VCAN Undervoltage Filtering Time 4.0 – 6.0 µs tCAN_OV VCAN Overvoltage Filtering Time 100 – 200 µs dICAN/dt VCAN Load Transient – 100 – A/ms VPRE Overvoltage Filtering Time 128 – 234 µs tCORE_UV VCORE FB Undervoltage Filtering Time 4.0 – 10 µs tCORE_OV VCORE FB Overvoltage Filtering Time 128 – 234 µs tCCA_UV VCCA Undervoltage Filtering Time 4.0 – 10 µs tCCA_OV VCCA Overvoltage Filtering Time 128 – 234 µs tAUX_UV VAUX Undervoltage Filtering Time 4.0 – 10 µs tAUX_OV VAUX Overvoltage Filtering Time 128 – 234 µs 0.0 – 100 kHz – – 10 (18) FAIL-SAFE MACHINE VOLTAGE SUPERVISOR tPRE_OV MULTI-PURPOSE IOS DIGITAL INPUT FIO_IN Digital Input Frequency Range ANALOG MULTIPLEXER tMUX_READY SPI Selection to Data Ready to be Sampled on Mux_out • VDDIO = 5.0 V, CMUX_OUT = 1.0 nF µs INTERRUPT tINTB_LG INTB Pulse Duration (long) 100 – – µs tINTB_ST INTB Pulse Duration (short) 25 – – µs 50 70 90 µs FUNCTIONAL SATE MACHINE tWU_GEN General Wake-up Signal Deglitch Time (for IO wu signal) Notes 18. Guaranteed by characterization. 33907_8 24 Analog Integrated Circuit Device Data Freescale Semiconductor 5 Functional Description 5.1 Introduction The 33907_8 is the third generation of the System Basis Chip, combining: • High efficiency switching voltage regulator for MCU, and linear voltage regulators for integrated CAN interface, external ICs such as sensors, and accurate reference voltage for A to D converters. • Built in enhanced high speed CAN interface (ISO11898-2 and -5), with local and bus failure diagnostic, Protection and Failsafe operation mode. • Low power mode, with ultra low current consumption. • Various wake-up capabilities • Enhanced safety features with multiple fail-safe outputs and scheme. 5.2 Functional Pin Description 5.2.1 Power Supply(VSUP1, VSUP2, VSUP3) VSUP1 and VSUP2 are the inputs pins for internal supply dedicated to SMPS regulators. VSUP3 is the input pin for internal voltage reference. VSUP1, 2, and 3 are robust against ISO7637 pulses. 5.2.2 VSENSE Input (VSENSE) This pin must be connected to the battery line (before the reverse battery protection diode), via a serial resistor. It incorporates a threshold detector to sense the battery voltage, and provide a battery early warning. It also includes a resistor divider to measure the VSENSE voltage via the MUX-OUT pin. VSENSE pin is robust against ISO7637 pulse. 5.2.3 VCORE Output (1.2 V, 3.3 V) On 33907 and 33908 product versions, the VCORE block is an SMPS regulator. The main difference between both versions is the current capability of the VCORE regulator. On 33907 and 33908 product versions, the voltage regulator is a step down DC-DC converter operating in voltage control mode. The output voltage is selectable (1.2 V or 3.3 V) through an external resistor divider connected between VCORE and the feedback pin (FB_Core) (Figure 1). The stability of the converter is done externally, by using the COMP_Core pin. 5.2.4 VAUX OUTPUT, 5.0 V, 3.3 V Selectable The VAUX pin provides an auxiliary output voltage (5.0 V, 3.3 V) selectable through an external resistor connected to SELECT pin. It uses an external PNP ballast transistor for flexibility and power dissipation constraints. The VAUX output voltage regulator can be used as “sensor supply” (external ECU supply) or “auxiliary supply” (local ECU supply). Overcurrent, overvoltage, and undervoltage detectors are provided. VAUX can be turned ON or OFF (if not configured as safety critical) via a SPI command. VAUX overcurrent and overvoltage information disables VAUX, reported in the dedicated register, and generates an Interrupt. VAUX is enabled by default. 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 25 5.2.5 VCCA Output, 5.0 V or 3.3 V Selectable The VCCA voltage regulator is used to provide an accurate voltage output (5.0 V, 3.3 V) selectable through an external resistor connected to the SELECT pin. The VCCA output voltage regulator can be configured using an internal ballast transistor delivering very good accuracy (+/- 1% for 5 V configuration and +/- 1.5% for 3.3 V configuration), with a limited current capability (100 mA) for an Analog to Digital converter, or with an external PNP transistor, giving higher current capability with lower output voltage accuracy when using a local ECU supply. Overcurrent, overvoltage, and undervoltage detectors are provided. VCCA can be turned ON or OFF (if not configured as safety critical) via a SPI command. VCCA overcurrent (with the use of external PNP only) and overvoltage information disables VCCA. Diagnostics are reported in the dedicated register and generate an Interrupt. VCCA is enabled by default. 5.2.6 SELECT Input (VCCA, VAUX Voltage Configuration) VCCA and VAUX output voltage configurations are set by connecting an external resistor between SELECT pin and Ground. According to the value of this resistor, the voltage of VCCA and VAUX are configured after each Power On Reset, and after a wake-up event when device is in LPOFF. Information latches until the next hardware configuration read. Regulator voltage values can be read on the dedicated register via the SPI. Table 6. VCCA/VAUX Voltage Selection VCCA(V) VAUX(V) R Select Recommended value 3.3 3.3 <7.0 K 5.1 K5.0% 5.0 5.0 10.8 << 13.2 K 12 K5.0% 3.3 5.0 21.6 << 26.2 K 24 K5.0% 5.0 3.3 45.9 << 56.1 K 51 K5.0% When VAUX is not used, the output VCCA voltage configuration is set using an external resistor connected between the SELECT and the VPRE pin. Table 7. VCCA Voltage Selection (VAUX not used) VCCA(V) R select Recommended Value 3.3 <7.0 K 5.1 K5.0% 21.6 << 26.2 K 24 K5.0% 10.8 << 13.2 K 12 K5.0% 45.9 << 56.1 K 51 K5.0% 5.0 5.2.7 Debug Input (Entering In Debug Mode) The DEBUG pin allows the product to enter Debug mode. To activate the Debug mode, voltage applied to the DEBUG pin must be within the VDEBUG_IL and VDEBUG_IH range at startup. If the voltage applied to DEBUG pin is out of these limits, before VCORE ramp-up, the device settles into Normal mode. When the Debug mode is activated, the FS0B output is asserted low at startup. As soon as the FS0B is released to “high” via SPI (Good WD answer and FS_OUT writing) this pin is never activated whatever the fault is reported. In debug mode, any errors from watchdog are ignored (No reset and No fail-safe), even if the whole functionality of the watchdog is kept ON (Seed, LFSR, Wd_refresh counter, WD error counter). This allows an easy debug of the hardware and software routines (i.e. SPI commands). 33907_8 26 Analog Integrated Circuit Device Data Freescale Semiconductor When the Debug mode is activated, the CAN transceiver is set to Normal operation mode. This allows communication with the MCU, in case SPI communication is not available (case of MCU not programmed). To exit Debug mode, the pin must be tied to ground through an external pull-down resistor. A Power On Reset occurs. 5.2.8 5 V-CAN Voltage Regulator 5 V-CAN voltage regulator is a linear regulator fully dedicated to the internal HSCAN interface. An external capacitor is required. Overcurrent, overvoltage, and undervoltage detectors are provided. During overvoltage, the 5 V-CAN regulator switches off. Information is reported in the dedicated register and this generates an Interrupt. The 5 V-CAN regulator is enabled by default. 5.2.9 Multiplexer Output Mux_out The MUX_OUT pin (Figure 7) delivers analog voltage to the MCU ADC input. The voltage to be delivered to MUX_OUT is selected via the SPI, from one of the following parameters: • VSENSE • VIO_O • VIO_1 • Internal 2.5 V reference • Die temperature sensor T (°C) = Vmux_Out * 165 / 2.15 Voltage range at MUX_OUT is from GND to VDDIO (3.3 V or 5.0 V) Vsense R 1 SPI selection Mux_out R 2 R 3 R 5 R 4 SPI selection 3.3V 3.3V Ratio#1 Ratio#2 5V Ratio#2 5V Ratio#1 Internal 2.5V reference SPI selection IO_0 Same as above IO_1 Same as above Die temperature sensor Figure 7. Simplified Analog Multiplexer Block Diagram 5.2.10 CANH, CANL, RXD, TXD These are the pins of the high speed CAN physical interface. The CAN interface is connected to the MCU via the RXD and TXD pins. The HSCAN also exhibits wake-up capability with a very low current consumption. 5.2.11 INTERRUPT (INTB) The INTB output pin generates a low pulse when an Interrupt condition occurs. The INTB behavior as well as the pulse duration are set through the SPI during INIT phase. 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 27 5.2.12 I/O pins (I/O_0:I/O_6) The 33907_8 includes six multi-purpose I/Os (I/O_0 to I/O_5). I/O_0, I/O_1, I/O_4, and I/O_5 are load dump proof and robust against ISO7637 pulses. An external serial resistor must be connected to those pins. I/O_2 and I/O_3 are not load dump proof. Table 8. I/Os Configuration I/0 Number Analog Input Digital Input Wake-up Capability Output Gate Driver IO_0 X X X IO_1 X X X IO_2 X X IO_3 X X IO_4 X X X IO_5 X X X • IO_0:1 are selectable as follows: Analog input (load dump proof) sent to the MCU through the MUX_OUT pin. Wake-up input on the rising or falling edge or based on the previous state. Digital input (logic level) sent to the MCU through the SPI. Safety purpose: Digital input (logic level) to perform an IC error monitoring (both IO_0 AND IO_1 are used if configured as safety inputs). • IO_2:3 are selectable as follows: Digital input (logic level) sent to the MCU through the SPI. Wake-up input (logic level) on the rising or falling edge or based on the previous state. Safety purpose: Digital input (logic level) to monitor MCU error signals (both IO_2 AND IO_3 are used if configured as safety inputs). Only bi-stable protocol is available. Reset Phase Normal Phase Error Phase Config Phase FCCU_eout[0] FCCU_eout[1] Figure 8. IO_2:3 MCU Error Monitoring: Bi-stable Protocol • IO_4:5 are selectable as follows: Digital input (logic level) sent to the MCU through the SPI. Wake-up input (load dump proof) on rising or falling edge or based on previous state. Output gate driver for LS logic level MOSFET. Safety purpose: Digital input (logic level) to perform an IC error monitoring (both IO_4 AND IO_5 are used if configured as safety inputs). 33907_8 28 Analog Integrated Circuit Device Data Freescale Semiconductor Error signal (IO_4 input) MC33907_8 Internal IO_4 signal PC33907_8 latched Acknowledgment counter Reset counter Restart Acknowledgment counter Acknowledgement signal from MCU (IO_5 input) Filter time RST RSTB FS0b FSOB The error is acknowledged by the MCU then, internal IO_4 signal is released The error is NOT acknowledged by the MCU So, FSOB FS0b is activated at the end of the counter Figure 9. External Error Signal Handling 5.2.13 SAFE Output PINs (FS0B, RSTB) FS0B is asserted low when a fault event occurs (See Faults Triggering FS0B Activation on page 42).The objective of this pin is to drive an electrical safe circuitry to deactivate the whole system and set the ECU in a protected and known state. An external pull-up circuitry is mandatory connected to VDDIO or VSUP3. If pull-up is connected to VSUP3, the value of this pullup must be above 10 kohm. After each power on reset or after each wake-up event (LPOFF) the FS0B pin is asserted low. Then the MCU can decide to release the FS0B pin, when the application is ready to start. The RSTB pin must be connected to MCU and is active low. An external pull-up resistor must be connected to VDDIO. In default configuration, the RST delay time has three possible values depending of the mode and product configuration: • The longest one is used automatically following a Power On Reset or when resulting from LPOFF mode (Low Power Off). • The two reset durations are then available in the INIT_FSSM1 register, which are 1.0 ms and 10 ms. The configured duration is finally used in the normal operation when a fault occurs leading to a reset activation. The INIT_FSSM1 register is available (writing) in the INIT FS phase. 5.2.14 Pre-regulator (VPRE) A highly flexible SMPS pre-regulator is implemented in the 33907_8. It can be configured as “Non-inverting Buck-boost converter” (Figure 24) or “Standard Buck converter” (Figure 23), depending of the external configuration (Low Side connection). The configuration is detected automatically during start-up sequence. The SMPS pre-regulator is working in current mode control and the compensation network is fully integrated in the device. The high side switching MOSFET is also integrated to make the current control easier. The pre-regulator delivers a voltage output of 6.5 V, which is used internally. Overcurrent, overvoltage, and undervoltage detectors are provided. 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 29 6 Functional Device Operation 6.1 Mode and State Description of MAIN State Machine The device has several operation modes. The transition and conditions to enter or leave each mode are illustrated in the functional state diagram (Figure 10). Two state machines are working in parallel. The Main state machine is in charge of the power management (VPRE, VCORE, VAUX, VCCA,...) and the fail-safe state machine is in charge of all the safety aspect (WD, RSTB, FS0B,...). 6.1.1 Buck or Buck Boost Configuration An external low side logic level MOSFET (N-type) is required to operate in “Non-inverting buck-boost converter”. The connection of the external MOSFET is detected automatically during the start-up phase. If the low side is not connected (GATE_LS pin connected to PGND), the product is configured as a standard buck converter. 6.1.2 VPRE ON Pre-regulator is an SMPS regulator. In this phase, the pre-regulator is switched ON and a softstart with a specified duration is started to control the VPRE output capacitor charge. 6.1.3 Select Pin Configuration This phase is detecting the required voltage level on VAUX and VCCA, according to resistor value connected between the SELECT pin and ground. If the SELECT pin is connected to VPRE via the resistor, it disables the VAUX regulator at start-up. 6.1.4 VCORE/VAUX/VCCA ON In this stage, the three regulators are switched ON at the same time with a specified soft start duration. 6.1.5 INIT Main This mode is automatically entered after the device is “Powered ON”. When RSTB is released, initialization phase starts where the device can be configured via the SPI. During INIT phase, some registers can only be configured in this mode (refer to Table 12 and Table 13). Other registers can be written in this mode, and also in Normal mode. Once the INIT registers configurations are complete, a last register called “INIT INT” must be configured to switch to Normal mode. Writing data in this register (even same default values), automatically locks the INIT registers, and the product switches automatically to Normal mode in the Main state machine. 6.1.6 Normal In this mode, all device functions are available. This mode is entered by a SPI command from the INIT phase by writing in the INIT INT register. While in Normal mode, the device can be set to Low power mode (LPOFF) using secured SPI command. 6.1.7 Low Power Mode OFF - LPOFF Sleep Entering in Low Power mode OFF - SLEEP is only available if the product is in Normal mode by sending a secured SPI command. In this mode, all the regulators are turned OFF and the MCU connected to VCORE regulator is unsupplied. 33907_8 30 Analog Integrated Circuit Device Data Freescale Semiconductor Once the 33907_8 is in LPOFF SLEEP, the device monitors external events to wake-up and leave the Low Power mode. The wake-up events can occur and depending of the device configuration from: • CAN • I/Os inputs When a wake-up event is detected, the device starts the main state machine again by detecting the VPRE configuration (BUCK or BUCK-BOOST), the wake-up source is reported to the dedicated SPI register, and the Fail-safe state machine is also restarted. Finally, after the wake-up event, the regulators are turned ON and the MCU operation restarts, and the initialization phase is accessible again. 6.1.8 Low Power Mode OFF - LPOFF VPRE_UV LPOFF- VPRE_UV is entered when the device is in the INIT or Normal mode, and if the VPRE voltage level is passing the VPRE_UV_L_4P3 threshold (4.3 V instead of 6.5 V) due to a problem on VPRE. As the device is in LPOFF, all the regulators are switched OFF. After 1.0 ms the device attempts to recover by switching ON the VPRE again. 6.1.9 Low Power Mode OFF - LPOFF DEEP FS LPOFF DEEP FS is entered during start-up if the Power On Reset of the Fail-safe machine is not rising and if the key is OFF. in this mode, all regulators are OFF and to exit this mode, a high level on IO_0 is required (often connected to key ON key OFF signal). LPOFF DEEP FS is also entered if the RSTB pin is asserted low within 8.0 s. 6.2 Mode and State Description of Fail-safe State Machine 6.2.1 LBIST Included in the fail-safe machine, the Logic Built In Self Test (LBIST) verifies the correct functionality of the FSSM at start-up. The fail-safe state machine is fully checked and if an issue is reported, the device does not start and the RSTB stays low to finally go in LPOFF DEEP FS. LBIST is run at start-up and after each wake-up event when device is in LPOFF mode. 6.2.2 Select Pin Configuration This phase detects the required voltage level on VAUX and VCCA, according to the resistor value connected between the SELECT pin and ground, in case VAUX is used or the SELECT pin and VPRE, if VAUX is not used in the application. This mode is the equivalent mode seen in the main sate machine. Difference is in the fail-safe machine. This detection is used to internally set the UV/OV threshold on VCCA and VAUX for the voltage supervision. 6.2.3 ABIST Included in the fail-safe machine, the Analog Built In Self Test (ABIST) verifies the correct functionality of the analog part of the device, like the voltage supervisor (overvoltage and undervoltage detection) and the fail-safe output feedback (RSTB and FS0B). The ABIST is run at start-up and after each wake-up event when device is in LPOFF mode. 6.2.4 Release RSTB In this state, the device releases the RSTB pin. 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 31 6.2.5 INIT FS This mode is automatically entered after the device is “powered on” and only if Built Self Tests (Logic and Analog) have been passed successfully. This INIT FS mode starts as soon as RSTB is released (means no “Activate RST” faults are present and no external reset is requested). Faults leading to an “Activate RST” are described in Watchdog Refresh Counter. In this mode, the device can be configured via the SPI within a maximum time of 256 ms, including first watchdog refresh. Some registers can only be configured in this mode and is locked when leaving INIT FS mode (refer to Table 12 and Table 13). It is recommended, to configure first the device before sending the first WD refresh. As soon as the first good watchdog refresh is sent by the MCU, the device leaves this mode and goes into Normal WD mode. 6.2.6 Normal WD is Running In this mode, the device is now waits for a periodic watchdog refresh, coming from the MCU within a specific configured window timing. Configuration of the watchdog window period can be set during INIT FS phase or in this mode. This mode is exited if there are consecutive bad watchdog refreshes, or if there is an external reset request. 6.2.7 RST Delay When the reset pin is asserted low by the device, a delay runs, to release the RSTB, if there is no more faults present. The reset low duration time is configurable via the SPI in the INIT_ FSSM1 register, which is accessible (writing) only in the INIT FS phase. All the sources of reset are available in the Watchdog Refresh Counter. 33907_8 32 Analog Integrated Circuit Device Data Freescale Semiconductor 6.3 Functional State Diagram Wait Fail SAFE VSUP > VSUP_UV_5 PowerDown No POR Fail Safe POR Fail Safe & Fail Safe Reg. ON & VSUP > VSUP_UV_5 VSUP < VSUP_UV_L From Anywhere POR Fail Safe VSUP < VSUP_UV_5 Buck or Buck Boost configuration detection - RSTb is asserted low LBIST LBIST Done & VPRE>VPRE_UV 120µs elapsed VSUP < VSUP_UV_5 VPRE ON VPRE<VPRE_UV VPRE>VPRE_UV SELECT pin config. detection SELECT pin config. detection No IO_0 - RSTb is asserted low 1ms elapsed & VCORE > VCORE_UV & VCCA > VCCA_UV & VAUX > VAUX_UV VPRE<VPRE_UV Wait Deep Fail Safe From Anywhere PowerDown - RSTb is asserted low ABIST 1ms elapsed RST delay=8s or RST error counter = 6 Vcore/Vaux/ Vcca ON ABIST Pass No activate RST & - RSTb delay running RST delay expired - RSTb is asserted low RST Delay - Unlock SPI init registers - SPI config Activate RST VPRE_UV_L4P3 INIT MAIN - SPI init registers locked NORMAL MODE Activate RST or WD Not OK LPOFF SLEEP - Unlock SPI init registers - Start 256ms open window - RSTb is released WD OK RSTb delay = 8s LPOFF VPRE_UV CAN/IOs event - VCAN/VCORE/VAUX/VCCA OFF - Fail Safe OFF External RST Activate RST NORMAL WD is RUNNING - Start WD close/open window 1ms Rise IO_0 POR Fail Safe & Fail Safe Reg. ON & VPRE OFF INIT FS VPRE_UV_L4P3 SPI command LPOFF DEEP FS - RSTb is released No external RST & No activate RST External RST INIT done (init int reg. writing) External RST Release RSTb Activate RST : any UV, any OV, WD, IO_23 error, deep fail safe, reset by spi, FS0b short to VDD, SPI DED Wake up - VCAN/VCORE OFF - VAUX/VCCA OFF - OSC Main ON - FailSafe ON MAIN STATE MACHINE FAIL SAFE STATE MACHINE Figure 10. Simplified State Diagram 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 33 6.4 Fail-safe Machine To fulfill safety critical applications, the 33907_8 integrates a dedicated Fail-safe machine (FSM). The FSM is composed of three main sub-blocks: the Voltage Supervisor (VS), the Fail-safe State Machine (FSSM), and the Fail-safe Output driver (FSO).The FSM is electrically independent from the rest of the circuitry, to avoid common cause failure. For this reason, the FSM has its own voltage regulators (analog and digital), dedicated bandgap, and its own oscillator. Three power supply pins (VSUP 1, 2, & 3) are used to overtake a pin lift issue. The internal voltage regulators are directly connected on VSUP (one bonding wire per pin is used). Additionally, the ground connection is redundant as well to avoid any loss of ground. All the voltages generated in the device are monitored by the voltage supervisor (under & overvoltage) due to a dedicated internal voltage reference (different from the one used for the voltage regulators). The result is reported to the MCU through the SPI and delivered to the Fail-safe state machine (FSSM) for action. The FSSM has its own voltage regulator and oscillator. All the safety relevant signals feed the FSSM, which handles the error handling and controls the fail-safe outputs. There are two fail-safe outputs: RSTB (asserted low to reset the MCU), and FS0B (asserted low to control any fail-safe circuitry). The Fail-safe machine is in charge of bringing and maintaining the application in a fail-safe state. Four sub fail-safe states are implemented to handle the different kinds of failures, and to give a chance for the system to come back to a normal state. 6.5 Fail-safe Machine State Diagram No POR Fail Safe From Anywhere PowerDown POR Fail Safe LBIST - RSTb is asserted low LBIST Done & VPRE>VPRE_UV SELECT pin config. detection VPRE<VPRE_UV - RSTb is asserted low 1ms elapsed & VCORE > VCORE_UV & VCCA > VCCA_UV & VAUX > VAUX_UV ABIST RSTb delay = 8s IO_0 - RSTb is asserted low ABIST Pass - RSTb delay running - RSTb is asserted low RST delay=8s OR Rst_error_count=6 - VCAN/VCORE OFF - VAUX/VCCA OFF - Fail Safe OFF Deep Fail Safe - FS0b = Low - RSTb = Low Assert RSTb No activate RST & RST delay expired Activate RST FS0b low & No activate RST & RST delay expired External RST - RSTb is released No external RST & No activate RST External RSTb = 8s External RST Activate RST 2 > RST_error_count < 6 Release RSTb Activate RST or WD Not OK INIT FS - Unlock SPI init registers - Start 256ms open window - RSTb is released WD OK RST delay=8s - FS0b is asserted low FS0B Low Ext. IC error (IO0:1 and/or IO4:5) Ext. IC error (IO0:1 and/or IO4:5) External RST RST_err_count = 0 & FS_OUT ok NORMAL WD is RUNNING - Start WD close/open window Release FSOb -FS0b is released No FS0b Figure 11. Simplified Fail-safe State Diagram 33907_8 34 Analog Integrated Circuit Device Data Freescale Semiconductor 6.6 Watchdog Operation A windowed watchdog is implemented in the PowerSBC and is based on "question/answer" principle. The watchdog must be continuously triggered by the MCU in the open watchdog window, otherwise an error is generated. The error handling and watchdog operations are managed by the Fail-safe state machine. For debugging purpose, this functionality can be inhibited by setting the right voltage on the DEBUG pin at start-up. The watchdog window duration is selectable through the SPI during the INIT FS phase or in normal mode. The following values are available: 1.0 ms, 2.0 ms, 3.0 ms, 4.0 ms, 6.0 ms, 8.0 ms, 12 ms, 16.0 ms, 24 ms, 32 ms, 64 ms, 128 ms, 256 ms, 512 ms, 1024 ms. The watchdog can also be inhibited through the SPI register to allow “reprogramming” (ie.at vehicle level through CAN). An 8-bit pseudo-random word is generated, due to a Linear Feedback Shift Register implemented in the PowerSBC. The MCU sends the seed of the LFSR during the INIT phase and then uses it to perform a pre-defined calculation. The result is sent through the SPI during the “open” watchdog window and verified by the PowerSBC. When the result is right, the LFSR is incremented and the watchdog window is restarted. When the result is wrong, the WD error counter is incremented, the watchdog window is restarted, and an INTB is generated. Any access to the WD register during the “closed” watchdog window is considered a wrong WD refresh. 6.6.1 Normal Operation (First Watchdog Refresh) At power up, when the RSTB is released as high (after around 13 ms), the INIT phase starts for a maximum duration of 256 ms and this is considered as a fully open watchdog window. During this initialization phase the MCU sends the seed for the LFSR, or uses the default LFSR value generated by the PowerSBC (0xB2), available in the WD_LFSR register (Table 73). Using this LFSR, the MCU performs a simple calculation based on this formula: the result of this calculation is based on the LSFSR default value: 0x4D. LFSR_OUT[7:0] x + - 4 6 4 NOT / WD_answer[7:0] 4 Figure 12. Watchdog Answer Calculation The MCU sends the results in the WD answer register (Table 75). When the watchdog is properly refreshed during the open window, the 256 ms open window is stopped and the initialization phase is finished. A new LFSR value is generated and available in the WD_LFSR register (Table 73). If the watchdog refresh is wrong or if the watchdog is not refreshed during this 256 ms open window (INIT FS phase), the device asserts the reset low and the RSTB error counter is incremented by “1”. After a good watchdog refresh, the device enters the Normal WD refresh mode, where open and closed windows are defined either by the configuration made during initialization phase in the watchdog window register (Table 71), or by the default value already present in this register (3.0 ms). 6.6.2 Normal Watchdog Refresh The watchdog must be refreshed during every open window of the window period configured in the register Table 71. Any WD refresh restarts the window. This ensures the synchronization between MCU and PowerSBC. The duration of the “window” is selectable through the SPI with no access restriction, means the window duration can be changed in the INIT phase or Normal mode. The duty cycle of the window is set to 50% and is not modifiable. 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 35 Window Period CLOSED OPEN Refresh Slot CLOSED OPEN Refresh Slot Figure 13. Windowed Watchdog 6.6.3 Watchdog in Debug Mode When the device is in debug mode (entered via the DEBUG pin), the watchdog continues to operate, but does not affect the device operation by asserting a reset or fail-safe pins. For the user, operation appears without the watchdog. If needed and to debug the watchdog itself, the user can operate as in Normal mode and check LFSR values, the watchdog refresh counter, the watchdog error counter, and reset counter. This allows the user to debug their software and ensure a good watchdog strategy in the application. 33907_8 36 Analog Integrated Circuit Device Data Freescale Semiconductor 6.7 Wrong Watchdog Refresh Handling Error counters and strategy are implemented in the device to manage wrong watchdog refreshes from the MCU. According to consecutive numbers of wrong watchdog refreshes, the device can decide to assert the RSTB only, or to go in deep fail-safe mode where only a Power On Reset or a transition on IO_O helps the system to recover. 6.7.1 Watchdog error counter The watchdog error counter is implemented in the device to filter the incorrect watchdog refresh. Each time a watchdog failure occurs, the device increments this counter by 2. The WD error counter is decremented by 1 each time the watchdog is properly refreshed. This principle ensures that a cyclic “OK/NOK” behavior converges to a failure detection. To allow flexibility in the application, the maximum value of this counter is configurable in the INIT_WD register, but only when device is in INIT FS mode. Watchdog Error Counter WD_CNT_error = 6 WD refresh NOK 0 WD refresh NOK 1 WD refresh NOK 2 Watchdog Error Counter WD_CNT_error = 4 WD refresh NOK 0 WD refresh OK WD refresh NOK 0 WD refresh OK WD refresh NOK 1 WD refresh NOK 2 WD refresh OK 1 WD refresh OK WD refresh OK WD refresh NOK Watchdog Error Counter WD_CNT_error = 2 2 WD refresh OK 3 3 WD refresh NOK WD refresh OK WD refresh NOK 4 4 WD refresh OK 5 WD refresh NOK 6 Figure 14. Watchdog Error Counter Configuration (Init_WD register, Bits WD_CNT_error_1:0) 6.7.2 Watchdog Refresh Counter The watchdog refresh counter is used to decrement the RST error counter. Each time the watchdog is properly refreshed, the watchdog refresh counter is incremented by “1”. Each time the watchdog refresh counter reaches “6” and if next WD refresh is also good, the RST error counter is decremented by “1” (case with WD_CNT_refresh_1:0 configured at 6). Whatever the position is in the watchdog refresh counter, each time there is a wrong refresh watchdog, the watchdog refresh counter is reseted to “0”. To allow flexibility in the application, the maximum value of this watchdog refresh counter is configurable in the INIT_WD register, but only when device is in INIT FS mode. 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 37 Watchdog Refresh Counter WD_CNT_refresh = 6 Watchdog Refresh Counter WD_CNT_refresh = 1 Watchdog Refresh Counter WD_CNT_refresh = 4 WD Refresh NOK 0 0 0 WD Refresh OK WD Refresh OK WD Refresh OK 1 WD Refresh OK 2 WD Refresh OK 3 WD Refresh OK 4 WD Refresh OK 5 WD Refresh OK 6 WD Refresh NOK WD Refresh NOK 1 WD Refresh NOK / WD_OFF WD Refresh OK WD Refresh NOK / WD_OFF WD Refresh OK WD Refresh NOK / WD_OFF WD Refresh OK 2 3 WD Refresh NOK / WD_OFF 4 1 WD Refresh NOK / WD_OFF WD Refresh OK / WD Refresh NOK / WD_OFF WD Refresh NOK / WD_OFF WD Refresh NOK / WD_OFF WD Refresh OK / WD Refresh NOK / WD_OFF WD Refresh NOK / WD_OFF WD Refresh OK / WD Refresh NOK / WD_OFF Figure 15. Watchdog Refresh Counter Configuration (Init_WD register, WD_CNT_refresh_1:0) Table 9. Watchdog Error Table WINDOW SPI CLOSED OPEN BAD Key WD_NOK WD_NOK GOOD Key WD_NOK WD_OK None (timeout) No_issue WD_NOK Any access to the watchdog register during the “closed” watchdog window is considered as a wrong watchdog refresh. Watchdog timeout, meaning no WD refresh during closed or open windows, is considered as a wrong WD refresh. 6.7.3 Reset Error Counter The reset error counter manages the reset events and counts the number of resets occurring in the application. This counter is incremented not only for the reset linked to consecutive wrong refresh watchdogs, but also for other sources of reset (undervoltage, overvoltage, external reset). The RST error counter is incremented by 1, each time a reset is generated. The reset error counter has two output values (intermediate and final). The intermediate output value is used to handle the transition from reset (RSTB is asserted low) to reset and fail where RSTB and FS0B are activated. The final value is used to handle the transition from reset and fail to deep reset and fail (Deep fail-safe mode), where regulators are off, reset and FS0B are activated, and a power on reset or a transition on IO_0 is needed to recover. The intermediate value of the reset error counter is configurable to “1” or “3” using the RSTB_err_FS bit in the INIT FSSM2 register (Table 69). If RSTB_err_FS is set to “0”, it means the device activates FS0B when the reset error counter reaches level “3”. If RSTB_err_FS is set to “1”, it means the device activates FS0B when the reset error counter reaches level “1”. This configuration must be done during INIT FS phase. The final value of the reset error counter is based on the intermediate configuration. 33907_8 38 Analog Integrated Circuit Device Data Freescale Semiconductor • RSTB_err_FS = 0 / Intermediate = 3; Final = 6 (Figure 16). When reset error counter reaches 6, the device goes into deep reset and fails. • RSTB_err_FS = 1 / Intermediate = 1; Final = 2 (Figure 17). When reset error counter reaches 2, the device goes into deep reset and fails. In any condition, if the RSTB is asserted LOW for a duration longer than eight seconds, the device goes into deep reset and fails. Conditions that leads to an incrementation of the RSTB error counter, and according to the product configuration are: • Watchdog error counter = 6 • Watchdog refresh NOK during INIT phase or Watchdog timeout • IO_23 error detection (FCCU) • Undervoltage • Overvoltage • FS0B shorted to VDD • SPI DED • Reset request by the SPI • External reset Conditions leading to a transition go to FS, according to the product configuration are: • IO_01/IO_23/IO_45 error detection • Undervoltage • Overvoltage • Analog BIST fail • SPI DED • RSTB shorted to high Reset Error Counter (Cfg SPI RSTb_err_FS=0; WD_CNT_refresh=6) 7 consecutive WD Refresh OK POR or from LPOFF mode INCR = WD error counter = WD_CNT_error[1:0] | WD refresh NOK during INIT | IO23_ERR |UV/OV | FS0b_shorttovdd | SPI DED | Reset by SPI | External reset gotoFS = IO01/23/45_ERR | UV/OV | ABIST_fail | SPI DED | RSTb_short2hi gotoFS (7 = WD_CNT_refresh + 1) 0 INCR 7 consecutive WD Refresh OK INCR 7 consecutive WD Refresh OK INCR 7 consecutive WD Refresh OK 1 gotoFS 2 Active FS0 3 INCR Active FS0 4 INCR Active FS0 7 consecutive WD Refresh OK 7 consecutive WD Refresh OK 5 INCR Active FS0 Turn OFF regulators 6 RSTb asserted for 8 seconds Figure 16. RSTB Error Counter (RSTB_err_FS = 0) 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 39 Reset Error Counter (Cfg SPI RSTb_err_FS=1; WD_CNT_refresh=6) INCR = WD error counter = WD_CNT_error[1:0] | WD refresh NOK during INIT | IO23_ERR |UV/OV | FS0b_shorttovdd | SPI DED | Reset by SPI | External reset 7 consecutive WD Refresh OK (7 = WD_CNT_refresh + 1) 0 POR or from LPOFF mode INCR/gotoFS Active FS0 7 consecutive WD Refresh OK 1 INCR gotoFS = IO01/23/45_ERR | UV/OV | ABIST_fail | SPI DED | RSTb_short2hi Active FS0 Turn OFF regulators 2 RSTb asserted for 8 seconds Figure 17. RSTB Error Counter(RSTb_err_FS = 1) 6.7.4 RST Error Counter at Start-up or Resuming from LPOFF Mode At start-up or when resuming from LPOFF mode the reset error counter starts at level 1 and FS0B is asserted low. To remove activation of FS0B, the RST error counter must go back to value “0” (seven consecutive good watchdog refresh decreases the reset error counter down to 0) and a right command is sent to FS_OUT register (Figure 20). 1st WD refresh OK after INIT phase. Start of the WD window New fully OPEN window of 256ms WD window OK WD error counter NOK 0 NOK 2 NOK OK 4 Reset error counter 3 OK 5 NOK 4 6 1 RSTb delay time RSTb WD Refresh counter 0 1 0 0 1 0 1 0 Figure 18. Example of WD Operation Generating a Reset (WD_error_cnt = 6) 33907_8 40 Analog Integrated Circuit Device Data Freescale Semiconductor New fully OPEN window of 256ms WD window OK NOK WD error counter 4 Reset error counter 1 OK OK OK OK OK OK OK 0 6 2 RSTb 1 RSTb delay time WD Refresh counter 1 0 2 3 4 6 5 0 1 Figure 19. Example of WD Operation Leading a Decrement of the Reset Error Counter (WD_resfresh_cnt = 6) # WD refresh counter max value +1 consecutive WD answers OK FS_OUT write OK Reset error counter RST_ERR_CNT 1 RSTb FS0b # WD refresh counter max value +1 consecutive WD answers OK WD error counter =6 WD error counter =6 0 1 WD error counter =6 2 FS_OUT write OK 3 2 1 0 Reset delay Output stage ON OFF ON OFF Figure 20. Reset Error Counter and FS0B DEACTIVATION Sequence (RSTB_err_FS = 0 & WD_CNT_error1:0 = 6) 6.7.5 Fail-safe Output (FS0B) De-activation When the fail-safe output FS0B is asserted low by the device due to a fault, some conditions must be validated before allowing the FS0B pin to be de-activated by the device. These conditions are: • Fault is removed • Reset error counter must be at “0” • FS_OUT register must be filled with the right value. 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 41 6.7.6 Faults Triggering FS0B Activation The activation of the FS0B is clearly dependent on the product configuration, but the following items can be settled: • IO_01/IO_23/IO_45 error detection • Undervoltage • Overvoltage • Analog BIST fail (not configurable) • SPI DED (not configurable) • RSTB shorted to high (not configurable) • RSTB error counter level 6.7.7 SPI DED Some SPI registers affect some safety critical aspects of the fail-safe functions, and thus are required to be protected against SEU (Single Event Upset). Only fail-safe registers are concerned. During INIT FS mode, access to fail-safe registers for product configuration is open. Then once the INIT FS phase is over, the Hamming circuitry is activated to protect registers content. At this stage, if there is 1 single bit flip, the detection is made due to hamming code, and the error is corrected automatically (fully transparent for the user), and a flag is sent. If there are two errors (DED - Dual Error Detection), the detection is made due to hamming code but detected errors cannot be corrected. Flag is sent, RSTB and FS0B are activated. 6.7.8 FS_OUT Register When fault is removed and reset error counter changes back to level “0”, a right word must be filled in the FS_OUT register. The value is dependant on the current WD_LFSR. LSB and MSB must be swapped and negative operation per bit must be applied. WD_LFSR_7:0= b7 b6 b5 b4 b3 b2 b1 b0 FS_OUT_7:0 = b0 b1 b2 b3 b4 b5 b6 b7 Figure 21. FS_OUT Register Based on LFSR Value 33907_8 42 Analog Integrated Circuit Device Data Freescale Semiconductor 6.7.9 INPUT VOLTAGE RANGE Due to the flexibility of the pre-regulator, the device can cover a wide battery input voltage range. However, a more standard voltage range can still be covered using only the Buck configuration. Vsup Buck-Boost Buck only No operation Risk of damage No operation Risk of damage 40V Extended voltage range Extended voltage range Potential Vpre thermal limitation Potential Vpre thermal limitation 28V Extended voltage range Extended voltage range Amux limitation Amux limitation 19V Normal voltage range Normal voltage range Vsup_uv_7 Extended voltage range 6V Extended voltage range Vpre output current limitation 4.6v Vpre output current limitation 2.7V No operation No operation Figure 22. Input Voltage Range • VSUP > 28 V : Potential VPRE thermal limitation RDSON, Current limitation and Overcurrent detection are specified for VSUP < 28 V • VSUP < 19 V : Mux_out limitation IO_0 and IO_1 maximum analog input voltage range is 19 V Internal 2.5 V reference voltage accuracy degraded • Buck only, VSUP < VSUP_UV_7 : CAN communication is guaranteed for VSUP > 6.0 V For VCCA and VAUX 5.0 V configuration, under voltage triggers at low VSUP (refer to VCCA_UV_5 and VAUX_UV_5) 6.7.10 Vpre Voltage Pre-regulator A highly flexible SMPS pre-regulator is implemented in the 33907_8. Depending on the input voltage requirement, the device can be configured as “Non-inverting Buck-boost converter” (Figure 24) or “Standard Buck converter” (Figure 23). An external low side MOSFET (N-type) is required to operate in “Non-inverting Buck-boost converter”. The connection of the external MOSFET is detected automatically during the start-up phase. The converter operates in Current Control mode in any configuration. The high side switching MOSFET is integrated to make the current control easier. The PWM frequency is fixed at 440 kHz typical. The compensation network is fully integrated. The output voltage (VPRE) is regulated between 6.0 V and 7.0 V. 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 43 L_Vpre ESR cap. <10 m PGND PGND PGND Cout_Vpre4 Cout_Vpre3 Cout_Vpre2 Cout_Vpre1 D_Vpre Rsunb_Vpre Csnub_Vpre Cboot_pre ESR cap. <100 m PGND PGND PGND PGND Vpre Gate_LS Boots_pre SW_pre2 SW_pre1 Figure 23. Pre-regulator: Buck configuration PGND PGND Cout_Vpre4 ESR cap. <10m Cout_Vpre3 Cout_Vpre1 Cout_Vpre2 ESR cap. <100m D_BB LS_BB D_Vpre Cboot_pre Rsunb_Vpre Csnub_Vpre L_Vpre PGND PGND PGND PGND Optional PGND Vpre Gate_LS Boots_pre SW_pre2 SW_pre1 Figure 24. Pre-regulator: Buck Boost configuration Transition between buck mode and boost mode is based on hysteresis (Figure 25). D (%) D buck D boost Vpre (V) 100 6.5 50 hysteresis 66 33 25 0 7.5 12 18 24 Vin (V) Figure 25. Transition between Buck and Boost 33907_8 44 Analog Integrated Circuit Device Data Freescale Semiconductor Vsns_UV Vsup_UV_5 Vsup_UV_L_B Vbattery 0V Vsup Buck_Boost Mask Boost Buck Buck Boost Vpre_EN Vpre Vcore Vcore_UV INTB RSTB RST delay time Figure 26. Buck Configuration Power-up and Power-down VSUP_UV_7 VSUP_UV_5 VSUP_UV_L Vbattery 0V Vsup Buck_Boost Mask Buck Boost Buck Boost Vpre_EN Vpre Vcore VCORE_FB_UV * ((R3+R4)/R4) INTB RSTB Figure 27. Buck Boost Configuration Power-up and Power-down 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 45 Vsense Vsup VSNS_UV VSUP_UV_L_B Buck_Boost Mask Buck Vpre_EN Vpre Vcore VCORE_FB_UV * ((R3+R4)/R4) INTB RSTB Figure 28. Behavior During a Cranking (Buck Configuration) Vsup Vsup_UV_7 VSUP_UV_L Buck_Boost Mask Buck Buck Boost Boost Vpre_EN Vpre Vcore VCORE_FB_UV * ((R3+R4)/R4) INTB RSTB Figure 29. Behavior During a Cranking (Buck Boost Configuration) 33907_8 46 Analog Integrated Circuit Device Data Freescale Semiconductor In order to improve the efficiency, the converter switches automatically to burst mode in light load condition. Moreover, the battery voltage sensing (VSENSE) is used to manage the load dump condition. An input power feed forward function is also implemented to minimize the switching losses during the load dump. VSUP_IPFF Vsup Ipk envelop IPFF Vpre_fsw 440 kHz 220 KHz 440 kHz Figure 30. Input Power Feed Forward Principle 6.7.11 Vcore Voltage Regulator This voltage regulator is a step-down DC-DC converter operating in Voltage Control mode. The switching MOSFET is integrated. The PWM frequency is fixed at 2.4 MHz typical. The high side MOSFET is integrated in the device. The output voltage is configured for 1.2 V and 3.3 V, due to an external resistor divider connected between VCORE and the feedback pin (FB-CORE) (Figure 34). The expected accuracy is 2.0%. The output current is up to 0.8 A for the 33907 and 1.5 A for the 33908 device. The stability of the overall converter is done externally by the pin COMP_CORE. In order to improve the efficiency, the converter switches automatically in burst mode in light load condition. 6.7.12 Charge Pump and Bootstrap Both switching MOSFETs of VPRE and VCORE SMPS are driven by external bootstrap capacitors. Additionally, a charge pump is implemented to ensure 100% duty cycle for both converters. Each converter uses a 100 nF external capacitor minimum to operate properly. 6.7.13 VCCA Voltage Regulator VCCA is a linear voltage regulator mainly dedicated to supply the MCU I/Os, especially the ADC. The output voltage is selectable at 5.0 V or 3.3 V. Since this output voltage can be used to supply MCU IOs, the output voltage selection is done using an external resistor connected to the SELECT pin and ground if VAUX is used. When VAUX is not used, the resistor is connected between the SELECT pin and VPRE. The expected accuracy is +/- 1% for 5 V configuration and +/- 1.5% for 3.3 V configuration with an output current capability at 100 mA. An external PNP transistor is used to boost the current capability up to 300 mA. When an external PNP is used, the connection is detected automatically during the start-up sequence of the PowerSBC. In such condition, the internal pass transistor is switched OFF and all the current is driven through the external PNP to reduce the internal power dissipation. The output voltage accuracy with an external PNP is reduced to 3.0%. The VCCA output voltage is used as a reference for the Auxiliary voltage supply (VAUX) when used as sensor supply output. 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 47 6.7.14 VAUX Voltage Regulator VAUX is a highly flexible linear voltage regulator either as an auxiliary supply dedicated to additional device in the ECU or as a sensor supply (i.e. outside the ECU). As an auxiliary supply, the output voltage is selectable between 5.0 V, 3.3 V. Since this voltage rail can be used to supply IOs, the selection is done with an external resistor connected between the SELECT pin and ground. In such case, the expected accuracy is 3.0%. The output current capability is up to 300 mA. An external PNP transistor must be used (no internal current capability). As a sensor supply rail, the output voltage is selectable between 5.0 V and 3.3 V. Moreover VCCA can be used as reference for the sensor supply used as tracker. The selection is also done during the INIT phase and secured. The tracking accuracy is expected to be 15 mV. 6.8 Startup Sequence In order to provide a safe and well known startup sequence, the 33907_8 includes an undervoltage lock-out. This undervoltage lock-out is only applicable when the device is under a Power-On-Reset condition, which means the initial condition is VSUP < VSUP_UV_L (i.e. below 2.7 V max). In all the other conditions (i.e. LPOFF), the device is able to operate (and therefore to (re)start) down to VSUP_UV_L. The other different voltage rails automatically start, as described in the following figure. Vsup_uv_5 Vsup Vint_2.5 120µs Vpre_EN Vpre_UV 1mS Vpre Vcore / Vaux / Vcca INTB INIT Initial RESET Softstart Vregs Select Pin config Detection Softstart Vpre LS detect UV Lock-out RSTB ~16ms Figure 31. Start-up Scheme 33907_8 48 Analog Integrated Circuit Device Data Freescale Semiconductor The final value of VAUX and VCCA depends on the hardware configuration (resistor values on the SELECT pin). It takes around 13 ms to release the RSTB. RSTB can be pulled low after those 13 ms by the MCU, if it is not ready to run after power up. 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 49 7 Serial Peripheral Interface 7.1 High Level Overview 7.1.1 SPI The device is using a 16 bits SPI, with the following arrangement: MOSI, Master Out Slave In bits: • Bit 15 read/write • Bit 14 Main or fail-safe register target • bit 13 to 9 (A4 to A0) to select the register address. Bit 8 is a parity bit in write mode, Next bit (=0) in read mode. • bit7 to 0 (D7 to D0): control bits MISO, Master IN Slave Out bits: • bits 15 to 8 (S15 to S8) are device status bits • bits 7 to 0(Do7 to Do0) are either extended device status bits, device internal control register content or device flags. Figure 32 is an overview of the SPI implementation. 7.1.2 Parity Bit 8 Calculation: The parity is used for write to register command (bit 15,14 = 01). It is calculated based on the number of logic ones contained in bits 15-9,7-0 sequence (this is the whole 16 bits of the write command except bit 8). Bit 8 must be set to 0 if the number of 1 is odd. Bit 8 must be set to 1 if the number of 1 is even. 7.1.3 Device Status on MISO When a write operation is performed to store data or control bit into the device, MISO pin reports a 16 bit fixed device status composed of 2 bytes: Device Fixed Status (bits 15 to 8) + extended Device Status (bits 7 to 0). In a read operation, MISO reports the fixed device status (bits 15 to 8), and the next 8 bits are content of the selected register. A standard serial peripheral interface (SPI) is integrated to allow bi-directional communication between the 33907_8 and the MCU. The SPI is used for configuration and diagnostic purposes. 33907_8 50 Analog Integrated Circuit Device Data Freescale Semiconductor Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 MOSI R/W M/FS A4 A2 A3 A1 A0 register address MISO S15 S14 S13 S11 S12 Bit 8 Bit 7 Bit 6 P D7 Bit 5 D6 D5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D4 D2 D1 D0 Do2 Do1 Do0 Parity S9 S10 D3 data S8 Do7 Do6 Do5 Do4 Do3 Extended Device Status, Register Control bits or Device Flags Device Status CSb CSb active low. Must be raised at end of 16 clocks, for write commands, MOSI bits [15] = [1]. SCLK SCLK signal is low outside of CSB active MOSI Don’t care MISO Tri state C1 S15 C0 D0 S14 Do0 Don’t care Tri state MOSI and MISO data changed at SCLK rising edge and sampled at falling edge. Msb first. MISO tri state outside of CSB active SPI wave form, and signals polarity Figure 32. SPI Overview The device contains several registers. Their address is coded on 7 bits (bits 15 to 9). Each register controls or reports part of the device function. Data can be written to the register, to control the device operation or set default value or behavior. Every register can also be read back in order to ensure that its content (default setting or value previously written) is correct. 7.1.4 Register Description Although the minimum time between two NCS low sequences is defined by tONNCS (Figure 33), two consecutive accesses to the fail-safe registers must be done with a 3.5 µs minimum NCS high time in between. Although the minimum time between two fail-safe registers accesses is 3.5 µs, some SPI accesses to the main registers can be done in between (Figure 34) 7.2 Detail Operation MOSI bi t15 R/W bit 14 M / FS bit 13 A4 bit 12 A3 bit 11 A2 bit 10 A1 bit 9 A0 bit 8 P bit 7 D7 bit 6 D6 bit 5 D5 bit4 D4 bit3 D3 bit2 D2 bit1 D1 bi t0 D0 bi t15 SP I_G bit 14 WU bit 13 CAN_G bit 12 RES ERV ED bit 11 IO_G bit 10 Vpre_G bit 9 V co re_G bit 8 Vothers_G bit 7 bit 6 bit 5 bit4 bit3 bit2 bit1 bi t0 MIS O Bits15:8 always sen t by Main digi tal Extended diagnostic: either sent by Main or Fail Safe based on bi ts15:9 on MOSI Figure 33. MOSI / MISO SPI Command Organization 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 51 Table 10. MOSI Bits Description R/W M / FS A4:0 Description Set if it is a READ or WRITE Command 0 READ 1 WRITE Description Split the addresses between Fail-safe State machine and Main Logic 0 Main 1 Fail-safe Description 0 Set the address to Read or Write See Register Mapping 1 P D7:0 Description Parity bit (only use in Write mode). Set to 0 in Read mode 0 Number of “1” (bit15:9 and bit 7:0) is odd 1 Number of “1” (bit15:9) and bit 7:0) is even Description 0 Data in Write mode. Shall be set to 00h in Read mode See register details 1 Table 11. MISO Bits Description SPI_G Description 0 NO Failure 1 Failure Reset Condition WU Description 1 WU event Description Power On Reset / When initial event cleared on read Report a CAN event (Diagnostic) 0 NO event 1 CAN event Description Power On Reset / When initial event cleared on read Report a change in IOs state 0 NO IO transition 1 IO transition Reset Condition VPRE_G Report a wake-up event. Logical OR of ALL wake-up sources NO WU event Reset Condition IO_G Power On Reset / When initial event cleared on read 0 Reset Condition CAN_G Report an error in the SPI communication Description Power On Reset / When initial event cleared on Read Report an event from Vpre-regulator and battery monitoring (Status change or failure) 0 NO event 1 Event occurred Reset Condition Power On Reset / When initial event cleared on Read 33907_8 52 Analog Integrated Circuit Device Data Freescale Semiconductor Table 11. MISO Bits Description (continued) VCORE_G Report an event from VCORE regulator (Status change or failure) Description 0 NO event 1 Event occurred Power On Reset / When initial event cleared on Read Reset Condition VOTHERS_G Report an event from VCCA, VAUX, or VCAN regulators (Status change or failure) Description 0 NO event 1 Event occurred Power On Reset / When initial event cleared on Read Reset Condition 7.2.1 Register Address Table Table 12 is a list of device registers and addresses coded in bits 13 to 9 in MOSI for main logic. Table 12. Register Mapping of Main Logic Address Register FS/M A4 A3 A2 A1 A0 Hex Write description Table Ref NOT USED 0 0 0 0 0 0 #0(00h) N/A N/A INIT Vreg 1 0 0 0 0 0 1 #1(01h) Write during INIT phase then read only Table 15 INIT Vreg2 0 0 0 0 1 0 #2(02h) Write during INIT phase then read only Table 17 INIT CAN 0 0 0 0 1 1 #3(03h) Write during INIT phase then read only Table 19 INIT IO_WU1 0 0 0 1 0 0 #4(04h) Write during INIT phase then read only Table 21 INIT IO_WU2 0 0 0 1 0 1 #5(05h) Write during INIT phase then read only Table 23 INIT INT 0 0 0 1 1 0 #6(06h) Write during INIT phase then read only Table 25 NOT USED 0 0 0 1 1 1 #7(07h) N/A N/A HW Config 0 0 1 0 0 0 #8(08h) Read only Table 27 WU source 0 0 1 0 0 1 #9(09h) Read only Table 29 NOT USED 0 0 1 0 1 0 #10(0Ah) N/A N/A IO_input 0 0 1 0 1 1 #11(0Bh) Read only Table 31 Status Vreg#1 0 0 1 1 0 0 #12(0Ch) Read only Table 33 Status Vreg#2 0 0 1 1 0 1 #13(0Dh) Read only Table 35 Diag Vreg#1 0 0 1 1 1 0 #14(0Eh) Read only Table 37 Diag Vreg#2 0 0 1 1 1 1 #15(0Fh) Read only Table 39 Diag Vreg#3 0 1 0 0 0 0 #16(10h) Read only Table 41 Diag CAN1 0 1 0 0 0 1 #17(11h) Read only Table 43 Diag CAN2 0 1 0 0 1 0 #18(12h) Read only Table 45 Diag SPI 0 1 0 0 1 1 #19(13h) Read only Table 48 NOT USED 0 1 0 1 0 0 #20(14h) N/A N/A 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 53 Table 12. Register Mapping of Main Logic Address Register FS/M A4 A3 A2 A1 A0 Hex Write description Table Ref MODE 0 1 0 1 0 1 #21(15h) Write during Normal and Read Table 50 Vreg_mode 0 1 0 1 1 0 #22(16h) Write during Normal and Read Table 52 IO_OUT/AMUX 0 1 0 1 1 1 #23(17h) Write during Normal and Read Table 54 CAN Mode 0 1 1 0 0 0 #24(18h) Write during Normal and Read Table 56 CAN Mode 2 0 1 1 0 0 1 #25(19h) Write during Normal and Read Table 58 Table 13 is a list of device registers and addresses coded in bits 13 to 9 in MOSI for Main logic Table 13. Register Mapping of Fail-safe Logic Address Register FS/M A4 A3 A2 A1 A0 Hex Write description Table Ref INIT Supervisor#1 1 0 0 0 0 1 #33(21h) Write during INIT phase then Read only Table 60 INIT Supervisor#2 1 0 0 0 1 0 #34(22h) Write during INIT phase then Read only Table 62 INIT Supervisor#3 1 0 0 0 1 1 #35(23h) Write during INIT phase then Read only Table 64 INIT FSSM#1 1 0 0 1 0 0 #36(24h) Write during INIT phase then Read only Table 66 INIT FSSM#2 1 0 0 1 0 1 #37(25h) Write during INIT phase then Read only Table 68 WD_Window 1 0 0 1 1 0 #38(26h) Write (No restriction) and Read Table 70 WD_LFSR 1 0 0 1 1 1 #39(27h) Write (No restriction) and Read Table 72 WD_answer 1 0 1 0 0 0 #40(28h) Write (No restriction) and Read Table 74 FS_OUT 1 0 1 0 0 1 #41(29h) Write (No restriction) Table 76 RSTb request 1 0 1 0 1 0 #42(2Ah) Write (No restriction) Table 78 INIT WD 1 0 1 0 1 1 #43(2Bh) Write during INIT phase then Read only Table 80 Diag FS1 1 0 1 1 0 0 #44(2Ch) Read only Table 82 WD_Counter 1 0 1 1 0 1 #45(2Dh) Read only Table 84 Diag_FS2 1 0 1 1 1 0 #46(2Eh) Read only Table 86 7.2.2 Secured SPI Command Some SPI commands must be secured to avoid unwanted change of the critical bits. In the fail-safe machine and in the main state machine, the secured bits are calculated from the data bits sent as follows: Table 14. Secured SPI • • • • Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Data 3 Data 2 Data 1 Data 0 Secure 3 Secure2 Secure 1 Secure 0 Secure 3 = NOT(Bit5) Secure 2 = NOT(Bit4) Secure 1 = Bit7 Secure 0 = Bit6 33907_8 54 Analog Integrated Circuit Device Data Freescale Semiconductor 7.3 Detail of Register Mapping Default value of the reserved bit must be "0". 7.3.1 Init VREG 1 Table 15. INIT VREG1 Register Configuration Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 MOSI 1 0 0 0 0 0 1 P 0 MISO SPI_G WU CAN_G Reserve d IO_G Vpre_G 0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 MOSI 0 0 0 0 0 0 1 0 0 0 MISO SPI_G WU CAN_G Reserve d IO_G Vpre_G 0 1 Vcore_ Vothers G _G bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reserv Vpre_D Ipff_DIS ed IS 0 0 Reserv ed 0 Reserv Vpre_D Ipff_DIS ed IS 0 0 Reserv ed 0 bit4 bit3 bit2 bit1 bit0 0 0 0 0 0 0 Ipff_DIS Vpre_D IS 0 0 1 0 bit3 bit2 bit1 bit0 Read Vcore_ Vothers G _G Table 16. Description and Configuration of the Bits (Default value in blue) IPFF_DIS Description DISABLE the input Power Feed Forward (IPFF) function of Vpre 0 ENABLED 1 DISABLED Reset condition Power On Reset Vpre_DIS Description DISABLE Vpre SMPS (in all mode). 0 ENABLED 1 DISABLED Reset condition Power On Reset 7.3.2 Init Vreg 2 Table 17. INIT VREG2 Register Configuration Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 MOSI 1 0 0 0 0 1 0 P 0 Tcca_li m_off Icca_li m 0 reserve Taux_li Vaux_tr reserve d m_off k_EN d MISO SPI_G WU IO_G Vpre_G 0 Tcca_li m_off Icca_li m 0 reserve Taux_li Vaux_tr reserve d m_off k_EN d CAN_G Reserved Vcore_ Vothers G _G 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 55 Table 17. INIT VREG2 Register Configuration Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU IO_G Vpre_G 0 Tcca_li m_off Icca_li m 0 CAN_G Reserved Vcore_ Vothers G _G reserve Taux_li Vaux_tr reserve d m_off k_EN d Table 18. INIT VREG2. Description and Configuration of the Bits (Default value in blue) Tcca_lim_off Icca_lim Taux_lim_off Vaux_trk_EN 7.3.3 Description Configure the current limitation duration before regulator is switched off. Only used for external PNP 0 10 ms 1 50 ms Reset condition Power On Reset Description Configure the current limitation threshold. Only available for external PNP 0 Icca_lim_in 1 Icca_lim_out Reset condition Power On Reset Description Configure the current limitation duration before regulator is switched off. Only used for external PNP 0 10 ms 1 50 ms Reset condition Power On Reset Description Configure Vaux regulator as a tracker 0 No tracking. HW configuration is used 1 Tracking enabled Reset condition Power On Reset Init CAN Table 19. INIT CAN Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 MOSI 1 0 0 0 0 1 1 P 0 CAN_w Reserv CAN_T CAN_w reserved reserved reserved u_conf ed OY u_TO MISO SPI_G WU CAN_G Reserv ed IO_G Vpre_G 0 CAN_w Reserv CAN_T CAN_w reserved reserved reserved u_conf ed OY u_TO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 Vcore_ Vothers G _G bit6 bit5 bit4 bit3 bit2 bit1 bit0 Read MOSI 33907_8 56 Analog Integrated Circuit Device Data Freescale Semiconductor Table 19. INIT CAN Register Description MISO SPI_G WU CAN_G Reserv ed IO_G Vpre_G Vcore_ Vothers G _G 0 CAN_w u_conf 0 CAN_T CAN_w reserved reserved reserved OY u_TO Table 20. INIT CAN. Description and Configuration of the Bits (Default value in blue) CAN_wu_conf Description Define the CAN wake-up mechanism 0 3 dominant pulses 1 Single dominant pulse Reset condition Power On Reset CAN_TOY Description Configure the CAN block to be compliant with TOYOTA specification 0 Standard CAN 1 Toyota compliance Reset condition Power On Reset CAN_wu_to Description Define the CAN wake-up time-out (in case of CAN_wu_conf=0) 0 120 µs 1 360 µs Reset condition Power On Reset 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 57 7.3.4 INIT IO_WU1 Table 21. INIT IO_WU1 Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 1 0 0 0 1 0 0 P MISO SPI_G WU CAN_G Reserv ed IO_G Vpre_G bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_G Reserv ed IO_G Vpre_G WU_0_ WU_0_ WU_1_ WU_1_ WU_2_ WU_2_ INT_inh INT_inh 1 0 1 0 1 0 _IO_1 _IO_0 Vcore_ Vothers WU_0_ WU_0_ WU_1_ WU_1_ WU_2_ INT_inh INT_inh WU-2-1 G _G 1 0 1 0 0 _IO_1 _IO_0 Read Vcore_ Vothers WU_0_ WU_0_ WU_1_ WU_1_ WU_2_ INT_inh INT_inh WU-2-1 G _G 1 0 1 0 0 _IO_1 _IO_0 Table 22. INIT IO_WU1. Description and Configuration of the Bits (Default value in blue) WU_0_1:0 Description Wake-up configuration for IO_0 00 NO wake-up capability 01 Wake-up on rising edge only 10 Wake-up on falling edge only 11 Wake-up on any edge Reset condition Power On Reset WU_1_1:0 Description Wake-up configuration for IO_1 00 NO wake-up capability 01 Wake-up on rising edge only 10 Wake-up on falling edge only 11 Wake-up on any edge Reset condition Power On Reset WU_2_1:0 Description Wake-up configuration for IO_2 00 NO wake-up capability 01 Wake-up on rising edge only 10 Wake-up on falling edge only 11 Wake-up on any edge Reset condition Power On Reset INT_inh_IO_1 Description Inhibit the INT pulse for IO_1. IO_1 masked in IO_G. Avoid INT when used in FS 0 INT NOT masked 1 INT masked Reset condition Power On Reset 33907_8 58 Analog Integrated Circuit Device Data Freescale Semiconductor Table 22. INIT IO_WU1. Description and Configuration of the Bits (Default value in blue) (continued) INT_inh_IO_0 Description Inhibit the INT pulse for IO_0. IO_0 masked in IO_G. Avoid INT when used in FS 0 INT NOT masked 1 INT masked Reset condition Power On Reset 7.3.5 INIT IO_WU2 Table 23. INIT IO_WU2 Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 0 0 0 1 0 1 P MISO SPI_G WU IO_G Vpre_G bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU IO_G Vpre_G CAN_G Reserved bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 WU_3_ WU_3_ WU_4_ WU_4_ WU_5_ WU_5_ INT_inh INT_inh 1 0 1 0 1 0 _IO_23 _IO_45 Vcore_ Vothers WU_3_ WU_3_ WU_4_ WU_4_ WU_5_ WU_5_ INT_inh INT_inh G _G 1 0 1 0 1 0 _IO_23 _IO_45 Read CAN_G Reserved Vcore_ Vothers WU_3_ WU_3_ WU_4_ WU_4_ WU_5_ WU_5_ INT_inh INT_inh G _G 1 0 1 0 1 0 _IO_23 _IO_45 Table 24. INIT IO_WU2. Description and Configuration of the Bits (Default value in blue) WU_3_1:0 Description Wake-up configuration for IO_3 00 NO wake-up capability 01 Wake-up on rising edge only 10 Wake-up on falling edge only 11 Wake-up on any edge Reset condition Power On Reset WU_4_1:0 Description Wake-up configuration for IO_4 00 NO wake-up capability 01 Wake-up on rising edge only 10 Wake-up on falling edge only 11 Wake-up on any edge Reset condition Power On Reset 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 59 Table 24. INIT IO_WU2. Description and Configuration of the Bits (Default value in blue) (continued) WU_5_1:0 Description Wake-up configuration for IO_5 00 NO wake-up capability 01 Wake-up on rising edge only 10 Wake-up on falling edge only 11 Wake-up on any edge Reset condition Power On Reset INT_inh_IO_45 Description Inhibit the INT pulse for IO_4 & IO_5. IO_4 & IO_5 masked in IO_G. Avoid INT when used in FS 0 INT NOT masked 1 INT masked Reset condition Power On Reset INT_inh_IO_23 Description Inhibit the INT pulse for IO_2 & IO_3. IO_2 & IO_3 masked in IO_G. Avoid INT when used in FS 0 INT NOT masked 1 INT masked Reset condition Power On Reset 7.3.6 INIT INT Table 25. INIT INT Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 0 0 0 1 1 0 P MISO SPI_G WU IO_G Vpre_G bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU IO_G Vpre_G CAN_G Reserved bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 INT_inh INT_dur reserve INT_inh INT_inh INT_inh INT_inh reserve _Vother ation d _all _Vsns _Vpre _Vcore d s Vcore_ Vothers INT_dur G _G ation 0 INT_inh INT_inh INT_inh INT_inh INT_inh _Vother _all _Vsns _Vpre _Vcore s 0 Read CAN_G Reserved Vcore_ Vothers INT_dur G _G ation 0 INT_inh INT_inh INT_inh INT_inh INT_inh _Vother _all _Vsns _Vpre _Vcore s 0 Table 26. INIT INT. Description and Configuration of the Bits (Default value in blue) INT_duration Description Define the duration of the INTerrupt pulse 0 100 µs 1 25 µs Reset condition Power On Reset 33907_8 60 Analog Integrated Circuit Device Data Freescale Semiconductor Table 26. INIT INT. Description and Configuration of the Bits (Default value in blue) (continued) INT_inh_all Description Inhibit ALL the INT 0 All INT sources 1 inhibit ALL INT Reset condition Power On Reset INT_inh_Vsns Description Inhibit the INT for VSNS_UV 0 All INT sources 1 inhibit VSNS_UV Reset condition Power On Reset INT_inh_Vpre Description Inhibit the INT for Vpre status event (cf. register status Vreg1) 0 All INT sources 1 Vpre status changed INHIBITED Reset condition Power On Reset INT_inh_Vcore Description Inhibit the INT for Vcore status event (cf. register status Vreg2) 0 All INT sources 1 Vcore status changed INHIBITED Reset condition Power On Reset INT_inh_Vothers Inhibit the INT for VCCA / VAUX and VCAN status event (cf. register status Vreg2) Description 0 All INT sources 1 VCCA / VAUX / VCAN status changed INHIBITED Reset condition Power On Reset 7.3.7 HW Config Table 27. HW Config Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU x 0 DBG CAN_G Reserved IO_G Vpre_G Vcore_ Vothers LS_det G _G ect Vaux not used Vcca_P Vcca_H Vaux_H W W NP_det ect Table 28. HW Config. Description and Configuration of the Bits (Default value in blue) LS_detect Vaux not used Description Report the hardware configuration of Vpre (Buck only or Buck-Boost) 0 Buck-Boost 1 Buck only Reset condition Power On Reset / Refresh after LPOFF Description Report if Vaux is used 0 Vaux is used (external PNP is assumed to be connected, Vaux can be switched OFF/ON through SPI) 1 Vaux is not used Reset condition Power On Reset / Refresh after LPOFF 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 61 Table 28. HW Config. Description and Configuration of the Bits (Default value in blue) (continued) Vcca_PNP_detect Vcca_HW Vaux_HW 1:0 DBG Description Report the connection of an external PNP on Vcca 0 External PNP connected 1 Internal MOSFET Reset condition Power On Reset / Refresh after LPOFF Description Report the hardware configuration for Vcca 0 3.3 V 1 5V Reset condition Power On Reset / Refresh after LPOFF Description Report the hardware configuration for Vaux 0 5V 1 3.3 V Reset condition Power On Reset / Refresh after LPOFF Description Report the configuration of the DEBUG mode 0 Normal operation 1 DEBUG mode selected Reset condition Power On Reset / Refresh after LPOFF 33907_8 62 Analog Integrated Circuit Device Data Freescale Semiconductor WU SOURCE Table 29. WU SOURCE Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU IO_5_ WU IO_4_ WU IO_3_ WU IO_2_ WU IO_1_ WU IO_0_ WU Vreg_ WU Phy_W U CAN_G Reserved IO_G Vpre_G Vcore_ Vothers G _G Table 30. WU source. Description and Configuration of the Bits (Default value in blue) IO_5_WU IO_4_WU IO_3_WU IO_2_WU IO_1_WU IO_0_WU Phy_WU Description Report a wake-up event from IO_5 0 No Wake-up 1 WU event detected Reset condition Power On Reset / Read Description Report a wake-up event from IO_4 0 No Wake-up 1 WU event detected Reset condition Power On Reset / Read Description Report a wake-up event from IO_3 0 No Wake-up 1 WU event detected Reset condition Power On Reset / Read Description Report a wake-up event from IO_2 0 No Wake-up 1 WU event detected Reset condition Power On Reset / Read Description Report a wake-up event from IO_1 0 No Wake-up 1 WU event detected Reset condition Power On Reset / Read Description Report a wake-up event from IO_0 0 No Wake-up 1 WU event detected Reset condition Power On Reset / Read Description Report a wake-up event from CAN 0 No Wake-up 1 WU event detected Reset condition Power On Reset/ Read CAN_wu 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 63 IO INPUT Table 31. IO INPUT Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU IO_5 IO_4 0 IO_3 IO_2 0 IO_1 IO_0 CAN_G Reserved IO_G Vpre_G Vcore_ Vothers G _G Table 32. IO input. Description and Configuration of the Bits IO_5 IO_4 IO_3 IO_2 IO_1 IO_0 Description Report IO_5 digital state in Normal mode. No update in LPOFF mode since wake-up features available 0 Low 1 High Reset condition Power On Reset Description Report IO_4 digital state in Normal mode. No update in LPOFF mode since wake-up features available 0 Low 1 High Reset condition Power On Reset Description Report IO_3 digital state in Normal mode. No update in LPOFF mode since wake-up features available 0 Low 1 High Reset condition Power On Reset Description Report IO_2 digital state in Normal mode. No update in LPOFF mode since wake-up features available 0 Low 1 High Reset condition Power On Reset Description Report IO_1 digital state in Normal mode. No update in LPOFF mode since wake-up features available 0 Low 1 High Reset condition Power On Reset Description Report IO_0 digital state in Normal mode. No update in LPOFF mode since wake-up features available 0 Low 1 High Reset condition Power On Reset 33907_8 64 Analog Integrated Circuit Device Data Freescale Semiconductor STATUS VREG1 Table 33. STATUS VREG1 Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 MOSI 0 0 MISO SPI_ G WU 0 1 1 CAN Res IO_ _G erve G d 0 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 0 0 0 0 0 0 0 0 0 0 Vpre_ Vcore Vothers_ G _G G IpFF Ilim_pr Twarm_ BoB Vpre_sta e pre te Table 34. Status Vreg1. Description and Configuration of the Bits (Default value in blue) IpFF Ilim_pre Twarm_pre BoB Vpre_state Description Input Power Feed Forward 0 Normal Operation 1 Ipff mode activated Reset condition Power On Reset / Read Description Report a current limitation condition on Vpre 0 No current limitation (Ipre_pk < Ipre_lim) 1 Current limitation (Ipre_pk > Ipre_lim) Reset condition Power On Reset / Read Description Report a thermal warning from Vpre 0 No thermal warning (Tj < Twarm_pre) 1 Thermal warning (Tj > Twarm_pre) Reset condition Power On Reset / Read Description Report a running mode of Vpre 0 Buck 1 Boost Reset condition Power On Reset Description Report the activation state of Vpre SMPS 0 SMPS OFF 1 SMPS ON Reset condition Power On Reset 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 65 STATUS VREG2 Table 35. STATUS VREG2 Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU Vcore_ state Twarm _cca CAN_G Reserved IO_G Vpre_G Vcore_ Vothers Ilim_cor Twarm G _G e _core Ilim_cc Ilim_au Ilim_ca a x n 0 Table 36. Status Vreg2. Description and Configuration of the Bits (Default value in blue) Ilim_core Twarm_core Vcore_state Twarm_cca Ilim_cca Ilim_aux Ilim_can Description Report a current limitation condition on Vcore 0 No current limitation (Icore_pk < Icore_lim) 1 Current limitation (Icore_pk > Icore_lim) Reset condition Power On Reset / Read Description Report a thermal warning from Vcore 0 No thermal warning (Tj < Twarm_core) 1 Thermal warning (Tj > Twarm_core) Reset condition Power On Reset / Read Description Report the activation state of Vcore SMPS 0 SMPS OFF 1 SMPS ON Reset condition Power On Reset Description Report a thermal warning from Vcca. Available only for internal pass MOSFET 0 No thermal warning (Tj < Twarm_cca) 1 Thermal warning (Tj > Twarm_cca) Reset condition Power On Reset Description Report a current limitation condition on Vcca 0 No current limitation (Icca < Icca_lim) 1 Current limitation (Icca > Icca_lim) Reset condition Power On Reset / Read Description Report a current limitation condition on Vaux 0 No current limitation (Iaux < Iaux_lim) 1 Current limitation (Iaux > Iaux_lim) Reset condition Power On Reset / Read Description Report a current limitation condition on Vcan 0 NO current limitation (Ican < Ican_lim) 1 Current limitation (Ican > Ican _lim) Reset condition Power On Reset / Read 33907_8 66 Analog Integrated Circuit Device Data Freescale Semiconductor DIAG VREG1 Table 37. DIAG VREG1 Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_G Reserved IO_G Vpre_G Vcore_ Vothers Vsns_u Vsup_u Tsd_pr Vpre_O Vpre_u Tsd_co Vcore_ Vcore_ G _G v v_7 e V v re OV uv Table 38. Diag Vreg1. Description and Configuration of the Bits (Default value in blue) Vsns_uv Vsup_uv_7 Tsd_pre Vpre_OV Vpre_UV Tsd_core Vcore_OV Vcore_UV Description Detection of Vbattery below Vsns_uv 0 Vbat > Vsns_uv 1 Vbat < Vsns_uv Reset condition Power On Reset / Read Description Detection of Vsup below Vsup_uv_7 0 Vsup > Vsup_uv_7 1 Vsup < Vsup_uv_7 Reset condition Power On Reset / Read Description Thermal shutdown of Vpre 0 No TSD (Tj < Tsd_pre) 1 TSD occurred (Tj > Tsd_pre) Reset condition Power On Reset / Read Description Vpre overvoltage detection 0 No overvoltage (Vpre < Vpre_ov) 1 Overvoltage detected (Vpre> Vpre_ov) Reset condition Power On Reset Description Vpre undervoltage detection 0 No undervoltage (Vpre > Vpre_uv) 1 Under voltage detected (Vpre < Vpre_uv) Reset condition Power On Reset / Read Description Thermal shutdown of Vcore 0 No TSD (Tj < Tsd_core) 1 TSD occurred (Tj > Tsd_core) Reset condition Power On Reset / Read Description Vcore overvoltage detection 0 No overvoltage (Vcore < Vcore_ov) 1 Overvoltage detected (Vcore > Vcore_ov) Reset condition Power On Reset / Read Description Vcore undervoltage detection 0 No undervoltage (Vcore > Vcore_uv) 1 Undervoltage (Vcore < Vcore_uv) Reset condition Power On Reset / Read 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 67 DIAG VREG2 Table 39. DIAG VREG2 Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU Vcan_u v 0 Vaux_ OV Vaux_u v CAN_G Reserved IO_G Vpre_G Vcore_ Vothers Tsd_Ca Vcan_ G _G n OV Tsd_au Ilim_au x x_off Table 40. Diag Vreg2. Description and Configuration of the Bits (Default value in blue) Tsd_can Vcan_OV Vcan_uv Tsd_aux Ilim_aux_off Vaux_OV Vaux_UV Description Thermal shutdown of Vcan 0 NO TSD (Tj < Tsd_can) 1 TSD occurred (Tj > Tsd_can) Reset condition Power On Reset / Read Description Vcan Overvoltage detection 0 No Overvoltage (Vcan < Vcan_OV) 1 Overvoltage detected (Vcan > Vcan_OV) Reset condition Power On Reset / Read Description Vcan undervoltage detection 0 No undervoltage (Vcan > Vcan_uv) 1 Undervoltage detected (Vcan < Vcan_uv) Reset condition Power On Reset / Read Description Thermal shutdown of Vaux 0 No TSD (Tj < Tsd_aux) 1 TSD occurred (Tj > Tsd_aux) Reset condition Power On Reset Description Maximum current limitation duration 0 T_limitation < Taux_lim_off 1 T_limitation >Taux_lim_off Reset condition Power On Reset / Read Description Vaux overvoltage detection 0 No overvoltage (Vaux < Vaux_OV) 1 Overvoltage detected (Vaux > Vaux_OV) Reset condition Power On Reset / Read Description Vaux undervoltage detection 0 No undervoltage (Vaux > Vaux_uv) 1 undervoltage detected (Vaux < Vaux_uv) Reset condition Power On Reset / Read 33907_8 68 Analog Integrated Circuit Device Data Freescale Semiconductor DIAG VREG 3 Table 41. DIAG VREG3 Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU 0 Ilimcca_off 0 Vcca_ OV 0 Vcca_U V 0 CAN_G Reserved IO_G Vpre_G Vcore_ Vothers Tsd_cc G _G a Table 42. Diag Vreg3. Description and Configuration of the Bits (Default value in blue) Tsd_cca Ilim_cca_off Vcca_OV Vcca_UV Description Thermal shutdown of Vcca 0 NO TSD (Tj < Tsd_cca) 1 TSD occurred (Tj > Tsd_cca) Reset condition Power On Reset / Read Description Maximum current limitation duration. Available only when an external PNP is connected 0 T_limitation < Tcca_lim_off 1 T_limitation >Tcca_lim_off Reset condition Power On Reset / Read Description Vcca overvoltage detection 0 No overvoltage (Vcca < Vcca_OV) 1 Overvoltage detected (Vcca > Vcca_OV) Reset condition Power On Reset / Read Description Vcca undervoltage detection 0 No undervoltage (Vcca > Vcca_uv) 1 Undervoltage detected (Vcca < Vcca_uv) Reset condition Power On Reset 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 69 DIAG CAN1 Table 43. DIAG CAN1 Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_G Reserved IO_G Vpre_G Vcore_ Vothers CANH_ CANH_ CANL_ CANL_ CAN_d G _G batt gnd batt gnd ominan t 0 RXD_r TXD_d ecessiv ominan t e Table 44. Diag CAN1. Description and Configuration of the Bits (Default value in blue) CANH_batt CANH_gnd CANL_batt CANL_gnd CAN_dominant RXD_recessive TXD_dominant Description CANH short circuit to battery detection 0 NO failure 1 Failure detected Reset condition Power On Reset / Read Description CANH short circuit to gnd detection 0 NO failure 1 Failure detected Reset condition Power On Reset / Read Description CANL short circuit to battery detection 0 NO failure 1 Failure detected Reset condition Power On Reset / Read Description CANL short circuit to gnd detection 0 NO failure 1 Failure detected Reset condition Power On Reset / Read Description CAN Bus dominant clamping detection 0 NO failure 1 Failure detected Reset condition Power On Reset / Read Description RXD recessive clamping detection (short circuit to 5V) 0 NO failure 1 Failure detected Reset condition Power On Reset / Read Description TXD dominant clamping detection (short circuit to GND) 0 NO failure 1 Failure detected Reset condition Power On Reset / Read 33907_8 70 Analog Integrated Circuit Device Data Freescale Semiconductor DIAG CAN2 Table 45. DIAG CAN2 Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_G Reserv ed IO_G Vpre_G Vcore_ Vothers reserve reserve G _G d d 0 reserve reserve d d 0 CAN_O CAN_O T C Table 46. Diag CAN2. Description and Configuration of the Bits (Default value in blue) CAN_OT CAN_OC Description CAN overtemperature detection 0 NO failure 1 Failure detected Reset condition Power On Reset / Read Description CAN overcurrent detection 0 NO failure 1 Failure detected Reset condition Power On Reset / Read Table 47. Distinguish between CAN Diagnostic and CAN Error Register DIAG CAN1 Bit Flag Type Effect CANH_batt Diagnostic No impact CANH_gnd Diagnostic No impact CANL_batt Diagnostic No impact CANL_gnd Diagnostic No impact CAN_dominant Error Turn OFF CAN transceiver RXD_recessive Error Turn OFF CAN transceiver TXD_dominant Error Turn OFF CAN transceiver CAN_OT Error Turn OFF CAN transceiver CAN_OC Diagnostic No impact DIAG CAN2 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 71 DIAG SPI Table 48. DIAG SPI Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU 0 SPI_clk 0 SPI_re q 0 SPI_pa rity 0 CAN_G Reserv ed IO_G Vpre_G Vcore_ Vothers SPI_err G _G Table 49. Diag SPI. Description and Configuration of the Bits (Default value in blue) SPI_err SPI_CLK SPI_req SPI_parity Description Secured SPI communication check 0 No error 1 Error detected in the secured bits Reset condition Power On Reset / Read Description SCLK error detection 0 16 clock cycles during NCS low 1 Wrong number of clock cycles (<16 or > 16) Reset condition Power On Reset / Read Description Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address) 0 No error 1 SPI violation Reset condition Power On Reset / Read Description SPI parity bit error detection 0 Parity bit OK 1 Parity bit error Reset condition Power On Reset / Read 33907_8 72 Analog Integrated Circuit Device Data Freescale Semiconductor MODE Table 50. MODE Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 0 1 0 1 0 1 P MISO SPI_G WU CAN_G Reserv ed IO_G Vpre_G Vcore_ Vothers G _G bit7 bit6 bit5 bit4 reserve reserve Goto_L INT_re d d POFF quest bit3 bit2 bit1 bit0 Secure Secure Secure Secure _3 _2 _1 _0 0 0 0 0 INIT Normal reserve reserve d d Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU 0 0 0 0 INIT CAN_G Reserv ed IO_G Vpre_G Vcore_ Vothers G _G Normal reserve reserve d d Table 51. MODE. Description and Configuration of the Bits (Default value in blue) Goto_LPOFF INIT Normal INT_request Secure 3:0 Description Configure the device in Low Power mode Vreg OFF (LPOFF) 0 No action 1 LPOFF mode Reset condition Power On Reset Description Report if INIT mode of the main logic state machine is entered 0 Not in INIT mode 1 INIT MODE Reset condition Power On Reset Description Report if Normal mode of the main logic state machine is entered 0 Not in Normal mode 1 Normal mode Reset condition Power On Reset Description Request for an INT pulse 0 No Request 1 Request for an INT pulse Reset condition Power On Reset Description Secured bits based on write bits secured_3 = NOT(bit5) Secured_2= NOT(bit4) Secured_1=bit7 Secured_0=bit6 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 73 VREG MODE Table 52. VREG MODE Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 0 1 0 1 1 0 P MISO SPI_G WU CAN_G Reserved IO_G bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Vcore_ Vcca_E Vaux_E Vcan_E Secure Secure Secure Secure EN N N N _3 _2 _1 _0 Vpre_G Vcore_ Vothers reserve reserve reserve reserve Vcore_ Vcca_E Vaux_E Vcan_E G _G d d d d EN N N N Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_G Reserved IO_G Vpre_G Vcore_ Vothers reserve reserve reserve reserve Vcore_ Vcca_E Vaux_E Vcan_E G _G d d d d EN N N N Table 53. VREG MODE. Description and Configuration of the Bits (Default value in blue) Vcore_EN Vcca_EN Vaux_EN VCAN_EN Secure 3:0 Description Vcore control (Switch OFF not possible if Vcore is SAFETY critical) 0 DISABLED 1 ENABLED Reset condition Power On Reset Description Vcca control (Switch OFF NOT possible if Vcca is SAFETY critical) 0 DISABLED 1 ENABLED Reset condition Power On Reset Description Vaux control (Switch OFF NOT possible if Vaux is SAFETY critical) 0 DISABLED 1 ENABLED Reset condition Power On Reset Description Vcan control 0 DISABLED 1 ENABLED Reset condition Power On Reset Description Secured bits based on write bits secured_3 = NOT(bit5) Secured_2= NOT(bit4) Secured_1=bit7 Secured_0=bit6 33907_8 74 Analog Integrated Circuit Device Data Freescale Semiconductor IO_OUT-AMUX Table 54. IO_OUT-AMUX Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 MOSI 1 0 1 0 1 1 1 P IO_out _4_EN IO_out _4 IO_out _5_EN IO_out _5 MISO SPI_G WU Vpre_G Vcore_ Vothers IO_out IO_oou IO_out G _G _4_EN t_4 _5_EN IO_out _5 CAN_G Reserv ed IO_G bit3 bit2 bit1 bit0 Reserv Amux_ ed 2 Amux_ 1 Amux_ 0 Reserv Amux_ ed 2 Amux_ 1 Amux_ 0 Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU Amux_ 1 Amux_ 0 CAN_G Reserv ed IO_G Vpre_G Vcore_ Vothers IO_out IO_oou IO_out G _G _4_EN t_4 _5_EN IO_out _5 Reserv Amux_ ed 2 Table 55. IO_OUT-AMUX. Description and Configuration of the Bits (Default value in blue) IO_out_4_EN IO_out_4 IO_out_5_EN IO_out_5 AMUX_2:0 Description Enable the output gate driver capability for IO_4 0 High impedance (IO_4 configured as input) 1 ENABLED (IO_4 configured as output gate driver) Reset condition Power On Reset Description Configure IO_4 output gate driver state 0 LOW 1 HIGH Reset condition Power On Reset Description Enable the output gate driver capability for IO_5 0 High impedance (IO_5 configured as input) 1 ENABLED (IO_5 configured as output gate driver) Reset condition Power On Reset Description Configure IO_5 output gate driver state 0 LOW 1 HIGH Reset condition Power On Reset Description Select AMUX output 000 Vref 001 Vsns wide range 010 IO_0 wide range 011 IO_1 wide range 100 Vsns tight range 101 IO_0 tight range 110 IO_1 tight range 111 Die temp. Sense Reset condition Power On Reset 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 75 CAN MODE Table 56. CAN MODE Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 0 1 1 0 0 0 P MISO SPI_G WU CAN_G Reserved IO_G bit7 bit6 bit5 bit4 bit3 bit2 CAN_m CAN_m CAN_a reserve reserve reserve ode_1 ode_0 uto_dis d d d bit1 bit0 0 0 Vpre_G Vcore_ Vothers CAN_m CAN_m CAN_a reserve reserve reserve CAN_w reserve G _G ode_1 ode_0 uto_dis d d d u d Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_G Reserved IO_G Vpre_G Vcore_ Vothers CAN_m CAN_m CAN_a reserve reserve reserve CAN_w reserve G _G ode_1 ode_0 uto_dis d d d u d Table 57. CAN MODE. Description and Configuration of the Bits (Default value in blue) CAN_mode_1:0 CAN_auto_dis CAN_wu Description Configure the CAN mode 00 Sleep / NO wake up capability 01 LISTEN ONLY 10 Sleep / Wake-up capability 11 Normal operation mode Reset condition Power On Reset Description Automatic CAN Tx disable 0 NO auto disable 1 Reset CAN_mode from “11” to “01” on CAN over temp or TXD dominant or RXD recessive event Reset condition Power On Reset Description Report a wake up event from the CAN 0 No wake-up 1 wake-up detected Reset condition Power On Reset / Read Notes 19. When the device is in Normal mode, the CAN mode bits cannot be read back by the SPI when the CAN transceiver is configured in Low Power mode. 20. CAN mode is automatically configured to "sleep + wake-up capability [10]" if CAN mode was different than "sleep + no wake-up capability [00]" before the device enters in LPOFF. After LPOFF, the initial CAN mode prior to enter LPOFF is restored. 33907_8 76 Analog Integrated Circuit Device Data Freescale Semiconductor CAN_MODE_2 Table 58. CAN_MODE_2 Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 0 1 1 0 0 1 P MISO SPI_G WU bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_G Reserv ed IO_G bit7 bit6 bit5 bit4 bit3 reserve reserve reserve Vcan_ secure _3 d d d OV_Mo n bit2 bit1 bit0 secure _2 secure _1 secure _0 Vpre_G Vcore_ Vothers Reserv Reserv Reserv Reserv Vcan_ Reserv Reserv Reserv ed ed ed G _G ed ed ed ed OV_Mo n Read CAN_G Reserv ed IO_G Vpre_G Vcore_ Vothers Reserv Reserv Reserv Reserv Vcan_ Reserv Reserv Reserv ed ed ed G _G ed ed ed ed OV_Mo n Table 59. CAN_MODE_2. Description and Configuration of the Bits (Default value in blue) Vcan_OV_Mon Secure 3:0 Description VCAN OV Monitoring 0 OFF. Vcan OV is not monitored. Flag is ignored 1 ON. Vcan OV flag is under monitoring. In case of OV the Vcan regulator is switched OFF. Reset condition Power On Reset Description Secured bits based on write bits secured_3 = NOT(bit5) Secured_2= NOT(bit4) Secured_1=bit7 Secured_0=bit6 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 77 INIT SUPERVISOR1 Table 60. INIT SUPERVISOR1 Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 1 0 0 0 0 1 P MISO SPI_G WU CAN_G Reserv ed IO_G bit7 bit6 bit5 bit4 bit3 Vcore_ Vcore_ Vcca_F Vcca_F secure FS1 FS_0 S_1 S_0 _3 bit2 bit1 bit0 Secure Secure Secure _2 _1 _0 Vpre_G Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS Vcore_ Vcore_ Vcca_F Vcca_F G _G _err _CLK _Req _Parity FS1 FS_0 S_1 S_0 Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_G Reserv ed IO_G Vpre_G Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS Vcore_ Vcore_ Vcca_F Vcca_F G _G _err _CLK _Req _Parity FS1 FS_0 S_1 S_0 Table 61. INIT SUPERVISOR1. Description and Configuration of the Bits (Default value in blue) Vcore_FS1:0 Vcca_FS1:0 Secure3:0 Description Vcore safety input. 00 No effect of Vcore_OV and Vcore_uv on RSTb and FSxx 01 Vcore_OV DOES HAVE an impact on RSTb and FSxx. Vcore_UV DOES HAVE an impact on RSTb only 10 Vcore_OV DOES HAVE an impact on RSTb and FSxx. No effect of Vcore_UV on RSTb and FSxx 11 Both Vcore_OV and Vcore_UV DO HAVE an impact on RSTb and FSxx Reset condition Power On Reset Description Vcca safety input. 00 No effect of Vcca_OV and Vcca_uv on RSTb and FSxx 01 Vcca_OV DOES HAVE an impact on RSTb and FSxx. Vcca_UV DOES HAVE an impact on RSTb only 10 Vcca_OV DOES HAVE an impact on RSTb and FSxx. No effect of Vcca_UV on RSTb and FSxx 11 Both Vcca_OV and Vcca_UV DO HAVE an impact on RSTb and FSxx Reset condition Power On Reset Description Secured bits based on write bits secured_3 = NOT(bit5) Secured_2= NOT(bit4) Secured_1=bit7 Secured_0=bit6 SPI_FS_err SPI_FS_CLK Description Secured SPI communication check 0 No error 1 Error detected in the secured bits Reset condition Power On Reset Description SCLK error detection, concerns internal error in Fail-safe logic only and external errors (at pin level) for both Main and Fail-safe logics. Other errors flagged by SPI_CLK_ bit 0 16 clock cycles during NCS low 1 Wrong number of clock cycles (<16 or >16) Reset condition Power On Reset 33907_8 78 Analog Integrated Circuit Device Data Freescale Semiconductor Table 61. INIT SUPERVISOR1. Description and Configuration of the Bits (Default value in blue) SPI_FS_Req SPI_FS_Parity Description Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns Fail-safe logic only. 0 No error 1 SPI violation Reset condition Power On Reset Description SPI parity bit error detection, concerns Fail-safe logic only 0 Parity bit OK 1 Parity bit ERROR Reset condition Power On Reset 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 79 INIT SUPERVISOR 2 Table 62. INIT SUPERVISOR2 Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 1 0 0 0 1 0 P MISO SPI_G WU bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_G Reserv ed IO_G bit7 bit6 Vaux_F Vaux_F S1 S_0 bit5 0 bit4 bit3 bit2 bit1 bit0 DIS_8s Secure Secure Secure Secure _3 _2 _1 _0 Vpre_G Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS G _G _err _CLK _req _Parity 0 DIS_8s Vaux_F Vaux_F S1 S_0 Read CAN_G Reserv ed IO_G Vpre_G Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS G _G _err _CLK _req _Parity 0 DIS_8s Vaux_F Vaux_F S1 S_0 Table 63. INIT SUPERVISOR2. Description and Configuration of the Bits (Default value in blue) Vaux_FS1:0 DIS_8s Secure3:0 Description Vaux safety input. 00 No effect of Vaux_OV and Vaux_uv on RSTb and FSxx 01 Vaux_OV DOES HAVE an impact on RSTb and FSxx. Vaux_UV DOES HAVE an impact on RSTb only 10 Vaux_OV DOES HAVE an impact on RSTb and FSxx. No effect of Vaux_UV on RSTb and FSxx 11 Both Vaux_OV and Vaux_UV DO HAVE an impact on RSTb and FSxx Reset condition Power On Reset Description Disable the 8s timer used to enter Deep FAILSAFE mode 0 ENABLED 1 DISABLED Reset condition Power On Reset Description Secured bits based on write bits secured_3 = NOT(bit5) Secured_2= NOT(bit4) Secured_1=bit7 Secured_0=bit6 SPI_FS_err SPI_FS_CLK Description Secured SPI communication check, concerns Fail-safe logic only. 0 No error 1 Error detected in the secured bits Reset condition Power On Reset Description SCLK error detection, concerns internal error in Fail-safe logic only and external errors (at pin level) for both Main and Fail-safe logics. Other errors flagged by SPI_CLK_ bit 0 16 clock cycles during NCS low 1 Wrong number of clock cycles (<16 or >16) Reset condition Power On Reset 33907_8 80 Analog Integrated Circuit Device Data Freescale Semiconductor Table 63. INIT SUPERVISOR2. Description and Configuration of the Bits (Default value in blue) SPI_FS_Req SPI_FS_Parity Description Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns Fail-safe Logic only 0 No error 1 SPI violation Reset condition Power On Reset Description SPI parity bit error detection, concerns Fail-safe logic only 0 Parity bit OK 1 Parity bit ERROR Reset condition Power On Reset 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 81 INIT SUPERVISOR 3 Table 64. INIT SUPERVISOR3 Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 1 0 0 0 1 1 P MISO SPI_G WU CAN_G Reserv ed IO_G bit7 bit6 bit5 bit4 Vcore_ Vcca_5 Vaux_5 5D D D 0 Vpre_G Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS G _G _err _CLK _req _Parity bit3 bit2 bit1 bit0 Secure Secure Secure Secure _3 _2 _1 _0 0 Vcore_ Vcca_5 Vaux_5 5D D D Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_G Reserv ed IO_G Vpre_G Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS G _G _err _CLK _req _Parity 0 Vcore_ Vcca_5 Vaux_5 5D D D Table 65. INIT SUPERVISOR3. Description and Configuration of the Bits (Default value in blue) Vcore_5D Vcca_5D Vaux_5D Secure3:0 Description Configure the Vcore undervoltage in degraded mode. Only valid for 5V 0 Normal 5 V undervoltage detection threshold (Vcore_uv) 1 Degraded mode, i.e lower under voltage detection threshold applied (Vcore_uv_D) Reset condition Power On Reset Description Configure the Vcca undervoltage in degraded mode. Only valid for 5V 0 Normal 5 V undervoltage detection threshold (Vcca_uv_5) 1 Degraded mode, i.e lower under voltage detection threshold applied (Vcca_uv_D) Reset condition Power On Reset Description Configure the Vaux undervoltage in degraded mode. Only valid for 5V 0 Normal 5 V undervoltage detection threshold (Vaux_uv_5) 1 Degraded mode, i.e lower under voltage detection threshold applied (Vaux_uv_5D) Reset condition Power On Reset Description Secured bits based on write bits secured_3 = NOT(bit5) Secured_2= NOT(bit4) Secured_1=bit7 Secured_0=bit6 SPI_FS_err SPI_FS_CLK Description Secured SPI communication check, concerns fail-safe logic only 0 No error 1 Error detected in the secured bits Reset condition Power On Reset Description SCLK error detection, concerns internal error in Fail-safe logic only and external errors (at pin level) for both Main and Fail-safe logics. Other errors flagged by SPI_CLK_ bit 0 16 clock cycles during NCS low 1 Wrong number of clock cycles (<16 or >16) Reset condition Power On Reset 33907_8 82 Analog Integrated Circuit Device Data Freescale Semiconductor Table 65. INIT SUPERVISOR3. Description and Configuration of the Bits (Default value in blue) SPI_FS_Req SPI_FS_Parity Description Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns Fail-Safe Logic only 0 No error 1 SPI violation Reset condition Power On Reset Description SPI parity bit error detection, concerns Fail-safe logic only 0 Parity bit OK 1 Parity bit ERROR Reset condition Power On Reset 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 83 INIT FSSM1 Table 66. INIT FSSM1 Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 MOSI 1 1 0 0 1 0 0 P IO_01_ FS 0 MISO SPI_G WU CAN_G Reserved IO_G bit5 bit4 bit3 bit2 bit1 bit0 IO_45_ RSTb_l Secure Secure Secure Secure FS ow _3 _2 _1 _0 Vpre_G Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS IO_01_ G _G _err _CLK _req _Parity FS 0 IO_45_ RSTb_l FS ow Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_G Reserved IO_G Vpre_G Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS IO_01_ G _G _err _CLK _req _Parity FS 0 IO_45_ RSTb_l FS ow Table 67. INIT FSSM1. Description and Configuration of the Bits (Default value in blue) IO_01_FS IO_45_FS RSTb_low Secure3:0 Description Configure the couple of IO_1:0 as safety inputs 0 NOT SAFETY 1 SAFETY CRITICAL Reset condition Power On Reset Description Configure the couple of IO_5:4 as safety inputs 0 NOT SAFETY 1 SAFETY CRITICAL Reset condition Power On Reset Description Configure the Rstb LOW duration time 0 10 ms 1 1ms Reset condition Power On Reset Description Secured bits based on write bits secured_3 = NOT(bit5) Secured_2= NOT(bit4) Secured_1=bit7 Secured_0=bit6 SPI_FS_err SPI_FS_CLK Description Secured SPI communication check, concerns Fail-safe logic only 0 No error 1 Error detected in the secured bits Reset condition Power On Reset Description SCLK error detection, concerns internal error in Fail-safe logic only and external errors (at pin level) for both Main and Fail-safe logics. Other errors flagged by SPI_CLK_ bit 0 16 clock cycles during NCS low 1 Wrong number of clock cycles (<16 or >16) Reset condition Power On Reset 33907_8 84 Analog Integrated Circuit Device Data Freescale Semiconductor Table 67. INIT FSSM1. Description and Configuration of the Bits (Default value in blue) SPI_FS_Req SPI_FS_Parity Description Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns Fail-safe logic only 0 No error 1 SPI violation Reset condition Power On Reset Description SPI parity bit error detection, concerns Fail-safe logic only 0 Parity bit OK 1 Parity bit ERROR Reset condition Power On Reset 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 85 INIT FSSM2 Table 68. INIT FSSM2 Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 1 0 0 1 0 1 P MISO SPI_G WU CAN_G Reserv ed IO_G bit7 bit6 RSTb_ IO_23_ err_FS FS bit5 bit4 PS 0 bit3 bit2 bit1 bit0 Secure Secure Secure Secure _3 _2 _1 _0 Vpre_G Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS RSTb_ IO_23_ G _G _err _CLK _req _Parity err_FS FS PS 0 Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU PS 0 CAN_G Reserv ed IO_G Vpre_G Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS RSTb_ IO_23_ G _G _err _CLK _req _Parity err_FS FS Table 69. INIT FSSM2. Description and Configuration of the Bits (Default value in blue) IO_23_FS RSTb_err_FS PS Secure3:0 Description Configure the couple of IO_3:2 as safety inputs for FCCU monitoring 0 NOT SAFETY 1 SAFETY CRITICAL Reset condition Power On Reset Description Configure the values of the RSTb error counter 0 intermediate=3; final=6 1 intermediate=1; final=2 Reset condition Power On Reset Description Configure the Fccu polarity 0 Fccu_eaout_1:0 active HIGH 1 Fccu_eaout_1:0 active LOW Reset condition Power On Reset Description Secured bits based on write bits secured_3 = NOT(bit5) Secured_2= NOT(bit4) Secured_1=bit7 Secured_0=bit6 SPI_FS_err SPI_FS_CLK Description Secured SPI communication check, concerns Fail-safe logic only 0 No error 1 Error detected in the secured bits Reset condition Power On Reset Description SCLK error detection, concerns internal error in Fail-safe logic only and external errors (at pin level) for both Main and Fail-safe logics. Other errors flagged by SPI_CLK_ bit 0 16 clock cycles during NCS low 1 Wrong number of clock cycles (<16 or >16) Reset condition Power On Reset 33907_8 86 Analog Integrated Circuit Device Data Freescale Semiconductor Table 69. INIT FSSM2. Description and Configuration of the Bits (Default value in blue) SPI_FS_Req SPI_FS_Parity Description Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns Fail-safe Logic only 0 No error 1 SPI violation Reset condition Power On Reset Description SPI parity bit error detection, concerns Fail-safe logic only 0 Parity bit OK 1 Parity bit ERROR Reset condition Power On Reset 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 87 WD WINDOW Table 70. WD WINDOW Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 1 0 0 1 1 0 P MISO SPI_G WU CAN_G Reserv ed IO_G bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 WD_wi WD_wi WD_wi WD_wi Secure Secure Secure Secure ndow3 ndow2 ndow1 ndow0 _3 _2 _1 _0 Vpre_G Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS WD_wi WD_wi WD_wi WD_wi G _G _err _CLK _req _Parity ndow3 ndow2 ndow1 ndow0 Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_G Reserv ed IO_G Vpre_G Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS WD_wi WD_wi WD_wi WD_wi G _G _err _CLK _req _Parity ndow3 ndow2 ndow1 ndow0 Any WRITE command to the WD_window in the Normal mode must be followed by a READ command to verify the correct change of the WD window duration Table 71. WD Window. Description and Configuration of the Bits (Default value in blue) WD_Window_3:0 Secure3:0 Description Configure the watchdog window duration. Duty cycle if set to 50% 0000 DISABLE 0001 1 ms 0010 2 ms 0011 3 ms 0100 4 ms 0101 6 ms 0110 8 ms 0111 12 ms 1000 16 ms 1001 24 ms 1010 32 ms 1011 64 ms 1100 128 ms 1101 256 ms 1110 512 ms 1111 1024 ms Reset condition Power On Reset Description Secured bits based on write bits secured_3 = NOT(bit5) Secured_2= NOT(bit4) Secured_1=bit7 Secured_0=bit6 33907_8 88 Analog Integrated Circuit Device Data Freescale Semiconductor Table 71. WD Window. Description and Configuration of the Bits (Default value in blue) SPI_FS_err SPI_FS_CLK SPI_FS_Req SPI_FS_Parity Description Secured SPI communication check, concerns Fail-safe logic only 0 No error 1 Error detected in the secured bits Reset condition Power On Reset Description SCLK error detection, concerns internal error in Fail-safe logic only and external errors (at pin level) for both Main and Fail-safe logics. Other errors flagged by SPI_CLK bit. 0 16 clock cycles during NCS low 1 Wrong number of clock cycles (<16 or >16) Reset condition Power On Reset Description Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns Fail-safe logic only 0 No error 1 SPI violation Reset condition Power On Reset Description SPI parity bit error detection, concerns Fail-safe logic only 0 Parity bit OK 1 Parity bit ERROR Reset condition Power On Reset 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 89 WD_LFSR Table 72. WD LFSR Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 1 0 0 1 1 1 P MISO SPI_G WU bit15 bit14 bit13 bit12 bit11 bit10 bit9 MOSI 0 1 0 0 1 1 1 MISO SPI_G WU CAN_G Reserved IO_G Vpre_G Vcore_ Vothers G _G bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF SR_7 SR_6 SR_5 SR_4 SR_3 SR_2 SR_1 SR_0 0 0 0 0 0 0 0 0 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 0 0 0 0 0 0 Read CAN_G Reserved IO_G Vpre_G Vcore_ Vothers WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF G _G SR_7 SR_6 SR_5 SR_4 SR_3 SR_2 SR_1 SR_0 Table 73. WD LFSR. Description and Configuration of the Bits (Default value in blue) WD_LFSR_7:0 Description WD 8 bits LFSR value. Used to write the seed at any time 0... bit7:bit0: 10110010 default value at startup or after a Power on reset: 0xB2 (21) 1... Reset condition Power On Reset Notes 21. Value Bit7:Bit0: 1111 1111 is prohibited. 33907_8 90 Analog Integrated Circuit Device Data Freescale Semiconductor WD ANSWER Table 74. WD ANSWER Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 1 0 1 0 0 0 P MISO SPI_G WU CAN_G Reserv ed IO_G bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 WD_an WD_an WD_an WD_an WD_an WD_an WD_an WD_an swer_7 swer_6 swer_5 swer_4 swer_3 swer_2 swer_1 swer_0 Vpre_G Vcore_ Vothers G _G RSTb FS0 WD FS0_G IO_FS_ G 0 FS_EC FS_reg C _Ecc Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU RSTb FS0 WD CAN_G Reserv ed IO_G Vpre_G Vcore_ Vothers G _G FS0_G IO_FS_ G 0 FS_EC FS_reg C _Ecc Table 75. WD answer. Description and Configuration of the Bits (Default value in blue) WD_answer_7:0 Description WD answer from the MCU 0... Answer = (NOT(((LFSR x 4)+6)-4))/4 1... RSTb FS0b WD FS0_G IO_FS_G Reset condition Power On Reset / RSTb LOW Description Report a reset event 0 No Reset 1 Reset occurred Reset condition Power On Reset / Read Description Report a fail-safe event 0 No Fail-safe 1 Fail safe event occurred / Also default state at power-up after LPOFF as FS0b is asserted low Reset condition Power On Reset / Read Description Report a watchdog refresh ERROR 0 WD refresh OK 1 WRONG WD refresh Reset condition Power On Reset / Read Description Report a fail-safe output failure 0 NO failure 1 Failure Reset condition Power On Reset / Read Description Report an IO monitoring error 0 No error 1 Error detected Reset condition Power On Reset 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 91 Table 75. WD answer. Description and Configuration of the Bits (Default value in blue) FS_ECC FS_req_ECC Description Report an error code correction on Fail-safe state machine 0 NO ECC 1 ECC done Reset condition Power On Reset / Read Description Report an error code correction on Fail-safe registers 0 NO ECC 1 ECC done Reset condition Power On Reset / Read 33907_8 92 Analog Integrated Circuit Device Data Freescale Semiconductor FAIL-SAFE OUT (FS_OUT) Table 76. FAIL-SAFE OUT Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 1 0 1 0 0 1 P MISO SPI_G WU CAN_G Reserv ed IO_G bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 FS_out FS_out FS_out FS_out FS_out FS_out FS_out FS_out _7 _6 _5 _4 _3 _2 _1 _0 Vpre_G Vcore_ Vothers G _G 0 0 0 0 0 0 0 0 bit2 bit1 bit0 Table 77. Fail-Safe OUT. Description and Configuration of the Bits (Default value in blue) FS_out_7:0 Description Secured 8 bits word to release the FS0b 0... Depend on LFSR_out value and calculation 1... Reset condition Power On Reset -> Default = 00h RSTB REQUEST Table 78. RSTb REQUEST register description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 MOSI 1 1 0 1 0 1 0 P 0 0 RSTb_r equest 0 MISO SPI_G WU 0 0 0 0 CAN_G Reserv ed IO_G Vpre_G Vcore_ Vothers G _G bit3 Secure Secure Secure Secure _3 _2 _1 _0 0 0 0 0 Table 79. RSTb Request. Description and configuration of the bits (Default value in blue) RSTb_request Secure3:0 Description Request a RSTb low pulse 0 No request 1 Request a RSTb low pulse Reset condition Power On Reset / When RSTb done Description Secured bits based on write bits secured_3 = NOT(bit5) Secured_2= NOT(bit4) Secured_1=bit7 Secured_0=bit6 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 93 INIT_WD Table 80. INIT WD Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 1 0 1 0 1 1 P MISO SPI_G WU CAN_G Reserved IO_G Vpre_G bit7 bit6 bit5 bit4 WD_CN WD_cnt_ WD_CN WD_CN T_refres refresh_ T_error_ T_error_ h_1 0 1 0 bit3 bit2 bit1 bit0 secure3 secure2 secure1 secure0 Vcore_G Vothers_ SPI_FS_ SPI_FS_ SPI_FS_ SPI_FS_ WD_CN WD_cnt_ WD_CN WD_CN G err CLK Req Parity T_refres refresh_ T_error_ T_error_ h_1 0 1 0 Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_G Reserve d IO_G Vpre_G Vcore_ Vothers SPI_FS_ SPI_FS_ SPI_FS_ SPI_FS_ WD_CN WD_cnt_ WD_CN WD_CN err CLK Req Parity T_refres refresh_ T_error_ T_error_ G _G h_1 0 1 0 Table 81. INIT WD. Description and Configuration of the Bits (Default value in blue) WD_CNT_error_1:0 WD_CNT_refresh_1 :0 Description Configure the maximum value of the WD error counter 00 6 01 6 10 4 11 2 Reset Condition Power On Reset Description Configure the maximum value of the WD refresh counter 00 6 01 6 10 4 11 1 Reset Condition Power On Reset 33907_8 94 Analog Integrated Circuit Device Data Freescale Semiconductor DIAG FS1 Table 82. DIAG FS1 Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU RSTb_ diag 0 0 0 0 CAN_G Reserv ed IO_G Vpre_G Vcore_ Vothers RSTb_ G _G ext FS0b_d FS0b_d iag_1 iag_0 Table 83. Diag FS1. Description and Configuration of the Bits (Default value in blue) RSTb_diag RSTb_ext FS0b_diag_1:0 Description Report a RSTb short-circuit to HIGH 0 NO Failure 1 short circuit HIGH Reset condition Power On Reset / Read Description Report an external RSTb 0 No external RSTb 1 external RSTb Reset condition Power On Reset / Read Description Report a failure on FS0b 00 No Failure 01 Short-circuit LOW / open load 1X short-circuit HIGH Reset condition Power On Reset / Read 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 95 WD COUNTER Table 84. WD COUNTER Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 MOSI 0 1 MISO SPI_ G WU 0 1 1 CAN Res IO_ _G erve G d 0 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1 0 0 0 0 0 0 0 0 0 Vpre_ Vcore Vothers_ WD_err WD_err WD_err G _G G _2 _1 _0 0 WD_re WD_ref WD_ref fresh_ resh_1 resh_0 2 0 Table 85. WD counter. Description and Configuration of the Bits (Default value in blue) WD_err_2:0 Description Report the value of the watchdog error counter 000 From 0 to 5 (6 generates a Reset and this counter is reset to 0) to 110 WD_refresh_2:0 Reset condition Power On Reset Description Report the value of the watchdog refresh counter 000 From 0 to 6 (7 generate a decrease of the RST_err_cnt and this counter is reset to 0) to 111 Reset condition Power On Reset 33907_8 96 Analog Integrated Circuit Device Data Freescale Semiconductor DIAG FS2 Table 86. DIAG FS2 Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU RSTb_ err_1 RSTb_ err_0 0 0 IO_01_ fail CAN_G Reserv ed IO_G Vpre_G Vcore_ Vothers RSTb_ G _G err_2 IO_45_ IO_23_ fail fail Table 87. Diag FS1. Description and Configuration of the Bits (Default value in blue) RSTb_err_2:0 IO_45_fail IO_23_fail IO_01_fail Description Report the value of the RSTb error counter 000 001 … 110 Error counter is set to 1 by default Reset condition Power On Reset Description Report an error in the IO_45 protocol 0 NO error 1 Error detected Reset condition Power On Reset / Read Description Report an error in the FCCU protocol 0 NO error 1 Error detected Reset condition Power On Reset / Read Description Report an error in the IO_01 protocol 0 NO error 1 Error detected Reset condition Power On Reset / Read 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 97 8 List of Interruptions and Description The INTb output pin generates a low pulse when an Interrupt condition occurs. The INTb behavior as well as the pulse duration are set through SPI during INIT phase. It is possible to mask some Interruption source (see register mapping). Table 88. Interruptions list Event Description VSNS_UV Detection of Vbattery below 8.5V VSUP_UV_7 Detection of VSUP below 7V (after reverse current protection diode) IPFF Input power feed forward. Based on VSUP and IPRE_PEAK ILIM_PRE Pre-Regulator Current Limitation TWARN_PRE Temperature warning on the pass transistor BoB Return the running state of VPRE converter (Buck or Boost mode) VPRE_STATE (VPRE_SMPS_EN) Return the activation state of VPRE DC/DC converter VPRE OV Report a VPRE overvoltage detection VPRE UV Report a VPRE under voltage detection ILIM_CORE VCORE Current limitation TWARN_CORE Temperature warning on the pass transistor VCORE_STATE (VCORE_SMPS_EN) Return the activation state of VCORE DC/DC converter VCORE OV Report a VCORE overvoltage detection VCORE UV Report a VCORE under voltage detection ILIM_CCA VCCA Current limitation TWARN_CCA Temperature warning on the pass transistor (Internal Pass transistor only) TSDVCCA Temperature shutdown of the VCCA ILIM_CCA_OFF Current limitation maximum duration expiration. Only used when external PNP connected. VCCA OV Report a VCCA overvoltage detection VCCA UV Report a VCCA under voltage detection ILIM_AUX VAUX Current limitation ILIM_AUX_OFF Current limitation maximum duration expiration. Only used when external PNP connected. VAUX OV Report a VAUX overvoltage detection VAUX UV Report a VAUX under voltage detection TSDVAUX Temperature shutdown of the VAUX ILIM_CAN VCAN Current limitation VCAN OV Report a VCAN overvoltage detection VCAN UV Report a VCAN under voltage detection TSDCAN Temperature shutdown on the pass transistor. Auto restart when TJ < (TSDCAN TSDCAN_HYST). 33907_8 98 Analog Integrated Circuit Device Data Freescale Semiconductor Table 88. Interruptions list IO_0 Report IO_0 digital state change IO_1 Report IO_1 digital state change IO_2 Report IO_2 digital state change IO_3 Report IO_3 digital state change IO_4 Report IO_4 digital state change IO_5 Report IO_5 digital state change IO_0_WU Report IO_0 WU event IO_1_WU Report IO_1 WU event IO_2_WU Report IO_2 WU event IO_3_WU Report IO_3 WU event IO_4_WU Report IO_4 WU event IO_5_WU Report IO_5 WU event CANLBATT CANL short-circuit to battery detection CANLGND CANL short-circuit to GND detection CANHBATT CANH short-circuit to battery detection CANHGND CANH short-circuit to GND detection CAN_WU Report a CAN wake-up event CAN_OT CAN overtemperature detection RXD_recessive CAN RXD recessive clamping detection (short circuit to 5 V) TXD_dominant CAN TXD dominant clamping detection (short circuit to GND) CAN_dominant CAN bus dominant clamping detection CAN_OC CAN overcurrent detection INT_Request MCU request for an Interrupt pulse SPI_err Secured SPI communication check SPI_CLK Report a wrong number of CLK pulse different than 16 during the NCS low pulse in Main state machine SPI_Req Invalid SPI access (Wrong write or read, write to INIT registers in normal mode, wrong address) SPI_Parity Report a Parity error in Main state machine 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 99 Typical Applications PGND 100nF Vcca_B 5.1K +/-5% 12K +/-5% 24K +/-5% 51K +/-5% Optional GND Vbat RSelect Key on Resistor must be close to Select pin GND 5.1 k SELECT IO_0 Vcca (5 V or 3.3 V), available configurations Whithout Ext. PNP : 100 mA capability +/-1% accuracy for 5 V configuration, +/-1.5% accuracy for 3.3V configuration, With Ext. PNP : < 200mA +/-2% accuracy With Ext. PNP : 300 mA capability +/-3% accuracy IO_1 Optional Recommended connection for IOs not used in the application IO_3 5.1 k GND IO_5 5.1 k 0R MUX_OUT MCU inputs GND INTb MCU Int. VDDIO GND MCU RESET VDDIO or VSUP3 GND 5.1K if connected to VDDIO >10K if connected to Vsup3 To Fail Safe circuitry 5.1K Vpre FS0b 10K GND 120 Ground Connections PGND ground plane connected to DGND pin GND ground plane connected to AGND and GND_COM pins PGND (DGND) and GND (AGND & GND_COM) connected together far from PGND ground plane. CANL GNDA GND_Com DGND GND GND PGND DEBUG RXD TXD DEBUG mode 10 nF CANH 100nF MCU SPI GND CAN BUS 4 GND RSTb MUX_OUT (output selected by SPI) Vsense or VIO_0 or VIO_1 or Internal 2.5V reference voltage (2.5V +/-1%) or Temp IO_4 MOSI MISO SCLK NCS 5.1K Vaux (5 V or 3.3 V) 300 mA capability +/-3% accuracy IO_2 FCCU monitoring from Freescale MCU C1 R2(+/‐5%) C2 Cout 220pF 39K 1nF 2*10µF 680pF 18K 150pF 2*10µF 10 nF CAN-5V R1(+/‐5%) 200 510 (If connected to Vcore, must be connected closed to coutx 10µF x 2) 1 nF 1µF R4(+/‐1%) 8.06K 8.06K 10 µF GND Connected to Vcca or Vcore VDDIO Components selection for Vcore voltage (current range 10mA ‐> 800mA, DI/DT = 2A/µs) Vcore voltage R3(+/‐1%) 1.23V 4.32K 3.3V 24.9K EMI sup. Capacitor must be connected closed to load (220nF) and connected to GND 4.7 µF Capacitor closed to Vcca pin Capacitor must be close to Vaux pin GND Example of IO connection and usage < 7 10.8 <<13.2 21.6 <<26.4 45.9 <<56.1 ESR cap. <100m Vcca Recommended Value 100 nF Vaux 3.3V 5V 5V 3.3V Vcca_PNP 10 nF 4.7µF 3.3V 5V 3.3V 5V Vaux_B ESR cap. <100m Optional 1 nF Vaux_PNP EMI sup. Capacitor must be connected closed to load (100nF + 100pF) and connected to GND Rselect (K) C2 R2 GND Vaux_E PGND R4 Vcca_E Vaux PGND GND Comp_core SELECT pin Configuration for VCCA & VAUX (R select connected to GND) Vcca 10 µF 2.2nF 10 µF 10 µF 33907_08 Vsense 1µF PGND R1 GND Vcore_sns FB_core Boot_core Vpre 5.1 k SW_core Vsup3 R3 330pF PGND Gate_LS Boot_pre SW_pre2 SW_pre1 Vsup1 PGND Vsup2 GND GND C1 PGND Vcore Voltage ESR cap. <10m Capacitors must be close to Vpre pin PGND GND 1K PGND Optional 4.7 µF 4.7 µF 22 µF 22 µF PGND PGND PGND 2.2 µH 22 pF PGND ESR cap. <10m 7.5 Vbat ESR cap. <100m 10 µF 8.0 1 µH Snubber values must be fine tuned as linked also to board layout performance 22 µH 100nF 2.2nF Snubber values must be fine tuned as linked also to board layout performance 10 µF 9 11K GND GND MCU CAN Figure 34. PowerSBC10/20 Simplified Application Schematic with Non-inverting Buck-boost Configuration 33907_08 Vcca_E Vaux_B Vcca_B Vcca ESR cap. <100m Cout_Vaux Vaux RSelect GND Optional Vcca_PNP ESR cap. <100m Cout_Vcca Vaux_PNP Vaux_E GND SELECT GND Figure 35. Vaux/Vcca Connection 33907_8 100 Analog Integrated Circuit Device Data Freescale Semiconductor Vpre NC 33907_08 Vaux_E Vcca_E Vaux_B Vcca_B Optional Vcca_PNP ESR cap . <100 m NC Cout_Vcca Vcca Vaux RSelect GND SELECT Figure 36. VCCA Connection, Vaux Not Used NC 33907_08 Vaux_E Vcca_E Vaux_B Vcca_B Vcca NC Vaux RSelect NC ESR cap. <100m Cout_Vcca Vpre GND SELECT Figure 37. Vaux Not Used, Vcca Configuration up to 100 mA 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 101 10 Packaging 10.1 Package Mechanical Dimensions Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.freescale.com and perform a keyword search for the drawing’s document number. Table 89. Package Mechanical Dimensions Package 7.0 x 7.0, 48-Pin LQFP Exposed Pad, with 0.5 mm pitch, and a 4.5 x 4.5 exposed pad Suffix AE Package Outline Drawing Number 98ASA00173D 33907_8 102 Analog Integrated Circuit Device Data Freescale Semiconductor AE SUFFIX 48-PIN LQFP-EP 98ASA00173D ISSUE A 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 103 AE SUFFIX 48-PIN LQFP-EP 98ASA00173D ISSUE A 33907_8 104 Analog Integrated Circuit Device Data Freescale Semiconductor AE SUFFIX 48-PIN LQFP-EP 98ASA00173D ISSUE A 33907_8 Analog Integrated Circuit Device Data Freescale Semiconductor 105 11 Revision History REVISION DATE DESCRIPTION OF CHANGES 1.0 11/2013 • Initial release 2.0 12/2013 • • • • • • • • • • • • • • • • • • • • • • • 3.0 2/2014 • • • • • • • • • Updated Figure 2 Deleted Rk: IO_1 can also be used to monitor a second external resistor bridge (in parallel of the one for VCORE output voltage set) for safety purposes from Table 2 on page 8 Updated Gun Test in Table 3 on page 10 Added IOs maximum current capability to Table 3 on page 10 Updated VCCA voltage in Table 4 on page 14 Updated VAUX_LIM_HYST in Table 4 on page 15 Updated VCORE_FB_UV_D in Table 4 on page 16 Updated VAMUX_TP_CO in Table 4 on page 17 Updated VSPI_IL in Table 4 on page 18 Deleted VCORE_FB_DRIFT Deleted IIO_IN1 Deleted tRDRIFT Updated tRSTB_POR in Table 5 on page 22 Added T_DFS_recovery time in Table 5 on page 22 Updated DVSUP/DT voltage in Table 5 on page 23 Updated tPRE_UV_4p3 in Table 5 on page 24 Updated tPRE_TSD, tCORE_TSD, and tCCA_TSD values in Table 5 on page 24 Updated tCAN_TSD and tCAN_UV values in Table 5 on page 25 Added a formula for temperature sensor Deleted Vreg_WU from Table 30 on page 63 Updated Figure 10, Figure 16, Figure 17, and Figure 22 Updated Table 15, Table 16, Table 19, Table 20,Table 27, Table 28, Table 56, Table 67, Table 71, Table 75, and Table 87 Added note (21) Updated Figure 34, Figure 35, and Figure 36 Added new Figure 37 Added notes to Table 57 Changed to Advance Information Changed Orderable Parts numbers 33907 and 33908 to MC Added new reference to Table 73 in Normal Operation (First Watchdog Refresh) Changed default in Status Vreg1. Description and Configuration of the Bits (Default value in blue) for Vpre_state, for Vcore_state in Status Vreg2. Description and Configuration of the Bits (Default value in blue), for CAN_mode_1:0 in CAN MODE. Description and Configuration of the Bits (Default value in blue), and RSTb_err_2:0 in Diag FS1. Description and Configuration of the Bits (Default value in blue) Corrected SW_PRE pin names 33907_8 106 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. Home Page: freescale.com There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based Web Support: freescale.com/support Freescale reserves the right to make changes without further notice to any products herein. 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