INTEGRATED CIRCUITS DATA SHEET 74LVC157A Quad 2-input multiplexer Product specification Supersedes data of 2003 Jun 17 2003 Dec 02 Philips Semiconductors Product specification Quad 2-input multiplexer 74LVC157A FEATURES Inputs can be driven from either 3.3 or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 and 5 V environment. • 5 V tolerant inputs for interfacing with 5 V logic • Wide supply voltage range from 1.2 to 3.6 V The 74LVC157A is a quad 2-input multiplexer which select four bits of data from two sources under the control of a common select input (S). The four outputs present the selected data in the true (non-inverted) form. The enable input (E) is active LOW. When pin E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all the other input conditions. Moving the data from two groups of registers to four common output buses is a common use of the 74LVC157A. The state of the common data select input (S) determines the particular register from which the data comes. It can also be used as function generator. • CMOS low power consumption • Direct interface with TTL levels • Inputs accept voltages up to 5.5 V • Complies with JEDEC standard no. 8-1A • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. • Specified from −40 to +85 °C and −40 to +125 °C. The device is useful for implementing highly irregular logic by generating any 4 of the 16 different functions of two variables with one variable common. DESCRIPTION The 74LVC157A is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC157A is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to pin S. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. SYMBOL tPHL/tPLH PARAMETER CONDITIONS UNIT propagation delay nI0, nI1 to nY CL = 50 pF; VCC = 3.3 V 2.6 ns E to nY CL = 50 pF; VCC = 3.3 V 2.8 ns S to nY CL = 50 pF; VCC = 3.3 V 2.6 ns 5.0 pF VCC = 3.3 V; notes 1 and 2 15 pF CI input capacitance CPD power dissipation capacitance per gate Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. 2003 Dec 02 TYPICAL 2 Philips Semiconductors Product specification Quad 2-input multiplexer 74LVC157A FUNCTION TABLE See note 1. INPUT OUTPUT E S nI0 nI1 nY H X X X L L L L X L L L H X H L H X L L L H X H H Note 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care. ORDERING INFORMATION PACKAGE TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE 74LVC157AD −40 to +125 °C 16 SO16 plastic SOT109-1 74LVC157ADB −40 to +125 °C 16 SSOP16 plastic SOT338-1 74LVC157APW −40 to +125 °C 16 TSSOP16 plastic SOT403-1 74LVC157ABQ −40 to +125 °C 16 DHVQFN16 plastic SOT763-1 TYPE NUMBER PINNING PIN SYMBOL DESCRIPTION 1 S common data select input 2 1I0 data input from source 0 3 1I1 data input from source 1 4 1Y multiplexer output 5 2I0 data input from source 0 6 2I1 data input from source 1 7 2Y multiplexer output 8 GND ground (0 V) 9 3Y multiplexer output 10 3I1 data input from source 1 11 3I0 data input from source 0 12 4Y multiplexer output 13 4I1 data input from source 1 14 4I0 data input from source 0 15 E enable input (active LOW) 16 VCC supply voltage 2003 Dec 02 3 Philips Semiconductors Product specification Quad 2-input multiplexer 74LVC157A handbook, halfpage handbook, halfpage 16 VCC S 1 1I0 2 15 E 1I1 3 14 4I0 1Y 4 13 4I1 12 4Y 2I1 6 11 3I0 2Y 7 10 3I1 GND 8 9 3Y VCC 1 16 1I0 2 15 E 1I1 3 14 4I0 1Y 4 13 4I1 GND(1) 157 2I0 5 S 2I0 5 12 4Y 2I1 6 11 3I0 2Y 7 10 3I1 MNA480 Top view 8 9 GND 3Y MDB106 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.1 Pin configuration SO16 and (T)SSOP16. Fig.2 Pin configuration DHVQFN16. handbook, halfpage handbook, halfpage 2 3 5 6 11 10 14 15 13 2 1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1 1 S 15 E 1 3 G1 EN 1 MUX 5 1Y 2Y 3Y 4Y 4 7 9 12 4 1 7 6 11 9 10 MNA481 14 12 13 MNA482 Fig.3 Logic symbol. 2003 Dec 02 Fig.4 Logic symbol (IEEE/IEC). 4 Philips Semiconductors Product specification Quad 2-input multiplexer 74LVC157A handbook, halfpage 2 1I0 3 1I1 5 2I0 6 2I1 11 3I0 10 3I1 14 4I0 13 4I1 MULTIPLEXER OUTPUTS SELECTOR 1Y 4 2Y 7 3Y 9 4Y 12 S E 1 15 MNA483 Fig.5 Functional diagram. handbook, halfpage S E 1I1 1Y 1I0 2I1 2Y 2I0 3I1 3Y 3I0 4I1 4Y 4I0 MNA484 Fig.6 Logic diagram. 2003 Dec 02 5 Philips Semiconductors Product specification Quad 2-input multiplexer 74LVC157A RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER supply voltage CONDITIONS MIN. MAX. UNIT for maximum speed performance 2.7 3.6 V for low voltage applications 1.2 3.6 V 0 5.5 V VI input voltage VO output voltage 0 VCC V Tamb operating ambient temperature −40 +125 °C tr, tf input rise and fall times VCC = 1.2 to 2.7 V 0 20 ns/V VCC = 2.7 to 3.6 V 0 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. −0.5 MAX. VCC supply voltage IIK input diode current VI < 0 − −50 mA VI input voltage note 1 −0.5 +6.5 V IOK output diode current VO > VCC or VO < 0 − ±50 mA VO output voltage note 1 −0.5 VCC + 0.5 V IO output source or sink current VO = 0 to VCC − ±50 mA ICC, IGND VCC or GND current − ±100 mA Tstg storage temperature −65 +150 °C PD power dissipation − 500 mW Tamb = −40 to +125 °C; note 2 +6.5 UNIT V Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO16 packages: above 70 °C the value of PD derates linearly with 8 mW/K. For (T)SSOP16 packages: above 60 °C the value of PD derates linearly with 5.5 mW/K. For DHVQFN16 packages: above 60 °C the value of PD derates linearly with 4.5 mW/K. 2003 Dec 02 6 Philips Semiconductors Product specification Quad 2-input multiplexer 74LVC157A DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER TYP.(1) MIN. OTHER MAX. UNIT VCC (V) Tamb = −40 to +85 °C VIH VIL LOW-level input voltage VOH HIGH-level output voltage VOL 1.2 VCC − − V 2.7 to 3.6 2.0 − − V 1.2 − − GND V 2.7 to 3.6 − − 0.8 V IO = −100 µA 2.7 to 3.6 VCC − 0.2 − − V IO = −12 mA 2.7 VCC − 0.5 − − V IO = −18 mA 3.0 VCC − 0.6 − − V IO = −24 mA 3.0 VCC − 0.8 − − V IO = 100 µA 2.7 to 3.6 − − 0.2 V IO = 12 mA 2.7 − − 0.4 V IO = 24 mA 3.0 − − 0.55 V HIGH-level input voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL ILI input leakage current VI = 5.5 V or GND 3.6 − ±0.1 ±5 µA ICC quiescent supply current VI = VCC or GND; IO = 0 3.6 − 0.1 10 µA ∆ICC additional quiescent VI =VCC − 0.6 V; supply current per IO = 0 input pin 2.7 to 3.6 − 5 500 µA 2003 Dec 02 7 Philips Semiconductors Product specification Quad 2-input multiplexer 74LVC157A TEST CONDITIONS SYMBOL PARAMETER TYP.(1) MIN. OTHER MAX. UNIT VCC (V) Tamb = −40 to +125 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage 1.2 VCC − − V 2.7 to 3.6 2.0 − − V 1.2 − − GND V 2.7 to 3.6 − − 0.8 V VI = VIH or VIL IO = −100 µA 2.7 to 3.6 VCC − 0.3 − − V IO = −12 mA 2.7 VCC − 0.65 − − V IO = −18 mA 3.0 VCC − 0.75 − − V IO = −24 mA 3.0 VCC − 1 − − V IO = 100 µA 2.7 to 3.6 − − 0.3 V IO = 12 mA 2.7 − − 0.6 V IO = 24 mA 3.0 − − 0.8 V VI = VIH or VIL ILI input leakage current VI = 5.5 V or GND 3.6 − − ±20 µA ICC quiescent supply current VI = VCC or GND; IO = 0 3.6 − − 40 µA ∆ICC additional quiescent VI =VCC − 0.6 V; supply current per IO = 0 input pin 2.7 to 3.6 − − 5000 µA Note 1. All typical values are measured at Tamb = 25 °C. 2003 Dec 02 8 Philips Semiconductors Product specification Quad 2-input multiplexer 74LVC157A AC CHARACTERISTICS GND = 0 V; tr = tf ≤ 2.5 ns. TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = −40 to +85 °C; note 1 tPHL/tPLH propagation delay nI0, nI1 to nY propagation delay E to nY propagation delay S to nY tsk(0) skew − 16 2.7 1.0 3.0 5.9 ns 3.0 to 3.6 1.0 2.6(2) 5.2 ns − 17 − ns 2.7 1.0 3.4 7.8 ns 3.0 to 3.6 1.0 2.8(2) 6.5 ns − 16 − ns 2.7 1.0 3.0 7.3 ns 3.0 to 3.6 1.0 2.6(2) 6.3 ns 3.0 to 3.6 − − 1.0 ns − − − ns 1.0 − 7.5 ns see Figs 8 and 9 1.2 see Figs 7 and 9 1.2 see Figs 8 and 9 1.2 note 3 − ns Tamb = −40 to +125 °C tPHL/tPLH propagation delay nI0, nI1 to nY see Figs 8 and 9 1.2 propagation delay E to nY see Figs 7 and 9 1.2 2.7 1.0 − 6.5 ns − − − ns 2.7 1.0 − 10.0 ns 3.0 to 3.6 1.0 − 8.5 ns 3.0 to 3.6 propagation delay S to nY tsk(0) skew − − − ns 2.7 1.0 − 9.5 ns 3.0 to 3.6 1.0 − 8.0 ns 3.0 to 3.6 − − 1.5 ns see Figs 8 and 9 1.2 note 3 Notes 1. All typical values are measured at Tamb = 25 °C. 2. This typical value is measured at VCC = 3.3 V and Tamb = 25 °C. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 2003 Dec 02 9 Philips Semiconductors Product specification Quad 2-input multiplexer 74LVC157A AC WAVEFORMS handbook, halfpage VCC VM E input GND t PHL t PLH VOH VM nY output VOL MNA485 INPUT VCC VM VI tr = tf 1.2 V 0.5 × VCC VCC ≤ 2.5 ns 2.7 V 1.5 V 2.7 V ≤ 2.5 ns 3.0 to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns VOL and VOH are typical output voltage drop that occur with the output load. Fig.7 Enable input (E) to output (nY) propagation delays. handbook, halfpage VI nI0, nI1, S VM input GND t PHL t PLH VOH VM nY output VOL MNA486 INPUT VCC VM VI tr = tf 1.2 V 0.5 × VCC VCC ≤ 2.5 ns 2.7 V 1.5 V 2.7 V ≤ 2.5 ns 3.0 to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns VOL and VOH are typical output voltage drop that occur with the output load. Fig.8 Data inputs (nI0, nI1) and common data select input (S) to output (nY) propagation delays. 2003 Dec 02 10 Philips Semiconductors Product specification Quad 2-input multiplexer 74LVC157A 2 × VCC open GND S1 handbook, full pagewidth VCC VI PULSE GENERATOR RL 500 Ω VO D.U.T. CL 50 pF RT RL 500 Ω MNA368 VCC VI CL RL Ω(1) VEXT tPLH/tPHL tPZH/tPHZ tPZL/tPLZ 1.2 V VCC 50 pF 500 open GND 2 × VCC 2.7 V 2.7 V 50 pF 500 Ω open GND 2 × VCC 3.0 to 3.6 V 2.7 V 50 pF 500 Ω open GND 2 × VCC Note 1. The circuit performs better when RL = 1000 Ω. Definitions for test circuits: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.9 Load circuitry for switching times. 2003 Dec 02 11 Philips Semiconductors Product specification Quad 2-input multiplexer 74LVC157A PACKAGE OUTLINES SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 inches 0.244 0.041 0.228 θ Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 2003 Dec 02 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 12 o 8 0o Philips Semiconductors Product specification Quad 2-input multiplexer 74LVC157A SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 2003 Dec 02 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 13 o Philips Semiconductors Product specification Quad 2-input multiplexer 74LVC157A TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 2003 Dec 02 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 14 o Philips Semiconductors Product specification Quad 2-input multiplexer 74LVC157A DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 0.5 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- 2003 Dec 02 15 EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Philips Semiconductors Product specification Quad 2-input multiplexer 74LVC157A DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2003 Dec 02 16 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA75 © Koninklijke Philips Electronics N.V. 2003 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R20/05/pp17 Date of release: 2003 Dec 02 Document order number: 9397 750 12371