INTEGRATED CIRCUITS DATA SHEET 74HC00; 74HCT00 Quad 2-input NAND gate Product specification Supersedes data of 1997 Aug 26 2003 Jun 30 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 FEATURES DESCRIPTION • Complies with JEDEC standard no. 8-1A The 74HC00/74HCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V The 74HC00/74HCT00 provide the 2-input NAND function. • Specified from −40 to +85 °C and −40 to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. TYPICAL SYMBOL PARAMETER CONDITIONS UNIT 74HC00 74HCT00 tPHL/tPLH propagation delay nA, nB to nY 7 10 ns CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per gate notes 1 and 2 22 22 pF CL = 15 pF; VCC = 5 V Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. For 74HC00 the condition is VI = GND to VCC. For 74HCT00 the condition is VI = GND to VCC − 1.5 V. FUNCTION TABLE See note 1. INPUT OUTPUT nA nB nY L L H L H H H L H H H L Note 1. H = HIGH voltage level; L = LOW voltage level. 2003 Jun 30 2 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE 74HC00N −40 to +125 °C 14 DIP14 plastic SOT27-1 74HCT00N −40 to +125 °C 14 DIP14 plastic SOT27-1 74HC00D −40 to +125 °C 14 SO14 plastic SOT108-1 74HCT00D −40 to +125 °C 14 SO14 plastic SOT108-1 74HC00DB −40 to +125 °C 14 SSOP14 plastic SOT337-1 74HCT00DB −40 to +125 °C 14 SSOP14 plastic SOT337-1 74HC00PW −40 to +125 °C 14 TSSOP14 plastic SOT402-1 74HCT00PW −40 to +125 °C 14 TSSOP14 plastic SOT402-1 74HC00BQ −40 to +125 °C 14 DHVQFN14 plastic SOT762-1 74HCT00BQ −40 to +125 °C 14 DHVQFN14 plastic SOT762-1 PINNING PIN SYMBOL DESCRIPTION 1 1A data input 2 1B data input 3 1Y data output 4 2A 5 handbook, halfpage 1A 1 14 VCC data input 1B 2 13 4B 2B data input 1Y 3 12 4A 6 2Y data output 2A 4 7 GND ground (0 V) 2B 5 10 3B 8 3Y data output 2Y 6 9 3A 9 3A data input GND 7 8 3Y 10 3B data input 11 4Y data output 12 4A data input 13 4B data input 14 VCC supply voltage 00 11 4Y MNA210 2003 Jun 30 Fig.1 3 Pin configuration DIP14, SO14 and (T)SSOP14. Philips Semiconductors Product specification Quad 2-input NAND gate handbook, halfpage 1A VCC 1 14 74HC00; 74HCT00 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 2B 5 10 3B 2Y 6 9 3A GND(1) handbook, halfpage A Y B Top view 7 8 GND 3Y MNA211 MNA950 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.2 Pin configuration DHVQFN14. Fig.3 Logic diagram (one gate). handbook, halfpage handbook, halfpage 1 & 3 & 6 & 8 & 11 2 1 2 1A 1B 4 5 2A 2B 2Y 6 5 9 10 3A 3B 3Y 8 9 1Y 3 4 10 12 13 4A 4B 4Y 11 12 13 MNA212 MNA246 Fig.4 Function diagram. 2003 Jun 30 Fig.5 IEC logic symbol. 4 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 RECOMMENDED OPERATING CONDITIONS 74HC00 SYMBOL PARAMETER 74HCT00 CONDITIONS UNIT MIN. TYP. MAX. MIN. TYP. MAX. VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 − VCC 0 − VCC V VO output voltage 0 − VCC 0 − VCC V Tamb operating ambient temperature +25 +125 −40 +25 +125 °C tr, tf input rise and fall times see DC and AC −40 characteristics per device VCC = 2.0 V − − 1000 − − − ns VCC = 4.5 V − 6.0 500 − 6.0 500 ns VCC = 6.0 V − − 400 − − − ns LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT −0.5 +7.0 V − ±20 mA VCC supply voltage IIK input diode current IOK output diode current VO < −0.5 V or VO > VCC + 0.5 V − ±20 mA IO output source or sink current −0.5 V < VO < VCC + 0.5 V − ±25 mA ICC, IGND VCC or GND current − ±50 mA Tstg storage temperature Ptot power dissipation VI < −0.5 V or VI > VCC + 0.5 V Tamb = −40 to +125 °C; note 1 −65 +150 °C − 500 mW Note 1. For DIP14 packages: above 70 °C derate linearly with 12 mW/K. For SO14 packages: above 70 °C derate linearly with 8 mW/K. For SSOP14 and TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K. 2003 Jun 30 5 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 DC CHARACTERISTICS Type 74HC00 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 to +85 °C; note 1 VIH VIL VOH VOL 2.0 1.5 1.2 − V 4.5 3.15 2.4 − V 6.0 4.2 3.2 − V 2.0 − 0.8 0.5 V 4.5 − 2.1 1.35 V 6.0 − 2.8 1.8 V IO = −20 µA 2.0 1.9 2.0 − V IO = −20 µA 4.5 4.4 4.5 − V IO = −20 µA 6.0 5.9 6.0 − V IO = −4.0 mA 4.5 3.84 4.32 − V IO = −5.2 mA 6.0 5.34 5.81 − V IO = 20 µA 2.0 − 0 0.1 V IO = 20 µA 4.5 − 0 0.1 V IO = 20 µA 6.0 − 0 0.1 V IO = 4.0 mA 4.5 − 0.15 0.33 V IO = 5.2 mA 6.0 − 0.16 0.33 V VI = VCC or GND 6.0 − − ±1.0 µA 6.0 − − ±.5.0 µA VI = VCC or GND; IO = 0 6.0 − − 20 µA HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL ILI input leakage current IOZ 3-state output OFF current VI = VIH or VIL; VO = VCC or GND ICC quiescent supply current 2003 Jun 30 6 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 to +125 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level output voltage − − V 4.5 3.15 − − V 4.2 − − V 2.0 − − 0.5 V 4.5 − − 1.35 V 6.0 − − 1.8 V IO = −20 µA 2.0 1.9 − − V IO = −20 µA 4.5 4.4 − − V IO = −20 µA 6.0 5.9 − − V IO = −4.0 mA 4.5 3.7 − − V IO = −5.2 mA 6.0 5.2 − − V IO = 20 µA 2.0 − − 0.1 V IO = 20 µA 4.5 − − 0.1 V IO = 20 µA 6.0 − − 0.1 V IO = 4.0 mA 4.5 − − 0.4 V IO = 5.2 mA 6.0 − − 0.4 V VI = VIH or VIL VI = VIH or VIL 6.0 − − ±1.0 µA 6.0 − − ±10.0 µA VI = VCC or GND; IO = 0 6.0 − − 40 µA ILI input leakage current IOZ 3-state output OFF current VI = VIH or VIL; VO = VCC or GND ICC quiescent supply current VI = VCC or GND Note 1. All typical values are measured at Tamb = 25 °C. 2003 Jun 30 1.5 6.0 LOW-level input voltage HIGH-level output voltage 2.0 7 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 Type 74HCT00 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 to +85 °C; note 1 VIH HIGH-level input voltage 4.5 to 5.5 2.0 1.6 − V VIL LOW-level input voltage 4.5 to 5.5 − 1.2 0.8 V VOH HIGH-level output voltage IO = −20 µA 4.5 4.4 4.5 − V IO = −4.0 mA 4.5 3.84 4.32 − V VOL LOW-level output voltage VI = VIH or VIL VI = VIH or VIL IO = 20 µA 4.5 − 0 0.1 V IO = 4.0 mA 4.5 − 0.15 0.33 V ILI input leakage current VI = VCC or GND 5.5 − − ±1.0 µA IOZ 3-state output OFF current VI = VIH or VIL; 5.5 VO = VCC or GND; IO = 0 − − ±5.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 20 µA ∆ICC additional supply current per input VI = VCC − 2.1 V; IO = 0 4.5 to 5.5 − 150 675 µA Tamb = −40 to +125 °C VIH HIGH-level input voltage 4.5 to 5.5 2.0 − − V VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 V VOH HIGH-level output voltage IO = −20 µA 4.5 4.4 − − V IO = −4.0 mA 4.5 3.7 − − V IO = 20 µA 4.5 − − 0.1 V IO = 4.0 mA 4.5 − − 0.4 V VOL LOW-level output voltage VI = VIH or VIL VI = VIH or VIL ILI input leakage current VI = VCC or GND 5.5 − − ±1.0 µA IOZ 3-state output OFF current VI = VIH or VIL; 5.5 VO = VCC or GND; IO = 0 − − ±10 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 40 µA ∆ICC additional supply current per input VI = VCC − 2.1 V; IO = 0 4.5 to 5.5 − − 735 µA Note 1. All typical values are measured at Tamb = 25 °C. 2003 Jun 30 8 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 AC CHARACTERISTICS Type 74HC00 GND = 0 V; tr = tf = 6 ns; CL = 50 pF. TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = −40 to +85 °C; note 1 tPHL/tPLH tTHL/tTLH propagation delay nA, nB to nY see Fig.6 2.0 − 25 115 ns see Fig.6 4.5 − 9 23 ns see Fig.6 6.0 − 7 20 ns 2.0 − 19 95 ns 4.5 − 7 19 ns 6.0 − 6 16 ns see Fig.6 2.0 − − 135 ns see Fig.6 4.5 − − 27 ns see Fig.6 6.0 − − 23 ns 2.0 − − 110 ns 4.5 − − 22 ns 6.0 − − 19 ns output transition time Tamb = −40 to +125 °C tPHL/tPLH tTHL/tTLH propagation delay nA, nB to nY output transition time Note 1. All typical values are measured at Tamb = 25 °C. Type 74HCT00 GND = 0 V; tr = tf = 6 ns; CL = 50 pF TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP MAX. UNIT VCC (V) Tamb = −40 to +85 °C; note 1 tPHL/tPLH propagation delay nA, nB to nY tTHL/tTLH output transition time see Fig.6 4.5 − 12 24 ns 4.5 − − 29 ns 4.5 − − 29 ns 4.5 − − 22 ns Tamb = −40 to +125 °C tPHL/tPLH propagation delay nA, nB to nY tTHL/tTLH output transition time see Fig.6 Note 1. All typical values are measured at Tamb = 25 °C. 2003 Jun 30 9 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 AC WAVEFORMS handbook, halfpage VI VM nA, nB input GND tPHL tPLH VOH VM nY output VOL tTHL tTLH MNA218 74HC00: VM = 50%; VI = GND to VCC. 74HCT00: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the input (nA, nB) to output (nY) propagation delays. 2003 Jun 30 10 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 PACKAGE OUTLINES DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.2 inches 0.17 0.02 0.13 0.068 0.044 0.021 0.015 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT27-1 050G04 MO-001 SC-501-14 2003 Jun 30 11 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.05 0.028 0.024 0.01 0.01 0.004 0.028 0.012 inches 0.069 0.244 0.039 0.041 0.228 0.016 θ Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 2003 Jun 30 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 12 o 8 0o Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.4 0.9 8 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 2003 Jun 30 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 13 o Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 2003 Jun 30 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 14 o Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 0.5 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- 2003 Jun 30 15 EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2003 Jun 30 16 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA75 © Koninklijke Philips Electronics N.V. 2003 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 613508/03/pp17 Date of release: 2003 Jun 30 Document order number: 9397 750 11258