INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4094B MSI 8-stage shift-and-store bus register Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4094B MSI 8-stage shift-and-store bus register Two serial outputs (Os and O’s) are available for cascading a number of HEF4094B devices. Data is available at Os on positive-going clock edges to allow high-speed operation in cascaded systems in which the clock rise time is fast. The same serial information is available at O’s on the next negative-going clock edge and provides cascading HEF4094B devices when the clock rise time is slow. DESCRIPTION The HEF4094B is an 8-stage serial shift register having a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs O0 to O7. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive-going clock transitions. The data in each shift register stage is transferred to the storage register when the strobe (STR) input is HIGH. Data in the storage register appears at the outputs whenever the output enable (EO) signal is HIGH. Fig.2 Pinning diagram. HEF4094BP(N): 16-lead DIL; plastic (SOT38-1) HEF4094BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4094BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING Fig.1 Functional diagram. D data input EO output enable input CP clock input Os, O’s serial outputs STR strobe input O0 to O7 parallel outputs FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Philips Semiconductors 8-stage shift-and-store bus register January 1995 3 Fig.3 Logic diagram. Product specification HEF4094B MSI Fig.4 One D-latch. Philips Semiconductors Product specification HEF4094B MSI 8-stage shift-and-store bus register FUNCTION TABLE INPUTS CP PARALLEL OUTPUTS SERIAL OUTPUTS EO STR D O0 On Os O’s L X X Z Z O’6 nc L X X Z Z nc O7 H L X nc nc O’6 nc H H L L On-1 O’6 nc H H H H On-1 O’6 nc H H H nc nc nc O7 Notes 1. H = HIGH state (the more positive voltage) 2. L = LOW state (the less positive voltage) 3. X = state is immaterial 4. = positive-going transition 5. = negative-going transition 6. Z = high impedance off state 7. nc = no change 8. O’6 = the information in the seventh shift register stage At the positive clock edge the information in the 7th register stage is transferred to the 8th register stage and the Os output. AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns VDD V Dynamic power 5 TYPICAL FORMULA FOR P (µW) 2100 fi + ∑ (foCL) × VDD2 where fi = input freq. (MHz) dissipation per 10 9700 fi + ∑ (foCL) × package (P) 15 26 000 fi + ∑ (foCL) × VDD2 VDD2 fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 4 Philips Semiconductors Product specification HEF4094B MSI 8-stage shift-and-store bus register AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL TYP. TYPICAL EXTRAPOLATION FORMULA MAX. Propagation delays CP → Os HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 CP → O’s HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 CP → On HIGH to LOW LOW to HIGH STR → On HIGH to LOW LOW to HIGH Output transition times HIGH to LOW LOW to HIGH 270 ns 108 ns + (0,55 ns/pF) CL 65 130 ns 54 ns + (0,23 ns/pF) CL 50 100 ns 42 ns + (0,16 ns/pF) CL 105 210 ns 78 ns + (0,55 ns/pF) CL 50 100 ns 39 ns + (0,23 ns/pF) CL 40 80 ns 32 ns + (0,16 ns/pF) CL 105 210 ns 78 ns + (0,55 ns/pF) CL 50 100 ns 39 ns + (0,23 ns/pF) CL 40 80 ns 32 ns + (0,16 ns/pF) CL 105 210 ns 78 ns + (0,55 ns/pF) CL 50 100 ns 39 ns + (0,23 ns/pF) CL 40 80 ns 32 ns + (0,16 ns/pF) CL 165 330 ns 138 ns + (0,55 ns/pF) CL 75 150 ns 64 ns + (0,23 ns/pF) CL 15 55 110 ns 47 ns + (0,16 ns/pF) CL 5 150 300 ns 123 ns + (0,55 ns/pF) CL 5 10 tPHL 70 140 ns 59 ns + (0,23 ns/pF) CL 15 55 110 ns 47 ns + (0,16 ns/pF) CL 5 110 220 ns 83 ns + (0,55 ns/pF) CL 10 tPLH 50 100 ns 39 ns + (0,23 ns/pF) CL 15 35 70 ns 27 ns + (0,16 ns/pF) CL 5 100 200 ns 73 ns + (0,55 ns/pF) CL 10 tPHL 45 90 ns 34 ns + (0,23 ns/pF) CL 15 35 70 ns 27 ns + (0,16 ns/pF) CL 5 60 120 ns 10 ns + (1,0 ns/pF) CL 10 tPLH 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 10 10 15 January 1995 135 tTHL tTLH 5 10 ns + (1,0 ns/pF) CL Philips Semiconductors Product specification HEF4094B MSI 8-stage shift-and-store bus register AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL MIN. TYP. MAX. 3-state propagation delays Output enable times EO → On 5 10 HIGH 15 LOW 10 tPZH 5 tPZL 15 Output disable times EO → On 5 10 HIGH 15 LOW 10 tPHZ 5 tPLZ 15 Minimum clock 5 pulse width 10 LOW 40 80 ns 25 50 ns 20 40 ns 40 80 ns 25 50 ns 20 40 ns 75 150 ns 40 80 ns 30 60 ns 80 160 ns 40 80 ns 30 60 ns 60 30 ns 30 15 ns 15 24 12 ns Minimum strobe 5 40 20 ns pulse width 10 30 15 ns HIGH 15 24 12 ns Set-up times 5 60 30 ns D → CP 10 Hold times D → CP Maximum clock pulse frequency tWCPL tWSTRH tsu 20 10 ns 15 15 5 ns 5 5 −15 ns 10 thold 20 5 ns 15 20 5 ns 5 5 10 MHz 11 22 MHz 14 28 MHz 10 fmax 15 January 1995 6 Philips Semiconductors Product specification HEF4094B MSI 8-stage shift-and-store bus register Fig.5 Timing diagram. APPLICATION INFORMATION Some examples of applications for the HEF4094B are: • Serial-to-parallel data conversion • Remote control holding register Fig.6 Remote control holding register. January 1995 7