PHILIPS HEF4521BT

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4521B
MSI
24-stage frequency divider and
oscillator
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
24-stage frequency divider and oscillator
operation as a crystal oscillator is enabled by connecting
external resistors to pins 3 (VSS’) and 5 (VDD’).
Each flip-flop divides the frequency of the previous flip-flop
by two, consequently the HEF4521B will count up to
224 = 16777216. The counting advances on the HIGH to
LOW transition of the clock (I2). The outputs of the last
seven stages are available for additional flexibility.
DESCRIPTION
The HEF4521B consists of a chain of 24 toggle flip-flops
with an overriding asynchronous master reset input (MR),
and an input circuit that allows three modes of operation.
The single inverting stage (I2/O2) will function as a crystal
oscillator, or in combination with I1 as an RC oscillator, or
as an input buffer for an external oscillator. Low-power
Fig.1 Functional diagram.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995
HEF4521B
MSI
2
Philips Semiconductors
Product specification
HEF4521B
MSI
24-stage frequency divider and oscillator
COUNT CAPACITY
OUTPUT
Fig.2 Pinning diagram.
COUNT CAPACITY
O18
218
= 262 144
O19
219
= 524 288
O20
220 = 1 048 576
O21
221 = 2 097 152
O22
222 = 4 194 304
O23
223 = 8 388 608
O24
224 = 16 777 216
HEF4521BP(N): 16-lead DIL; plastic (SOT38-1)
HEF4521BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)
HEF4521BT(D): 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
FUNCTIONAL TEST SEQUENCE
CONTROL
TERMINALS
INPUTS
OUTPUTS
REMARKS
MR
I2
O2
VSS’
VDD’
O18 to O24
H
L
L
VDD
VSS
L
counter is in three 8-stage sections
in parallel mode; I2 and O2 are
interconnected (O2 is now input);
counter is reset by MR
VDD
VSS
H
255 pulses are clocked into I2, O2
(the counter advances on the LOW
to HIGH transition)
L
L
L
L
VSS
VSS
H
VSS’ is connected to VSS
L
H
L
VSS
VSS
H
the input I2 is made HIGH
L
H
L
VSS
VDD
H
VDD’ is connected to VDD; O2 is
now made floating and becomes an
output; the device is now in the
224 mode
VSS
VDD
L
L
A test function has been included for the reduction of the
test time required to exercise all 24 counter stages. This
test function divides the counter into three 8-stage
sections by connecting VSS’ to VDD and VDD’ to VSS. Via
I2 (connected to O2) 255 counts are loaded into each of
the 8-stage sections in parallel. All flip-flops are now at a
HIGH state.
January 1995
counter ripples from an all HIGH
state to an all LOW state
The counter is now returned to the normal 24-stage in
series configuration by connecting VSS’ to VSS and VDD’ to
VDD. One more pulse is entered into input I2, which will
cause the counter to ripple from an all HIGH state to an all
LOW state.
3
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Philips Semiconductors
4
24-stage frequency divider and oscillator
January 1995
Product specification
HEF4521B
MSI
Fig.3 Logic diagram; for schematic diagram of clock circuit see Fig.4.
Philips Semiconductors
Product specification
HEF4521B
MSI
24-stage frequency divider and oscillator
Fig.4 Schematic diagram of clock input circuitry.
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
MIN.
TYP.
TYPICAL
EXTRAPOLATION
FORMULA
MAX.
Propagation delays
I2 → O18
HIGH to LOW
LOW to HIGH
On → On + 1
HIGH to LOW
LOW to HIGH
MR → On
HIGH to LOW
I1 → O1
HIGH to LOW
LOW to HIGH
5
950
ns
923 ns + (0,55 ns/pF) CL
350
700
ns
339 ns + (0,23 ns/pF) CL
15
220
440
ns
212 ns + (0,16 ns/pF) CL
5
950
1900
ns
923 ns + (0,55 ns/pF) CL
350
700
ns
339 ns + (0,23 ns/pF) CL
15
220
440
ns
212 ns + (0,16 ns/pF) CL
5
40
80
ns
13 ns + (0,55 ns/pF) CL
15
30
ns
4 ns + (0,23 ns/pF) CL
10
10
10
tPHL
tPLH
tPHL
15
10
20
ns
2 ns + (0,16 ns/pF) CL
5
40
80
ns
13 ns + (0,55 ns/pF) CL
15
30
ns
4 ns + (0,23 ns/pF) CL
10
tPLH
15
10
20
ns
2 ns + (0,16 ns/pF) CL
5
120
240
ns
93 ns + (0,55 ns/pF) CL
55
110
ns
44 ns + (0,23 ns/pF) CL
10
tPHL
15
40
80
ns
32 ns + (0,16 ns/pF) CL
5
90
180
ns
63 ns + (0,55 ns/pF) CL
35
70
ns
24 ns + (0,23 ns/pF) CL
10
tPHL
15
25
50
ns
17 ns + (0,16 ns/pF) CL
5
60
120
ns
33 ns + (0,55 ns/pF) CL
30
60
ns
19 ns + (0,23 ns/pF) CL
20
40
ns
12 ns + (0,16 ns/pF) CL
10
tPLH
15
January 1995
1900
5
Philips Semiconductors
Product specification
HEF4521B
MSI
24-stage frequency divider and oscillator
VDD
V
Output transition times
HIGH to LOW
LOW to HIGH
SYMBOL
MIN.
TYP.
5
TYPICAL
EXTRAPOLATION
FORMULA
MAX.
60
120
ns
10 ns + (1,0 ns/pF) CL
30
60
ns
9 ns + (0,42 ns/pF) CL
15
20
40
ns
6 ns + (0,28 ns/pF) CL
5
60
120
ns
10
tTHL
10
tTLH
15
10 ns + (1,0 ns/pF) CL
30
60
ns
9 ns + (0,42 ns/pF) CL
20
40
ns
6 ns + (0,28 ns/pF) CL
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
Minimum I2 pulse
5
width; HIGH
10
Minimum MR
pulse width; HIGH
Recovery time
for MR
Maximum clock
pulse frequency
SYMBOL
TYP.
MAX.
80
40
ns
40
20
ns
15
30
15
ns
5
70
35
ns
40
20
ns
15
30
15
ns
5
20
−10
ns
tWI2H
10
tWMRH
15
−5
ns
15
15
0
ns
5
6
12
MHz
12
25
MHz
17
35
MHz
10
tRMR
10
fmax
15
VDD
V
Dynamic power
MIN.
5
see also waveforms
Fig.5
TYPICAL FORMULA FOR P (µW)
1 200 fi + ∑ (foCL) × VDD2
where
fi = input freq. (MHz)
dissipation per
10
5 100 fi + ∑ (foCL) ×
package (P)
15
13 050 fi + ∑ (foCL) ×
VDD2
VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
6
Philips Semiconductors
Product specification
24-stage frequency divider and oscillator
HEF4521B
MSI
Fig.5 Waveforms showing minimum pulse widths for MR and I2, recovery time for MR.
January 1995
7
Philips Semiconductors
Product specification
HEF4521B
MSI
24-stage frequency divider and oscillator
APPLICATION INFORMATION
(1) Optional for low power operation.
Fig.6 Crystal oscillator circuit.
Typical characteristics for crystal oscillator circuit (Fig.6):
500 kHz
CIRCUIT
50 kHz
CIRCUIT
UNIT
Crystal characteristics
resonance frequency
500
50
kHz
crystal cut
S
N
−
equivalent resistance; RS
1
6,2
kΩ
Ro
47
750
kΩ
CT
82
82
pF
CS
20
20
pF
External resistor/capacitor values
January 1995
8
Philips Semiconductors
Product specification
HEF4521B
MSI
24-stage frequency divider and oscillator
Fig.7
RC oscillator circuit;
1
f ≈ ------------------------------------ ; R S ≥ 2 R TC, in which:
2,3 × R TC × C
f in Hz, R in Ω, C in F.
V IL max
R S + R TC < -----------------I LI
( maximum input voltage LOW )
( input leakage current )
   RTC; C = 1 nF; RS ≈ 2 RTC
 C; RTC = 56 kΩ; RS = 120 kΩ
Fig.8
January 1995
9
Oscillator frequency as a
function of RTC and C;
VDD = 10 V; test circuit is
Fig.7.
Philips Semiconductors
Product specification
24-stage frequency divider and oscillator
Fig.9
HEF4521B
MSI
Test set-up for measuring forward transconductance gfs = dio/dvi at vo is constant (see also graph Fig.10).
A: average,
B: average + 2 s,
C: average − 2 s, in which: ‘s’ is the observed standard deviation.
Fig.10 Typical forward transconductance gfs as a function of the supply voltage at Tamb = 25 °C.
January 1995
10
Philips Semiconductors
Product specification
HEF4521B
MSI
24-stage frequency divider and oscillator
Fig.11 Voltage gain VO/VI as a function of supply
voltage.
Fig.12 Supply current as a function of supply
voltage.
Fig.13 Test set-up for measuring graphs of Figs 11 and 12.
January 1995
11
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