74HC594; 74HCT594 8-bit shift register with output register Rev. 03 — 20 December 2006 Product data sheet 1. General description The 74HC594; 74HCT594 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC594; 74HCT594 is an 8-bit, non-inverting, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks (SHCP and STCP) and direct overriding clears (SHR and STR) are provided on both the shift and storage registers. A serial output (Q7S) is provided for cascading purposes. Both the shift and storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register will always be one count pulse ahead of the storage register. 2. Features n n n n n n n n Synchronous serial input and output Complies with JEDEC standard No.7A 8-bit parallel output Shift and storage registers have independent direct clear and clocks Independent clocks for shift and storage registers 100 MHz (typical) Multiple package options Specified from −40 °C to +85 °C and from −40 °C to +125 °C 3. Applications n Serial-to parallel data conversion n Remote control holding register 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC594D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC594DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74HC594N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HCT594D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HCT594DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74HCT594N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 5. Functional diagram DS SHCP SHR 14 11 8-STAGE SHIFT REGISTER 10 9 STCP STR Q7S 12 13 8-BIT STORAGE REGISTER 15 1 2 3 4 5 6 7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mbc320 Fig 1. Functional diagram 74HC_HCT594_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 2 of 26 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register SHCP STCP STR 11 12 STCP Q7S 9 DS SHR R2 12 C2 10 R1 SRG8 11 15 Q0 1 Q1 2 Q2 3 Q3 2 4 Q4 3 5 Q5 4 6 Q6 7 Q7 14 10 13 SHR STR SHCP DS C1/ 14 1D 15 2D 1 5 6 7 9 mbc319 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q7S mbc322 Fig 2. Logic symbol Fig 3. IEC logic symbol STAGES 1 TO 6 STAGE 0 DS 13 D Q D STAGE 7 Q FFSH0 D Q7S Q FFSH7 CP CP R R SHCP SHR D D Q FFST0 Q FFST7 CP CP R R STCP STR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mbc321 Fig 4. Logic diagram 74HC_HCT594_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 3 of 26 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register SHCP DS STCP SHR STR Q0 Q1 Q6 Q7 Q7S mbc323 Fig 5. Timing diagram 6. Pinning information 6.1 Pinning 74HC594 74HCT594 Q1 1 16 VCC Q2 2 15 Q0 Q3 3 14 DS Q4 4 13 STR Q5 5 12 STCP Q6 6 11 SHCP Q7 7 10 SHR GND 8 9 Q7S 001aaf611 Fig 6. Pin configuration SO16 74HC_HCT594_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 4 of 26 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register 74HC594 74HCT594 74HC594 74HCT594 Q1 1 16 VCC Q2 2 15 Q0 Q3 3 14 DS Q1 1 16 VCC Q2 2 15 Q0 Q4 4 13 STR Q3 3 14 DS Q5 5 12 STCP Q4 4 13 STR Q5 5 12 STCP Q6 6 11 SHCP Q6 6 11 SHCP Q7 7 10 SHR Q7 7 10 SHR GND 8 GND 8 9 Q7S 9 Q7S 001aaf614 001aaf613 Fig 7. Pin configuration SSOP16 Fig 8. Pin configuration DIP16 6.2 Pin description Table 2. Pin description Symbol Pin Description Q1 1 parallel data output 1 Q2 2 parallel data output 2 Q3 3 parallel data output 3 Q4 4 parallel data output 4 Q5 5 parallel data output 5 Q6 6 parallel data output 6 Q7 7 parallel data output 7 GND 8 ground (0 V) Q7S 9 serial data output SHR 10 shift register reset (active LOW) SHCP 11 shift register clock input STCP 12 storage register clock input STR 13 storage register reset (active LOW) DS 14 serial data input Q0 15 parallel data output 0 VCC 16 supply voltage 74HC_HCT594_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 5 of 26 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register 7. Functional description Table 3. Function table[1] Function Input SHR STR SHCP STCP DS Clear shift register L X X X Clear storage register X L X X X Load DS into shift register stage 0, advance previous stage data to the next stage H X ↑ X H or L Transfer shift register data to storage register and outputs Qn X H X ↑ X Shift register one count pulse ahead of storage register H H ↑ ↑ X [1] X H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH transition; X = don’t care. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI < −0.5 V or VI > VCC + 0.5 V IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V IO output current VO = −0.5 V to VCC + 0.5 V ICC supply current IGND ground current Conditions Min Max Unit −0.5 +7.0 V [1] - ±20 mA [1] - ±20 mA Serial data output Q7S - ±25 mA Parallel data output - ±35 mA Serial data output Q7S - 50 mA Parallel data output - 70 mA Serial data output Q7S - −50 mA Parallel data output - −70 mA −65 +150 °C - 500 mW storage temperature Tstg total power dissipation Ptot Tamb = −40 °C to +125 °C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For DIP16 packages: above 70 °C the value of Ptot derates linearly with 12 mW/K. For SO16 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K. For SSOP16 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K. 74HC_HCT594_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 6 of 26 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit Type 74HC594 VCC supply voltage 2.0 5.0 6.0 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C tr rise time VCC = 2.0 V - - 1000 ns VCC = 4.5 V - 6.0 500 ns VCC = 6.0 V - - 400 ns VCC = 2.0 V - - 1000 ns VCC = 4.5 V - 6.0 500 ns VCC = 6.0 V - - 400 ns fall time tf Type 74HCT594 VCC supply voltage 4.5 5.0 5.5 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C tr rise time VCC = 4.5 V - 6.0 500 ns tf fall time VCC = 4.5 V - 6.0 500 ns Conditions Min Typ Max Unit VCC = 2.0 V 1.5 1.2 - V VCC = 4.5 V 3.15 2.4 - V 10. Static characteristics Table 6. Static characteristics type 74HC594 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VCC = 6.0 V 4.2 3.2 - V VCC = 2.0 V - 0.8 0.5 V VCC = 4.5 V - 2.1 1.35 V VCC = 6.0 V - 2.8 1.8 V IO = −4.0 mA; VCC = 4.5 V 3.98 4.32 - V IO = −5.2 mA; VCC = 6.0 V 5.48 5.81 - V IO = −6.0 mA; VCC = 4.5 V 3.98 4.32 - V IO = −7.8 mA; VCC = 6.0 V 5.48 5.81 - V VI = VIH or VIL Serial data output Q7S Parallel data outputs 74HC_HCT594_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 7 of 26 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register Table 6. Static characteristics type 74HC594 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VOL LOW-level output voltage VI = VIH or VIL IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 V IO = 6.0 mA; VCC = 4.5 V - 0.15 0.26 V Serial data output Q7S Parallel data outputs IO = 7.8 mA; VCC = 6.0 V - 0.16 0.26 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±0.1 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 µA Ci input capacitance - 3.5 - pF VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V Tamb = −40 °C to +85 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VCC = 6.0 V 4.2 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V IO = −4.0 mA; VCC = 4.5 V 3.84 - - V IO = −5.2 mA; VCC = 6.0 V 5.34 - - V IO = −6.0 mA; VCC = 4.5 V 3.84 - - V IO = −7.8 mA; VCC = 6.0 V 5.34 - - V IO = 4.0 mA; VCC = 4.5 V - - 0.33 V IO = 5.2 mA; VCC = 6.0 V - - 0.33 V IO = 6.0 mA; VCC = 4.5 V - - 0.33 V IO = 7.8 mA; VCC = 6.0 V - - 0.33 V VI = VIH or VIL Serial data output Q7S Parallel data outputs VOL LOW-level output voltage VI = VIH or VIL Serial data output Q7S Parallel data outputs II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±1.0 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 80 µA VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V Tamb = −40 °C to +125 °C VIH HIGH-level input voltage 74HC_HCT594_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 8 of 26 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register Table 6. Static characteristics type 74HC594 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VIL LOW-level input voltage VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V IO = −4.0 mA; VCC = 4.5 V 3.7 - - V IO = −5.2 mA; VCC = 6.0 V 5.2 - - V IO = −6.0 mA; VCC = 4.5 V 3.7 - - V IO = −7.8 mA; VCC = 6.0 V 5.2 - - V IO = 4.0 mA; VCC = 4.5 V - - 0.4 V IO = 5.2 mA; VCC = 6.0 V - - 0.4 V IO = 6.0 mA; VCC = 4.5 V - - 0.4 V IO = 7.8 mA; VCC = 6.0 V - - 0.4 V VOH HIGH-level output voltage VI = VIH or VIL Serial data output Q7S Parallel data outputs VOL LOW-level output voltage VI = VIH or VIL Serial data output Q7S Parallel data outputs II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±1.0 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 160 µA 74HC_HCT594_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 9 of 26 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register Table 7. Static characteristics type 74HCT594 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit Tamb = 25 °C VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 V VOH HIGH-level output voltage VI = VIH or VIL 3.98 4.32 - V 3.98 4.32 - V - 0.15 0.26 V Serial data output Q7S IO = −4.0 mA; VCC = 4.5 V Parallel data outputs IO = −6.0 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL Serial data output Q7S IO = 4.0 mA; VCC = 4.5 V Parallel data outputs IO = 6.0 mA; VCC = 4.5 V - 0.16 0.26 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - ±0.1 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 8.0 µA ∆ICC additional supply current per input pin; VI = VCC − 2.1 V and other inputs at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V pins SHR, SHCP, STCP, STR - 150 540 µA pin DS - 25 90 µA - 3.5 - pF Ci input capacitance Tamb = −40 °C to +85 °C VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL 3.84 - - V 3.84 - - V - - 0.33 V IO = 6.0 mA; VCC = 4.5 V - - 0.33 V Serial data output Q7S IO = −4.0 mA; VCC = 4.5 V Parallel data outputs IO = −6.0 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL Serial data output IO = 4.0 mA; VCC = 4.5 V Parallel data outputs II input leakage current VI = VCC or GND; VCC = 5.5 V - - ±1.0 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 80 µA 74HC_HCT594_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 10 of 26 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register Table 7. Static characteristics type 74HCT594 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit ∆ICC additional supply current per input pin; VI = VCC − 2.1 V and other inputs at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V pins SHR, SHCP, STCP, STR - - 675 µA pin DS - - 112.5 µA Tamb = −40 °C to +125 °C VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL 3.7 - - V 3.7 - - V - - 0.4 V - - 0.4 V Serial data output Q7S IO = −4.0 mA; VCC = 4.5 V Parallel data outputs IO = −6.0 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL Serial data output Q7S IO = 4.0 mA; VCC = 4.5 V Parallel data outputs IO = 6.0 mA; VCC = 4.5 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - ±1.0 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 160 µA ∆ICC additional supply current per input pin; VI = VCC − 2.1 V and other inputs at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V pins SHR, SHCP, STCP, STR - - 735 µA pin DS - - 122.5 µA 74HC_HCT594_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 11 of 26 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register 11. Dynamic characteristics Table 8. Dynamic characteristics type 74HC594 GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 15. Symbol tpd Parameter propagation delay 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V - 44 150 - 185 - 225 ns VCC = 4.5 V - 16 30 - 37 - 45 ns VCC = 5.0 V; CL = 15 pF - 13 - - - - - ns VCC = 6.0 V - 14 26 - 31 - 38 ns VCC = 2.0 V - 44 150 - 185 - 225 ns VCC = 4.5 V - 16 30 - 37 - 45 ns VCC = 5.0 V; CL = 15 pF - 13 - - - - - ns VCC = 6.0 V - 14 26 - 31 - 38 ns SHCP to Q7S; see Figure 9 [1] STCP to Qn; see Figure 10 tPHL HIGH to LOW propagation delay SHR to Q7S; see Figure 13 VCC = 2.0 V - 39 150 - 185 - 225 ns VCC = 4.5 V - 14 30 - 37 - 45 ns VCC = 5.0 V; CL = 15 pF - 11 - - - - - ns VCC = 6.0 V - 12 26 - 31 - 38 ns - 39 125 - 155 - 185 ns STR to Qn; see Figure 14 VCC = 2.0 V tTHL HIGH to LOW output transition time VCC = 4.5 V - 14 25 - 31 - 37 ns VCC = 5.0 V; CL = 15 pF - 11 - - - - - ns VCC = 6.0 V - 12 21 - 26 - 31 ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V - 14 60 - 75 - 90 ns VCC = 4.5 V - 5 12 - 15 - 18 ns VCC = 6.0 V - 4 10 - 13 - 15 ns see Figure 9 Serial data output Q7S Parallel data outputs 74HC_HCT594_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 12 of 26 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register Table 8. Dynamic characteristics type 74HC594 …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 15. Symbol Parameter 25 °C Conditions Min tTLH −40 °C to +85 °C −40 °C to +125 °C Unit Typ Max Min Max Min Max 19 75 - 95 - 110 ns 7 15 - 19 - 22 ns - 6 13 - 16 - 19 ns VCC = 2.0 V - 14 60 - 75 - 90 ns VCC = 4.5 V - 5 12 - 15 - 18 ns VCC = 6.0 V - 4 10 - 13 - 15 ns VCC = 2.0 V 80 10 - 100 - 120 - ns VCC = 4.5 V 16 4 - 20 - 24 - ns VCC = 6.0 V 14 3 - 17 - 20 - ns VCC = 2.0 V 80 10 - 100 - 120 - ns VCC = 4.5 V 16 4 - 20 - 24 - ns VCC = 6.0 V 14 3 - 17 - 20 - ns VCC = 2.0 V 80 14 - 100 - 120 - ns VCC = 4.5 V 16 5 - 20 - 24 - ns VCC = 6.0 V 14 4 - 17 - 20 - ns see Figure 9 LOW to HIGH output Serial data output Q7S transition VCC = 2.0 V time VCC = 4.5 V VCC = 6.0 V Parallel data outputs tW pulse width SHCP (HIGH or LOW); see Figure 9 STCP (HIGH or LOW); see Figure 10 SHR and STR (HIGH or LOW); see Figure 13 and Figure 14 74HC_HCT594_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 13 of 26 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register Table 8. Dynamic characteristics type 74HC594 …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 15. Symbol tsu Parameter set-up time 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 100 10 - 125 - 150 - ns VCC = 4.5 V 20 4 - 25 - 30 - ns VCC = 6.0 V 17 3 - 21 - 26 - ns VCC = 2.0 V 100 14 - 125 - 150 - ns VCC = 4.5 V 20 5 - 25 - 30 - ns VCC = 6.0 V 17 4 - 21 - 26 - ns VCC = 2.0 V 100 17 - 125 - 150 - ns VCC = 4.5 V 20 6 - 25 - 30 - ns VCC = 6.0 V 17 5 - 21 - 26 - ns DS to SHCP; see Figure 11 SHR to STCP; see Figure 12 SHCP to STCP; see Figure 10 th trec fmax hold time recovery time maximum frequency DS to SHCP; see Figure 11 VCC = 2.0 V 25 −8 - 30 - 35 - ns VCC = 4.5 V 5 −3 - 6 - 7 - ns VCC = 6.0 V 4 −2 - 5 - 6 - ns VCC = 2.0 V 50 −14 - 65 - 75 - ns VCC = 4.5 V 10 −5 - 13 - 15 - ns VCC = 6.0 V 9 −4 - 11 - 13 - ns VCC = 2.0 V 6.0 30 - 4.8 - 4.0 - MHz VCC = 4.5 V 30 92 - 24 - 20 - MHz VCC = 5.0 V; CL = 15 pF - 100 - - - - - MHz VCC = 6.0 V 35 109 - 28 - 24 - MHz SHR to SHCP and STR to STCP; see Figure 13 and Figure 14 SHCP or STCP; see Figure 9 and Figure 10 74HC_HCT594_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 14 of 26 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register Table 8. Dynamic characteristics type 74HC594 …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 15. Symbol CPD Parameter power dissipation capacitance 25 °C Conditions VI = GND to VCC; VCC = 5 V; fi = 1 MHz [2] −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max - 84 - - - - - [1] tpd is the same as tPHL and tPLH. [2] CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. pF Table 9. Dynamic characteristics type 74HCT594 GND = 0 V; VCC = 4.5 V; tr = tf = 6 ns; CL = 50 pF; see Figure 15. Symbol tpd tPHL tTHL Parameter propagation delay HIGH to LOW propagation delay HIGH to LOW output transition time 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max - 18 32 - 40 - 48 ns VCC = 5.0 V; CL = 15 pF - 15 - - - - - ns STCP to Qn; see Figure 10 - 18 32 - 40 - 48 ns VCC = 5.0 V; CL = 15 pF - 15 - - - - - ns SHR to Q7S; see Figure 13 - 17 30 - 38 - 45 ns VCC = 5.0 V; CL = 15 pF - 14 - - - - - ns STR to Qn; see Figure 14 - 17 30 - 38 - 45 ns VCC = 5.0 V; CL = 15 pF - 14 - - - - - ns - 7 15 - 19 - 22 ns - 5 12 - 15 - 18 ns 7 15 - 19 - 22 ns 5 12 - 15 - 18 ns SHCP to Q7S; see Figure 9 [1] see Figure 9 Serial data output Q7S VCC = 4.5 V Parallel data outputs VCC = 4.5 V tTLH see Figure 9 LOW to HIGH output Serial data output Q7S transition VCC = 4.5 V time Parallel data outputs VCC = 4.5 V - 74HC_HCT594_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 15 of 26 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register Table 9. Dynamic characteristics type 74HCT594 …continued GND = 0 V; VCC = 4.5 V; tr = tf = 6 ns; CL = 50 pF; see Figure 15. Symbol tW Parameter pulse width tsu set-up time 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max SHCP (HIGH or LOW); see Figure 9 16 4 - 20 - 24 - ns STCP (HIGH or LOW); see Figure 10 16 4 - 20 - 24 - ns SHR and STR (HIGH or LOW); see Figure 13 and Figure 14 16 6 - 20 - 24 - ns DS to SHCP; see Figure 11 20 4 - 25 - 30 - ns SHR to STCP; see Figure 12 20 6 - 25 - 30 - ns SHCP to STCP; see Figure 10 20 7 - 25 - 30 - ns th hold time DS to SHCP; see Figure 11 5 −3 - 6 - 7 - ns trec recovery time SHR to SHCP and STR to STCP; see Figure 13 and Figure 14 10 −5 - 13 - 15 - ns fmax maximum frequency SHCP or STCP; see Figure 9 and Figure 10 30 92 - 24 - 20 - MHz VCC = 5.0 V; CL = 15 pF - 100 - - - - - MHz - 89 - - - - - pF power dissipation capacitance CPD VI = GND to VCC − 1.5 V; VCC = 5 V; fi = 1 MHz [2] [1] tpd is the same as tPHL and tPLH. [2] CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 74HC_HCT594_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 16 of 26 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register 12. Waveforms 1/fmax SHCP input VM tW tPLH Q7S output tPHL VM tTLH tTHL 001aae341 Measurement points are given in Table 10. tPLH and tPHL are the same as tpd. tTLH = LOW to HIGH output transition time; tTHL = HIGH to LOW output transition time. Fig 9. The shift clock (SHCP) to output (Q7S) propagation delays, the shift clock pulse width, the maximum shift clock frequency, and output transition times SHCP input VM tsu STCP input 1/ fmax VM tW tPHL tPLH Qn outputs VM mla512 Measurement points are given in Table 10. tPLH and tPHL are the same as tpd. Fig 10. The storage clock (STCP) to output (Qn), propagation delays, the storage clock pulse width, the maximum storage clock pulse frequency and the shift clock to storage clock set-up time 74HC_HCT594_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 17 of 26 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register VM SHCP input t su t su th th VM DS input VM Q7 output 001aae342 Measurement points are given in Table 10. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 11. The data set-up time and hold times for DS input to SHCP SHR input VM tsu STCP input VM Qn outputs VM mbc326 Measurement points are given in Table 10. Fig 12. The set-up time shift reset (SHR) to storage clock (STCP) 74HC_HCT594_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 18 of 26 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register SHR input VM tW trec VM SHCP input tPHL VM Q7S output mbc324 Measurement points are given in Table 10. tPLH and tPHL are the same as tpd. Fig 13. The shift reset (SHR) pulse width, the shift reset to output (Q7S) propagation delay and the shift reset to shift clock (SHCP) recovery time STR input VM tW trec VM STCP input tPHL Qn outputs VM mbc325 Measurement points are given in Table 10. tPLH and tPHL are the same as tpd. Fig 14. The storage reset (STR) pulse width, the storage reset to output (Qn) propagation delay and the storage reset to storage clock (STCP) recovery time Table 10. Type Measurement points Input Output VM VM 74HC594 0.5 × VCC 0.5 × VCC 74HCT594 1.3 V 1.3 V 74HC_HCT594_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 19 of 26 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC PULSE GENERATOR VI VO RL S1 open DUT RT CL 001aad983 Test data is given in Table 11. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator CL = Load capacitance including jig and probe capacitance RL = Load resistor S1 = Test selection switch Fig 15. Load circuitry for measuring switching times Table 11. Type Test data Input Load VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74HC594 VCC 6 ns 15 pF, 50 pF 1 kΩ open GND VCC 74HCT594 3V 6 ns 15 pF, 50 pF 1 kΩ open GND VCC 74HC_HCT594_3 Product data sheet S1 position © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 20 of 26 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register 13. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 16. Package outline SOT109-1 (SO16) 74HC_HCT594_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 21 of 26 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA MO-150 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 17. Package outline SOT338-1 (SSOP16) 74HC_HCT594_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 22 of 26 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 18. Package outline SOT38-4 (DIP16) 74HC_HCT594_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 23 of 26 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register 14. Abbreviations Table 12. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-Power Schottky Transistor-Transistor Logic MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT594_3 20061220 Product data sheet - 74HC_HCT594_CNV_2 Modifications: 74HC_HCT594_CNV_2 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Table 1 “Ordering information” updated. 19970908 Product specification - 74HC_HCT594_3 Product data sheet 74HC_HCT594_CNV_1 © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 24 of 26 74HC594; 74HCT594 NXP Semiconductors 8-bit shift register with output register 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] 74HC_HCT594_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 20 December 2006 25 of 26 NXP Semiconductors 74HC594; 74HCT594 8-bit shift register with output register 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 24 Legal information. . . . . . . . . . . . . . . . . . . . . . . 25 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Contact information. . . . . . . . . . . . . . . . . . . . . 25 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2006. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 20 December 2006 Document identifier: 74HC_HCT594_3