74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Rev. 03 — 23 May 2007 Product data sheet 1. General description The 74HC193 and 74HCT193 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC193 and 74HCT193 are 4-bit synchronous binary up/down counters. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at any time, or erroneous operation will result. The device can be cleared at any time by the asynchronous master reset input (MR); it may also be loaded in parallel by activating the asynchronous parallel load input (PL). The 74HC193 and 74HCT193 each contain four master-slave JK flip-flops with the necessary steering logic to provide the asynchronous reset, load, and synchronous count up and count down functions. Each flip-flop contains JK feedback from slave to master, such that a LOW-to-HIGH transition on the CPD input will decrease the count by one, while a similar transition on the CPU input will advance the count by one. One clock should be held HIGH while counting with the other, otherwise the circuit will either count by twos or not at all, depending on the state of the first flip-flop, which cannot toggle as long as either clock input is LOW. Applications requiring reversible operation must make the reversing decision while the activating clock is HIGH to avoid erroneous counts. The terminal count up (TCU) and terminal count down (TCD) outputs are normally HIGH. When the circuit has reached the maximum count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise, the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW. The terminal count outputs can be used as the clock input signals to the next higher order circuit in a multistage counter, since they duplicate the clock waveforms. Multistage counters will not be fully synchronous, since there is a slight delay time difference added for each stage that is added. The counter may be preset by the asynchronous parallel load capability of the circuit. Information present on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on the master reset (MR) input will disable the parallel load gates, override both clock inputs and set all outputs (Q0 to 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter Q3) LOW. If one of the clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will be counted. 2. Features n n n n Synchronous reversible 4-bit binary counting Asynchronous parallel load Asynchronous reset Expandable without external logic 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC193D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC193DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74HC193N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HC193PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74HCT193D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HCT193DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74HCT193N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HCT193PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 4. Functional diagram 15 11 5 4 14 1 D0 PL 10 D1 9 D2 D3 TCU CPU COUNTER TCD CPD MR 12 13 FLIP-FLOPS Q0 3 Q1 2 Fig 1. Functional diagram Q2 6 D1 D2 D3 11 15 1 10 9 5 12 TCU CPD 4 13 TCD 001aag405 14 3 2 6 7 MR Q0 Q1 Q2 Q3 001aag409 Fig 2. Logic symbol 74HC_HCT193_3 Product data sheet D0 CPU Q3 7 PL © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 2 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter 11 5 4 14 15 1 10 9 C3 2+ G1 1− G2 R CTR4 3 2 6 7 3D 2CT = 0 1CT = 15 13 12 001aag410 Fig 3. IEC logic symbol 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 3 of 29 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx D1 D2 NXP Semiconductors 74HC_HCT193_3 Product data sheet D0 D3 PL CPU TCU T SD Q T FF1 SD Q FF2 T FF3 Q Q T Q FF4 Q RD RD SD Q Q RD RD CPD MR Q0 4 of 29 © NXP B.V. 2007. All rights reserved. Fig 4. Logic diagram Q1 Q2 Q3 001aag412 74HC193; 74HCT193 TCD Presettable synchronous 4-bit binary up/down counter Rev. 03 — 23 May 2007 SD 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter 5. Pinning information 5.1 Pinning 74HC193 74HCT193 74HC193 74HCT193 D1 1 16 VCC Q1 2 15 D0 Q0 3 14 MR CPD 4 13 TCD CPU 5 12 TCU Q2 6 11 PL Q3 7 10 D2 GND 8 9 D3 74HC193 74HCT193 1 16 VCC Q1 2 15 D0 Q0 3 14 MR 2 16 VCC 15 D0 CPD 4 13 TCD 3 14 MR CPU 5 12 TCU CPD 4 13 TCD CPU 5 12 TCU Q2 6 11 PL Q2 6 11 PL Q3 7 10 D2 Q3 7 10 D2 GND 8 GND 8 D1 1 Q1 Q0 9 001aag406 Fig 5. Pin configuration SO16 D1 D3 D3 001aaf408 001aag407 Fig 6. Pin configuration TSSOP16 and SSOP16 9 Fig 7. Pin configuration DIP16 5.2 Pin description Table 2. Pin description Symbol Pin Description D0 15 data input 0 D1 1 data input 1 D2 10 data input 2 D3 9 data input 3 Q0 3 flip-flop output 0 Q1 2 flip-flop output 1 Q2 6 flip-flop output 2 Q3 7 flip-flop output 3 CPD 4 count down clock input[1] CPU 5 count up clock input[1] GND 8 ground (0 V) PL 11 asynchronous parallel load input (active LOW) TCU 12 terminal count up (carry) output (active LOW) TCD 13 terminal count down (borrow) output (active LOW) MR 14 asynchronous master reset input (active HIGH) VCC 16 supply voltage [1] LOW-to-HIGH, edge triggered. 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 5 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter 6. Functional description Table 3. Function table[1] Operating mode Reset (clear) Parallel load Inputs Outputs MR PL CPU CPD D0 D1 D2 D3 Q0 Q1 Q2 Q3 TCU TCD H X X L X X X X L L L L H H X X H X X X X L L L L H H L L X L L L L L L L L L H L L L X H L L L L L L L L H H L L L X H H H H H H H H L H H H H L L L H X H H H H H H H Count up L H ↑ H X X X X count up H[2] H Count down L H H ↑ X X X X count down H H[3] [1] H = HIGH voltage level L = LOW voltage level X = don’t care ↑ = LOW-to-HIGH clock transition. [2] TCU = CPU at terminal count up (HHHH) [3] TCD = CPD at terminal count down (LLLL). 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 6 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter MR(1) PL D0 D1 D2 D3 CPU(2) CPD(2) Q0 Q1 Q2 Q3 TCU TCD 0 13 CLEAR PRESET 14 15 0 COUNT UP 1 2 1 0 15 14 COUNT DOWN 13 001aag411 (1) Clear overrides load, data and count inputs. (2) When counting up, the count down clock input (CPD) must be HIGH, when counting down the count up clock input (CPU) must be HIGH. Sequence Clear (reset outputs to zero); load (preset) to binary thirteen; count up to fourteen, fifteen, terminal count up, zero, one and two; count down to one, zero, terminal count down, fifteen, fourteen and thirteen. Fig 8. Typical clear, load and count sequence 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 7 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit −0.5 +7.0 V - ±20 mA - ±20 mA - ±25 mA - 50 mA IIK input clamping current VI < −0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] IO output current VO = −0.5 V to VCC + 0.5 V ICC supply current IGND ground current - −50 mA Tstg storage temperature −65 +150 °C DIP16 package [2] - 750 mW SO16 package [2] - 500 mW SSOP16 package [2] - 500 mW TSSOP16 package [2] - 500 mW total power dissipation Ptot [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For DIP16 packages: above 70 °C the value of Ptot derates linearly at 12 mW/K. For SO16 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K. For SSOP16 and TSSOP16 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit 74HC193 VCC supply voltage 2.0 5.0 6.0 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C tr rise time VCC = 2.0 V - - 1000 ns VCC = 4.5 V - 6.0 500 ns VCC = 6.0 V - - 400 ns VCC = 2.0 V - - 1000 ns VCC = 4.5 V - 6.0 500 ns VCC = 6.0 V - - 400 ns tf fall time inputs inputs 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 8 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter Table 5. Recommended operating conditions …continued Symbol Parameter Conditions Min Typ Max Unit 74HCT193 VCC supply voltage 4.5 5.0 5.5 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C tr rise time inputs; VCC = 4.5 V - 6.0 500 ns tf fall time inputs; VCC = 4.5 V - 6.0 500 ns 9. Static characteristics Table 6. Static characteristics type 74HC193 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VCC = 2.0 V 1.5 1.2 - V VCC = 4.5 V 3.15 2.4 - V Tamb = 25 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 6.0 V 4.2 3.2 - V VCC = 2.0 V - 0.8 0.5 V VCC = 4.5 V - 2.1 1.35 V VCC = 6.0 V - 2.8 1.8 V VI = VIH or VIL - - - IO = −20 µA; VCC = 2.0 V 1.9 2.0 - V IO = −20 µA; VCC = 4.5 V 4.4 4.5 - V IO = −20 µA; VCC = 6.0 V 5.9 6.0 - V IO = −4.0 mA; VCC = 4.5 V 3.98 4.32 - V IO = −5.2 mA; VCC = 6.0 V 5.48 5.81 - V IO = 20 µA; VCC = 2.0 V - 0 0.1 V IO = 20 µA; VCC = 4.5 V - 0 0.1 V IO = 20 µA; VCC = 6.0 V - 0 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 V VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±0.1 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 µA Ci input capacitance - 3.5 - pF VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V Tamb = −40 °C to +85 °C VIH HIGH-level input voltage 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 9 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter Table 6. Static characteristics type 74HC193 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VIL LOW-level input voltage VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V IO = −20 µA; VCC = 2.0 V 1.9 - - V IO = −20 µA; VCC = 4.5 V 4.4 - - V IO = −20 µA; VCC = 6.0 V 5.9 - - V IO = −4.0 mA; VCC = 4.5 V 3.84 - - V IO = −5.2 mA; VCC = 6.0 V 5.34 - - V IO = 20 µA; VCC = 2.0 V - - 0.1 V IO = 20 µA; VCC = 4.5 V - - 0.1 V IO = 20 µA; VCC = 6.0 V - - 0.1 V IO = 4.0 mA; VCC = 4.5 V - - 0.33 V VOH VOL HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL IO = 5.2 mA; VCC = 6.0 V - - 0.33 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±1.0 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 80 µA VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V Tamb = −40 °C to +125 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL IO = −20 µA; VCC = 2.0 V 1.9 - - V IO = −20 µA; VCC = 4.5 V 4.4 - - V IO = −20 µA; VCC = 6.0 V 5.9 - - V IO = −4.0 mA; VCC = 4.5 V 3.7 - - V IO = −5.2 mA; VCC = 6.0 V 5.2 - - V IO = 20 µA; VCC = 2.0 V - - 0.1 V IO = 20 µA; VCC = 4.5 V - - 0.1 V VI = VIH or VIL IO = 20 µA; VCC = 6.0 V - - 0.1 V IO = 4.0 mA; VCC = 4.5 V - - 0.4 V IO = 5.2 mA; VCC = 6.0 V - - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±1.0 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 160 µA 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 10 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter Table 7. Static characteristics type 74HCT193 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit Tamb = 25 °C VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = −20 µA 4.4 4.5 - V IO = −4.0 mA 3.98 4.32 - V - 0 0.1 V VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 µA - 0.15 0.26 V II input leakage current VI = VCC or GND; VCC = 5.5 V IO = 4.0 mA - - ±0.1 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 8.0 µA ∆ICC additional supply current per input pin; VI = VCC − 2.1 V and other inputs at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V pin Dn - 35 126 µA pins CPU, CPD - 140 504 µA pin PL - 65 234 µA pin MR - 105 378 µA - 3.5 - pF Ci input capacitance Tamb = −40 °C to +85 °C VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = −20 µA 4.4 - - V IO = −4.0 mA 3.84 - - V - - 0.1 V VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 µA - - 0.33 V II input leakage current VI = VCC or GND; VCC = 5.5 V IO = 4.0 mA - - ±1.0 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 80 µA ∆ICC additional supply current per input pin; VI = VCC − 2.1 V and other inputs at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V pin Dn - - 157.5 µA pins CPU, CPD - - 630 µA pin PL - - 292.5 µA pin MR - - 472.5 µA Tamb = −40 °C to +125 °C VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 11 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter Table 7. Static characteristics type 74HCT193 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V VOL LOW-level output voltage Min Typ Max Unit IO = −20 µA 4.4 - - V IO = −4.0 mA 3.7 - - V IO = 20 µA - - 0.1 V IO = 4.0 mA - - 0.4 V VI = VIH or VIL; VCC = 4.5 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - ±1.0 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 160 µA ∆ICC additional supply current per input pin; VI = VCC − 2.1 V and other inputs at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V pin Dn - - 171.5 µA pins CPU, CPD - - 686 µA pin PL - - 318.5 µA pin MR - - 514.5 µA 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 12 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter 10. Dynamic characteristics Table 8. Dynamic characteristics type 74HC193 Symbol Parameter 25 °C Conditions Min tpd propagation delay CPU, CPD to Qn; see Figure 9 [1] −40 °C to +85 °C −40 °C to +125 °C Unit Typ Max Min Max Min Max - VCC = 2.0 V - 63 215 - 270 - 325 ns VCC = 4.5 V - 23 43 - 54 - 65 ns VCC = 6.0 V - 18 37 - 46 - 55 ns VCC = 2.0 V - 39 125 - 155 - 190 ns VCC = 4.5 V - 14 25 - 31 - 38 ns VCC = 6.0 V - 11 21 - 26 - 32 ns VCC = 2.0 V - 39 125 - 155 - 190 ns VCC = 4.5 V - 14 25 - 31 - 38 ns VCC = 6.0 V - 11 21 - 26 - 32 ns CPU to TCU; see Figure 10 CPD to TCD; see Figure 10 PL to Qn; see Figure 11 VCC = 2.0 V - 69 220 - 275 - 330 ns VCC = 4.5 V - 25 44 - 55 - 66 ns VCC = 6.0 V - 20 37 - 47 - 56 ns VCC = 2.0 V - 58 200 - 250 - 300 ns VCC = 4.5 V - 21 40 - 50 - 60 ns VCC = 6.0 V - 17 34 43 - 51 ns VCC = 2.0 V - 69 210 - 265 - 315 ns VCC = 4.5 V - 25 42 - 53 - 63 ns VCC = 6.0 V - 20 36 - 45 - 54 ns VCC = 2.0 V - 80 290 - 365 - 435 ns VCC = 4.5 V - 29 58 - 73 - 87 ns VCC = 6.0 V - 23 49 - 62 - 74 ns MR to Qn; see Figure 12 Dn to Qn; see Figure 11 PL to TCU, PL to TCD; see Figure 14 MR to TCU, MR to TCD; see Figure 14 VCC = 2.0 V - 74 285 - 355 - 430 ns VCC = 4.5 V - 27 57 - 71 - 86 ns VCC = 6.0 V - 22 48 - 60 - 73 ns 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 13 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter Table 8. Dynamic characteristics type 74HC193 …continued Symbol Parameter tpd tTHL tTLH tW propagation delay 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max Dn to TCU, Dn to TCD; see Figure 14 VCC = 2.0 V - 80 290 - 365 - 435 ns VCC = 4.5 V - 29 58 - 73 - 87 ns VCC = 6.0 V - 23 49 - 62 - 74 ns HIGH to LOW see Figure 12 output transition VCC = 2.0 V time VCC = 4.5 V - 19 75 - 95 - 110 ns - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns LOW to HIGH see Figure 12 output transition VCC = 2.0 V time VCC = 4.5 V - 19 75 - 95 - 110 ns - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 100 22 - 125 - 150 - ns VCC = 4.5 V 20 8 - 25 - 30 - ns VCC = 6.0 V 17 6 - 21 - 26 - ns VCC = 2.0 V 100 25 - 125 - 150 - ns VCC = 4.5 V 20 9 - 25 - 30 - ns VCC = 6.0 V 17 7 - 21 - 26 - ns pulse width CPU, CPD (HIGH or LOW); see Figure 9 MR (HIGH); see Figure 12 PL (LOW); see Figure 11 trec recovery time VCC = 2.0 V 100 19 - 125 - 150 - ns VCC = 4.5 V 20 7 - 25 - 30 - ns VCC = 6.0 V 17 6 - 21 - 26 - ns VCC = 2.0 V 50 8 - 65 - 75 - ns VCC = 4.5 V 10 3 - 13 - 15 - ns VCC = 6.0 V 9 2 - 11 - 13 - ns VCC = 2.0 V 50 0 - 65 - 75 - ns VCC = 4.5 V 10 0 - 13 - 15 - ns VCC = 6.0 V 9 0 - 11 - 13 - ns PL to CPU, CPD; see Figure 11 MR to CPU, CPD; see Figure 12 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 14 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter Table 8. Dynamic characteristics type 74HC193 …continued Symbol Parameter tsu set-up time hold time th 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 80 22 - 100 - 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns VCC = 2.0 V 0 −14 - 0 - 0 - ns VCC = 4.5 V 0 −5 - 0 - VCC = 6.0 V 0 −4 - 0 VCC = 2.0 V 80 22 - 100 VCC = 4.5 V 16 8 - VCC = 6.0 V 8 6 VCC = 2.0 V 4.0 VCC = 4.5 V Dn to PL; see Figure 13; note: CPU = CPD = HIGH Dn to PL; see Figure 13 0 - ns 0 - ns - 120 - ns 20 - 24 - ns - 17 - 20 - ns 13.5 - 3.2 - 2.6 - MHz 20 41 - 16 - 13 - MHz 24 49 - 19 - 15 - MHz - 24 - - - - - pF CPU to CPD, CPD to CPU; see Figure 15 maximum frequency fmax CPU, CPD; see Figure 9 VCC = 6.0 V power dissipation capacitance CPD VI = GND to VCC; VCC = 5 V; fi = 1 MHz [2] [1] tpd is the same as tPHL and tPLH. [2] CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 15 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter Table 9. Dynamic characteristics type 74HCT193 Symbol Parameter tpd 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max - 23 43 - 54 - 65 ns - 15 27 - 34 - 41 ns - 15 27 - 34 - 41 ns - 26 46 - 58 - 69 ns - 22 40 - 50 - 60 ns - 27 46 - 58 - 69 ns - 31 55 - 69 - 83 ns - 29 55 - 69 - 83 ns VCC = 4.5 V - 32 58 - 73 - 87 ns HIGH to LOW see Figure 12 output transition VCC = 4.5 V time - 7 15 - 19 - 22 ns LOW to HIGH see Figure 12 output transition VCC = 4.5 V time - 7 15 - 19 - 22 ns 25 11 - 31 - 38 - ns 20 7 - 25 - 30 - ns 20 8 - 25 - 30 - ns propagation delay CPU, CPD to Qn; see Figure 9 VCC = 4.5 V [1] CPU to TCU; see Figure 10 VCC = 4.5 V CPD to TCD; see Figure 10 VCC = 4.5 V PL to Qn; see Figure 11 VCC = 4.5 V MR to Qn; see Figure 12 VCC = 4.5 V Dn to Qn; see Figure 11 VCC = 4.5 V PL to TCU, PL to TCD; see Figure 14 VCC = 4.5 V MR to TCU, MR to TCD; see Figure 14 VCC = 4.5 V Dn to TCU, Dn to TCD; see Figure 14 tTHL tTLH tW pulse width CPU, CPD (HIGH or LOW); see Figure 9 VCC = 4.5 V MR (HIGH); see Figure 12 VCC = 4.5 V PL (LOW); see Figure 11 VCC = 4.5 V 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 16 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter Table 9. Dynamic characteristics type 74HCT193 …continued Symbol Parameter trec recovery time 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max 10 2 - 13 - 15 - ns 10 0 - 13 - 15 - ns 16 8 - 20 - 24 - ns 0 −6 - 0 - 0 - ns 16 7 - 20 - 24 - ns 20 43 - 16 - 13 - MHz - 26 - - - - - pF PL to CPU, CPD; see Figure 11 VCC = 4.5 V MR to CPU, CPD; see Figure 12 VCC = 4.5 V tsu set-up time Dn to PL; see Figure 13; note: CPU = CPD = HIGH th hold time Dn to PL; see Figure 13 VCC = 4.5 V VCC = 4.5 V CPU to CPD, CPD to CPU; see Figure 15 VCC = 4.5 V maximum frequency fmax CPU, CPD; see Figure 9 VCC = 4.5 V power dissipation capacitance CPD VI = GND to VCC − 1.5 V; VCC = 5 V; fi = 1 MHz [2] [1] tpd is the same as tPHL and tPLH. [2] CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 17 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter 11. Waveforms 1/fmax VI CPU, CPD input VM GND tW t PHL t PLH VOH VM Qn output 001aag413 VOL Measurement points are given in Table 10. tPLH and tPHL are the same as tpd. Logic levels VOL and VOH are typical output voltage drops that occur with the output load. Fig 9. The clock (CPU, CPD) to output (Qn) propagation delays, the clock pulse width, and the maximum clock pulse frequency VI CPU, CPD input VM GND tPHL tPLH VOH TCU, TCD output VM VOL 001aag414 Measurement points are given in Table 10. tPLH and tPHL are the same as tpd. Logic levels VOL and VOH are typical output voltage drops that occur with the output load. Fig 10. The clock (CPU, CPD) to terminal count output (TCU, TCD) propagation delays 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 18 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter VI Dn input VM GND VI PL input VM GND t rec tW VI CPU, CPD input VM GND t PLH t PHL VOH Qn output VM VOL 001aag415 Measurement points are given in Table 10. tPLH and tPHL are the same as tpd. Logic levels VOL and VOH are typical output voltage drops that occur with the output load. Fig 11. The parallel load input (PL) and data (Dn) to Qn output propagation delays and PL removal time to clock input (CPU, CPD) VI MR input VM GND tW t rec VI CPU, CPD input VM GND t PHL VOH Qn output VOL 90 % VM 10 % t THL t TLH 001aag416 Measurement points are given in Table 10. tPLH and tPHL are the same as tpd. Logic levels VOL and VOH are typical output voltage drops that occur with the output load. Fig 12. The master reset input (MR) pulse width, MR to Qn propagation delays, MR to CPU, CPD removal time and output transition times 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 19 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter VI VM Dn input GND tsu tsu th th VI VM PL input GND VOH Qn output VOL 001aag417 The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 10. Logic levels VOL and VOH are typical output voltage drops that occur with the output load. Fig 13. The data input (Dn) to parallel load input (PL) set-up and hold times VI PL, MR, Dn input VM GND tPLH tPHL VOH TCU, TCD output VM VOL 001aag418 Measurement points are given in Table 10. tPLH and tPHL are the same as tpd. Logic levels VOL and VOH are typical output voltage drops that occur with the output load. Fig 14. The data input (Dn), parallel load input (PL) and the master reset input (MR) to the terminal count outputs (TCU, TCD) propagation delays VI CPU or CPD input VM GND th VI CPD or CPU input VM GND 001aag419 Measurement points are given in Table 10. Fig 15. The CPU to CPD or CPD to CPU hold times 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 20 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter Table 10. Measurement points Type Input Output VM VI VM 74HC193 0.5 × VCC GND to VCC 0.5 × VCC 74HCT193 1.3 V GND to 3 V 1.3 V tW VI 90 % negative pulse VM VM 10 % 0V VI tf tr tr tf 90 % positive pulse VM VM 10 % 0V tW VCC VCC PULSE GENERATOR VI VO RL S1 open DUT RT CL 001aad983 Test data is given in Table 11. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator CL = Load capacitance including jig and probe capacitance RL = Load resistor S1 = Test selection switch Fig 16. Load circuitry for measuring switching times Table 11. Test data Type Input VI Load tr, tf CL S1 position RL tPHL, tPLH 74HC193 VCC 6 ns 15 pF, 50 pF 1 kΩ open 74HCT193 3V 6 ns 15 pF, 50 pF 1 kΩ open 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 21 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter 12. Application information data input D0 D1 D2 D3 D0 D1 D2 D3 up clock CPU TCU CPU TCU down clock CPD IC1 TCD CPD IC2 TCD PL MR PL Q0 Q1 Q2 Q3 carry borrow MR Q0 Q1 Q2 Q3 asynchronous parallel load reset data output 001aag420 Fig 17. Application for cascaded up/down counter with parallel load 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 22 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter 13. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 18. Package outline SOT109-1 (SO16) 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 23 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 19. Package outline SOT338-1 (SSOP16) 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 24 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 20. Package outline SOT38-4 (DIP16) 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 25 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 21. Package outline SOT403-1 (TSSOP16) 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 26 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT193_3 20070523 Product data sheet - 74HC_HCT193_CNV_2 Modifications: 74HC_HCT193_CNV_2 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Family specification included 19970828 Product specification 74HC_HCT193_3 Product data sheet - - © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 27 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter 15. Legal information 16. Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.1 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.2 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] 74HC_HCT193_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 — 23 May 2007 28 of 29 74HC193; 74HCT193 NXP Semiconductors Presettable synchronous 4-bit binary up/down counter 18. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 13 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Application information. . . . . . . . . . . . . . . . . . 22 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 27 Legal information. . . . . . . . . . . . . . . . . . . . . . . 28 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Contact information. . . . . . . . . . . . . . . . . . . . . 28 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 23 May 2007 Document identifier: 74HC_HCT193_3