PESD5V0L6UAS; PESD5V0L6US Low capacitance 6-fold ESD protection diode arrays Rev. 03 — 18 August 2009 Product data sheet 1. Product profile 1.1 General description Low capacitance 6-fold ESD protection diode arrays in small plastic packages designed to protect up to six transmission or data lines from the damage caused by ElectroStatic Discharge (ESD) and other transients. Table 1. Product overview Type number Package Name NXP PESD5V0L6UAS TSSOP8 SOT505-1 PESD5V0L6US SO8 SOT96-1 1.2 Features n n n n ESD protection of up to six lines Low diode capacitance Max. peak pulse power: PPP = 35 W Low clamping voltage: V(CL)R = 15 V n n n n Ultra low leakage current: IRM = 8 nA ESD protection of up to 20 kV IEC 61000-4-2, level 4 (ESD) IEC 61000-4-5 (surge); IPP = 2.5 A 1.3 Applications n Computers and peripherals n Communication systems n Audio and video equipment n High speed data lines n Parallel ports 1.4 Quick reference data Table 2. Quick reference data Symbol Parameter VRWM reverse stand-off voltage Cd diode capacitance Conditions VR = 0 V; f = 1 MHz Min Typ Max Unit - - 5 V - 16 19 pF PESD5V0L6UAS; PESD5V0L6US NXP Semiconductors Low capacitance 6-fold ESD protection diode arrays 2. Pinning information Table 3. Discrete pinning Pin Description Simplified outline Symbol TSSOP8 1 cathode 1 2 cathode 2 3 cathode 3 4 cathode 4 5 cathode 5 6 common anode 7 common anode 8 cathode 6 8 1 5 4 1 8 2 7 3 6 4 5 sym004 SO8 1 cathode 1 2 cathode 2 3 cathode 3 4 cathode 4 5 cathode 5 6 common anode 7 common anode 8 cathode 6 8 1 5 4 1 8 2 7 3 6 4 5 sym004 3. Ordering information Table 4. Ordering information Type number Package Name Description Version PESD5V0L6UAS TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 PESD5V0L6US SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 4. Marking Table 5. Marking Type number Marking code PESD5V0L6UAS 5V06U PESD5V0L6US 5V06US PESD5V0L6UAS_US_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 18 August 2009 2 of 14 NXP Semiconductors PESD5V0L6UAS; PESD5V0L6US Low capacitance 6-fold ESD protection diode arrays 5. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit PPP peak pulse power 8/20 µs pulse [1][2] IPP peak pulse current 8/20 µs pulse - 35 W [1][2] - 2.5 A Tj junction temperature - 150 °C Tamb ambient temperature −65 +150 °C Tstg storage temperature −65 +150 °C Per diode [1] Non-repetitive current pulse 8/20 µs exponentially decay waveform according to IEC 61000-4-5; see Figure 1. [2] Measured from pin 1, 2, 3, 4, 5 or 8 to pin 6 or 7. Table 7. Symbol ESD ESD maximum ratings Parameter Conditions electrostatic discharge capability IEC 61000-4-2 (contact discharge) HBM MIL-STD883 Min Max Unit - 20 kV - 10 kV [1] Device stressed with ten non-repetitive ElectroStatic Discharge (ESD) pulses; see Figure 2. [2] Measured from pin 1, 2, 3, 4, 5 or 8 to pin 6 or 7. Table 8. ESD standards compliance Standard Conditions IEC 61000-4-2, level 4 (ESD); see Figure 2 > 15 kV (air); > 8 kV (contact) HBM MIL-STD883, class 3 > 4 kV PESD5V0L6UAS_US_3 Product data sheet [1][2] © NXP B.V. 2009. All rights reserved. Rev. 03 — 18 August 2009 3 of 14 PESD5V0L6UAS; PESD5V0L6US NXP Semiconductors Low capacitance 6-fold ESD protection diode arrays 001aaa191 Ipp 001aaa630 120 100 % 90 % 100 % IPP; 8 µs IPP (%) 80 e−t 50 % IPP; 20 µs 40 10 % tr = 0.7 to 1 ns 0 0 10 20 30 t (µs) Fig 1. 60 ns 8/20 µs pulse waveform according to IEC 61000-4-5 Fig 2. ElectroStatic Discharge (ESD) pulse waveform according to IEC 61000-4-2 PESD5V0L6UAS_US_3 Product data sheet t 30 ns 40 © NXP B.V. 2009. All rights reserved. Rev. 03 — 18 August 2009 4 of 14 NXP Semiconductors PESD5V0L6UAS; PESD5V0L6US Low capacitance 6-fold ESD protection diode arrays 6. Characteristics Table 9. Characteristics Tamb = 25 °C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit - - 5 V - 8 25 nA IPP = 1 A [1][2] - - 10 V IPP = 2.5 A [1][2] - - 15 V Per diode VRWM reverse stand-off voltage IRM reverse leakage current V(CL)R clamping voltage VRWM = 5 V V(BR) breakdown voltage IR = 1 mA 6.4 6.8 7.2 V rdif differential resistance IR = 1 mA - - 100 Ω Cd diode capacitance VR = 0 V; f = 1 MHz; see Figure 5 - 16 19 pF [1] Non-repetitive current pulse 8/20 µs exponentially decay waveform according to IEC 61000-4-5; see Figure 1. [2] Measured between each cathode on pins 1, 2, 3, 4, 5 or 8 and anode on pin 6 or 7. PESD5V0L6UAS_US_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 18 August 2009 5 of 14 PESD5V0L6UAS; PESD5V0L6US NXP Semiconductors Low capacitance 6-fold ESD protection diode arrays 001aaa192 102 001aaa193 1.2 PPP PPP(25°C) Ppp (W) 0.8 10 0.4 1 1 102 10 103 0 104 0 50 100 150 tp (µs) 200 Tj (°C) Tamb = 25 °C Fig 3. Peak pulse power as a function of exponential pulse duration tp; typical values Fig 4. 001aaa194 18 Cd (pF) 16 Relative variation of peak pulse power as a function of junction temperature; typical values 001aaa195 10 IRM IRM(25˚C) 14 1 12 10 8 0 1 2 3 4 5 10−1 −100 VR (V) −50 0 50 100 150 Tj (°C) Tamb = 25 °C; f = 1 MHz Fig 5. Diode capacitance as a function of reverse voltage; typical values Fig 6. Relative variation of reverse leakage current as a function of junction temperature; typical values PESD5V0L6UAS_US_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 18 August 2009 6 of 14 PESD5V0L6UAS; PESD5V0L6US NXP Semiconductors Low capacitance 6-fold ESD protection diode arrays ESD TESTER RZ 450 Ω RG 223/U 50 Ω coax 10× ATTENUATOR 4 GHz DIGITIZING OSCILLOSCOPE 50 Ω CZ IEC61000-4-2 network CZ = 150 pF; RZ = 330 Ω DUT: PESD5V0L6UAS PESD5V0L6US vertical scale = 200 V/div horizontal scale = 50 ns/div vertical scale = 10 V/div horizontal scale = 50 ns/div GND GND unclamped +1 kV ESD voltage waveform (IEC61000-4-2 network) clamped +1 kV ESD voltage waveform (IEC61000-4-2 network) GND GND vertical scale = 10 V/div horizontal scale = 50 ns/div vertical scale = 200 V/div horizontal scale = 50 ns/div unclamped −1 kV ESD voltage waveform (IEC61000-4-2 network) clamped −1 kV ESD voltage waveform (IEC61000-4-2 network) 006aaa064 Fig 7. ESD clamping test setup and waveforms PESD5V0L6UAS_US_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 18 August 2009 7 of 14 PESD5V0L6UAS; PESD5V0L6US NXP Semiconductors Low capacitance 6-fold ESD protection diode arrays 7. Application information The PESD5V0L6UAS and the PESD5V0L6US are designed for protection of up to six unidirectional data lines from the damage caused by ElectroStatic Discharge (ESD) and surge pulses. The PESD5V0L6UAS and the PESD5V0L6US may be used on lines where the signal polarity is above or below ground. The PESD5V0L6UAS and the PESD5V0L6US provide a surge capability of 35 W per line for a 8/20 µs waveform. high speed data lines PESD5V0L6UAS PESD5V0L6US PESD5V0L6UAS PESD5V0L6US n.c. n.c. unidirectional protection of 6 lines bidirectional protection of 5 lines 006aaa065 Fig 8. Typical application for ESD protection of data lines Circuit board layout and protection device placement: Circuit board layout is critical for the suppression of ESD, EFT and surge transients. The following guidelines are recommended: 1. Place the protection device as close to the input terminal or connector as possible. 2. The path length between the protection device and the protected line should be minimized. 3. Keep parallel signal paths to a minimum. 4. Avoid running protection conductors in parallel with unprotected conductor. 5. Minimize all printed-circuit board conductive loops including power and ground loops. 6. Minimize the length of the transient return path to ground. 7. Avoid using shared transient return paths to a common ground point. 8. Ground planes should be used whenever possible. For multilayer printed-circuit boards, use ground vias. PESD5V0L6UAS_US_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 18 August 2009 8 of 14 PESD5V0L6UAS; PESD5V0L6US NXP Semiconductors Low capacitance 6-fold ESD protection diode arrays 8. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm D E SOT505-1 A X c y HE v M A Z 5 8 A2 pin 1 index (A3) A1 A θ Lp L 1 4 detail X e w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.45 0.25 0.28 0.15 3.1 2.9 3.1 2.9 0.65 5.1 4.7 0.94 0.7 0.4 0.1 0.1 0.1 0.70 0.35 6° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 99-04-09 03-02-18 SOT505-1 Fig 9. EUROPEAN PROJECTION Package outline SOT505-1 (TSSOP8) PESD5V0L6UAS_US_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 18 August 2009 9 of 14 PESD5V0L6UAS; PESD5V0L6US NXP Semiconductors Low capacitance 6-fold ESD protection diode arrays SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 10. Package outline SOT96-1 (SO8/MS-012) PESD5V0L6UAS_US_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 18 August 2009 10 of 14 NXP Semiconductors PESD5V0L6UAS; PESD5V0L6US Low capacitance 6-fold ESD protection diode arrays 9. Packing information Table 10. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description Packing quantity 1000 2500 PESD5V0L6UAS SOT505-1 8 mm pitch, 12 mm tape and reel - -118 PESD5V0L6US SOT96-1 8 mm pitch, 12 mm tape and reel -115 -118 [1] For further information and the availability of packing methods, see Section 12. PESD5V0L6UAS_US_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 18 August 2009 11 of 14 PESD5V0L6UAS; PESD5V0L6US NXP Semiconductors Low capacitance 6-fold ESD protection diode arrays 10. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes PESD5V06UAS_US_3 20090818 Product data sheet - PESD5V06UAS_US_2 Modifications: • This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content. • Table 3 “Discrete pinning”: amended PESD5V06UAS_US_2 20041109 Product data sheet - PESD5V0L6US_1 PESD5V0L6US_1 20040315 Product specification - - PESD5V0L6UAS_US_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 18 August 2009 12 of 14 NXP Semiconductors PESD5V0L6UAS; PESD5V0L6US Low capacitance 6-fold ESD protection diode arrays 11. Legal information 11.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 11.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 11.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 11.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 12. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PESD5V0L6UAS_US_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 18 August 2009 13 of 14 NXP Semiconductors PESD5V0L6UAS; PESD5V0L6US Low capacitance 6-fold ESD protection diode arrays 13. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 10 11 11.1 11.2 11.3 11.4 12 13 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Application information. . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Packing information. . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 18 August 2009 Document identifier: PESD5V0L6UAS_US_3