74LV259 8-bit addressable latch Rev. 03 — 2 January 2008 Product data sheet 1. General description The 74LV259 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC259 and 74HCT259. The 74LV259 is a high-speed 8-bit addressable latch designed for general purpose storage applications in digital systems. The 74LV259 is multifunctional device capable of storing single-line data in eight addressable latches, and also 3-to-8 decoder and demultiplexer, with active HIGH outputs (Q0 to Q7), functions are available. The 74LV259 also incorporates an active LOW common reset (MR) for resetting all latches, as well as, an active LOW enable input (LE). The 74LV259 has four modes of operation as shown in the mode select table. In the addressable latch mode, data on the data line (D) is written into the addressed latch. The addressed latch will follow the data input with all non-addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state of the (D) input with all other outputs in the LOW state. In the reset mode all outputs are LOW and unaffected by the address (A0 to A2) and data (D) input. When operating the 74LV259 as an address latch, changing more than one bit of address could impose a transient-wrong address. Therefore, this should only be done while in the memory mode. 2. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C Combines demultiplexer and 8-bit latch Serial-to-parallel capability Output from each storage bit available Random (addressable) data entry Easily expandable Common reset input Useful as a 3-to-8 active HIGH decoder ESD protection: ◆ HBM JESD22-A114E exceeds 2000 V ◆ MM JESD22-A115-A exceeds 200 V Multiple package options Specified from −40 °C to +85 °C and from −40 °C to +125 °C 74LV259 NXP Semiconductors 8-bit addressable latch 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV259N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74LV259D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74LV259DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74LV259PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74LV259BQ −40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm SOT763-1 4. Functional diagram 15 13 G8 Z9 DX 14 0 LE 13 D Q0 4 Q1 5 Q2 6 Q3 7 1 A0 Q4 9 2 A1 Q5 10 3 A2 Q6 11 Q7 12 1 2 3 14 0 G 0 7 2 Fig 1. Logic symbol 7 9 10 5 11 6 12 7 001aah119 Fig 2. IEC logic symbol 74LV259_3 Product data sheet 6 2 4 001aah118 4 5 1 3 MR 15 9,10D 1 C10 8R © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 January 2008 2 of 19 74LV259 NXP Semiconductors 8-bit addressable latch Q0 Q1 A0 1 A1 2 1 OF 8 DECODER Q2 Q3 A2 3 8 LATCHES Q4 Q5 LE 14 15 13 MR Q6 D Q7 4 5 6 7 9 10 11 12 001aah120 Fig 3. Functional diagram 5. Pinning information 5.1 Pinning 1 A0 terminal 1 index area A1 2 15 MR A2 3 14 LE 13 D A1 2 15 MR Q0 4 A2 3 14 LE Q1 5 Q0 4 13 D Q2 6 Q1 5 12 Q7 Q3 7 Q2 6 11 Q6 Q3 7 10 Q5 GND 8 9 Q4 12 Q7 VCC (1) 11 Q6 10 Q5 9 16 VCC Q4 1 8 A0 GND 74LV259 16 VCC 74LV259 001aah117 Transparent top view 001aah127 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration DIP16, SO16 and (T)SSOP16 Fig 5. Pin configuration DHVQFN16 5.2 Pin description Table 2. Pin description Symbol Pin Description A0 1 address input A1 2 address input A2 3 address input GND 8 ground (0 V) Q[0:7] 4, 5, 6, 7, 9, 10, 11, 12 latch output 74LV259_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 January 2008 3 of 19 74LV259 NXP Semiconductors 8-bit addressable latch Table 2. Pin description …continued Symbol Pin Description D 13 data input LE 14 latch enable input (active LOW) MR 15 conditional reset input (active LOW) VCC 16 supply voltage 6. Functional description Table 3. Mode select table H = HIGH voltage level; L = LOW voltage level LE MR Mode L H addressable latch H H memory L L active HIGH 8-channel demultiplexer H L reset Table 4. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; d = High or LOW data one set-up time prior to the LOW-to-HIGH LE transition; q<n> = state of the output established during the last cycle in which it was addressed or cleared Operating modes Input Output MR LE D A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 master reset L H X X X X L L L L L L L L demultiplex (active HIGH) decoder (when D = H) L L d L L L Q=d L L L L L L L L L d H L L L Q=d L L L L L L L L d L H L L L Q=d L L L L L L L d H H L L L L Q=d L L L L L L d L L H L L L L Q=d L L L L L d H L H L L L L L Q=d L L d L H H L L L L L L Q=d L L L d H H H L L L L L L L Q=d L store (do nothing) H H X X X X q0 q1 q2 q3 q4 q5 q6 q7 addressable latch H L d L L L Q=d q1 q2 q3 q4 q5 q6 q7 H L d H L L q0 Q=d q2 q3 q4 q5 q6 q7 H L d L H L q0 q1 Q=d q3 q4 q5 q6 q7 H L d H H L q0 q1 q2 Q=d q4 q5 q6 q7 H L d L L H q0 q1 q2 q3 Q=d q5 q6 q7 H L d H L H q0 q1 q2 q3 q4 Q = d q6 q7 H L d L H H q0 q1 q2 q3 q4 q5 Q=d q7 H L H H H H q0 q1 q2 q3 q4 q5 q6 Q=d 74LV259_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 January 2008 4 of 19 74LV259 NXP Semiconductors 8-bit addressable latch 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit −0.5 +4.6 V - ±20 mA - ±50 mA - ±25 mA mA IIK input clamping current VI < −0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] IO output current VO = −0.5 V to (VCC + 0.5 V) ICC supply current - 50 IGND ground current −50 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation [1] Tamb = −40 °C to +125 °C DIP16 package [2] - 750 mW SO16 package [3] - 500 mW (T)SSOP16 package [4] - 500 mW DHVQFN16 package [5] - 500 mW The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 12 mW/K above 70 °C. [3] Ptot derates linearly with 8 mW/K above 70 °C. [4] Ptot derates linearly with 5.5 mW/K above 60 °C. [5] Ptot derates linearly with 4.5 mW/K above 60 °C. 8. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min [1] Typ Max Unit VCC supply voltage 1.0 3.3 3.6 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C ∆t/∆V input transition rise and fall rate VCC = 1.0 V to 2.0 V - - 500 ns/V VCC = 2.0 V to 2.7 V - - 200 ns/V VCC = 2.7 V to 3.6 V - - 100 ns/V [1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to VCC = 1.0 V (with input levels GND or VCC). 74LV259_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 January 2008 5 of 19 74LV259 NXP Semiconductors 8-bit addressable latch 9. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter HIGH-level input voltage VIH LOW-level input voltage VIL VOH HIGH-level output voltage LOW-level output voltage VOL −40 °C to +85 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max VCC = 1.2 V 0.9 - - 0.9 - V VCC = 2.0 V 1.4 - - 1.4 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 1.2 V - - 0.3 - 0.3 V VCC = 2.0 V - - 0.6 - 0.6 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V IO = −100 µA; VCC = 1.2 V - 1.2 - - - V IO = −100 µA; VCC = 2.0 V 1.8 2.0 - 1.8 - V IO = −100 µA; VCC = 2.7 V 2.5 2.7 - 2.5 - V IO = −100 µA; VCC = 3.0 V 2.8 3.0 - 2.8 - V IO = −6 mA; VCC = 3.0 V 2.4 2.82 - 2.2 - V IO = 100 µA; VCC = 1.2 V - 0 - - - V IO = 100 µA; VCC = 2.0 V - 0 0.2 - 0.2 V IO = 100 µA; VCC = 2.7 V - 0 0.2 - 0.2 V IO = 100 µA; VCC = 3.0 V - 0 0.2 - 0.2 V IO = 6 mA; VCC = 3.0 V - 0.25 0.40 - 0.50 V VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 5.5 V - - 1.0 - 1.0 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 20.0 - 160 µA ∆ICC additional supply current per input; VI = VCC − 0.6 V; VCC = 2.7 V to 3.6 V - - 500 - 850 µA CI input capacitance - 3.5 - - - pF [1] Typical values are measured at Tamb = 25 °C. 74LV259_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 January 2008 6 of 19 74LV259 NXP Semiconductors 8-bit addressable latch 10. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V; For test circuit see Figure 12. Symbol Parameter tpd −40 °C to +85 °C Conditions tpd Min Max Min Max VCC = 1.2 V - 105 - - - ns VCC = 2.0 V - 36 49 - 61 ns 36 - 45 ns propagation delay D to Qn; see Figure 8 - 26 VCC = 3.0 V to 3.6 V; CL = 15 pF [3] - 17 - - - ns VCC = 3.0 V to 3.6 V [3] - 20 29 - 36 ns VCC = 1.2 V - 105 - - - ns VCC = 2.0 V - 36 49 - 61 ns VCC = 2.7 V - 26 36 - 45 ns VCC = 3.0 V to 3.6 V; CL = 15 pF [3] - 17 - - - ns VCC = 3.0 V to 3.6 V [3] - 20 29 - 36 ns VCC = 1.2 V - 100 - - - ns VCC = 2.0 V - 34 48 - 60 ns 35 - 44 ns propagation delay An to Qn; see Figure 7 [2] [2] propagation delay LE to Qn; Figure 6 VCC = 2.7 V tPHL tW - 25 VCC = 3.0 V to 3.6 V; CL = 15 pF [3] - 16 - - - ns VCC = 3.0 V to 3.6 V [3] - 19 28 - 35 ns propagation delay VCC = 1.2 V - 90 - - - ns VCC = 2.0 V - 31 43 - 53 ns VCC = 2.7 V - 23 31 - 39 ns VCC = 3.0 V to 3.6 V; CL = 15 pF [3] - 14 - - - ns VCC = 3.0 V to 3.6 V [3] - 17 25 - 31 ns 34 10 - 41 - ns 25 8 - 30 - ns 20 6 - 24 - ns 34 10 - 41 - ns 25 8 - 30 - ns 20 6 - 24 - ns HIGH to LOW pulse width MR to Qn; Figure 9 LE, HIGH or LOW; see Figure 6 VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tW Unit [2] VCC = 2.7 V tpd −40 °C to +125 °C Typ[1] pulse width [3] MR, LOW; see Figure 9 VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V [3] 74LV259_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 January 2008 7 of 19 74LV259 NXP Semiconductors 8-bit addressable latch Table 8. Dynamic characteristics …continued GND = 0 V; For test circuit see Figure 12. Symbol Parameter tsu set-up time −40 °C to +85 °C Conditions Max Min Max VCC = 1.2 V - 35 - - - ns VCC = 2.0 V 24 12 - 29 - ns 18 9 - 21 - ns 14 7 - 17 - ns VCC = 1.2 V - −30 - - - ns VCC = 2.0 V 5 −10 - 5 - ns 5 −8 - 5 - ns 5 −6 - 5 - ns VCC = 1.2 V - −20 - - - ns VCC = 2.0 V 5 −7 - 5 - ns VCC = 2.7 V 5 −5 - 5 - ns 5 −4 - 5 - ns D, An to LE; see Figure 10 and Figure 11 VCC = 3.0 V to 3.6 V hold time [3] D to LE; see Figure 10 VCC = 2.7 V VCC = 3.0 V to 3.6 V hold time th power dissipation capacitance CPD [3] An to LE; see Figure 11 VCC = 3.0 V to 3.6 V [3] CL = 50 pF; fi = 1 MHz; VI = GND to VCC [4] [1] Typical values are measured at Tamb = 25 °C. [2] tpd is the same as tPLH and tPHL. [3] Typical value measured at VCC = 3.3 V. [4] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 74LV259_3 Product data sheet Unit Min VCC = 2.7 V th −40 °C to +125 °C Typ[1] 19 pF © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 January 2008 8 of 19 74LV259 NXP Semiconductors 8-bit addressable latch 11. Waveforms VCC D input GND VCC LE input VM GND tW tPHL tPLH VOH VM Qn output VOL 001aah121 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. The enable input (LE) to output (Qn) propagation delays and the enable input pulse width VCC VM An input GND tPHL tPLH VOH VM Qn output VOL 001aah122 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. The address input (An) to output (Qn) propagation delays VCC D input VM GND tPHL tPLH VOH VM Qn output VOL 001aah123 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. The data input (D) to output (Qn) propagation delays 74LV259_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 January 2008 9 of 19 74LV259 NXP Semiconductors 8-bit addressable latch VCC MR input VM GND tW tPHL VOH VM Qn output VOL 001aah124 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. The conditional reset input (MR) to output (Qn) propagation delays VCC LE input VM GND tsu tsu th VCC th VM D input GND VOH Qn output VM Q=D Q=D VOL 001aah125 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 10. The data set-up and hold times for the D input to the LE input VCC An input VM ADDRESS STABLE GND tsu th VCC LE input VM GND 001aah126 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 11. The address input set-up and hold times for the An inputs to the LE input 74LV259_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 January 2008 10 of 19 74LV259 NXP Semiconductors 8-bit addressable latch Table 9. Measurement points Supply voltage Input Output VCC VM VM < 2.7 V 0.5VCC 0.5VCC 2.7 V to 3.6 V 1.5 V 1.5 V VCC PULSE GENERATOR VI VO D.U.T. RT CL 50 pF RL 1 kΩ 001aaa663 Test data is given in Table 10. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. Fig 12. Load circuit for switching times Table 10. Test data Supply voltage Input VCC VI tr, tf < 2.7 V VCC ≤ 2.5 ns 2.7 V to 3.6 V 2.7 V ≤ 2.5 ns 74LV259_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 January 2008 11 of 19 74LV259 NXP Semiconductors 8-bit addressable latch 12. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 13. Package outline SOT38-4 (DIP16) 74LV259_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 January 2008 12 of 19 74LV259 NXP Semiconductors 8-bit addressable latch SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 14. Package outline SOT109-1 (SO16) 74LV259_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 January 2008 13 of 19 74LV259 NXP Semiconductors 8-bit addressable latch SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 15. Package outline SOT338-1 (SSOP16) 74LV259_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 January 2008 14 of 19 74LV259 NXP Semiconductors 8-bit addressable latch TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 16. Package outline SOT403-1 (TSSOP16) 74LV259_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 January 2008 15 of 19 74LV259 NXP Semiconductors 8-bit addressable latch DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 17. Package outline SOT763-1 (DHVQFN16) 74LV259_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 January 2008 16 of 19 74LV259 NXP Semiconductors 8-bit addressable latch 13. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LV259_3 20080102 Product data sheet - 74LV259_2 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • • Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN16 package added. Section 7: derating values added for DHVQFN16 package. Section 12: outline drawing added for DHVQFN16 package. 74LV259_2 19980520 Product specification - 74LV259_1 74LV259_1 19970606 Product specification - - 74LV259_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 January 2008 17 of 19 74LV259 NXP Semiconductors 8-bit addressable latch 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] 74LV259_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 January 2008 18 of 19 74LV259 NXP Semiconductors 8-bit addressable latch 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 2 January 2008 Document identifier: 74LV259_3