INTEGRATED CIRCUITS DATA SHEET TDA8310A PAL/NTSC colour processor for PIP applications Product specification Supersedes data of 1995 Nov 29 File under Integrated Circuits, IC02 1996 Jan 25 Philips Semiconductors Product specification PAL/NTSC colour processor for PIP applications TDA8310A FEATURES GENERAL DESCRIPTION • Video switch with 2 CVBS inputs. One input can be switched between CVBS and Y/C and the circuit can automatically detect whether the incoming signal is CVBS or Y/C The TDA8310A is an alignment-free PAL/NTSC colour processor for Picture-in-Picture (PIP) applications. The main difference between the TDA8310 and the TDA8310A is that the vision IF amplifier has been omitted in the TDA8310A. Therefore, the circuit contains an input signal selector, a PAL/NTSC colour decoder, horizontal and vertical synchronization and an RGB/YUV switch. • Integrated chrominance trap and bandpass filters (automatically calibrated) • Integrated luminance delay line The input signal selector has 2 CVBS inputs. One of the inputs can be switched between CVBS and Y/C and the circuit can automatically detect whether the incoming signal is CVBS or Y/C. The output signals for the PIP processor are; • Automatic PAL/NTSC decoder which can decode all standards available in the world • Easy interfacing with the TDA8395 (SECAM decoder) for multistandard applications • Horizontal PLL with an alignment-free horizontal oscillator Luminance signal Colour difference signals (U and V) • Vertical count-down circuit Horizontal and vertical synchronization pulses. • RGB/YUV and fast blanking switch with 3-state output and active clamping The RGB/YUV switch can select between two RGB or YUV sources, e.g. between the PIP processor and the SCART input signal. • Low dissipation (560 mW) • Small amount of peripheral components compared with competition ICs. The supply voltage for the IC is 8 V. It is available in a 52-pin SDIP package. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8310A 1996 Jan 25 SDIP52 DESCRIPTION plastic shrink dual in-line package; 52 leads (600 mil) 2 VERSION SOT247-1 Philips Semiconductors Product specification PAL/NTSC colour processor for PIP applications TDA8310A QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VP supply voltage (pins 19 and 41) 7.2 8.0 8.8 V IP supply current − 70 1.4 mA Input voltages V17,20(p-p) CVBS/Y input voltage (peak-to-peak value) − 1.0 − V V16(p-p) chrominance input voltage (peak-to-peak value) − 0.3 − V Vi(p-p) RGB/YUV input signal voltage amplitude (peak-to-peak value) − − 1.3 V Output signals Vo(p-p) luminance output voltage (peak-to-peak value) − 1.4 − V V50(p-p) (B−Y) output voltage (peak-to-peak value) 1.06 1.33 1.6 V V51(p-p) (R−Y) output voltage (peak-to-peak value) 0.84 1.05 1.26 V V39 horizontal sync pulse output voltage − 4.0 − V V36 vertical sync pulse output voltage − 4.0 − V Gv voltage gain of the RGB switches −0.5 0 +0.5 dB 0 − 5.0 V Control voltage Vcontrol 1996 Jan 25 control voltage for HUE 3 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... COINCIDENCE/ NOISE DETECTOR DECBG DECDIG 37 35 21 VP2 19 HOUT VOUT 30 41 39 36 40 10 VCO + CONTROL PHASE DETECTOR SAND PULSE SHAPER R1 SANDCASTLE GENERATOR 11 12 G1 B1 13 i.c. n.c. BLANK1 22, 29 VERTICAL SYNC SEPARATOR SYNC SEPARATOR 33, 34 14 HORIZONTAL/ VERTICAL DIVIDER CLAMP 8 RGB/YUV SWITCH 7 6 DECFT 5 TDA8310A 15 1 4 2 3 CHROMINANCE BANDPASS CHROMINANCE TRAP 52 FILTER TUNING 4 32 REF 28 AUTOMATIC Y/C DETECTOR 31 20 17 CVBSEXT GND2 PAL/NTSC DECODER INPUT SELECTOR CVBSINT 9 16 CHROMAI SYSTSW 47 48 LUMINANCE DELAY LINE 27 46 45 44 43 42 PLL XTAL4 XTAL3 XTAL2 XTAL1 SECAM R/W CHROMAO 26 24 50 23 LOGIC2 LOGIC1 B Y 51 18 38 GND1 GND3 49 R G B BLANK R2 G2 B2 BLANK2 IDENT HUE Y MGD128 R Y Product specification TDA8310A Fig.1 Block diagram. 25 COLOUR2 COLOUR1 handbook, full pagewidth CVBSSW Philips Semiconductors VP1 PH1LF PAL/NTSC colour processor for PIP applications BLOCK DIAGRAM 1996 Jan 25 INTB Philips Semiconductors Product specification PAL/NTSC colour processor for PIP applications TDA8310A PINNING SYMBOL PIN SYMBOL DESCRIPTION PIN DESCRIPTION R2 1 RED input 2 (PIP) HUE 28 HUE control input G2 2 GREEN input 2 (PIP) i.c. 29 internally connected (test purposes) B2 3 BLUE input 2 (PIP) INTB 30 internal bias IDENT 4 colour standard identification output GND2 31 ground 2 (0 V) BLANK 5 blanking output CVBSSW 32 B 6 BLUE output CVBS positive/negative modulation control switch input G 7 GREEN output n.c. 33 not connected R 8 RED output n.c. 34 not connected 35 bandgap decoupling SYSTSW 9 CVBS/system switch DECBG R1 10 RED input 1 VOUT 36 vertical sync output pulse G1 11 GREEN input 1 PH1LF 37 phase 1 loop filter B1 12 BLUE input 1 GND3 38 ground 3 (0 V) 39 horizontal sync output pulse BLANK1 13 blanking input 1 HOUT CLAMP 14 clamping pulse input SAND 40 sandcastle pulse output DECFT 15 decoupling filter tuning VP2 41 supply voltage 2 (+8 V) 42 4.4336 MHz crystal CHROMAI 16 chrominance input XTAL1 CVBSEXT 17 external CVBS/Y input XTAL2 43 3.5820 MHz crystal for PAL-N GND1 18 ground 1 (0 V) XTAL3 44 3.5756 MHz crystal for PAL-M 45 3.5795 MHz crystal for NTSC 46 PLL colour filter VP1 19 supply voltage 1 (+8 V) XTAL4 CVBSINT 20 internal CVBS input PLL DECDIG 21 decoupling digital supply rail CHROMAO 47 chrominance output for TDA8395 48 SECAM reference output i.c. 22 internally connected (test purposes) SECAM LOGIC2 23 crystal logic 2 input/output Y 49 Y output LOGIC1 24 crystal logic 1 input/output B−Y 50 B−Y output 51 R−Y output 52 blanking/insertion input 2 (PIP) COLOUR2 25 colour system logic 2 input/output R−Y COLOUR1 26 colour system logic 1 input/output BLANK2 R/W 27 read/write selection input 1996 Jan 25 5 Philips Semiconductors Product specification PAL/NTSC colour processor for PIP applications TDA8310A handbook, halfpage R2 1 52 BLANK2 G2 2 51 R−Y B2 3 50 B−Y IDENT 4 49 Y BLANK 5 48 SECAM B 6 47 CHROMAO G 7 46 PLL R 8 45 XTAL4 SYSTSW 9 44 XTAL3 R1 10 43 XTAL2 G1 11 42 XTAL1 B1 12 41 VP2 BLANK1 13 40 SAND TDA8310A CLAMP 14 39 HOUT DECFT 15 38 GND3 CHROMAI 16 37 PH1LF CVBSEXT 17 36 VOUT GND1 18 35 DECBG VP1 19 34 n.c. CVBSINT 20 33 n.c. DECDIG 21 32 CVBSSW i.c. 22 31 GND2 LOGIC2 23 30 INTB LOGIC1 24 29 i.c. COLOUR2 25 28 HUE COLOUR1 26 27 R/W MGD127 Fig.2 Pin configuration. 1996 Jan 25 6 Philips Semiconductors Product specification PAL/NTSC colour processor for PIP applications TDA8310A FUNCTIONAL DESCRIPTION Integrated video filters CVBS switch The circuit contains a chrominance bandpass and trap circuit. The filters are realised by gyrator circuits that are automatically tuned by comparing the tuning frequency with the crystal frequency of the decoder. When a Y/C signal is supplied to the input the chrominance trap is automatically switched off by the Y/C detection circuit however, it is also possible to force the filters in the CVBS or Y/C position. The circuit contains a 2 input CVBS switch and one of the inputs can be switched between CVBS and Y/C. The circuit contains an identification circuit which can automatically switch between the CVBS and Y/C signals. It is also possible to force the switch to CVBS or Y/C. Synchronization circuit The luminance delay line is also realised by gyrator circuits. The sync separator is preceded by a voltage controlled amplifier which adjusts the sync pulse amplitude to a fixed level. The sync pulses are fed to the slicing stage (separator) which operates at 50% of the amplitude. Colour decoder The colour decoder contains an alignment-free crystal oscillator, a colour killer circuit and colour difference demodulators. The 90° phase shift for the reference signal is achieved internally. The separated sync pulses are fed to the first phase detector and to the coincidence detector. The coincidence detector is used to detect whether the line oscillator is synchronized and for transmitter identification. The first PLL has a very high static steepness this ensures that the phase of the picture is independent of the line frequency. The line oscillator operates at twice the line frequency. The colour decoder is very flexible. Together with the SECAM decoder (TDA8395) an automatic multistandard decoder can be designed but it is also possible to use it for one standard when only one crystal is connected to the IC. The decoder can be forced to one of the standards via the ‘forced mode’ pins. The crystal pins which are not used must be connected to the positive supply line via a 8.2 kΩ resistor. It is also possible to connect the non-used pins with one resistor to the positive supply line. In this event the resistor must have a value of 8.2 kΩ divided by the number of pins. The oscillator network is internal. Because of the spread of internal components an automatic adjustment circuit has been added to the IC. The circuit compares the oscillator frequency with that of the crystal oscillator in the colour decoder. This results in a free-running frequency which deviates less than 2% from the typical value. The chrominance output signal of the video switch is externally available and must be used as an input signal for the SECAM decoder. The horizontal output pulse is derived from the horizontal oscillator via a pulse shaper. The pulse width of the output pulse is 5.4 µs, the front edge of this pulse coincides with the front edge of the sync pulse at the input. RGB/YUV switch The vertical output pulse is generated by a count-down circuit. The pulse width is approximately 380 µs. Both the horizontal and vertical output pulses will always be available at the outputs even when no input signal is available. The RGB/YUV switch is for switching between two RGB or YUV video sources. The outputs of the switch can be set to high-impedance state so that other switches can be used in parallel. In addition to the horizontal and vertical sync pulse outputs the IC has a sandcastle pulse output which contains burst key and blanking pulses. 1996 Jan 25 The switch is controlled via pins 13 and 52. The details of switch control are shown in Table 4. 7 Philips Semiconductors Product specification PAL/NTSC colour processor for PIP applications TDA8310A LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC134). SYMBOL PARAMETER MIN. MAX. UNIT VP supply voltage − 9.0 V Tstg storage temperature −25 +150 °C Tamb operating ambient temperature −25 +70 °C Tsld soldering temperature for 5 s − 260 °C Tj maximum operating junction temperature − 150 °C THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE UNIT ≤40 K/W CHARACTERISTICS VP = 8 V; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VP supply voltage (pins 19 and 41) 7.2 8.0 8.8 V IP1 supply current (pin 19) 45 65 80 mA IP2 supply current (pin 41) 3 5 10 mA Ptot total power dissipation − 560 − mW Rbias value of resistor to be connected between pin 30 and the positive supply line − 10 − kΩ − 1 1.4 V CVBS and Y/C switch INTERNAL CVBS AND EXTERNAL CVBS/Y INPUTS (PINS 20 AND 17) V20,17(p-p) CVBS/Y input voltage (peak-to-peak value) I20,17 input current − 4 6 µA Vclamp top sync clamping voltage level − 3.3 − V Iclamp clamping input current 80 100 − µA − 0.3 − V 1.0 − − V notes 1 and 3 CHROMINANCE INPUT (PIN 16) V16(p-p) chrominance input voltage (peak-to-peak value) V16(p-p) input signal amplitude before clipping note 2 occurs (peak-to-peak value) RI chrominance input resistance CI chrominance input capacitance 1996 Jan 25 notes 1, 4 and 11 note 1 8 14 20 26 kΩ − − 5 pF Philips Semiconductors Product specification PAL/NTSC colour processor for PIP applications SYMBOL PARAMETER TDA8310A CONDITIONS MIN. TYP. MAX. UNIT CHROMINANCE OUTPUT (PIN 47) V47(p-p) output signal voltage amplitude (peak-to-peak value) 0.18 0.20 0.22 V ZO output impedance 200 250 300 Ω VO DC output voltage 1.2 1.4 1.6 V V open-circuit output SWITCH CONTROL INPUT FOR INTERNAL/EXTERNAL POSITIVE/NEGATIVE MODULATION (PIN 32); note 5 − − 1.0 external CVBS or Y/C signal selected 3.9 − VP V input impedance 25 − − kΩ 50 − − dB − − 1.0 V 2.0 − 3.0 V V32 internal CVBS signal selected V32 ZI ISS suppression of non-selected video input signal note 2 SWITCH CONTROL INPUT FOR EXTERNAL CVBS OR Y/C SELECTION (PIN 9) V9 filters switched to CVBS condition V9 filters switched to Y/C condition V9 automatic selection of CVBS or Y/C 3.9 − VP V ZI input impedance 25 − − kΩ − fosc − MHz − 2 − 20 − − dB MHz note 6 Chrominance filters, luminance delay line and luminance output CHROMINANCE TRAP CIRCUIT ftrap trap frequency QF trap quality factor SR colour subcarrier rejection notes 2 and 7 CHROMINANCE BANDPASS CIRCUIT fc centre frequency − fosc − QBP bandpass quality factor note 2 − 3 − ∆td difference in delay time between the luminance and the demodulated chrominance signals note 2 0 50 100 ns B bandwidth of internal delay line note 2 8 − − MHz note 23 0.8 1.0 1.2 V 80 100 120 Ω Y DELAY LINE Y OUTPUT (PIN 49) V49(b-w) output signal voltage amplitude (black-to-white value) ZO output impedance V49(DC) DC output voltage level (top sync) 2.7 2.9 3.1 V Ibias internal bias current of NPN emitter follower output transistor 0.4 0.5 − mA Isource maximum source current − − 2 mA 1996 Jan 25 9 Philips Semiconductors Product specification PAL/NTSC colour processor for PIP applications SYMBOL TDA8310A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Horizontal and vertical synchronization circuits SYNC VIDEO INPUT (PINS 17 AND 20) V17,20 sync pulse voltage amplitude note 1 50 300 − mV SL slicing level note 8 − 50 − % note 9 22 − − µs VERTICAL SYNC tW width of the vertical sync pulse without sync instability HORIZONTAL OSCILLATOR ffr free running frequency − 15625 − Hz ∆ffr spread on free running frequency − − ±2 % ∆fosc/∆VP frequency variation with respect to the supply voltage VP = 8 V ±10%; note 2 − 0.2 0.5 % ∆fosc frequency variation with temperature Tamb = 0 to 70 °C; note 2 − − 80 Hz ∆fosc(max) maximum frequency deviation at the start of the horizontal output no calibration − − 75 % − ±0.9 ±1.2 kHz HORIZONTAL PLL (FILTER CONNECTED TO PIN 37); note 18 fHR holding range PLL fCR catching range PLL ±0.6 ±0.9 − kHz S/N signal-to-noise ratio of the video input signal at which the time constant is switched 14 20 26 dB HYS hysteresis at the switching point 1 3 6 dB − V note 2 HORIZONTAL OUTPUT (PIN 39) VOH HIGH level output voltage IO = 2 mA 2.4 4.0 IO = 2 mA VOL LOW level output voltage − 0.3 0.6 V Isink sink current − − 2 mA Isource source current − − 2 mA tW pulse width − 5.4 − µs td delay between the positive edge of the horizontal output pulse and the start of the horizontal sync pulse at the input − 0 − µs 1996 Jan 25 10 Philips Semiconductors Product specification PAL/NTSC colour processor for PIP applications SYMBOL PARAMETER TDA8310A CONDITIONS MIN. TYP. MAX. UNIT VERTICAL OUTPUT (PIN 36); note 10 ffr free running frequency − 50/60 − Hz flock locking range 45 − 64.5 Hz divider value not locked − 625/525 − lines locking range 488 − 722 lines/ frame VOH HIGH level output voltage IOL = 2 mA 2.4 4.0 − V VOL LOW level output voltage IOL = 2 mA − 0.3 0.6 V Isink sink current − − 2 mA Isource source current − − 2 mA tW pulse width − 380 − µs td delay between the start of the vertical sync pulse at the input and the positive edge of the output pulse − 37.5 − µs SANDCASTLE PULSE OUTPUT (PIN 40); note 16 VO output voltage during scan IO = 1 mA; note 24 − − 0.9 V VO output voltage during burst key IO = 1 mA; note 24 4.1 − 5.2 V ZO output impedance during blanking 1.0 − − MΩ tW pulse width burst key 3.3 3.5 3.7 µs line blanking 8.4 8.7 9.0 µs vertical blanking − 14 − lines 5.2 5.4 5.6 µs 26 − − dB − − 2 dB −38 −41 −44 dB 0 +3 +6 dB 0 +1 +8 dB 2.3 − 2.7 td delay of start of burst key to start of sync Colour demodulation part CHROMINANCE AMPLIFIER ACCcr ACC control range ∆V change in amplitude of the output signals over the ACC range THRon threshold colour killer ON HYSoff hysteresis colour killer OFF strong input signal note 11 note 2 S/N ≥ 40 dB noisy input signal ACL CIRCUIT chrominance burst ratio at which the ACL starts to operate 1996 Jan 25 11 Philips Semiconductors Product specification PAL/NTSC colour processor for PIP applications SYMBOL PARAMETER TDA8310A CONDITIONS MIN. TYP. MAX. UNIT REFERENCE PART Phase-locked loop; note 12 fCR catching range 300 500 − Hz ∆ϕ phase shift for a ±300 Hz deviation of note 2 the oscillator frequency − − 2 deg TCosc temperature coefficient of fosc note 2 − 2.0 2.5 Hz/K Oscillator ∆fosc fosc deviation with respect to VP VP = 8 V ±10%; note 2 − − 250 Hz RI input resistance (pins 43 to 45) fi = 3.58 MHz; note 1 − 1.5 − kΩ RI input resistance (pin 42) fi = 4.43 MHz; note 1 − 1 − kΩ CI input capacitance (pins 42 to 45) note 1 R required resistance to VP for a crystal note 20 pin which is not used − − 10 pF 7.8 8.2 8.6 kΩ HUE CONTROL INPUT (PIN 28); note 21 HUEcr HUE control range see also Fig.3 ±35 ±40 − deg Vcontrol control voltage to switch the colour PLL in the free-running mode note 12 VP − 1 − − V RI input resistance 45 − − kΩ DEMODULATOR OUTPUTS (PINS 50 AND 51) V50(p-p) −(B−Y) output signal voltage amplitude (peak-to-peak value) note 25 1.06 1.33 1.60 V V51(p-p) −(R−Y) output signal voltage amplitude (peak-to-peak value) note 25 0.84 1.05 1.26 V spread of signal amplitude ratio PAL/NTSC note 2 −1 − +1 dB − − 500 Ω ZO output impedance (R−Y)/(B−Y) output B bandwidth of demodulators −3 dB; note 19 − 650 − kHz V50(p-p) (B−Y) residual carrier output voltage (peak-to-peak value) f = fosc − − 1 mV f = 2fosc − − 5 mV V51(p-p) (R−Y) residual carrier output voltage (peak-to-peak value) f = fosc − − 1 mV f = 2fosc − − 5 mV V51(p-p) H/2 ripple at (R−Y) output (peak-to-peak value) only burst fed to input − − 25 mV ∆VO/∆T change of output signal amplitude with temperature note 2 − 0.1 − %/K ∆VO/∆VP change of output signal amplitude with supply voltage note 2 − − ±0.1 dB Ibias internal bias current of NPN emitter follower output transistor 0.16 0.20 − mA Isource maximum source current − − 1 mA 1996 Jan 25 12 Philips Semiconductors Product specification PAL/NTSC colour processor for PIP applications SYMBOL PARAMETER TDA8310A CONDITIONS MIN. TYP. MAX. UNIT DEMODULATION ANGLE AND GAIN RATIO G demodulation angle 85 90 95 gain ratio of both demodulators G(B−Y) to G(R−Y) 1.60 1.78 1.96 deg − 4.43 − MHz 0.2 0.25 0.3 V REFERENCE SIGNAL OUTPUT FOR TDA8395 (PIN 48) fref reference frequency V48(p-p) output signal amplitude (peak-to-peak value) note 13 VO output voltage level PAL/NTSC identified 1.5 1.6 1.7 V VO output voltage level no PAL/NTSC; SECAM (by TDA8395) identified 4.3 4.5 4.7 V I48 required current to force the decoder in SECAM mode 120 − − µA STANDARD IDENTIFICATION AND FORCED SYSTEM SWITCHING (PINS 4 AND 23 TO 27); note 14 VI/O input/output voltage in ‘low’ condition − − 1.0 V in ‘high’ condition 4.0 − 5.3 V − − VP V − − 1 mA − − 1 µA − − 10 µA VI(max) maximum input voltage Iload maximum load current (pins 23 to 26) II input current (pins 23 to 26) note 22 in ‘low’ or ‘high’ condition when connected to VP RI input resistance (pin 27) VO output voltage (pin 4) during PAL note 22 80 − − kΩ IO = 0.5 mA; notes 17 and 24 − − 0.9 V 4.1 − 5.5 V note 17 1 − − MΩ − − 0.5 mA during SECAM ZO output impedance (pin 4) during NTSC Iload maximum load current (pin 4) RGB switch RGB INPUTS (PINS 1 TO 3 AND 10 TO 12) Vi(p-p) signal voltage amplitude (peak-to-peak value) − − 1.3 V ZI input impedance 100 − − kΩ Vclamp active clamping voltage level 2.6 2.8 3.0 V ILI input leakage current − − 3 µA Iclamp active clamping current −200 − +200 µA 1996 Jan 25 note 2 13 Philips Semiconductors Product specification PAL/NTSC colour processor for PIP applications SYMBOL TDA8310A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT FAST BLANKING/SWITCH INPUTS (PINS 13 AND 52); note 15 II input current − −0.2 −0.3 mA VIH HIGH level input voltage 0.9 − 3.0 V VIL LOW level input voltage 0 − 0.5 V td delay between input and output pulse − − 50 ns td delay between switch input and RGB output − − 70 ns V13 input voltage on pin 13 to make RGB outputs and the fast blanking output high-ohmic 4 − VP V 4.0 4.5 VP V CLAMPING PULSE INPUT (PIN 14) VIH HIGH level input voltage VIL LOW level input voltage − − 1 V ZI input impedance 1 − − MΩ RGB OUTPUTS (PINS 6 TO 8) Gv voltage gain of the switches −0.5 0 +0.5 dB Gdiff gain difference of the three channels − − 0.5 dB ZO output impedance − − 150 Ω f = 1 MHz ZO(off) output impedance in the ‘off’ state f = 10 MHz 100 − − kΩ VO output voltage during blanking open-circuit output 1.2 1.4 1.6 V Vos blanking off-set voltage of the two sources − − 5 mV Isource(max) maximum source current − − 1 mA Ibias internal bias current of NPN emitter follower output transistor 0.16 0.2 − mA ISS input signal suppression when RGB outputs are high-ohmic f = 5 MHz; note 2 60 − − dB f = 10 MHz; note 2 50 − − dB f = 22 MHz; note 2 40 − − dB f = 5 MHz; note 2 −60 − − dB f = 10 MHz; note 2 −50 − − dB f = 22 MHz; note 2 −40 − − dB gain reduction −0.5 dB 5 − − MHz gain reduction −1 dB 10 − − MHz gain reduction −3 dB 22 − − MHz − − 20 ns αct B td 1996 Jan 25 crosstalk between the two RGB channels bandwidth of the RGB channels delay from RGB input to output CL = 20 pF; note 2 note 2 14 Philips Semiconductors Product specification PAL/NTSC colour processor for PIP applications SYMBOL PARAMETER TDA8310A CONDITIONS MIN. TYP. MAX. UNIT FAST BLANKING OUTPUT (PIN 5) VOH HIGH level output voltage 2 − 3 V VOL LOW level output voltage 0 − 0.3 V ZO output impedance − − 300 Ω ZO(off) output impedance in the ‘off’ state 100 − − kΩ tr rise time of the output pulse − − 30 ns tf fall time of the output pulse − − 30 ns td delay difference between fast blanking and RGB at the outputs − − 30 ns Iload maximum load current − − 1 mA Notes 1. This parameter is not tested during production and is just given as application information for the designer of the television receiver. 2. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix batches which are made in the pilot production period. 3. Signal with negative-going sync. Amplitude includes sync pulse amplitude. 4. Burst amplitude; for a colour bar with 75% saturation the chrominance signal amplitude is 660 mV (p-p). 5. The IC has two 3-level switch control inputs for the selection of the video signal for the decoder and synchronization circuits. The video source for internal or external signal is selected via pin 32, also the polarity of the demodulation for the internal signal. When the video switch is in the external position the voltage level of pin 9 determines whether the video filters are switched to CVBS or Y/C. It is also possible via pin 9 to select an automatic detection of the Y/C signal. 6. This value is internally generated when the pin is left open-circuit (the minimum value of the series resistor is 25 kΩ). 7. The −3 dB bandwidth of the circuit can be calculated by means of the following equation: 1 f –3 dB = f osc 1 – -------- 2Q 8. The slicing level is independent of the sync pulse amplitude. 9. The horizontal and vertical sync are stable while processing Copy Guard signals and signals with phase shifted sync pulses (stretched tapes). Trick mode conditions of the VCR will also not disturb the synchronization. The value given is the delay caused by the vertical sync pulse integrator. The integrator has been designed such that the vertical sync is not disturbed for special anti-copy tapes with vertical sync pulses with an on/off time of 10/22 µs. 10. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit. This divider circuit has 2 search modes of operation: a) The ‘large window’ mode is switched on when the circuit is not synchronized or, when a non-standard signal is received (the number of lines per frame in the 50 Hz mode is between 311 and 314 and in the 60 Hz mode between 261 and 264). In the search mode the divider can be triggered between line 244 and line 361 (approximately 45 to 64.5 Hz). b) The ‘narrow window’ mode is switched on when more than 15 successive vertical sync pulses are detected in the narrow window. When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp generator is started at the end of the window. Consequently, the disturbance of the picture is very small. The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found within the window. 1996 Jan 25 15 Philips Semiconductors Product specification PAL/NTSC colour processor for PIP applications TDA8310A 11. At a chrominance input voltage of 660 mV (p-p) (colour bar with 75% saturation i.e. burst signal amplitude 300 mV (p-p)) as given in Characteristics first parameter of Section “Chrominance input (pin 16)” the dynamic range of the ACC is +6 and −20 dB. 12. All frequency variations are referenced to 3.58/4.43 MHz carrier frequency. All oscillator specifications are measured with the Philips crystal series 9922 520. If the spurious response of the 4.43 MHz crystal is lower than −3 dB with respect to the fundamental frequency for a damping resistance of 1 kΩ, oscillation at the fundamental frequency is guaranteed. The spurious response of the 3.58 MHz crystal must be lower than −3 dB with respect to the fundamental frequency for a damping resistance of 1.5 kΩ. The catching and detuning range are measured for nominal crystal parameters. These are: a) Load resonance frequency f0 (CL = 20 pF) = 4.433619 or 3.579545 MHz b) Motional capacitance CM = 20.6 fF (4.43 MHz crystal) or 14.7 fF (3.58 MHz crystal) c) Parallel capacitance C0 = 5.5 pF (4.43 MHz crystal) or 4.5 pF (3.58 MHz crystal). The actual load capacitance in the application should be CL = 18 pF to account for parasitic capacitances on and off chip. The free-running frequency of the oscillator can be checked by the HUE control pin to the positive supply rail. In that condition the colour killer is not active so that the frequency offset is visible on the screen. When two or more crystals are connected to the IC the circuit must be forced to one of the crystals during this test to prevent the oscillator continuously switching between the various frequencies. 13. The reference signal for the TDA8395 is available only when the crystal oscillator is operating at a frequency of 4.43 MHz. When a SECAM signal is identified this signal is only available during the vertical retrace period thus avoiding crosstalk with the incoming SECAM signal during scan. 14. The identified colour standard can be read from the IC in two ways: a) From the voltage level of pin 4. The voltage during the demodulation of the various standards is given in the last three parameters of this section. b) From the pins 23 to 26 when pin 27 is in the ‘read’ mode. When pin 27 is in the ‘write’ mode the colour decoder can be forced to one of the colour standards. The levels for the various standards are given in Tables 1, 2 and 3. 15. The control possibilities of the RGB switch via pins 13 and 52 are shown in Table 4. 16. To obtain a simple interface between the TDA8310A and the PIP processor the sandcastle output has been designed such that the output is pulled down during scan and pulled up during the burst key pulse. During blanking the output is high-ohmic and therefore the output voltage is determined by the load. 17. The output of pin 4 is designed similar to the sandcastle output. The output is pulled down during PAL and pulled up during SECAM. During NTSC the pin is floating so that the output level is determined by the load. 18. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is switched depending on the input signal condition. Therefore the circuit contains a noise detector and the time constant is switched to ‘slow’ when excessive noise is present in the signal. This occurs when the internal video signal is selected or for an external CVBS signal when the chrominance input (pin 16) is left open-circuit. The time constant is always ‘fast’ when the chrominance input pin is connected to ground and the input is switched to the Y/C mode. In the ‘fast’ mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to head-switching of the VCR are corrected as soon as possible. During weak signal conditions (noise detector active) the phase detector is gated and the width of the gate pulse has a value of 5.7 µs so that the effect of the noise is reduced to a minimum. The output current of the phase detector for the various conditions is shown in Table 5. 19. This value indicates the bandwidth of the complete chrominance circuit including the chrominance bandpass filter. The bandwidth of the demodulator low-pass filter is approximately 1 MHz. 1996 Jan 25 16 Philips Semiconductors Product specification PAL/NTSC colour processor for PIP applications TDA8310A 20. The crystal pins which are not used must be connected to the positive supply line via an 8.2 kΩ resistor. It is also possible to connect the non-used pins together and use a resistor with a value of 8.2 kΩ divided by the number of pins which are not used. 21. When this pin is left open-circuit the HUE control is set to the nominal value. 22. When one or more pins have to be connected to the positive supply line the total current must be limited to 40 µA. This can be achieved by connecting these pins together and connecting them to a positive supply line via a 100 kΩ resistor. When separate resistors are used a resistor with a higher value must be used so that the total current is limited to the required level. 23. This output signal value is obtained when the CVBS or Y input signal at pins 17 and/or 20 has an amplitude of 0.7 V (black-to-white value). 24. The output buffer consists of a combination of a PMOS and an NMOS. The maximum output impedance in the low state can be calculated by dividing the maximum output voltage (for this parameter 0.9 V) by the specified current. For the high state this resistance can be calculated by dividing the difference between the maximum and minimum output voltage by the specified current. The output impedance is independent of the value of the output current. 25. These output signal values are obtained for a colour bar input signal with 75% saturation. 1996 Jan 25 17 Philips Semiconductors Product specification PAL/NTSC colour processor for PIP applications TDA8310A Table 1 Read/write pin input (pin 27) MODE Table 5 Output current of phase detector CURRENT PHASE SCAN DETECTOR (µA) DURING LEVEL Decoder automatic LOW Forced decoder mode HIGH Table 2 Colour system logic (pins 25 and 26) PIN 25 PIN 26 STANDARD LOW LOW auto/no colour LOW HIGH PAL HIGH LOW NTSC HIGH HIGH SECAM VERTICAL RETRACE (µA) GATED YES/NO Weak signal and synchronized 30 30 YES (5.7 µs) Strong signal and synchronized 180 270 NO Not synchronized 180 270 NO MBE018 handbook, halfpage 40 Table 3 Crystal logic (pins 23 and 24) (deg) SELECTED CRYSTAL (MHz) PIN 23 PIN 24 LOW LOW 4.43 LOW HIGH 3.579 (NTSC) HIGH LOW 3.575 (PAL-M) HIGH HIGH 3.582 (PAL-N) 20 0 Table 4 Control logic RGB switch (pins 13 and 52) FAST BLANKING OUTPUT PIN 13 PIN 52 RGB OUTPUT LOW LOW black LOW LOW HIGH RGB 2 HIGH HIGH LOW RGB 1 HIGH HIGH HIGH RGB 2 HIGH 1996 Jan 25 20 40 0 1 2 3 4 Fig.3 HUE control curve. 18 (V) 5 Philips Semiconductors Product specification PAL/NTSC colour processor for PIP applications TDA8310A PACKAGE OUTLINE seating plane SDIP52: plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1 ME D A2 L A A1 c e Z b1 (e 1) w M MH b 27 52 pin 1 index E 1 26 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 5.08 0.51 4.0 1.3 0.8 0.53 0.40 0.32 0.23 47.9 47.1 14.0 13.7 1.778 15.24 3.2 2.8 15.80 15.24 17.15 15.90 0.18 1.73 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 90-01-22 95-03-11 SOT247-1 1996 Jan 25 EUROPEAN PROJECTION 19 Philips Semiconductors Product specification PAL/NTSC colour processor for PIP applications TDA8310A The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Jan 25 20 Philips Semiconductors Product specification PAL/NTSC colour processor for PIP applications TDA8310A NOTES 1996 Jan 25 21 Philips Semiconductors Product specification PAL/NTSC colour processor for PIP applications TDA8310A NOTES 1996 Jan 25 22 Philips Semiconductors Product specification PAL/NTSC colour processor for PIP applications TDA8310A NOTES 1996 Jan 25 23 Philips Semiconductors – a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40-2783749, Fax. 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Printed in The Netherlands 537021/1100/02/pp24 Document order number: Date of release: 1996 Jan 25 9397 750 00589