PHILIPS BUK9540-100A

Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9540-100A
BUK9640-100A
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope available in
TO220AB and SOT404 . Using
’trench’ technology which features
very low on-state resistance. It is
intended for use in automotive and
general
purpose
switching
applications.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VDS
ID
Ptot
Tj
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
VGS = 5 V
VGS = 10 V
MAX.
UNIT
100
37
138
175
V
A
W
˚C
40
39
mΩ
mΩ
PINNING
TO220AB & SOT404
PIN
PIN CONFIGURATION
DESCRIPTION
1
gate
2
drain
3
source
SYMBOL
d
tab
mb
g
2
1
tab/mb drain
3
1 2 3
TO220AB
SOT404
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VDGR
±VGS
±VGSM
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Non-repetitive gate-source voltage
RGS = 20 kΩ
tp≤50µS
-
100
100
10
15
V
V
V
V
ID
ID
IDM
Ptot
Tstg, Tj
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
- 55
37
26
149
138
175
A
A
A
W
˚C
TYP.
MAX.
UNIT
-
1.1
K/W
in free air
60
-
K/W
Minimum footprint, FR4
board
50
-
K/W
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
Rth j-mb
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient(TO220AB)
Thermal resistance junction to
ambient(SOT404)
-
Rth j-a
Rth j-a
December 1999
1
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9540-100A
BUK9640-100A
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
V(BR)DSS
Drain-source breakdown
voltage
Gate threshold voltage
VGS = 0 V; ID = 0.25 mA;
VGS(TO)
MIN.
TYP.
MAX.
UNIT
VGS = 10 V; ID = 25 A
VGS = 4.5 V; ID = 25 A
100
89
1
0.5
-
1.5
0.05
2
30
29
31
2.0
2.3
10
500
100
40
100
39
43
V
V
V
V
V
µA
µA
nA
mΩ
mΩ
mΩ
mΩ
MIN.
TYP.
MAX.
UNIT
Tj = -55˚C
VDS = VGS; ID = 1 mA
Tj = 175˚C
Tj = -55˚C
IDSS
Zero gate voltage drain current
VDS = 100 V; VGS = 0 V;
IGSS
RDS(ON)
Gate source leakage current
Drain-source on-state
resistance
VGS = ±10 V; VDS = 0 V
VGS = 5 V; ID = 25 A
Tj = 175˚C
Tj = 175˚C
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
2304
222
151
3072
266
207
pF
pF
pF
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; Rload =1.2Ω;
VGS = 5 V; RG = 10 Ω
-
20
135
125
90
30
189
189
135
ns
ns
ns
ns
Ld
Internal drain inductance
-
4.5
-
nH
Ld
Internal drain inductance
-
3.5
-
nH
Ld
Internal drain inductance
-
2.5
-
nH
Ls
Internal source inductance
Measured from drain lead 6 mm
from package to centre of die
Measured from contact screw on
tab to centre of die(TO220AB)
Measured from upper edge of drain
tab to centre of die(SOT404)
Measured from source lead to
source bond pad
-
7.5
-
nH
MIN.
TYP.
MAX.
UNIT
-
-
37
A
IF = 25 A; VGS = 0 V
IF = 37 A; VGS = 0 V
-
0.85
1.1
149
1.2
-
A
V
V
IF = 37 A; -dIF/dt = 100 A/µs;
VGS = -10 V; VR = 30 V
-
60
0.24
-
ns
µC
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL
PARAMETER
IDR
IDRM
VSD
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
trr
Qrr
Reverse recovery time
Reverse recovery charge
December 1999
CONDITIONS
2
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9540-100A
BUK9640-100A
AVALANCHE LIMITING VALUE
SYMBOL
1
DSS
W
120
PARAMETER
CONDITIONS
Drain-source non-repetitive
unclamped inductive turn-off
energy
ID = 25 A; VDD ≤ 25 V;
VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
Normalised Power Derating
PD%
MIN.
TYP.
MAX.
UNIT
-
-
31
mJ
1000
110
ID/A
100
90
RDS(ON)=VDS/ID
tp =
1us
100
80
70
10us
60
50
100us
40
10
30
1ms
20
DC
10ms
10
100ms
0
0
20
40
60
80 100
Tmb / C
120
140
160
180
1
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
120
VDS/V
1000
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Normalised Current Derating
ID%
10
1
100
10
Zth/(K/W)
110
100
1
90
0.5
80
0.2
70
0.1
60
0.1
0.05
50
0.02
40
0.01
0
30
20
10
0.001
1E-07
0
0
20
40
60
80 100
Tmb / C
120
140
160
180
1E-05
1E-03
1E-01
1E+01
t/s
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
1 For maximum permissible repetive avanche current see fig.18.
December 1999
3
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9540-100A
BUK9640-100A
VGS/V =
120
ID/A
100
Drain current, ID (A)
5.0
10.0
40
4.0
3.8
3.6
3.4
80
30
3.2
20
175 C
20
2.8
40
Tj = 25 C
25
3.0
60
VDS > ID X RDS(ON)
35
15
2.6
10
2.4
5
0
0
0
0
2
4
VDS/V
6
8
1
2
10
3
4
5
6
7
8
9
10
Gate-source voltage, VGS (V)
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
Fig.8. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
50
70
gfs/S
3.0
ID/A
60
45
3.2
3.4
3.6
4.0
5.0
40
35
50
40
30
30
20
25
10
20
0
10
20
30
VDS/V
40
50
60
70
0
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
ID/A
20
30
40
Fig.9. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
3
38
RDS(ON) Ohm
10
36
Rds(on) normalised to 25degC
a
2.5
34
2
32
1.5
30
28
1
26
3
4
5
6
7
VGS/V
8
9
0.5
10
Fig.7. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(VGS); conditions: ID = 25 A;
December 1999
-100
-50
0
50
100
Tmb / degC
150
200
Fig.10. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V
4
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
2.5
BUK9540-100A
BUK9640-100A
VGS(TO) / V
5
VGS / V
max.
4
2
VDS = 14V
VDS = 44V
typ.
3
1.5
min.
2
1
1
0.5
0
-100
0
-50
0
50
Tj / C
100
150
200
0
Fig.11. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
20 QG / nC 30
40
50
Fig.14. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 25 A; parameter VDS
Sub-Threshold Conduction
1E-01
10
Source-Drain Diode Current, IF (A)
50
VGS = 0 V
45
40
1E-02
35
2%
1E-03
typ
30
98%
175 C
25
Tj = 25 C
20
1E-04
15
10
5
1E-05
0
0
1E-05
0
0.5
1
1.5
2
2.5
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
3
Fig.12. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Capacitance/nF
5
110
4.5
100
4
90
3.5
80
WDSS%
70
3
60
2.5
50
Ciss
2
40
1.5
30
1
20
0.5
10
Coss
Crss
0.1
1
VDS/V
10
0
100
20
Fig.13. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
December 1999
1.1 1.2 1.3 1.4 1.5
Fig.15. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
120
0
0.01
1
Source-Drain Voltage, VSDS (V)
40
60
80
100
120
Tmb / C
140
160
180
Fig.16. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 75 A
5
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9540-100A
BUK9640-100A
VDD
+
+
RD
L
VDS
VDS
-
VGS
-
VGS
-ID/100
T.U.T.
0
VDD
0
RG
T.U.T.
R 01
shunt
RGS
Fig.17. Avalanche energy test circuit.
WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD )
Fig.19. Switching test circuit.
100
25ºC
IAV
10
Tj prior to avanche 150ºC
1
0.001
0.01
0.1
Avalanche Time, tAV (ms)
1
10
Fig.18. Maximum permissible repetitive avalanche
current(IAV) versus avalanche time(tAV) for unclamped
inductive loads.
December 1999
6
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9540-100A
BUK9640-100A
MECHANICAL DATA
Dimensions in mm
4,5
max
Net Mass: 2 g
10,3
max
1,3
3,7
2,8
5,9
min
15,8
max
3,0 max
not tinned
3,0
13,5
min
1,3
max 1 2 3
(2x)
0,9 max (3x)
2,54 2,54
0,6
2,4
Fig.20. SOT78 (TO220AB); pin 2 connected to mounting base.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for SOT78 (TO220) envelopes.
3. Epoxy meets UL94 V0 at 1/8".
December 1999
7
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9540-100A
BUK9640-100A
MECHANICAL DATA
Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads
(one lead cropped)
SOT404
A
A1
E
mounting
base
D1
D
HD
2
Lp
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
c
mm
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
OUTLINE
VERSION
D
max.
D1
E
11
1.60
1.20
10.30
9.70
e
Lp
HD
Q
2.54
2.90
2.10
15.40
14.80
2.60
2.20
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
98-12-14
99-06-25
SOT404
Fig.21. SOT404 surface mounting package. Centre pin connected to mounting base.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
December 1999
8
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9540-100A
BUK9640-100A
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5
2.0
3.8
5.08
Fig.22. SOT404 : soldering pattern for surface mounting.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
December 1999
9
Rev 1.000