Philips Semiconductors Product specification TrenchMOS transistor Logic level FET FEATURES PHB45N03LT SYMBOL • ’Trench’ technology • Very low on-state resistance • Fast switching • Stable off-state characteristics • High thermal cycling performance • Low thermal resistance • Surface mounting package QUICK REFERENCE DATA VDSS = 30 V d ID = 45 A RDS(ON) ≤ 24 mΩ (VGS = 5 V) g RDS(ON) ≤ 21 mΩ (VGS = 10 V) s GENERAL DESCRIPTION PINNING N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. PIN The PHB45N03LT is supplied in the SOT404 surface mounting package. tab SOT404 DESCRIPTION mb 1 gate 2 drain (no connection possible) 3 source 2 1 drain 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS VDGR ±VGS ID ID IDM Ptot Tstg, Tj Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature RGS = 20 kΩ Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C - - 55 30 30 15 45 36 180 86 175 V V V A A A W ˚C TYP. MAX. UNIT - 1.75 K/W 50 - K/W THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS Rth j-mb Thermal resistance junction to mounting base Thermal resistance junction to ambient - Rth j-a December 1997 pcb mounted, minimum footprint 1 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHB45N03LT STATIC CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS Drain-source breakdown voltage Gate threshold voltage VGS = 0 V; ID = 0.25 mA; VGS(TO) Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C IDSS Zero gate voltage drain current VDS = 30 V; VGS = 0 V; Tj = 175˚C IGSS RDS(ON) Gate source leakage current Drain-source on-state resistance VGS = ±5 V; VDS = 0 V VGS = 5 V; ID = 25 A VGS = 10 V; ID = 25 A VGS = 5 V; ID = 25 A; Tj = 175˚C MIN. TYP. MAX. UNIT 30 27 1 0.5 - 1.5 0.05 10 20 16 - 2 2.3 10 500 100 24 21 45 V V V V µA µA nA mΩ mΩ mΩ MIN. TYP. MAX. UNIT DYNAMIC CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS gfs Forward transconductance VDS = 25 V; ID = 25 A 8 16 - S Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 40 A; VDD = 24 V; VGS = 5 V - 23 3 9 - nC nC nC Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1050 270 140 - pF pF pF td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 15 V; ID = 25 A; VGS = 5 V; RG = 5 Ω Resistive load - 30 80 95 40 45 130 135 55 ns ns ns ns Ld Ld Internal drain inductance Internal drain inductance - 3.5 4.5 - nH nH Ls Internal source inductance Measured from tab to centre of die Measured from drain lead solder point to centre of die Measured from source lead solder point to source bond pad - 7.5 - nH MIN. TYP. MAX. UNIT - - 45 A IF = 25 A; VGS = 0 V IF = 40 A; VGS = 0 V - 0.95 1.0 180 1.2 - A V IF = 40 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 25 V - 52 0.08 - ns µC REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER IDR IDRM VSD Continuous reverse drain current Pulsed reverse drain current Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge December 1997 CONDITIONS 2 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHB45N03LT AVALANCHE LIMITING VALUE SYMBOL PARAMETER CONDITIONS WDSS Drain-source non-repetitive unclamped inductive turn-off energy ID = 25 A; VDD ≤ 25 V; VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C December 1997 3 MIN. TYP. MAX. UNIT - - 60 mJ Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET 120 PHB45N03LT Normalised Power Derating PD% Zth j-mb / (K/W) 10 110 7528-30 D= 100 90 80 1 70 0.5 60 0.2 50 30 0.1 0.05 20 0.02 40 0.1 10 0 0 0 20 40 60 80 100 Tmb / C 120 140 160 1E-05 1E-03 t/s tp T t 1E-01 1E+01 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Normalised Current Derating ID% D= T 0.01 1E-07 180 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) 120 tp PD ID / A 80 10 110 100 9528-30 4.5 5 6 90 60 4 80 70 VGS / V = 60 40 3.5 50 40 30 3 20 20 2.5 10 0 0 20 40 60 80 100 Tmb / C 120 140 160 0 180 ID / A DS V )= 40 / ID 6 8 4 4.5 30 5 20 10 6 RD 100 us 10 DC 1 ms VGS / V = 10 10 ms 1 1 10 VDS / V 0 100 Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp December 1997 10 9528-30 RDS(ON) / mOhm tp = 10 us N S(O 4 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS 7528-30 100 2 VDS / V Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V 1000 0 0 20 40 ID / A 60 80 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS 4 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHB45N03LT ID / A 60 9528-30 BUK959-60 VGS(TO) / V 2.5 max. 50 2 Tj / C = 25 175 typ. 40 1.5 30 min. 1 20 0.5 10 0 0 1 2 3 VGS / V 4 5 0 -100 6 Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj gfs / S 25 -50 0 50 Tj / C 100 150 200 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS 9528-30 Sub-Threshold Conduction 1E-01 20 1E-02 Tj / C = 25 175 15 10 typ 98% 1E-04 5 0 2% 1E-03 1E-05 0 10 20 30 ID / A 40 50 60 1E-05 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID); conditions: VDS = 25 V a 0.5 1 1.5 2 2.5 3 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS 30V TrenchMOS 2 0 10000 C / pF 9528-30 1.5 Ciss 1000 1 Coss 0.5 Crss 0 -100 -50 0 50 Tj / C 100 150 100 0.1 200 10 100 VDS / V Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V December 1997 1 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 5 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHB45N03LT VGS / V 5 9528-30 120 WDSS% 110 VDS / V = 6 4 100 24 90 80 3 70 60 50 2 40 30 1 20 10 0 0 0 5 10 15 20 25 20 40 60 QG / nC Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 40 A; parameter VDS 60 IF / A 80 100 120 Tmb / C 140 160 180 Fig.15. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 25 A 9528-30 VDD + 50 L VDS 40 Tj / C = 175 25 -ID/100 T.U.T. 0 20 R 01 shunt RGS 10 0 - VGS 30 0 0.5 1 VSDS / V 1.5 2 Fig.16. Avalanche energy test circuit. WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD ) Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj + VDD RD VDS - VGS 0 RG T.U.T. Fig.17. Switching test circuit. December 1997 6 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHB45N03LT MECHANICAL DATA Dimensions in mm 4.5 max 1.4 max 10.3 max Net Mass: 1.4 g 11 max 15.4 2.5 0.85 max (x2) 0.5 2.54 (x2) Fig.18. SOT404 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.19. SOT404 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". December 1997 7 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHB45N03LT DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1997 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. December 1997 8 Rev 1.300