INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4023B gates Triple 3-input NAND gate Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4023B gates Triple 3-input NAND gate DESCRIPTION The HEF4023B provides the positive triple 3-input NAND function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance. Fig.2 Pinning diagram. HEF4023BP(N): Fig.1 Functional diagram. 14-lead DIL; plastic (SOT27-1) HEF4023BD(F): 14-lead DIL; ceramic (cerdip) HEF4023BT(D): 14-lead SO; plastic (SOT73) (SOT108-1) ( ): Package Designator North America Fig.3 Logic diagram (one gate). FAMILY DATA, IDD LIMITS category GATES See Family Specifications January 1995 2 Philips Semiconductors Product specification HEF4023B gates Triple 3-input NAND gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL TYPICAL EXTRAPOLATION FORMULA TYP. MAX. 65 135 ns 38 ns + (0,55 ns/pF) CL 25 50 ns 14 ns + (0,23 ns/pF) CL 15 30 ns 7 ns + (0,16 ns/pF) CL 65 130 ns 38 ns + (0,55 ns/pF) CL 30 60 ns 19 ns + (0,23 ns/pF) CL 25 45 ns 17 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL Propagation delays In → On HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 Output transition times HIGH to LOW 5 10 tTHL 15 5 LOW to HIGH 10 15 VDD V Dynamic power dissipation per package (P) tTLH 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL TYPICAL FORMULA FOR P (µW) 5 1200 fi + ∑ (foCL) × VDD2 where 10 5500 fi + ∑ (foCL) × VDD 2 fi = input freq. (MHz) 15 16 400 fi + ∑ (foCL) × VDD 2 fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 3